Advanced VLSI Design

CMOS Inverter

CMPE 640

The Inverter The electrical behavior of complex circuits (adders, multipliers) can be almost completely derived by extrapolating the results obtained for inverters!

VGS < Vt Vin Vout CL Modeled Ron

Vout VGS > Vt

Ron

Vout

Observations Fully restored (VDD and GND) output levels results in high noise margins. Ratioless: Logic levels are not dependent on the relative device sizes. Low output impedance in steady state (kW connection to either VDD or GND), increases robustness to noise. High input impedance: fanout is theoretically unlimited for static operation, transient response is impacted however. Low static power dissipation: No path between power and ground.
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Advanced VLSI Design

CMOS Inverter
2.5V 2.0V 1.5V

CMPE 640

The Inverter DC current characteristics

Load-line plot Here, PMOS curves have been mirrored around x and shifted. The current of the NMOS and PMOS device MUST be equal. All points are located at either the 0V high or low output levels. NMOS sat PMOS lin NMOS sat PMOS sat NMOS lin PMOS sat NMOS lin PMOS off

1V 1.5V 2.0V

1V 0.5V

2.5V

NMOS off VDD PMOS lin Vout 1.25V

Inverter exhibits a very narrow transition zone.

0V

Vin

1.25V

VDD
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Advanced VLSI Design

CMOS Inverter

CMPE 640

Inverter Models It is possible to approximate the transient response to an RC model. The response is dominated by the output capacitance of the gate, CL. Rp

Vout Rn CL

Vout CL

Load capacitance, CL, is due to diffusion, routing and downstream gates. The propagation delay assuming an instantaneous input transition is RpCL. This indicates a fast gate is built by keeping either or both of Rp and CL small. Rp is reduced by increasing the W/L ratio. Bear in mind that, in reality, Rn/p is a nonlinear function of the voltage across the transistor.

Advanced VLSI Design

CMOS Inverter

CMPE 640

Switching Threshold Previously, we defined VM as the inverter threshold voltage but did not derive an analytical expression for it. The same is true for VIH and VIL, and consequently the noise margins (see text for this analysis). VM is defined as the intersection of the line Vin = Vout and the inverter VTC. VTC Vin=Vout

Vout

VM (gate threshold voltage)

Vin In this region, both the NMOS and PMOS transistors are in saturation since VDS = VGS.
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Advanced VLSI Design

CMOS Inverter

CMPE 640

Switching Threshold Therefore, the value of VM can be obtained by equating the NMOS and PMOS currents (assuming devices are velocity saturated). V V V DSATn + k V V V V V DSATp -----------------------------------k n V DSATn M Tn p DSATp M DD Tp 2 2 Solving for VM: VM
2

V DSATn V DSATp r V Tn ------------------- + r V DD + V Tp + ------------------ 2 2 = --------------------------------------------------------------------------------------------------------------1+r k p V DSATp satp W p r = ------------------------- = -------------------k n V DSATn satn W n

Further simplified: rV DD ------------VM 1+r

with

VM is set by the ratio r, and r compares the relative driving strengths of the PMOS and NMOS transistors. It is desirable to have r = 1, i.e., VM situated in the middle of the available voltage swing (VDD/2) to provide comparable low and high noise margins.
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Advanced VLSI Design

CMOS Inverter

CMPE 640

Switching Threshold The required ratio can be determined for any value of VM using: V V V DSATn ------------------V DSATn k n M Tn ( W L )p 2 ------------------- = ---------------------------------------------------------------------------------------------------( W L )n V DSATp V DSATp k p V DD V M + V Tp + ------------------ 2 Using a generic 0.25 mm CMOS process, this means making the PMOS 3.5 times wider than the NMOS. VM plotted as a function of the PMOS-to-NMOS ratio. 2.0 VM (V) 1.6 1.2 0.8 0.1 x scale gives the log of the ratio of PMOS and NMOS widths as the difference.
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1.0

Wp-Wn

10.0

Advanced VLSI Design

CMOS Inverter

CMPE 640

Switching Threshold Observations from plot VM is relatively insensitive to variations in device ratio. Small variations in the ratio (3.0 -> 2.5) do not disturb the VTC much. Industry sets the ratio of PMOS width to NMOS width to values smaller than that needed for an exact symmetry. For example, setting the ratio to 3, 2.5 and 2 yields switching thresholds of 1.22 V, 1.18 V and 1.13 V, respectively. Increasing the width of the PMOS or the NMOS moves VM toward VDD or GND, respectively. This feature may be desirable in some applications, e.g., when the input signal is noisy (see text). Bear in mind that when the ratio of VDD to VT is relatively small, e.g. 2.5/0.4 = 6), moving VM a lot is difficult and requires very large differences in the width ratios.
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Advanced VLSI Design

CMOS Inverter

CMPE 640

Inverter Threshold Robustness under process variations:

Weak NMOS Strong PMOS

Strong NMOS Weak PMOS

Nominal

VDD

Process variations will cause only small shifts in the transfer curve. The functionality of the gate is not effected however, and this feature has contributed in a big way to the popularity of the static CMOS gate.

Advanced VLSI Design

CMOS Inverter

CMPE 640

Dynamic Behavior Propagation delay is determined by the time it takes to charge/discharge the load cap, CL, so it's worth looking closely at CL before developing a delay model. Simple propagation delay models lumps all capacitances into CL. M2 Vin Cgd12 Cdb2 Cdb1 M1 Cw

Vout
Cg4 Cg3

M4 Vout2 M3

All cap influencing transient response of node Vout.

In this analysis, assume Vin is driven by an ideal voltage source with fixed rise/fall times.

Advanced VLSI Design

CMOS Inverter

CMPE 640

Dynamic Behavior Gate-drain capacitance Cgd12: Capacitance between the gate and drain of the first inverter. M1 and M2 are either in cut-off or in saturation during the first half (up to 50% point) of the output transient. It is reasonable to assume that only M1 & M2 overlap capacitances contribute. Remember, gate cap is either completely between gate/bulk (cut-off) or gate/src (sat). In the lumped model, we need to replace the Cgd12 with a capacitor to GND. The value of this capacitor is given as Cgd = 2*CGD0*W where CGD0 is overlap capacitance per unit width. Note it is doubled due to the Miller effect.

10

Advanced VLSI Design

CMOS Inverter

CMPE 640

Dynamic Behavior Diffusion capacitances Cdb1 and Cdb2: Capacitances due to the reversed biased pn-junction. These caps are quite nonlinear (voltage dependent). We linearized these caps over the voltage range of interest: C eq = K eq C j0 with Cj0 the junction cap/unit area under zero bias conditions. The bottom plate and sidewall zero bias values can be obtained from the SPICE model CJ and CJSW parameters. Keq was derived in an earlier lecture. K eq = ------------------------------------------------------ ( 0 V high ) ( V high V low ) ( 1 m )

1m

( 0 V low )

1m

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Advanced VLSI Design

CMOS Inverter

CMPE 640

Example Consider a 0.25 mm 2.5 V technology and the previous inverter chain. Assume f0 is 0.9 V for both NMOS and PMOS and m = 0.5. Let's compute Cdb1 for the NMOS transistor. Propagation delay is computed between the 50% points. This is the time-instance when Vout reaches 1.25 V. For the high-to-low (H-to-L) transition, we linearize over {2.5 V, 1.25 V} and for the low-to-high transition over {0, 1.25 V}. H-to-L: Vout is initially 2.5 V: Vhigh = -2.5V. At 50%, Vlow = -1.25V. Keq= 0.57. L-to-H: Vout is initially 0 V: Vlow = 0. At 50%, Vhigh = -1.25 V. Keq = 0.79. Sidewall capacitance can be computed in a similar way (see text). Also, similar, but reversed, values are obtained for PMOS device. This linearized simplification has only minor effects on logic delays.
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Advanced VLSI Design

CMOS Inverter

CMPE 640

Dynamic Behavior Wire capacitance Cw: The capacitance is dependent on the length and width of the interconnecting wires and is growing in importance. Gate capacitance of fan-out Cg3 and Cg4: Includes both overlap and gate capacitance of each transistor: C
fan out

= C gate ( NMOS ) + C gate ( PMOS ) = ( C GSOn + C GDOn + W n L n C ox ) + ( C GSOp + C GDOp + W p L p C ox )

But what about the Miller effect? We can safely ignore it here by assuming the driven gate's output does not change until after the 50% point of the input is reached. We also assume, with about a 10% over-estimation error, that the channel cap of the driven gate remains constant over this interval.

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Advanced VLSI Design

CMOS Inverter

CMPE 640

Dynamic Behavior Text gives the capacitance calculated from the layout of a two-inverter chain. Results are given as follows: Overlap capacitance: NMOS: 0.31 fF/m PMOS: 0.27 fF/m Bottom junction capacitance: NMOS: 2.0 fF/m2 PMOS: 1.9 fF/m2 Sidewall junction capacitance: NMOS: 0.28 fF/m PMOS: 0.22 fF/m Gate capacitance: NMOS = PMOS: 6.0 fF/m2 Wire capacitance: Cwire: 0.12 fF Total load for H-to-L: 6.1 fF, for L-to-H: 6.0 fF In text, this cap is almost evenly split between intrinsic and extrinsic srcs.
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Advanced VLSI Design

CMOS Inverter

CMPE 640

Propagation Delay: First-Order Analysis One way to compute delay is to integrate the capacitor (dis)charge current: CL ( v ) t p = -------------- dv i(v)
v1 v2

But both CL(v) and i(v) are nonlinear functions of v. Instead, we can use a simple switch model given earlier to derive an approximation. Here, both the "on" resistance and load capacitance are replaced by a constant elements, assigned average values over the region of interest. Although we didn't cover it in class, the average "on" resistance is given by: R eq 1 = ----------------V DD 2 with
V DD

V DD 2

V DD 3 -------------- V ------------------------------------- dV -- 1 7 V DD 4 I DSAT I DSAT ( 1 + V ) 9

I DSAT

V DSAT W ---- ( V DD V T )V DSAT ---------------- = k 2 L

(see text)

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Advanced VLSI Design

CMOS Inverter

CMPE 640

Propagation Delay: First-Order Analysis The linearized load capacitance is derived as shown previously. Propagation delay is then computed using a first-order linear RC network model: t pHL = ln ( 2 ) R eqn C L = 0.69R eqn C L t pLH = ln ( 2 ) R eqp C L = 0.69R eqp C L Assuming that the equivalent load cap is approximately the same for either transition. The propagation delay is the average of the two: R eqn + R eqp t pHL + t pLH t p = ---------------------------- = 0.69C L ---------------------------- 2 2 This indicates to make rise and fall times identical, it is necessary to make the "on" resistance of the NMOS and PMOS equal. See text for a good example.

16

Advanced VLSI Design

CMOS Inverter

CMPE 640

Propagation Delay: First-Order Analysis Minimizing propagation delay amounts to: Reducing CL. Which is composed of self-loading (diffusion) (intrinsic), routing and fan-out (extrinsic) capacitance. Careful layout can reduce diffusion and interconnect caps. Increase W/L ratio of the transistors. Warning: doing so increases the self-loading and therefore CL! Once intrinsic (self-loading) cap starts to dominate the extrinsic load cap (wires + fanout), increasing the width doesn't help delay. Increase VDD. The delay of a gate can be modulated by modifying the supply voltage. This allows the designer to trade off energy dissipation for performance. However, rising above a certain level yields on a minor improvement. Also, reliability concerns (oxide breakdown, hot-electron effects) set firm upper bounds.
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