Forward Discrete Wavelet Transform IP User Guide

Ha Minh Tran Hanh Spec2 team, ICDREC hanh.haminhtran@icdrec.edu.vn December 8, 2011

Contents
1 FDWT IP model 2 IP Usage 1 4

List of Figures List of Tables

Forward Discrete Wavelet Transform IP User Guide

Abstract This material includes necessary information to use Forward Discrete Wavelet Transform IP.

Prerequisites
Wavelet Transform knowledge. Verilog HDL. This material explains the operation and usage of Forward Discrete Wavelet Transform (FDWT) IP. Above knowledge is necessary to understand the function of interface signals and parameters to use this controller IP.

FDWT IP model
icdrec wavelet a arrange.v icdrec wavelet a line2matrix.v icdrec wavelet a line2matrix wait support.v icdrec wavelet a lossless calc.v icdrec wavelet a lossy calc.v icdrec wavelet b 2 stages lossless calc.v icdrec wavelet b 2 stages lossy calc.v icdrec wavelet c 1d calc.v icdrec wavelet d 2d calc.v icdrec wavelet e multilvl calc.v icdrec wavelet calc.v icdrec wavelet matrixlib.v icdrec misclib.v icdrec wavelet arithmetic.v icdrec wavelet conguration.vh icdrec wavelet parameters.vh icdrec wavelet ratios.vh icdrec wavelet assertion.vh Parameters of top module icdrec wavelet e multilvl calc are described in table 1:

All source les to use this IP are listed below:

Forward Discrete Wavelet Transform IP User Guide

No 1

Table 1: Parameter descriptions for multi-level top module Parameter Default Description Choose Lossy or Lossless computation. The valid values is either LOSSY or LOSSLESS. INPUT DATAWIDTH 8 Data bit width of input data. RATIO BITWIDTH 34 Data bit width of Ratios. The greater this value is, the more accuracy result is. RATIO FRAC BITWIDTH 32 Data bit width of Fractional part of Ratios. These bit will be truncated in nal result by rounding algorithm. ADDER PIPELINE NUM 5 Latency of Adder used. MULT S ADDER PIPELINE NUM 5 Latency of Adder used in Multiplier. MULT PIPELINE NUM 5 Stage of pipeline in Multiplier. MULT LATENCY 24 Latency of Multiplier. IMAGE WIDTH 550 Number of column of input data matrix. IMAGE HEIGHT 825 Number of row of input data matrix. COMPUTATION LEVEL 1 Number of computing level of Wavelet Transform. MATH DATAWIDTH (*) Data bitwidth in lossy computing method. INPUT DATAWIDTH + RATIO FRAC BITWIDTH + 12 COMPUTE TYPE LOSSY

2 3

5 6 7 8 9 10 11 12 (*)

The ratios alpha, beta, gamma, delta and k are dened as parameters in xed-point number format. Table 2: Parameter descriptions for ratios Default Description -34h1960CE676 -34h00D901AE2 34h0E20675D0 34h07189AA41 -34h13AECB0AD Alpha ratio in xed-point number. Beta ratio in xed-point number. Gamma ratio in xed-point number. Delta ratio in xed-point number. -k ratio in xed-point number.

No 1 2 3 4 5

Parameter

RATIO CONST 1 RATIO CONST 2 RATIO CONST 3 RATIO CONST 4 NEG K RATIO

Forward Discrete Wavelet Transform IP User Guide

No 6

Table 2 continued from previous page Parameter Default Description INVERTED K RATIO 34h0D019C28E 1/k ratio in xed-point number.

Top modules have interface signals as described in table 3: Table 3: Signal description of FDWT module Type Width Description In In In In In In In 1 1 INPUT DATAWIDTH INPUT DATAWIDTH INPUT DATAWIDTH 1 4 Clock Asynchronous reset Data input 1 Data input 2 Data input 3 Data input valid Bit 0 - data 2 is end of line data. Bit 1 - data 2 is end of frame data. Bit 2 - data 2 is start of line data. Bit 3 - data 2 is start of frame data. Data out of all computing level. Data out valid of all computing level Meaning of each 6 bits: Bit 0-3 - same meaning as input data Bit 4 - data is belong to low pass column. Bit 5 - data is belong to low pass row.

No. 1 2 3 4 5 6 7

Signals clk drv rst n inp1 in inp2 in inp3 in inp vld in usr ctl in

8 9 10

data out data vld out usr ctl out

Out Out Out

Base on other parameters COMPUTATION LEVEL 6 x COMPUTATION LEVEL

Output data of all computing level are assigned to output pin as below table in case of lossy computing method: Table 4: Lossy output data assignment data out [MATH DATAWIDTH - RATIO FRAC BITWIDTH - 1 : 0] next above bitwidth next above bitwidth

Level 1 2 3

data vld [0] [1] [2]

usr ctl out [5:0] [11:6] [17:12]

In case of lossless computing method, output data of all computing level are assigned to output pin as below table:

Forward Discrete Wavelet Transform IP User Guide

Level 1 2 3

data vld [0] [1] [2]

Table 5: Lossless output data assignment data out [INPUT DATAWIDTH + 4 - 1 : 0] (INPUT DATAWIDTH + 2x4) bits next to above portion (INPUT DATAWIDTH + 3x4) bits next to above portion

usr ctl out [5:0] [11:6] [17:12]

IP Usage
Dertemine ratios values in xed-point number with expected accuracy and modify icdrec wavelet ratios.vh to new values. Modify parameters in icdrec wavelet parameters.vh and top module les to match requirement, or defparam those parameters when top module is instanced. Instance top module icdrec wavelet multilevel.v . Go to sim folder, compile and simulate design. Dont need to check the function in this step. Open waveform of the simulations result. Check any instance of module icdrec specii s lb mul trunc round to get the latency from signal enable in to signal enable out. Modify parameter MULT LATENCY in icdrec wavelet parameters.vh to above value. Go to sim folder, re-compile and simulate to verify function.

To prevent unique function of golden model and IP, do following steps to use this IP:

This IP re-uses many modules in common library. Be sure to indicate common library revision 21 or greater to get correct function.

Forward Discrete Wavelet Transform IP User Guide

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