UNIT VI

Real World Interfacing Part - II

 Introduction
 In serial communication data/information is transmitted bit after
bit.
 In parallel communication a number of bits are transmitted at once
from one computer to the second computer.
 The operation of the Enhanced USART module is controlled through
three registers:
 Transmit Status and Control (TXSTA)
 Receive Status and Control (RCSTA)
 Baud Rate Control (BAUDCON)

TXSTA RCSTA BAUDCON

Control settings for Tx Control settings for <BRG16> is used to access

mode Rx mode SPBRGH:SPBRG or only SPBRG
TXSTA: Transmit Status and Control
R/W-0
SENDB
D7 D6 D5 D4 D3 D2 D1 D0
CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D

 TXEN: Transmit enable bit

 1: enable 0: disable
 SYNC: EUSART mode select bit
 1:Synchronous mode 0: Asynchronous mode
 BRGH: High baud rate select bit
 Asyn : 1:high speed 0: low speed
 Sync: unused
 TRMT: Transmit shift register status bit
 1:
CSRC: Clock TSRSelect
Source empty bit 0: TSR full TX9: 9-Bit Transmit Enable bit
TXEN: Transmit Enable bit SYNC: EUSART Mode Select bit
SENDB: Send Break Character bit BRGH: High Baud Rate Select bit
TRMT: Transmit Shift Register Status bit TX9D: 9th bit of Transmit Data
 RCSTA: Receive Status and Control Register

D7 D6 D5 D4 D3 D2 D1 D0
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

 SPEN: Serial Port Enable bit

1: Serial Port enable(configures Rx/DT and Tx/CK pins as serial port
pins)
 CREN: Continuous Receive Enable bit
Asyn: 1: Enables receiver 0: Disables reception

SPEN: Serial Port Enable bit RX9: 9-Bit Receive Enable bit
SREN: Single Receive Enable bit CREN: Continuous Receive Enable bit
ADDEN: Address Detect Enable bit FERR: Framing Error bit
OERR: Overrun Error bit RX9D: 9th bit of Received Data
Transmission Block Diagram
Serial Transmission and associated SFRs
 The information we want to transmit is loaded into register TXREG (8
bits size). In case the transmitted data is 9 bits long, the 9th bit is placed
TX9D.
 At the same time, the information above is being loaded into the
register TSR, which is used as a temporary buffer before that
information is transmitted.
 TXIF – is set then TXREG is empty/free and ready to be loaded with a new
information.
 TXIE – is enabling the interrupt in the case TXREG is loaded/filled and
TXIF = 1.
 SPBRG – sets the desired baud rate in the system.
 TXEN – is enabling the SPBRG.
Reception Block Diagram
 Baud rates supported by PIC 18
 1200, 2400,4800,9600,19200,38400,57600,115200
 The BRG is a dedicated, 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous modes of
the EUSART.
 By default, the BRG operates in 8-bit mode; setting the
BRG16 bit (BAUDCON<3>) selects 16-bit mode.
 The SPBRGH:SPBRG register pair controls the period of a
free-running timer.
 In Asynchronous mode, bits, BRGH (TXSTA<2>) and
BRG16 (BAUDCON<3>), also control the baud rate.
Configuration bits BRG mode Baud rate formula
SYNC =0(Asynchronous mode)
BRG16 BRGH N=SPBRGH:SPBRG
0 0 8bit BR= FOSC/[64 (n + 1)]
0 1 8bit BR=FOSC/[16 (n + 1)]
1 0 16bit BR=FOSC/[16 (n + 1)]
1 1 16bit BR=FOSC/[4 (n + 1)]

➢ Examples
SFRs associated with Serial
communication
 TXREG: Transfer register
 8 bit register used for serial communication in PIC18
 For a byte of data to be transferred via Tx pin, it must be
placed in TXREG.
 The moment the byte is written into TXREG it is fetched
into TSR(transmit shift register)
 The TSR frames the 8 bit data with the start and stop bits.
 The 10 bit data is transferred serially via the Tx pin.
 TSR is not accessible and is strictly for internal use.
 RCREG: Receive register
 When the bits are received serially via the Rx pin, the PIC18
de frames them by eliminating the stop bit and start bits.
 The value for generation of baud rate is loaded in
SPBRGH:SPBRG SFRs.
 Algorithm for serial transmission
1. Initialize RxD line as i/p and TxD line as o/p
2. Calculate the count value for desired baud rate and load
SPBRGH:SPBRG using one of the formulae from the table.
3. Load a value in TXSTA, indicating asynchronous mode and 8
bit data frame, baud rate speed (high/low)
4. Select BRG mode=16 bit by setting BRG16 in BAUDCON
SFR.
5. Enable serial port by setting SPEN bit in RCSTA
6. Load TXREG with byte to be transmitted.
7. Monitor TXIF flag in PIR1 register to make sure UART is
ready for next transmission.
8. Repeat step 6 until all bytes are transmitted.
 Enable the reception by setting bit CREN bit in RCSTA
 Flag bit, RCIF, will be set when reception is complete and an
interrupt will be generated if enable bit, RCIE, was set.
 Read the 8-bit received data by reading the RCREG register.
 If any error occurred, clear the error by clearing enable bit
CREN.
 To check the received data either display it on LCD or on PC
by transmitting it through EUSART.
Serial Communication
 Registers associated with the EUSART:
 TXREG(Transfer register)
 RCREG(Receive register)
 BRG(Serial port Baud rate Generator)
 TXSTA(Transmit Status and control register)
 RCSTA(Receive status and control register)
 BAUDCON (Baud Rate Control) [BRG16]
 PIR1 (Peripheral Interrupt request 1) [Flags TXIF(4) & RCIF(5)]
 PIE1(Peripheral Interrupt enable 1) [TXIE(4) & RCIE(5)]
“BITS” TO REMEMBER
 SYNC
 BRGH
 TXEN
 TXIF
 SPEN
 BRG16
 SPBRGH: SPBRG
Serial Communication interfacing
diagram
ADC INTERFACING
 ADC is used to convert analog signals into digital signal.
 The physical quantities are all analog (continuous). These
physical quantities must be first converted into electrical
signals through transducers or sensors.
 While interfacing a microcontroller with the real world
quantities such converters are quite essential.
 Characteristics of ADC are:
 Resolution
 Conversion time
 Reference voltage
 10bit A/D module of PIC18
 The Analog-to-Digital (A/D) Converter module 13 inputs for the
40/44-pin devices.
 This module allows conversion of an analog input signal to a
corresponding 10-bit digital number.
 The module has five registers:
SFR Function
A/D Result High Register To store the 10 bit result after conversion
(ADRESH)
A/D Result Low Register(ADRESL)
A/D Control Register 0 (ADCON0) .control the A/D module, SOC and EOC
A/D Control Register1 (ADCON1) configures the functions of the port pins
A/D Control Register 2 (ADCON2) configures the A/D clock source, programme acquisition time
and justification.
 Pin
Signal
description
Pin No. Function
Channel 0 (AN0) 2 RA0/AN0
Channel 1 (AN1) 3 RA1
Channel 2 (AN2) 4 RA2
Channel 3 (AN3) 5 RA3
Channel 4 (AN4) 7 RA5
Channel 5 (AN5) 8 RE0
Channel 6 (AN6) 9 RE1
Channel 7 (AN7) 10 RE2
Channel 8 (AN8) 35 RB2
Channel 9 (AN9) 36 RB3
Channel 10 (AN10) 34 RB1
Channel 11(AN11) 37 RB4
Channel 12 (AN12) 33 RB0
 ADCON0 (A/D CONTROL 0 )
D7 D6 D5 D4 D3 D2 D1 D0
-- -- CHS3 CHS2 CHS1 CHS0 GO/*DONE ADON

 CHS<3:0>: Analog Channel Select bits

0000 Channel 0 (AD0)
0001 Channel 1 (AD1)
0010 Channel 2 (AN2/RA2)
0011 Channel 3 (AN3)
 GO/DONE: A/D Conversion Status bit
 When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
 ADON: A/D On bit
1 = A/D Converter module is enabled
0 = A/D Converter module is disabled
 ADCON1 (A/D CONTROL 1)
D7 D6 D5 D4 D3 D2 D1 D0
-- -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

 VCFG1: Voltage Reference Configuration bit (VREF-

source)
1 = VREF- (AN2)
0 = VSS
 VCFG0: Voltage Reference Configuration bit (VREF+
source)
1 = VREF+ (AN3)
0 = VDD
 PCFG<3:0>: A/D Port Configuration Control bits
 ADCON2(A/D CONTROL 2)
D7 D6 D5 D4 D3 D2 D1 D0
ADFM -- ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0

 ADFM: A/D Result Format Select bit

 1 = Right justified
 0 = Left justified
 ACQT<2:0>: A/D Acquisition Time Select bits
111 = 20 TAD 110 = 16 TAD
101 = 12 TAD 100 = 8 TAD
011 = 6 TAD 010 = 4 TAD
001 = 2 TAD 000 = 0 TAD
 ADCS<2:0>: A/D Conversion Clock Select bits
111 = FRC (clock derived from A/D RC oscillator) 110 = FOSC/64
101 = FOSC/16 100 = FOSC/4
011 = FRC (clock derived from A/D RC oscillator) 010 = FOSC/32
001 = FOSC/8 000 = FOSC/2
Theory
 The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
 Each port pin associated with the A/D Converter can be
configured as an analog input, or as a digital I/O.
 The ADRESH and ADRESL registers contain the result of the
A/D conversion.
 When the A/D conversion is complete, the result is loaded
into the ADRESH:ADRESL register pair, the GO/*DONE
bit (ADCON0 register) is cleared and the A/D Interrupt
Flag bit, ADIF, is set.
On chip ADC module Block diagram
 Algorithm
 The following steps should be followed to perform an A/D conversion:
 Configure the A/D module:
 Configure analog pins, voltage reference and digital I/O (ADCON1)
 Select A/D input channel (ADCON0)
 Select A/D acquisition time (ADCON2)
 Select A/D conversion clock (ADCON2)
 Turn on A/D module (ADCON0)
 Configure A/D interrupt (if desired):
 Clear ADIF bit
 Set ADIE bit
 Set GIE bit
 Wait the required acquisition time (if required).
 Start conversion:
 Set GO/DONE bit (ADCON0 register)
 Wait for A/D conversion to complete, by either:
 Polling for the GO/DONE bit to be cleared
OR
 Waiting for the A/D interrupt
 Read A/D Result registers (ADRESH:ADRESL);clear bit ADIF, if required.
 For next conversion, go to step 1 or step 2, as required.
A/D interfacing diagram
 MSSP: Master Synchronous Serial Port
 The Master Synchronous Serial Port (MSSP) module is a serial interface,
useful for communicating with other peripheral or microcontroller
devices.
 These peripheral devices may be serial EEPROMs, shift registers, display
drivers, A/D converters, etc.
 The MSSP module can operate in one of two modes:
 Serial Peripheral Interface (SPI)
 Inter-Integrated Circuit (I2C™)
 Full Master mode
 Slave mode (with general address call)
 The I2C interface supports the following modes in hardware:
 Master mode
 Multi-Master mode
 Slave mode
SPI: Serial Peripheral Interface Module
 The MSSP module has four registers for SPI mode operation.
 MSSP Control Register 1 (SSPCON1)
 MSSP Status Register (SSPSTAT)
 Serial Receive/Transmit Buffer Register (SSPBUF)
 MSSP Shift Register (SSPSR) – Not directly accessible
 SPI Mode:
 The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four modes of the SPI
are supported. To accomplish communication, typically three pins
are used:
 Serial Data Out (SDO) – RC7/RX/DT/SDO
 Serial Data In (SDI) – RB0/AN12/INT0/FLT0/SDI/SDA
 Serial Clock (SCK) – RB1/AN10/INT1/SCK/SCL
 Chip select can be any i/o line
 SSPSTAT: Status Register
 Lower 6 bits : read only
 Upper 2 bits read/write
D7 D6 D5 D4 D3 D2 D1 d0

SMP CKE D/*A P S R/*w UA BF

SMP: Sample bit BF: Buffer Full Status bit (Receive mode
SPI Master mode: only)
1 = Input data sampled at end of data output time 1 = Receive complete, SSPBUF is full
0 = Input data sampled at middle of data output time 0 = Receive not complete, SSPBUF is empty
CKE: SPI Clock Select bit
1 = Transmit occurs on transition from active to Idle
clock state
0 = Transmit occurs on transition from Idle to active
clock state
 SSPCON1
D7 D6 D5 D4 D3 D2 D1 d0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

SSPEN: Master Synchronous Serial Port Enable bit

1 = Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
0 = Disables serial port and configures these pins as I/O port pins bit 4
CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0011 = SPI Master mode, clock = TMR2 output/2
0010 = SPI Master mode, clock = FOSC/64
0001 = SPI Master mode, clock = FOSC/16
0000 = SPI Master mode, clock = FOSC/4
 Initializing SPI module
 SSPCON1<5:0> and SSPSTAT<7:6> control bits have to be programmed
appropriately. Following configurations can be achieved:
 Master mode (SCK is the clock output)
 Slave mode (SCK is the clock input)
 Clock Polarity (Idle state of SCK)
 Data Input Sample Phase (middle or end of data output time)
 Clock Edge (output data on rising/falling edge of SCK)
 Clock Rate (Master mode only)
 Slave Select mode (Slave mode only)
 To enable the serial port, MSSP Enable bit, SSPEN (SSPCON1<5>), must be set.
 This configures the SDI, SDO, SCK and SS pins as serial port pins.
 SDI is automatically controlled by the SPI module RB0
 SDO must have TRISC<7> bit cleared RC7
 SCK (Master mode) must have TRISB<1> bit cleared RB1
 SCK (Slave mode) must have TRISB<1> bit set
 /SS must have TRISA<5> bit set