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CS 207 Computer Organization and Architecture

(Section-B)

Basic Computer Organization and Design

Instruction Code
• An instruction code is a group of bits that instruct the computer to perform a specific
operation.
• The operation code of an
instruction is a group of bits
that define operations such as
addition, subtraction, shift,
complement, etc.
• An instruction must also
include one or more operands,
which indicate the registers
and/or memory addresses from
which data is taken or to which
data is deposited.
• For a memory unit with 4096 words- 12 bits are required to specify the address of the
operand. (16-bit memory word)

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Direct and Indirect Address

Effective address: The address where the
operand is found.
Indirect address: The address where the
address of the operand is found.
Direct address: The address of the operand.

AC  AC + M [457]

AR  M [300]
AC  AC + M [AR]
where AR = 1350

Computer Registers
• We need registers which can hold
the address at which a memory
operand is stored as well as the
value itself.
• We need a place where we can
store
– temporary data
– the instruction being executed,
– a character being read in
– a character being written out.
• Computer instructions are stored in
consecutive locations and are
executed sequentially; this requires
a register which can stored the
address of the next instruction; we
call it the Program Counter.

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List of Registers for the Basic Computer

Common Bus System

• To avoid excessive wiring, memory and all the 7-
(except- INPR) register are connected via a common
bus.
• The specific output that is selected for the bus is
determined by S2S1S0.
• The register whose LD (Load) is enable receives the
data from the bus.
• Registers can be incremented by setting the INR
control input and can be cleared by setting the CLR
control input.
• The Accumulator’s input must come via the Adder
& Logic Circuit. This allows the Accumulator and
Data Register to swap data simultaneously.
• The address of any memory location being accessed
must be loaded in the Address Register.
All except INPR and Adder are connected to a clock pulse

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Common Bus System

Example: 1 The 16 bit outputs of DR are placed on
the bus lines when S2S1S0 = 011 (DR=3). The
particular register whose LD (load) input is enabled
receives the data from the bus during the next clock
pulse transition.
Example: 2 The memory receives the contents of the
bus when its write input is activated and S2S1S0 =
111. The memory places its 16-bit output onto the
bus when the read input is activated and S2S1S0 =
111.
Example: 3 INPR is connected to provide
information to the bus but OUTR can only receive
information from the bus. (communicate with the
eight least significant bits in the bus).

Computer Instructions
The basic computer has three instruction code formats:
Memory-reference format – where seven
3-bit op-codes are followed by a 12-bit
memory address and preceded by a bit
which indicates whether direct or indirect
addressing is being used.
Register-reference format – where 01112 is
followed by 12 bits which indicate a register
instruction.
Input-output format – where 11112 is
followed by 12 bit which indicate an input-
output instruction. Basic Computer Instruction formats

The bit at position 15 in the instruction code is not used as a mode bit when the operation code is equal to 111.

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Basic Computer Instructions

Memory Reference
Instruction (7)

Register Reference
Instruction (12)

Input-output
Instruction (6)

Timing and Control

• The timings for all registers in the basic computer is controlled by
a master clock generator.
• The clock pulses are applied to all FFs and registers in the system
as well as in the control unit.
• The clock pulses do not change the state of a register unless the
register is enabled by a control signal.
• The control signals are generated in the control unit and provide
control inputs for the multiplexers in the common bus, processor
registers, and micro-operations for the accumulator.

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Timing and Control

• Control logic is implemented with gates, flip-
There are two types of control:

flops, decoders and other digital circuits.

• It has the advantage that it can be optimized
Hardwired to produced a fast mode of operation.

• Control information is stored in a control memory,

which is programmed to implement instructions (to
initiate the sequence of micro-operations).
• It requires changes in the wiring among the various
Micro- components if the design has to be modified (By
programed updating the micro-program in the control memory).

Control Unit
• Control unit block diagram:
• Two decoder
• A sequence counter
• Number of control logic gates
• Instruction register (IR)
• The operation code in bits 12 through 14
are decoded with 3 x 8 decoder.
• The 4-bit sequence counter can count in
binary from 0 through 15. The outputs of the
counter are decoded into 16 timing signals T0
to T15 which are used to control the sequence
of operations.
• The sequence counter SC can be
incremented (to provide the next active
timing signals T0 , T1, T2……) or cleared
synchronously.

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Timing and Control

• Timing signals are generated by the sequence
counter (SC), which receives as inputs the clock
pulse, increment and clear.

Example: 1 The RTL statement

D3T4 : SC 0
At time T4, SC is cleared to 0 if decoder output
D3 is active. The next timing signal is T0.

Example: 2 The Register transfer statement

T0 : AR PC
At time T0, (during an entire clock cycle interval)
content of PC is transferred to AR (S2S1S0 = 010
and LD input of AR should be enabled).

The actual transfer does not occur until the end of the clock cycle when the clock goes through a positive transition. This same
positive clock transition increments the sequence counter SC from 0000 to 0001 . The next clock cycle has T1 Active and T0 inactive.

Instruction Cycle
• The instructions of a program are carried out
by a process called the instruction cycle.
• The instruction cycle consists of these phases:
1. Fetch an instruction from memory
2. Decode the instruction.
3. Read the effective address from memory
if the operand has an indirect address.
4. Execute the instruction.
5. Repeat the steps until the HALT
instruction is encountered.

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Fetch and Decode

• Initially, the PC has stored the address of the instruction about to be executed and the
SC is cleared to 0.
• With each clock pulses the SC is incremented and the timing signals go through the
sequence T0, T1, T2, etc.
• It is necessary to load the AR with the PC’s address (it is connected to memory address
inputs):
T0: AR  PC
• Subsequently, as we fetch the instruction to be executed, we must increment the
program counter so that it points to the next instruction:
T1: IR M[AR], PC  PC + 1
• In order to carry out the instruction, we must decode and prepare to fetch the
operand. In the event it is an indirect operand, we need to have the indirect
addressing bit as well:
T2: D0, … D7  Decode IR(12-14),
AR  IR (0-11), I  IR(15)

Register Transfers For

the Fetch Phase

At Time T0:
1. Place the content of PC onto the bus by
making the bus selection inputs S2 S1 S0 =
010.
2. Transfer the content of the bus to AR by
enabling the LD input of AR.
At Time T1:
1. Enable the read input of memory.
2. Place the content of memory onto the bus
by making S2 S1 S0 = 111.
3. Transfer the content of the bus to IR by
enabling the LD input of IR.
4. Increment PC by enabling the INR input of
PC.

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Instruction Cycle
At time T3:
• The control unit determines if this is a memory-
reference, register-reference or input/output
instruction.
• The D7 output line of the decoder is used to
discriminate the type of the instruction.
• The latter two are distinguished by the I (indirect)
bit.
• If it is a memory-reference instruction, the I bit
will determine direct or indirect addressing.
• The four separate paths are:
• D7’ I T3 : AR  M[AR]
T4
• D7’ I’ T3 : Nothing
• D7 I’ T3: Execute a register-reference
instruction
• D7 I T3 : Execute an input-output instruction

Memory-Reference Instructions
• All memory-reference instructions have to wait until T4 so that the timing
is the same whether the operand is direct or indirect.
• AND, ADD and LDA must all be performed in two steps because AC can
only be access via DR:

AND: D0T4 : DR  M[AR]

D0T5 : AC  AC ^ DR, SC  0

ADD: D1T4 : DR  M[AR]

D1T5 : AC  AC + DR, E Cout , SC  0

LDA: D2T4 : DR  M[AR]

D2T5 : AC  DR, SC  0

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Memory-Reference Instructions
STA : stores the contents of the AC, which can be applied directly to the bus:

D3T4 : M[AR] AC, SC  0

BUN: transfers control unconditionally to the effective address indicated by the effective
address:
D4T4: PC  AR, SC  0

BSA: is used to branch to a subprogram. This requires saving the return address, which is
saved at the operand’s effective address with the beginning one word later in memory:

D5T4: M[AR]  PC, AR AR + 1

D5T5: PC  AR, SC  0

Example of BSA Instruction Execution

Branch and Save Return Address:
• This instruction is useful
for branching to a portion
of the program called a
subroutine or procedure.
• When BSA executed, it
stores the address of the
next instruction in
sequence (available in
PC) into a memory
location specified by the
effective address.
D5T4: M[AR]  PC, AR AR + 1
D5T5: PC  AR, SC  0

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Memory-Reference Instructions (continued)

• ISZ: skips the next instruction if the operand stored at the effective address
is 0. This requires that the PC incremented, which cannot be done directly:
D6T4 : DR  M[AR]
D6T5 : DR  DR + 1
D6T6 : M[AR]  DR,
if (DR = 0) then (PC  PC + 1), SC  0

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Input-Output Configuration
Basic input- output communication
with a terminal unit Keyboard and
printer:
• The terminal sends and receive serial
information.
• The serial information from the
keyboard is transmitted to INPR.
• The serial information for the printer is
stored in OUTR.
• INPR and OUTR communicate with
the terminal serially and with the AC in
parallel.
• The flags are needed to synchronize the
timing difference between I/O device Programmed control transfer
and the computer.

Input-Output Configuration

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Interrupt Cycle
• Programmed control transfer for implementing the input-output communication is inefficient
because computer is always busy for checking the status of flag bit.
• An alternative approach to use the external device which inform to computer when it is ready for
the transfer, in a meantime the computer can be busy with other tasks. (interrupt facility)
• During the program running mode, computer does not check the flags.

Interrupt Cycle
• The interrupt cycle is added in the
instruction cycle to handle the interrupt
(input-output transfer).
• The interrupt cycle is a HW implementation
of a branch and save return address
operation.
• Interrupt enable FF (IEN) can be made set
and reset (with the use IOF instruction). If
IEN=0 then flags cannot interrupt the
computer, otherwise (IEN=1) computer can
be interrupted.

Process for handing the interrupt by the computer

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Branch and Save Return address

• At the beginning of the next
instruction that is read from
memory is in address 1.
• At memory address 1, the
programmer must store a
branch instruction that sends
the control to an interrupt
service routine.
• The instruction that returns
the control to the original
program is “indirect BUN
0”.
Complete Instruction cycle

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Problem and Discussion

Problems and Discussion

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Problems and Discussion

Problems and Discussion

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Problems and Discussion

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