OM6621Ex Datasheet V3.2

OM6621Ex Bluetooth Low Energy Application
OM6621Ex
Bluetooth Low Energy Compliant & 2.4-GHz Proprietary
System-on-Chip
V3.2
Datasheet
www.onmicro.com.cn
Table of Contents
Table of Contents ................................................................................................................. 1

Version History ..................................................................................................................... 7
1. OM6621Ex Overview ....................................................................................................... 8
1.1. Description............................................................................................................. 8
1.2. Features ................................................................................................................ 8
1.3. System Function Block Diagram ......................................................................... 10
1.4. Applications ......................................................................................................... 10
2. Pinout ............................................................................................................................. 11
2.1. OM6621EM ......................................................................................................... 11
2.2. OM6621ED .......................................................................................................... 12
2.3. Pin Description .................................................................................................... 13
3. MCU Subsystem ............................................................................................................ 16
3.1. MCU Debug ......................................................................................................... 16
3.2. Interrupts Vector .................................................................................................. 17
3.3. Electrical Specifications....................................................................................... 17
3.4. Module Address Mapping .................................................................................... 18
4. Memory .......................................................................................................................... 20
4.1. Memory Introduction............................................................................................ 20
4.2. Memory Map........................................................................................................ 20
4.3. APB Address Space ............................................................................................ 21
5. PMU ............................................................................................................................... 22
5.1. Power Management ............................................................................................ 22
5.2. DC-DC Converter ................................................................................................ 23
5.3. Digital LDO .......................................................................................................... 23
5.4. POR/BOD ............................................................................................................ 23
5.5. Current Consumption .......................................................................................... 24
6. 2.4G RF Transceiver...................................................................................................... 25
6.1. Block Diagram ..................................................................................................... 25
6.2. Function Description ............................................................................................ 25
6.3. Baseband ............................................................................................................ 26
7. Watchdog Timer ............................................................................................................. 29
7.1. Introduction .......................................................................................................... 29
7.2. Main Features...................................................................................................... 29
7.3. Function Description ............................................................................................ 29
7.4. WDT Register Map .............................................................................................. 29
8. Clock .............................................................................................................................. 31
8.1. Introduction .......................................................................................................... 31
8.2. Features .............................................................................................................. 31
8.3. Function Description............................................................................................ 31
8.4. CPM Register Map .............................................................................................. 33
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9. Peripherals ..................................................................................................................... 43
9.1. PINMUX ............................................................................................................... 43
9.2. DMA ..................................................................................................................... 47
9.3. Control SPI Interface ........................................................................................... 57
9.4. GPIO .................................................................................................................... 69
9.5. UART1 ................................................................................................................. 78
9.6. UART0 ............................................................................................................... 115
9.7. TIMER................................................................................................................ 120
9.8. GPADC .............................................................................................................. 200
9.9. I2S ..................................................................................................................... 210
9.10. Audio ................................................................................................................ 227
9.11. I2C ................................................................................................................... 233
9.12. EFUSE ............................................................................................................. 261
9.13. IR ..................................................................................................................... 268
10. Communication Subsystem ....................................................................................... 280
10.1. Supported Features......................................................................................... 280
10.2. Radio Transceiver ........................................................................................... 280
10.3. Bluetooth Baseband Unit................................................................................. 281
10.4. Performance .................................................................................................... 282
11. Application Circuit ...................................................................................................... 284
12. Package Information .................................................................................................. 287
13. Ordering Information .................................................................................................. 291
14. Tape and Reel Information ........................................................................................ 292
14.1. Tape Orientation .............................................................................................. 292
14.2. Tape and Reel Dimensions ............................................................................. 292
15. Glossary and Abbreviations ....................................................................................... 295
16. Declaration of No Harmful Substances ..................................................................... 296
Figure 1.1 OM6621Ex block diagram......................................................................... 10
Figure 1.2 OM6621Ex applications ............................................................................ 10
Figure 2.1 OM6621EM chip pin definition .................................................................. 11
Figure 2.2 OM6621ED chip pin definition .................................................................. 12
Figure 2.3 OM6621EG chip pin definition .................................................................. 13
Figure 3.1 Micro-controller Subsystem ...................................................................... 16
Figure 4.1 Memory Map ............................................................................................. 20
Figure 4.2 APB Memory Map ..................................................................................... 21
Figure 5.1 DC-DC Mode ............................................................................................. 22
Figure 5.2 LDO Mode ................................................................................................. 22
Figure 6.1 OM6621E block diagram .......................................................................... 25
Figure 8.1 main_clk .................................................................................................... 31
Figure 8.2 System clocks ........................................................................................... 32
Figure 9.1 Example of DMA Data Transfers .............................................................. 47
Figure 9.2 Example of Hardware Handshaking ......................................................... 48
Figure 9.3 Linked List Structure for Chain Transfers ................................................. 49
Figure 9.4 Data Order at the Destination ................................................................... 50
Figure 9.7 Specific SPI Device Configuration ............................................................ 58
Figure 9.8 Basic structure of a standard I/O Port Bit ................................................. 69
Figure 9.9 Input Floating/Pull up/Pull down Configurations ....................................... 70
Figure 9.10 Output Configuration ............................................................................... 71
Figure 9.11 High Impedance-analog Configuration ................................................... 72
Figure 9.12 Serial Data Format .................................................................................. 79
Figure 9.13 Receiver Serial Data Sample Points....................................................... 80
Figure 9.14 Baud Clock Reference Timing Diagram ................................................. 80
Figure 9.15 IrDA SIR Data Format ............................................................................. 81
Figure 9.16 Timing for RAM Reads ............................................................................ 82
Figure 9.17 Timing for RAM Writes ............................................................................ 83
Figure 9.18 RTL Diagram of Data Synchronization Module ...................................... 84
Figure 9.19 Timing Diagram for Data Synchronization Module ................................. 84
Figure 9.20 Auto Flow Control Block Diagram ........................................................... 86
Figure 9.21 Auto RTS Timing ..................................................................................... 87
Figure 9.22 Auto CTS Timing ..................................................................................... 87
Figure 9.23 Flowchart of Interrupt Generation ........................................................... 88
Figure 9.24 Flowchart of Interrupt generation ............................................................ 89
Figure 9.25 Clock Gate Enable Timing ...................................................................... 90
Figure 9.26 Resuming Clock(s) After Low Power Mode Timing ................................ 91
Figure 9.27 Advanced control timer block diagram .................................................. 121
Figure 9.28 Counter timing diagram ......................................................................... 122
Figure 9.29 Counter timing diagram ......................................................................... 123
Figure 9.30 Counter timing diagram, internal clock divided by 1 ............................. 124
Figure 9.33 Counter timing diagram, internal clock divided by N ............................ 125
Figure 9.34 Counter timing diagram, update event when ARPE = 0 (TIM_ARR not
preloaded) ......................................................................................................... 125
Figure 9.35 Counter timing diagram, update event when ARPE = 0 (TIM_ARR
preloaded) ......................................................................................................... 125
Figure 9.40 Counter timing diagram,........................................................................ 127
Figure 9.42 Counter sequence diagram,.................................................................. 128
Figure 9.47 Update rate examples depending on mode and TIM_RCR register .... 131
Figure 9.48 Control circuit in normal mode, internal clock divided by 1 .................. 131
Figure 9.49 TI1 external clock connection example................................................. 132
Figure 9.50 Control circuit in external clock mode 1 ................................................ 132
Figure 9.51 External trigger input block ................................................................... 133
Figure 9.52 Control circuit in external clock mode 2 ................................................ 133
Figure 9.53 Capture/compare channel..................................................................... 134
Figure 9.54 Main circuit of capture/compare channel 1 ........................................... 134
Figure 9.55 Capture/compare the output portion of the channel (channel 4) .......... 135
Figure 9.56 PWM Input Mode Timing....................................................................... 137
Figure 9.57 Output compare mode, toggle on OC1 ................................................. 138
Figure 9.58 Edge-aligned PWM waveforms (ARR=8) ............................................. 139
Figure 9.59 Center-aligned PWM waveforms (ARR=8) ........................................... 140
Figure 9.60 Complementary output with dead-time insertion .................................. 141
Figure 9.61 Dead-time waveforms with delay greater than the negative pulse....... 141
Figure 9.62 Dead-time waveforms with delay greater than the positive pulse ........ 141
Figure 9.63 Output behavior in response to a break ............................................... 144
Figure 9.64 Clearing TIMx OCxREF ........................................................................ 145
Figure 9.65 step generation, COM example (OSSR=1) .......................................... 145
Figure 9.66 Example of one pulse mode ................................................................. 146
Figure 9.67 Example of counter operation in encoder interface mode .................... 149
Figure 9.68 Example of hall sensor interface ........................................................... 150
Figure 9.69 Control circuit in reset mode ................................................................. 151
Figure 9.70 Control circuit in gated mode ................................................................ 152
Figure 9.71 Control circuit in trigger mode ............................................................... 152
Figure 9.72 Control circuit in external clock mode2 + trigger mode ........................ 153
Figure 9.73 Master/Slave timer example ................................................................. 154
Figure 9.74 Gating timer 2 with OC1REF of timer 1 ................................................ 155
Figure 9.75 Gating timer 2 with Enable of timer 1.................................................... 155
Figure 9.76 Triggering timer 2 with update of timer 1 .............................................. 156
Figure 9.77 Triggering timer 2 with Enable of timer 1 .............................................. 156
Figure 9.78 Triggering timer 1 and 2 with timer 1 TI1 input ..................................... 158
Figure 9.79 Block Diagram ....................................................................................... 200
Figure 9.80 Basic Usage Flow – I2S as Transmitter ............................................... 212
Figure 9.81 Basic Usage Flow – I2S_RX as Receiver ............................................ 216
Figure 9.82 Audio Block Diagram ............................................................................. 227
Figure 9.83 Master/Slave and Transmitter/Receiver Relationships......................... 234
Figure 9.84 Data Transfer on The I2C Bus .............................................................. 235
Figure 9.85 START and STOP Condition ................................................................. 236
Figure 9.86 7-bit Address Format ............................................................................. 237
Figure 9.87 10-bit Address Format........................................................................... 237
Figure 9.88 Master-Transmitter Protocol ................................................................. 238
Figure 9.89 Master-Receiver Protocol ..................................................................... 239
Figure 9.90 START BYTE Transfer .......................................................................... 239
Figure 9.91 Multiple Master Arbitration .................................................................... 240
Figure 9.92 Multi-Master Clock Synchronization ..................................................... 241
Figure 9.93 I2C Master Implementing tHD;.............................................................. 248
Figure 9.94 Timing Diagram for Program Mode....................................................... 262
Figure 9.95 Timing Diagram for Read Mode ............................................................ 263
Figure 9.96 Timing Change ...................................................................................... 264
Figure 9.97 Signal Frame ......................................................................................... 269
Figure 9.98 PWM Output Waveform Chart .............................................................. 269
Figure 9.99 IR Mode ................................................................................................. 270
Figure 9.100 IR Format Examples ........................................................................... 271
Figure 9.101 BLOCK Diagram of Analog ................................................................. 274
Figure 10.1 RF Block Diagram ................................................................................. 280
Figure 10.2 OM6621Ex BT Baseband ..................................................................... 281
Figure 11.1 OM6621EM Circuit Diagram ................................................................. 284
Figure 11.2 OM6621ED Circuit Diagram.................................................................. 285
Figure 11.3 OM6621EG Circuit Diagram ................................................................. 286
Figure 12.1 OM6621EM QFN32 package................................................................ 287
Figure 12.2 OM6621ED QFN24 package ................................................................ 288
Figure 14.1 OM6621Ex Tape Orientation................................................................. 292
Figure 14.2 OM6621EM/ED Tape and Reel Dimensions ........................................ 292
Figure 14.3 OM6621EG Tape and Reel Dimensions ............................................... 294
Table 2.1 OM6621Ex pin definition ............................................................................ 15
Table 3.1 The MCU interrupt vector ........................................................................... 17
Table 3.2 OM6621Ex Absolute Maximum Ratings ..................................................... 17
Table 3.3 OM6621Ex Recommend Operating Conditions ......................................... 18
Table 3.4 ESD Characteristic ..................................................................................... 18
Table 3.5 Module Address Mapping ........................................................................... 19
Table 5.1 OM6621EM DC-DC Converter Specifications ........................................... 23
Table 5.2 Digital Core LDO Specifications ................................................................. 23
Table 5.3 POR/BOD Specifications ............................................................................ 23
Table 5.4 Sleep Current .............................................................................................. 24
Table 5.5 CPU Running Current ................................................................................. 24
Table 5.6 Radio Transmitting/Receiving Current........................................................ 24
Table 6.1 A Protocol Engine Packet with Payload (0-32 bytes) ................................. 26
Table 6.2 Packet Control Field (PCF)......................................................................... 27
Table 9.1 Peripheral PINMUX .................................................................................... 45
Table 9.2 Format of Linked List Descriptor ................................................................ 49
Table 9.3 Electrical Specification ................................................................................ 72
Table 9.4 Detection of SCLK values for narrow pulses is not allowed....................... 81
Table 9.5 Counting direction versus encoder signals .............................................. 148
Table 9.6 Output control bits for complementary OCx and OCxN channels ........... 178
Table 9.7 GPADC Specifications .............................................................................. 201
Table 9.8 Electrical Specification .............................................................................. 227
Table 9.9 I2C Definition of Bits in First Byte ............................................................. 237
Table 9.10 ic_clk in Relation to High and Low Counts ............................................. 247
Table 9.11 Typical Parameter Configuration ............................................................ 262
Table 9.12 Timing Diagram for Program Mode ........................................................ 263
Table 9.13 ACDD/DVDD Timing ............................................................................... 264
Table 10.1 OM6621Ex BLE Receiver Architecture .................................................. 282
Table 10.2 OM6621Ex BLE Transceiver Architecture ............................................. 283
Table 12.1 OM6621EM QFN32 package ................................................................. 287
Table 12.2 OM6621ED QFN24 package.................................................................. 289
Table 13.1 OM6621Ex Ordering Information ........................................................... 291
Table 14.1 OM6621EM/ED Common Size ............................................................... 293
Table 14.2 OM6621EM/ED Bag Size........................................................................ 293
Table 14.3 OM6621EG Common Size...................................................................... 294
Table 14.4 OM6621EG Bag Size .............................................................................. 294
Table 15.1 Glossary and Abbreviations .................................................................... 295
Version History
Version Revision Date Author Reviewer
V1.0 Initial version 2023/01/30 Zhuj
V1.1 Update the flash register description 2023/01/31 Zhuj
V1.2 Add the Audio Electrical Specification 2023/02/02 Zhuj
Update the IR_TX register and APB
V1.3 2023/02/14 Zhuj
memory map description
V1.4 Add the circuit diagram 2023/02/23 Zhuj
V1.5 Update the company logo 2023/02/23 Zhuj
V1.6 Update the ADC channel description 2023/03/03 Zhuj
Update the current consumption
V1.7 2023/03/13 Zhuj
description
Add the current description of the
V1.8 2023/03/14 Zhuj
different sleep modes in chapter 1.2
Add special instruction for GPIO19 in
V1.9 2023/03/29 Zhuj
chapter 2.2
Update the UART1 TX and RX FIFO
V2.0 2023/05/09 Zhuj
depth description
V2.1 Update Table 3.3 description 2023/05/31 Zhuj
V2.2 Update PINMUX register description 2023/06/07 Zhuj
V2.3 Add the OM6621ED description 2023/06/27 Zhuj
Add the OM6621ED doesn’t support
V2.4 DCDC mode description 2023/07/24 Zhuj
Update the flash size of OM6621ED
V2.5 Update the description of timer 2023/08/07 Zhuj
Update the description of timer in
V2.6 2023/08/22 Zhuj
chapter 6.7
V2.7 Delete the description of mesh 2023/08/26 Zhuj
Update the package information
description
V2.8 2023/09/13 Zhuj
Add the sensitivity description of
special frequency
Add the description of 2.4G RF, clock
V2.9 2023/09/19 Zhuj
and WDT
V3.0 Update the description of clock feature 2023/09/21 Zhuj
V3.1 Update the table 5.1 2024/01/18 Sdw
V3.2 Add the OM6621EG description 2024/02/06 Sdw
1. OM6621Ex Overview
1.1. Description
The OM6621Ex is a power-optimized true system-on-chip (SOC) solution for both

Bluetooth low energy and proprietary 2.4GHz applications. It integrates a high performance
and low power RF transceiver with Bluetooth base band and rich peripheral IO extension.
OM6621Ex also integrates power management unit (PMU) to provide high-efficient power
management. It targets 2.4GHz Bluetooth low energy systems, proprietary 2.4GHz
systems, Human-Interface Devices (keyboard, mouse, and remote control), sports and
leisure equipment, mobile phone accessories and consumer electronics.
OM6621Ex on-chip Bluetooth system compliant with version 5.1, supports all Bluetooth
standard 4.2 feature.
The chip integrates up to 64MHz high-performance MCU, DMA, GPIO, SPI, UART, Timer,
Watchdog, supports 32MHz external crystal, integrates multi-purpose max 12-bit ADC.
The OM6621Ex integrates on chip 40K SRAM, 256-bit EFUSE and supports user defined
IDE system on chip SFLASH MCU development and JTAG software upgrade.
1.2. Features
• RF transceiver
• -97dBm sensitivity @ 1Mbps GFSK
• -94dBm sensitivity @ 2Mbps GFSK
• TX Power -20 to +7dBm
• AGC (Auto Gain Control)
• RSSI (1dB Resolution)
• CPU
• ARM® Cortex™-M4, max 64MHz
• SWD interface
• Memory
• EFUSE: 256-bit
• SRAM: 40KB
• Serial Flash
• OM6621EM/EG: 512KB
• OM6621ED: 256KB
• I-Cache RAM: 4KB
• Clocks
• 32MHz crystal, 32MHz RC, 32KHz RC
• Link Controller
• BT 5.1 LE PHY, link controller
• Proprietary 2.4-GHz link controller
• Power Management
• Single power supply voltage: 1.8V ~ 3.6V
• 4.9mA peak current in RX
• 4.9mA peak current in TX (0dBm)
• 1.2uA in sleep mode (no RAM retention, wakeup by GPIO)
• 1.8uA in sleep mode (with 40K RAM retention, wakeup by GPIO)
• 2.9uA in sleep mode (with 40K RAM retention, RC32K on)
• Integrated DCDC BUCK Converter(for OM6621EM only)
• Software
• Compliant with BLE version 5.1
• Supported data rates: 1Mbps, 2Mbps
• Sample applications and profiles
• Supports OTA
• Peripherals
• OM6621EM: up to 23 General Purpose I/O
• OM6621ED: up to 16 General Purpose I/O
• OM6621EG: up to 37 general purpose I/O
• 4 x DMA
• 2 x UART
• 1 x I2S interface
• 1 x I2C interface
• QSPI Flash Controller
• 1 x 16-bit Advanced Timer,1 x 16-bit 1 channel PWM Timer,1 x 16-bit 4 channels
PWM Timer
• Watchdog
• 8 channel single-end max 12-bit GPADC, up to 500Ksps (precision and sample
rate can be configured)
• Audio ADC
• 16-bit ADC
• support PDM, IIS
• SNR 93dB (A-weighted)
• 1 x DMIC (Digital Mic)
• 1 x AMIC (Analog Mic)
• Embedded IR Transmitter and Receiver
• Security
• AES HW encryption (Integrated in the Bluetooth module)
• Support AES-128 key
• Support encryption mode
• HW Random Number Generator
• Package and Work Environment
• OM6621EM: 32-pin 4x4mm, 0.4mm pitch QFN32OM6621ED: 24-pin 4x4mm,
0.5mm pitch QFN24
• OM6621EG: 48-pin 6x6mm, 0.4mm pitch QFN48
• -40 ℃ ~ +85 ℃
1.3. System Function Block Diagram
OM6621Ex is a low power Bluetooth wireless transceiver chip. The chip integrates
Bluetooth base band, PHY and proprietary 2.4GHz protocol. The MCU accesses system
hardware resource by AHB bus, RAM, DMA, SFLASH, GPIO exchange data through AHB
bus, and all other peripheral is accessed through AHB to APB Bridge and APB bus.
I-Cache RAM 4KB XTAL

2-WAY ASSOCIATIVE BOR & POR
32MHz
CACHE CO NTROLLER PMU
BUCK DCDC
RC RC
32KHz 32MHz
Retention LDO
Clocking
RADIO & Analog LDOs
SWD Cortex M4
EFUSE
RAM
MAC Radio
(BLE5.1) Transceiver
(AES-128 CCM) 2.4GHz
APB
AHB
UART TIMER
QUAD-SPI I2S WATCHDOG

DMA
FLASH CTRL
I2C
TIMERS
GPADC
Audio ADC
DMA
PERIPHERALS
CONTROLLER
4 CHANNELS
GPIO MULTIPLEXING
Figure 1.1 OM6621Ex block diagram
1.4. Applications
The OM6621Ex integrated circuit has a fully integrated radio transceiver and base band
processor for Bluetooth® Smart. It can be used as an application processor as well as a
data pump in fully hosted systems.
OM6621E
Figure 1.2 OM6621Ex applications
2. Pinout
2.1. OM6621EM
The OM6621EM is a 4mmx4mm QFN32 package. The chip pin definition is as below:
GPIO00/SWCLK
GPIO01/SWDIO
VDD1P2
GPIO20
GPIO18
GPIO17
GPIO19
DVDD
32
30
28
27
26
25
31
29
GPIO21 1 24 SW
GPIO22 2 23 VBAT
XTAL32M_N 3 22 GPIO16
XTAL32M_P 4 OM6621EM 21 GPIO06/UART_RX

XXXXXXXX
GPIO07 5 XXXXXXX 20 GPIO05/UART_TX
RFP 6 19 GPIO04/BOOT
VDD_AUDIO 7 18 GPIO15
AUREF 8 17 GPIO14
11
13
14
15
16
10
12
9
GPIO10/ADC05/Resetb
GPIO03/MICN/ADC09
GPIO09/ADC04/IR
GPIO11/ADC06
GPIO12/ADC07
GPIO13/ADC02
GPIO08/ADC03
GPIO02/MICP/ADC08
Figure 2.1 OM6621EM chip pin definition

Note: The OM6621EM has a pin in each corner (bottom view). Those pins are connected
to the chip’s EPAD (Pin33) internally.
2.2. OM6621ED
The OM6621ED is a 4mmx4mm QFN24 package. The chip pin definition is as below:
GPIO00/SWCLK
GPIO01/SWDIO
VDD1P2
GPIO17
DVDD
VBAT
24
23
22
20
19
21
GPIO18 1 18 GPIO16
XTAL32M_N 2 17 GPIO06/UART_RX
XTAL32M_P 3 OM6621ED 16 GPIO05/UART_TX

XXXXXXXX
GPIO07 4 XXXXXXX 15 GPIO04/BOOT
RFP 5 14 GPIO15
VDD_AUDIO 6 13 GPIO13/ADC02
10
11
12
9
7
GPIO10/ADC05/Resetb
GPIO03/MICN/ADC09
AUREF
GPIO09/ADC04/IR
GPIO02/MICP/ADC08
GPIO08/ADC03
Figure 2.2 OM6621ED chip pin definition

Note: The OM6621ED has a pin in each corner (bottom view). Those pins are connected
to the chip’s EPAD (Pin25) internally.
2.3. OM6621EG
The OM6621EG is a 6mmx6mm QFN48 package. The chip pin definition is as below:
Figure 2.3 OM6621EG chip pin definition

Note: The OM6621EG has a pin in each corner (bottom view). Those pins are connected
to the chip’s EPAD internally.
2.4. Pin Description
6621E 6621E
Name 6621ED Type Description Note
M G
GPIO21 1 - 2 Digital Digital GPIO Note 1
XTAL32M_N 3 2 4 Analog 32M crystal oscillator N input
XTAL32M_P 4 3 5 Analog 32M crystal oscillator P input
GPIO07 5 4 48 Digital Digital GPIO Note 1
RFP 6 5 7 Analog RF input/output
VDD_AUDIO 7 6 8 Power Power for Microphone
AUREF 8 7 9 Analog Reference voltage for audio
GPIO02/MICP/ Digital/ Digital GPIO/Microphone P input/
9 8 10 Note 1
ADC08 Analog GPADC
GPIO03/MICN/ Digital/ Digital GPIO/Microphone N input/
10 9 11 Note 1
ADC09 Analog GPADC
Resetb/GPIO10/ Digital/ Note 1
11 10 12 Digital GPIO/GPADC input/Resetb
ADC05 Analog /(**)
Digital/
GPIO08/ADC03 12 11 28 Digital GPIO/GPADC input Note 1
Analog
Digital/
GPIO11/ADC06 13 - 29 Digital GPIO/GPADC input Note 1
Analog
Digital/
GPIO12/ADC07 14 - 30 Digital GPIO/GPADC input Note 1
Analog
GPIO09/ADC04/ Digital/
15 12 31 Digital GPIO/GPADC input/IR Note 1
IR Analog
Digital/
GPIO13/ADC02 16 13 32 Digital GPIO/GPADC input Note 1
Analog
GPIO04/BOOT 19 15 35 Digital Digital GPIO/BOOT Note 1
GPIO05/UART_
20 16 36 Digital Digital GPIO/UART_TX Note 1
TX
GPIO06/UART_
21 17 37 Digital Digital GPIO/UART_RX Note 1
RX
VBAT 23 19 39 Power Power supply
DCDC output connected to external
SW 24 - 40 Analog
inductance
Internal LDO generated power supply
DVDD 25 20 41 Analog
for digital core
Internal DCDC generated power
VDD1P2 26 21 42 Power
supply
GPIO00/SWCLK 28 23 44 Digital Digital GPIO/SWCLK Note 1
GPIO01/SWDIO 29 24 45 Digital Digital GPIO/SWDIO Note 1
GPIO44 13 Digital Digital GPIO Note 3
VDD 17 Power Power supply
NC 6 NC NC
Note 1: All digital peripheral pins can be programmed to any GPIO.
Note 2: GPIO19 cannot be used as a wakeup pin.
Note 3：Universal GPIO functions.
Note 4：The pin is an open drain and GPIO mode.
(**): To ensure the Reset function, the pull down time of RSTB pin should be greater than
40us.
Table 2.1 OM6621Ex pin definition
3. MCU Subsystem
OM6621Ex has an MCU subsystem that contains an ARM Cortex-M4 processor, its
corresponding buses and peripherals, including all the multiplexing options for the GPIOs,
as illustrated in the following figure.
The processor has a 32-bit instruction set with Thumb-2 mode support to use a hybrid of
16-bit and 32-bit instructions to maximize the code performance and density.
MCU memories have a special retention voltage and its control to have the memories in
different modes according to the application usage:
• OFF
• ON
• Retention
The following are the supported options for the Cortex-M4:
• System Tick Timer (SysTick)
• Flash Patch and Breakpoint Unit (FPB)
AHB Bus
Watchdog
APB
Cortex M4 bridge
UART
MAC Audio
DMA
I2C
GPIOs SRAM
Timer
Display GPADC
Controller
Flash
Controller
Figure 3.1 Micro-controller Subsystem
3.1. MCU Debug
Serial Wire Debug (SWD) is used for debug.
3.2. Interrupts Vector
The following table shows the MCU interrupt vector table for OM6621Ex.
Number Interrupt name Bit Description
0 BT BB COMBO 1 BLE event
1 BB_NATIVE_INT 1 Baseband sleep wake
2 DMA COMBO 1 DMA interrupt
3 GPIO COMBO 1 GPIO interrupt
4 TIMER COMBO 1 Timer interrupt
5 2P4G_RF_IRQ 1 Proprietary 2.4G protocol interrupt
6 2P4G_RF_SPI_IRQ 1
7 PMU_TIMER 1 System timer
8 IR_INT 1 IR_TX interrupt
9 UART1 COMBO 1 UART1 global interrupt
10 EFUSE_INT 1 EFUSE interrupt
11 PIN_WAKEUP_INT 1 GPIO wakeup interrupt
12 ADC 1 GPADC interrupt
13 I2C_INT 1 I2C interrupt
14 SFLASH0 INT 1 SFLASH0 control interrupt
15~22 SOFT_INT 8 Soft interrupt
24 CRY32M_DIG_READY 1 32M crystal oscillator can give digital flag
25 UART0 INT 1 UART0 interrupt
26 GPIO INT 1 GPIO COMBO
28-30 TIMER 3 Timers global interrupt
31 SFLASH1 INT 1 SFLASH1 control interrupt
32 AUDIO_INT 1 audio interrupt
33 I2S_RX_INT 1 i2s_rx interrupt
34 I2S_TX_INT 1 i2s_tx interrupt
Table 3.1 The MCU interrupt vector
3.3. Electrical Specifications
3.3.1. Absolute Maximum Ratings
Parameter Min Typ Max Unit

Supply voltage (VBAT) -0.3 - 3.9 V
Maximum Junction Temperature -40 - 125 ºC
Storage Temperature -40 - 125 ºC
Table 3.2 OM6621Ex Absolute Maximum Ratings
3.3.2. Recommend Operating Conditions
Rating Min Typ Max Unit

Operation Temperature -40 - 85 ºC
Digital Core supply voltage 0.9 1.0 1.1 V
Supply voltage (VBAT) 1.8 3.3 3.6 V
I/O voltage VBAT VBAT VBAT V
Supply voltage during power on reset 1.9 V
Table 3.3 OM6621Ex Recommend Operating Conditions
3.3.3. ESD Characteristic
Parameter Condition Min Typ Max Unit

Human Body Mode Test method:
- ±4000 - V
(HBM) ESDA/JEDEC JS-001-2017
All pins, test method:
Machine Mode (MM) - ±100 - V
JESD22 -A115C
Charge Device Mode All pins, test method:
- ±1000 - V
(CDM) ESDA/JEDEC JS-002-2018
Table 3.4 ESD Characteristic
3.3.4. SFLASH Controller Characteristic
Spec
Description Symbol Alt Unit
Min Typ Max
Clock frequency except for read
FR D.C. 64 MHz
data(3.3V)
3.4. Module Address Mapping
Base Address Module

0x40000000 SYS_REG
0x40001000 CPM
0x40002000 EFUSE
0x40004000 RNG
0x4000B000 2.4G_RF
0x40020000 BT_PHY
0x40040000 UART1
0x40050000 AUDIO
0x40070000 I2C
0x40080000 UART0
0x400A0000 DA_IF
0x400C0000 TIMER
0x400E0000 PMU
0x400F0000 IR_TX
0x41100000 DMA
0x41200000 GPIO0
0x41400000 I2S_TX
0x41500000 I2S_RX
0x51000000 SFLASH0
0x53000000 SFLASH1
Table 3.5 Module Address Mapping
4. Memory
4.1. Memory Introduction
OM6621Ex SOC memory includes SRAM and stacked flash for code and data storage.
The CPU and peripheral devices can access the memory. The CPU can access the
peripherals as well. The address mapping of the memories and devices are explained in
the following sections.
4.2. Memory Map
0x400FFFFF
Device
0x40000000
0x2000A000 SRAM
0x20000000 (40KB)
0x00800000
FLASH
0x00400000
Figure 4.1 Memory Map
4.3. APB Address Space
The following figure shows the details of Advanced Peripheral Bus (APB) portion of the
memory map.
0x40000FFF
0x40000000 SYS_REG
0x4002FFFF 0x40001FFF
0x40000000 0x40001000 CPM
0x4004FFFF 0x40002FFF
0x40040000 UART1 EFUSE
0x40002000
0x4005FFFF Audio
0x40050000 0x40007FFF RNG
0x40004000
0x4007FFFF I2C
0x40070000 0x4000BFFF 2P4G_RF
0x4008FFFF 0x4000B000
0x40080000 UART0 0x4002FFFF
0x400AFFFF 0x40020000 BT_PHY
0x400A0000 DA_IF
0x400CFFFF Timer
0x400C0000
0x400EFFFF PMU
0x400E0000
0x400FFFFF IR_TX
0x400F0000
0x411FFFFF DMA
0x41100000
0x412FFFFF GPIO0
0x41200000
0x414FFFFF I2S_TX
0x41400000
0x415FFFFF I2S_RX
0x41500000
0x51FFFFFF SFLASH0
0x51000000
0x53FFFFFF SFLASH1
0x53000000
Figure 4.2 APB Memory Map
5. PMU
5.1. Power Management
Figure 5.1 DC-DC Mode
Figure 5.2 LDO Mode
Power management Unit (PMU) provide variable voltages and current bias for different
blocks of OM6621Ex, and realize the power on/off function.
The system contains one main supply regulator stage, which has the options of
Low-dropout regulator (LDO) and Buck regulator (DC/DC).
When the DC/DC converter is enabled, the corresponding LDO regulator is disabled.
External LC filter must be connected for the DC/DC regulator if it is being used. The
advantage of using a DC/DC regulator is that the overall power consumption is normally
reduced as the efficiency of such a regulator is higher than that of LDO. The efficiency
gained by using a DC/DC regulator is best seen when the regulator voltage drops
(difference between input and output voltage) is high. The efficiency of internal regulators
varies with the supply voltage and the current drawn from the regulators.
5.2. DC-DC Converter
Symbol Description Min Typ Max Unit

VDCDC Output Voltage 1.1 1.25 1.45 V
ILOAD Load Current - - 50 mA
TSTARTUP Startup Time - - 300 us
1
VRIPP Voltage Ripples - 10 - mV
2
EFF Efficiency - 90 - %
LDCDC External inductance 2.2 4.7 10 uH
CLOAD External Load Capacitor 2.2 4.7 10 µF
Table 5.1 OM6621EM DC-DC Converter Specifications
Note1: Using 10uH inductance and 4.7uF Capacitor.
Note2: Loading current is 10mA.
5.3. Digital LDO
Digital LDO regulates the supply power to all the Digital Logic and Memory blocks.
Parameter Symbol Min Typ Max Unit
Input Voltage VIN 1.8 3.3 3.6 V
Output Voltage VOUT 0.9 1.0 1.1 V
External Load Capacitor CLOAD 1.0 µF
Table 5.2 Digital Core LDO Specifications
5.4. POR/BOD
Power-on Reset (POR) circuit holds the system at reset while the supply reaches the
required voltage level. Brown-out detector (BOD) circuit puts the system into reset state
when the supply falls below the Brown-out Threshold.
Parameter Symbol Min Typ Max Unit Comment
Brown Out Threshold 1.67 V
Table 5.3 POR/BOD Specifications
5.5. Current Consumption
A set of current consumption scenarios are provided to show the typical current drawn from
VBAT supply. Each scenario specifies a set of operations and conditions applying to the
given scenario.
5.5.1. Sleep

ISLEEP_RAMOFF_GPIO No RAM retention, wakeup by GPIO 1.2 uA
ISLEEP_RAMON_GPIO 40K RAM retention, wakeup by GPIO 1.8 uA
40K RAM retention, wakeup by
ISLEEP_RAMON_RC32K 2.9 uA
RC32K
Table 5.4 Sleep Current
5.5.2. CPU Running

ICPU0_32M CPU running Coremark@32MHz from Flash 1.36 mA
ICPU1_32M CPU running Coremark@32MHz from RAM 1.32 mA
ICPU0_64M CPU running Coremark@64MHz from Flash 2.34 mA
ICPU1_64M CPU running Coremark@64MHz from RAM 2.26 mA
Table 5.5 CPU Running Current
5.5.3. Radio Transmitting/Receiving

IRADIO_TX0 Radio transmitting@7dbm output power, 1Mbps 9.2 mA
IRADIO_TX1 Radio transmitting@0dbm output power, 1Mbps 4.9 mA
IRADIO_RX0 Radio receiving, 1Mbps 4.9 mA
Table 5.6 Radio Transmitting/Receiving Current
6. 2.4G RF Transceiver
Features of the OM6621E include:

• Radio
• Worldwide 2.4GHz ISM band operation
• Common RX and TX interface
• GFSK modulation
• 1 and 2Mbps air data rate
• 1MHz non-overlapping channel spacing at 1Mbps
• 2MHz non-overlapping channel spacing at 2Mbps
• Protocol engine
• 1 to 32 bytes dynamic payload length
• Automatic packet handling
• Auto packet transaction handling
• 6 data pipe for 1:6 star networks
6.1. Block Diagram
Figure 6.1 OM6621E block diagram
6.2. Function Description
6.2.1. Air Interface Data Rate
The air data rate is the modulated signaling rate the chip uses when transmitting and
receiving data. It can be 500kbps, 1Mbps or 2Mbps. Using lower air data rate gives better
receiver sensitivity than higher air data rate. But, high air data rate gives lower average
current consumption and reduced probability of on-air collisions. The air data rate is set by
the RF_DR bit in the RF_SETUP register. A transmitter and a receiver must be
programmed with the same air data rate to communicate with each other.
6.2.2. RF Channel Frequency
The RF channel frequency determines the center of the channel used by the chip. The
channel occupies a bandwidth of less than 1MHz at 500kbps and 1Mbps and a bandwidth
of less than 2MHz at 2Mbps. The chip can operate on frequencies from 2.400GHz to
2.525GHz. The programming resolution of the RF channel frequency setting is 1MHz.
At 2Mbps the channel occupies a bandwidth wider than the resolution of the RF channel
frequency setting. To ensure non-overlapping channels in 2Mbps mode, the channel
spacing must be 2MHz or more. At 1Mbps, the channel bandwidth is the same or lower
than the resolution of the RF frequency.
The RF channel frequency is set by the RF_CH register according to the following formula:
F0= 2400 + RF_CH [MHz]
User must program a transmitter and a receiver with the same RF channel frequency to
communicate with each other.
6.3. Baseband
6.3.1. Packet Format
The format of the Protocol engine packet is described in this section. The Protocol engine
packet contains a preamble field, address field, packet control field, payload field and a
CRC field. The following table shows the packet format with MSB to the left.
Preamble Address 4- 2-byte Packet control field Payload CRC
1-byte 5 byte guard 9-bit 0-32 bytes 1-2 bytes
Table 6.1 A Protocol Engine Packet with Payload (0-32 bytes)
6.3.1.1. Preamble
The preamble is a bit sequence used to synchronize the receiver demodulator to the
incoming bit stream. The preamble is one byte long and is either 01010101 or 10101010.
If the first bit in the address is 1 the preamble is automatically set to 10101010 and if the
first bit is 0 the preamble is automatically set to 01010101. This is done to ensure there are
enough transitions in the preamble to stabilize the receiver.
6.3.1.2. Address
This is the address for the receiver. An address ensures that the packet is detected and
received by the correct receiver, preventing accidental cross talk between multiple
OM6621E systems. User can configure the address field width in the AW register to be 5
bytes or 4 bytes address.
6.3.1.3. Guard
The above table shows the format of the 2-byte guard packet has better synchronous
characteristics.
6.3.1.4. Packet Control Field (PCF)
The following table shows the format of the 9-bit packet control field, MSB to the left.
Payload length 6-bit PID 2-bit NO_ACK 1-bit
Table 6.2 Packet Control Field (PCF)
The packet control field contains a 6-bit payload length field, a 2-bit PID (Packet Identity)
field and a 1-bit NO_ACK flag.
• Payload Length
This 6-bit field specifies the length of the payload in bytes. The length of the payload can
be from 0 to 32-byte.
Coding: 000000 = 0-byte (only used in empty ACK packets. The 0-length packet also need
to be read out use R_RX_PAYLOAD with no data following) 100000 = 32-byte, 100001 =
Don’t care.
This field is only used if the Dynamic Payload Length function is enabled.
• PID (Packet identification)
The 2-bit PID field is used to detect if the received packet is new or re-transmitted. PID
prevents the PRX operation from presenting the same payload more than once to the MCU.
The PID field is incremented at the TX side for each new packet received through the SPI.
The PID and CRC field are used by the PRX operation to determine if a packet is re-
transmitted or new. When several data packets are lost on the link, the PID fields may
become equal to the last received PID. If a packet has the same PID as the previous packet,
the RF transceiver compares the CRC sums from both packets. If the CRC sums are also
equal, the last received packet is considered a copy of the previously received packet and
discarded.
• No Acknowledgment Flag (NO_ACK)
The Selective Auto Acknowledgement feature controls the NO_ACK flag.
This flag is only used when the auto acknowledgement feature is used. Setting the flag
high, tells the receiver that the packet is not to be auto acknowledged.
On the PTX you can set the NO_ACK flag bit in the Packet Control Field with this command:
W_TX_PAYLOAD_NOACK
However, the function must first be enabled in the FEATURE register by setting the
EN_DYN_ACK bit. When you use this option, the PTX goes directly to standby-I mode
after transmitting the packet. The PRX does not transmit an ACK packet when it receives
the packet.
6.3.1.5. Payload
The payload is the user defined content of the packet. It can be 0 to 32 bytes wide and is
transmitted on-air when it is uploaded to the device.
Protocol engine provides two alternatives for handling payload lengths; static and dynamic.
The default is static payload length. With static payload length all packets between a
transmitter and a receiver have the same length. Static payload length is set by the
RX_PW_Px registers on the receiver side. The payload length on the transmitter side is
set by the number of bytes clocked into the TX_FIFO and must equal the value in the
RX_PW_Px register on the receiver side.
Dynamic Payload Length (DPL) is an alternative to static payload length. DPL enables the
transmitter to send packets with variable payload length to the receiver. This means that
for a system with different payload lengths it is not necessary to scale the packet length to
the longest payload.
With the DPL feature the OM6621E can decode the payload length of the received packet
automatically instead of using the RX_PW_Px registers. The MCU can read the length of
the received payload by using the R_RX_PL_WID command.
Note: Always check if the packet width reported is 32 bytes or shorter when using the
R_RX_PL_WID command. If its width is longer than 32 bytes then the packet contains
errors and must be discarded. Discard the packet by using the Flush_RX command.
In order to enable DPL the EN_DPL bit in the FEATURE register must be enabled. In RX
mode the DYNPD register must be set. A PTX that transmits to a PRX with DPL enabled
must have the DPL_P0 bit in DYNPD set.
6.3.1.6. CRC (Cyclic Redundancy Check)
The CRC is the error detection mechanism in the packet. It may either be 1 or 2 bytes and
is calculated over the address, Packet Control Field and Payload.
The polynomial for 1 byte CRC is X8 + X2 + X + 1. Initial value 0Xff.
The polynomial for 2 bytes CRC is X16 + X12 + X5 + 1. Initial value 0Xffff.
The number of bytes in the CRC is set by the CRCO bit in the CONFIG register. No packet
is accepted by protocol engine if the CRC fails.
7. Watchdog Timer
7.1. Introduction
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interference or by unforeseen logical conditions, which causes the
application program to abandon its normal sequence. The watchdog circuit generates an
system reset on expiry of a programmed time period, unless the program refreshes the
contents of the down counter before the down counter becomes zero. This implies that the
counter must be refreshed in a limited window.
7.2. Main Features
• Programmable free-running downcounter

• Reset (if watchdog activated) when the downcounter value reaches 0x0.
7.3.1. Clock
The clock is connected to the the internal RC32K, RC32K is always open.
7.3.2. Counter
The wdt_timer is 12-bit, the default value is 0xfff, and the count mode is down-counting
mode. When the wdt_timer value is 0, to produce a reset signal. The count clock of
wdt_timer is 256 frequencies division of RC32K, and the count unit of wdt_timer is about
7.8ms (it means that one clock period is 30.72*256 = 7.8ms), and the reset signal width is
also about 7.8ms.
7.4. WDT Register Map
Offset Register Description

0x00bc WDT_RLR_CFG Reset period register
0x0094 WDT_STATUS WDT status register
0x00e8 WDT_KR_CFG WDT key value register
WDT_RLR_CFG in the pmu_hib_spi register, offset address:0x00bc
Bit R/W Reset Name Description
31:12 N/A N/A RESERVED Reserved
11:0 RW 0xfff WDT_RLR Reset period register
WDT_STATUS address offset: 0x0094

27:16 R 0xfff WDT_TIMER The current value of the WDT counter
4 R 0x0 WDT_FLAG WDT reset flag
wdt_flag=1 indicates that the WDT
reset has occurred, write any value to
WDT_STATUS to clear wdt_flag
0 R 0x0 LD_WDT_KR key register configuration status
WDT_KR_CFG address offset: 0x00e8

15:0 RW 0x0 WDT_KR WDT key value register
It will be clear to 0 when writing to value
that is not 0x6666
8. Clock
8.1. Introduction
The CPM (Clock Process Manager) is responsible for switching among various oscillator
sources and provides clocks to the peripheral modules. Oscillators are automatically turned
on and off based on demand from the peripherals to minimize power consumption.
8.2. Features
• Multiple clock sources available:

• 32 MHz High Frequency Crystal Oscillator
• 32 MHz High Frequency RC Oscillator
• 32.768 kHz Low Frequency RC Oscillator with Precision Mode
• Fast start-up times.
• Cascaded prescalers for AHB Clocks (HCLK) and APB Clocks (PCLK).
• Clock gating on an individual basis to most peripherals based on module enable.
• Hardware support for calibration of RC oscillators.
The CPM is comprised of several programmable clock trees, which connect oscillator
resources to peripherals and buses. This section describes clock sources and peripherals
available to the largest devices in the OM6621Ex family.
8.3.1. System Clocks
8.3.1.1. SYSCLK - SYS_CLK
rc_32m rc_32m
X2 clk_64m
main_clk
xtal_32m sys_clk
xtal_32m
sel_rc_osc main_clk_sel
sel_cpuclk
Figure 8.1 main_clk

As the figure shown above, the clocking scheme of OM6621Ex. by default, OM6621Ex
clocks are generated using a crystal oscillator (XO) that requires a 32 MHz external crystal.
The external crystal is needed to meet the offset requirements of the BLE specifications.
sys_clk is the selected system clock. HCLK and PCLK are both the same frequency with
cpu_clk. The cpu_clk, and therefore HCLK and PCLK, be driven by the main_clk. By default,
the main_clk is selected xtal_32m-. To change the selected clock source, write to the
sel_cpuclk bitfield in XTAL32M_CNS0.
The multiplier setting can be changed dynamically and the new setting takes effect with
updated.
scan_muxed_clk scan_muxed_48m_clk_gate
MUX ICG
rng_48m_clk
main_gated_clk
ICG
sf*_clk
timer*_clk
main_clk_en *_clk_pre_gate *_div_clk *_sel_clk
ICG DIV SYN MUX uart*_clk
i2c*_clk
main_clk cpu*_tclk
gpio_clk sf*_apb_clk
cpu_div_clk main_sel_clk main_scan_muxed_clk
DIV SYN MUX ICG ahb_clk_ram spi_2_ahb_clk
ahb_clk_periph dma_clk
cpu_clk_g
ICG ahb_clk_g rom_clk
ahb2_clk
ICG ram*_clk
apb_clk cpm_apb_clk_g timer*_apb_clk phy_apb_clk

ICG
ana_if_ahb_clk uart*_apb_clk rng_apb_clk
audio_apb_clk i2c*_apb_clk hs6200_apb_clk
pmu_apb_clk rom_apb_clk pso_apb_clk
rtc_apb_clk pmu_hib_apb_clk kpp_apb_clk
i2s_tx_ahb_clk
ahb_clk
ICG i2s_rx_ahb_clk
pic_dec_clk
Figure 8.2 System clocks
8.3.1.2. HCLK - AHB_CLK
HCLK is a prescaled version of main_gated_clk. This clock drives the AHB bus interface.
Example modules include the CPU, I2S, Bus Matrix, RAM, DMA and GPIO. HCLK can be
prescaled by setting *div_coeff as CPM register map to DIV2 or DIV4. This prescales HCLK
to all AHB bus clocks and is typically used to save energy in applications where the system
is not required to run at the higher frequency. The setting can be changed dynamically and
the new setting takes effect immediately. But will be generate glitch, so if you want to use
lower frequency, it best to use cpu_div_sel to change the source to main_gated_clk, and
then config the cpu_div_clk as wanted, invert the cpu_div_sel back to cpu_div_clk while
the new setting takes effect. Some of the modules that are driven by this clock can be clock
gated completely when not in use. This is done by clearing the module enable (EN) bit in
the module's EN register.
8.3.1.3. PCLK - APB Clock
PCLK is a prescaled version of main_gated_clk. This clock drives the APB bus interface.
Example modules include TIMER and I2C. PCLK can be prescaled by setting
cpu_div_coeff in CPM register to DIV2. This prescales PCLK to all APB bus clocks and is
need to note then the PCLK will be always the same frequency with HCLK. The setting can
be changed dynamically and the new setting takes effect immediately. This also like HCLK,
if you don’t want a glitch, you should operate like HCLK. Some of the peripherals that are
driven by this clock can be clock gated completely when not in use. This is done by clearing
the module enable (EN) bit in the module's EN register.
8.4. CPM Register Map
Offset Name Description

0x0000 CPM_REV Revision information
0x0004 CPM_CPU_CFG CPU clock config
0x0008 CPM_APB_CFG APB clock config
0x000c CPM_REG_UPD CPM update control
0x0010 CPM_SF_CFG SF clock config
0x0014 CPM_TIMER0_CFG TIMER0 clock config
0x0018 CPM_TIMER1_CFG TIMER1 clock config
0x001c CPM_TIMER2_CFG TIMER2 clock config
0x0020 CPM_UART0_CFG UART0 clock config
0x0024 CPM_UART1_CFG UART1 clock config
0x0028 CPM_I2C_CFG I2C clock config
0x002c CPM_IRTX_CFG IRTX clock config
0x0030 CPM_BLE_CFG BLE clock config
0x0038 CPM_AHB_CFG AHB clock config
0x003c CPM_DMA_CFG DMA clock config
0x0040 CPM_RAM_CFG RAM clock config
0x0044 CPM_AUDIO_CFG AUDIO clock config
0x0048 CPM_GPIO_CFG GPIO clock config
0x004c CPM_PHY_CFG PHY clock config
0x0050 CPM_RNG_CFG RNG clock config
0x0054 CPM_I2S_CFG I2S clock config
0x0058 CPM_STATUS_READ CPM status
0x005c CPM_ANA_IF_APB_CFG ANA_IF apb clock config
0x0060 CPM_HS6200_CFG 2.4G clock config
0x0064 CPM_ANA_IF_CFG ANA_IF clock config
0x0068 CPM_EFUSE_CFG efuse clock config
0x006c CPM_SF1_CFG SF1 clock config
CPM_REV address offset: 0x0000

31:0 R 6621 CPM REVISION cpm revision
_e0a
1
CPM_CPU_CFG address offset: 0x0004
31:24 N/A 0x0 N/A reserved
23 RW 0x1 AHB_CLK_EN_PERIPH Peripheral ahb clock enable
1: enable
22 RW 0x1 AHB_CLK_EN_RAM RAM ahb clock enable
1: enable
21:16 RW 0x0 N/A reserved
15:8 RW 0x2 CPU_DIV_COEFF cpu divider config
0: no frequency division
2 N/A 0x0 CPU_DIV_SEL cpu divider config
0: no frequency division
1 RW 0x1 CPU_DIV_EN cpu clock enable
1: enable
0 RW 0x1 N/A resvered
CPM_APB_CFG address offset: 0x0008

19 RW 0x0 ROM_APB_SOFT_RES ROM apb soft reset:
ET 1: soft reset
18 RW 0x0 PSO_APB_SOFT_RES PSO apb soft reset:
ET 1: soft reset
17 N/A 0x0 N/A reserved
16 RW 0x0 PMU_APB_SOFE_RES PMU apb soft reset:
ET 1: soft reset
3 RW 0x1 ROM_APB_GATE_EN ROM apb clock gate
1: gate
2 RW 0x0 PSO_APB_GATE_EN PSO apb clock gate
1: gate
1 RW 0x0 N/A
0 RW 0x0 PMU_APB_GATE_EN PMU apb clock gate
1: gate
CPM_REG_UPD address offset: 0x000c

6 R 0x0 REG_UPD_32K_STATU update status,
S 1: update is done
5 R 0x0 REG_UPD_24M_STATU update status,
S 1: update is done
4 R 0x0 REG_UPD_48M_STATU update status,
S 1: update is done
3 RW 0x0 REG_UPD_STATUS_CL Clear the status bits [3:1], write 1 to
R clear, self-clear
2 RW 0x0 REG_UPD_32K_APB Write 1 to update shadow reg of
32k clock, self-clear
1 RW 0x0 REG_UPD_24M_APB Write 1 to update shadow reg of
24m clock, self-clear
0 RW 0x0 REG_UPD_48M_APB Write 1 to update shadow reg of
48m clock, self-clear
Note: After setting the clock config of the following modules, bit reg_upd_xxx should be
set, otherwise the setting will not take effect.
Reg_upd_ble_apb: ble module
Reg_upd_peri: timer, i2c, uart
reg_upd_xtal32m: ana_if, hs6200, phy
Other module’s clock config will take effect immediately.
CPM_SF_CFG address offset:0x0010

15:8 RW 0x0 SF_DIV_COEFF sf divider config
4 RW 0x0 SF_SOFT_RESET sf soft reset:
1: reset
2 RW 0x0 SF_DIV_SEL sf divided clock select:
1: divided clock is selected
1 RW 0x0 SF_DIV_EN sf divider enable:
1: enable
0: disable
0 RW 0x0 SF_GATE_EN sf clock gate:
1: gate
0: enable
CPM_TIMERx_CFG address offset:

CPM_TIMER1_CFG: 0x0014
CPM_TIMER2_CFG: 0x0018
CPM_TIMER3_CFG: 0x001c
15:8 RW 0x0 TIMERX_DIV_COEFF TIMERx divider config
4 RW 0x0 TIMERX_SOFT_RESET TIMERx soft reset:
1: reset
2 RW 0x0 TIMERX_DIV_SEL TIMERx divided clock select:
1 RW 0x0 TIMERX_DIV_EN TIMERx divider enable:
1: enable
0: disable
0 RW 0x1 TIMERX_GATE_EN TIMERx clock gate:
1: gate
0: enable
CPM_UART0_CFG address offset: 0x0020

31:5 N/A 0x0 N/A Reserved
4 RW 0x0 UART1_SOFT_RESET UART1 soft reset:
1: reset
0 RW 0x1 UART1_GATE_EN UART1 clock gate:
1: gate
0: enable
CPM_UART1_CFG address offset: 0x0024

31:24 RW 0x40 UART1_DIV_COEFF_F UART1 divider config (fraction part)
RC
16:8 RW 0x156 UART1_DIV_COEFF_IN UART1 divider config (integer part)
T
4 RW 0x0 UART1_SOFT_RESET UART1 soft reset:
1: reset
3 N/A 0x0 N/A Reserved
2 RW 0x1 UART1_DIV_SEL UART1 divided clock select:
1 RW 0x1 UART1_DIV_EN UART1 divider enable:
1: enable
0: disable
0 RW 0x1 UART1_GATE_EN UART1 clock gate:
1: gate
0: enable
CPM_I2C_CFG address offset: 0x0028

15:8 RW 0x0 I2C_DIV_COEFF I2C divider config
4 RW 0x0 I2C_SOFT_RESET I2C soft reset:
1: reset
2 RW 0x0 I2C_DIV_SEL I2C divided clock select:
1 RW 0x0 I2C_DIV_EN I2C divider enable:
1: enable
0: disable
0 RW 0x1 I2C_GATE_EN I2C clock gate:
1: gate
0: enable
CPM_IRTX_CFG address offset: 0x002c

15:8 RW 0x0 IRTX_DIV_COEFF IRTX divider config
4 RW 0x0 IRTX _SOFT_RESET IRTX soft reset:
1: reset
2 RW 0x0 IRTX _DIV_SEL IRTX divided clock select:
1 RW 0x0 IRTX _DIV_EN IRTX divider enable:
1: enable
0: disable
0 RW 0x1 IRTX _GATE_EN IRTX clock gate:
1: gate
0: enable
CPM_BLE_CFG address offset: 0x0030

4 RW 0x0 BLE_SOFT_RESET BLE soft reset:
1: reset
1 RW 0x1 BLE_XTAL_GATE_EN BLE XTAL clock gate:
1:gate
0:enable
0 RW 0x1 BLE_GATE_EN BLE clock gate:
1: gate
0: enable
CPM_AHB_CFG address offset: 0x0038

16 RW 0x0 RAM_AUTO_GATE_EN Ram clock auto gate enable
1: ram clock is auto gate while ram
is not accessed
4 RW 0x0 AHB_SOFT_RESET ahb soft reset,
Write 1 to soft reset, self clear
CPM_DMA_CFG address offset: 0x003C

4 RW 0x0 DMA_SOFT_RESET DMA soft reset:
1: reset
0 RW 0x1 DMA_GATE_EN DMA clock gate:
1: gate
0: enable
CPM_RAM_CFG address offset: 0x0040

31:6 R N/A N/A N/A
3:0 RW 0x0 RAM_GATE_EN RAM clock gate: (ram0 to ram5)
1: gate
0: enable
CPM_AUDIO_CFG address offset: 0x0044

4 RW 0x0 AUDIO_SOFT_RESET AUDIO soft reset:
1: reset
1 RW 0x1 AUDIO_16M_GATE_EN AUDIO 24m clock gate:
1:gate
0:enable
0 RW 0x1 AUDIO_GATE_EN AUDIO clock gate:
1: gate
0: enable
CPM_GPIO_CFG address offset: 0x0048

4 RW 0x0 GPIO_SOFT_RESET GPIO soft reset:
Write 1 to soft reset, self clear
0 RW 0x1 GPIO_GATE_EN GPIO clock gate:
1: gate
0: enable
CPM_PHY_CFG address offset: 0x004C

4 RW 0x0 PHY_SOFT_RESET PHY soft reset:
1: reset
1 RW 0x1 PHY_16M_GATE_EN PHY 16mHz clock gate:
1: gate
0: enable
0 RW 0x1 PHY_APB_GATE_EN PHY apb clock gate:
1: gate
0: enable
CPM_RNG_CFG address offset: 0x0050

4 RW 0x0 RNG_SOFT_RESET RNG soft reset:
1: reset
0 RW 0x1 RNG_GATE_EN RNG clock gate:
1: gate
0: enable
CPM_I2S_CFG address offset: 0x54

7 RW 0x0 I2S_SLV_SEL i2s_rxclk sel command：
1: i2s_txclk_mux,
0: i2s_rxclk_mux
6 RW 0x0 I2S_EXT_INV i2s clk reverse
1: i2s_rxclk_slv_mux =
~i2s_rxclk_slv
i2s_txclk_slv_mux =
~i2s_txclk_slv
0: i2s_rxclk_slv_mux =
i2s_rxclk_slv
i2s_txclk_slv_mux =
i2s_txclk_slv
5 RW 0x0 I2S_TX_SOFT_SEL I2S TX soft reset: self clear
1: reset
4 RW 0x0 I2S_RX_SOFT_SEL I2S RX soft reset: self clear
1: reset
1 RW 0x0 I2S_TX_AHB_EN 1: i2s_tx ahb_clk enable
0 RW 0x0 I2S_RX_AHB_EN 1: i2s_rx ahb_clk enable
CPM_STATUS_READ address offset: 0x0058

12 R 0x0 CPU_TCLK_SYNC_DO cpu_tclk sync done flag:
NE 1: done
11:8 R 0x0 N/A N/A
7 R 0x0 I2C_CLK_SYNC_DONE i2c clock sync done flag:
1: done
6 R 0x0 UART1_CLK_SYNC_D uart1 clock sync done flag:
ONE 1: done
5 R 0x0 IRTX_CLK_SYNC_DON irtx clock sync done flag:
E 1: done
4 R 0x0 TIMER3_CLK_SYNC_D timer3 clock sync done flag:
ONE 1: done
ONE 1: done
ONE 1: done
1 R 0x0 SF_CLK_SYNC_DONE sflash clock sync done flag:
1: done
0 R 0x0 MAIN_CLK_SYNC_DON main clock sync done flag:
E 1: done
CPM_ANA_IF_APB_CFG address offset: 0x005c

4 RW 0x0 ANA_IF_AHB_SOFT_R ana_if ahb soft reset:
ESET 1: reset
0 RW 0x1 ANA_IF_AHB_GATE_E ana_if ahb clock gate:
N 1: gate
0: enable
CPM_HS6200_CFG address offset: 0x0060

4 RW 0x0 HS6200_SOFT_RESET hs6200 soft reset:
1: reset
0 RW 0x1 HS6200_GATE_EN hs6200 clock gate:
1: gate
0: enable
CPM_ANA_IF_CFG address offset: 0x64

0 RW 0x1 ANA_IF_GATE_EN ana_if clock gate:
1: gate
0: enable
CPM_EFUSE_CFG address offset: 0x0068

4 RW 0x0 EFUSE_SOFT_RESET hs6200 soft reset:
1: reset
0 RW 0x1 EFUSE_GATE_EN hs6200 clock gate:
1: gate
0: enable
CPM_SF1_CFG address offset:0x006C

15:8 RW 0x0 SF1_DIV_COEFF Sf1 divider config
4 RW 0x0 SF1_SOFT_RESET Sf1 soft reset:
1: reset
2 RW 0x0 SF1_DIV_SEL Sf1 divided clock select:
1 RW 0x0 SF1_DIV_EN Sf1 divider enable:
1: enable
0: disable
0 RW 0x0 SF1_GATE_EN Sf1 clock gate:
1: gate
0: enable
9. Peripherals
9.1. PINMUX
9.1.1. Introduction
OM6621Ex has a configurable pin multiplexing module (PINMUX) which can bring different
peripherals on different GPIOs.
9.1.2. Main Features
PINMUX has the following features:

• There are many choices (except GPADC) for the Peripheral PINMUX.
• Peripheral PINMUX can be config by REG_GPIOX_MUX.
• Peripheral PINMUX can be configured as UART, I2C, SPI, GPIO, I2S, Timer, Audio,
sFlash and sFlash LCD.
9.1.3. Function Description
The pin multiplexing choices for all pads are shown in the following table.
There are more mux choices for the PINMUX. When you pick a mux choice for an interface,
make sure that all signal of the interface should be configured to the picked mux choice.
The following PINMUX tables set the signals of an interface.
Name Number
PINMUX_JTAG_MODE_CFG 0
PINMUX_DBG_MODE_CFG 1
PINMUX_I2C_SCK_CFG 2
PINMUX_I2C_SDA _CFG 3
PINMUX_UART0_SDA _O_CFG 4
PINMUX_UART0_SDA_I_CFG 5
PINMUX_SFLASH_1_SI_CFG 8
PINMUX_SFLASH_1_SO_CFG 9
PINMUX_SFLASH_1_HD_CFG 10
PINMUX_SFLASH_1_WP_CFG 11
PINMUX_SFLASH_1_CK_CFG 12
PINMUX_SFLASH_1_CSN_CFG 13
PINMUX_UART1_SDA_I_CFG 15
PINMUX_UART1_SDA_O_CFG 16
PINMUX_UART1_CTS_I_N_CFG 17
PINMUX_UART1_RTS_O_N_CFG 18
PINMUX_TX_EXT_PD_CFG 19
PINMUX_RX_EXT_PD_CFG 20
PINMUX_DMIC_IN_CFG 26
PINMUX_DMIC_CLK_CFG 27
PINMUX_GPIO_MODE_CFG 28
PINMUX_SFLASH_LCD_CSN_1_CFG 24
PINMUX_SFLASH_LCD_SI_CFG 25
PINMUX_SFLASH_LCD_SO_CFG 29
PINMUX_SFLASH_LCD_HD_CFG 30
PINMUX_SFLASH_LCD_WP_CFG 31
PINMUX_SFLASH_LCD_CK_CFG 32
PINMUX_SFLASH_LCD_CSN_CFG 33
PINMUX_TIMER0_ETR_CFG 34
PINMUX_TIMER0_BKIN_CFG 37
PINMUX_TIMER0_IO_0_CFG 40
PINMUX_TIMER0_TOGGLE_N_0_CFG 44
PINMUX_ TIMER2_TOGGLE_N_1_CFG 59
PINMUX_ TIMER2_TOGGLE_N_2_CFG 60
PINMUX_I2S_SDI_CFG 61
PINMUX_I2S_TX_WS_CFG 62
PINMUX_I2S_TX_SCLK_CFG 63
PINMUX_I2S_SDO_0_CFG 64
PINMUX_I2S_RX_WS_CFG 66
PINMUX_I2S_RX_SCLK_CFG 67
Table 9.1 Peripheral PINMUX
9.1.4. PINMUX Register Map
Address Name Description

0X40000080 PIN_MUX_CTRL_1 PINMUX control
0X4000008C PIN_MUX_CTRL_4 PINMUX control
PIN_MUX_CTRL_1 address: 0x40000080

30:24 RW 0x0 GPIO3_MUX_REG gpio3 mux config


PIN_MUX_CTRL_4 address: 0x4000008C

29:24 RW 0x1c GPIO15_MUX_REG gpio15 mux config


9.2. DMA
9.2.1. Introduction
DMA is a direct memory access controller which transfers regions of data efficiently on bus.
• Compliant with AMBA™ 2 AHB protocol specification.

• Supports up to 4 DMA channels.
• Supports up to 8 request/acknowledge pairs for hardware handshaking.
• Provides the round-robin arbitration with 2 priority levels.
• Supports 8/16/32-bit wide data transfer.
DMA supports up to 8 DMA channels. Each DMA channel provides a set of registers to
describe the intended data transfers. Multiple DMA channels can be enabled concurrently,
but the DMA controller services one channel at a time.
The following figure shows an illustration of data transfer timing for a channel. To prevent
channels from being starved, the DMA controller services all ready-channels alternatively,
performing at most SrcBurstSize data transfers each time. Consequently, the data
transfers of a channel may be split into several chunks when the total transfer size
(TranSize) is larger than the source burst size (SrcBurstSize). When the overall data
transfers of a channel complete, the DMA controller will update the interrupt status register,
IntStatus, and assert the dma_int interrupt signal if the terminal count interrupt is enabled.
The data transfers of a channel will be stopped when an error occurs. The data transfers
of a channel can also be aborted by software. In either case, the DMA controller will disable
the channel, and assert dma_int if the corresponding interrupt is enabled.
Figure 9.1 Example of DMA Data Transfers
9.2.3.1. Channel Arbitration
DMA provides two priority levels for channel arbitration. Every channel is associated with
a priority level by the Priority field of the channel control register, ChnCtrl. During the
channel arbitration, the DMA controller selects a high priority channel first. A low priority
channel is only selected if there is no high priority channel. Channels of the same priority
level will be selected by the round-robin scheme.
9.2.3.2. Hardware Handshake
DMA provides up to 16 pairs of hardware handshake signals ( dma_req/dma_ack ) for data

transfers with low-speed devices. The following figure gives an example of hardware
handshaking. The device should assert dma_req only when it prepares enough data to
transfer or when it has enough empty space to receive the incoming data. The DMA
controller only issues bus requests to read/write the data when it sees the dma_req
asserted, avoiding holding the bus in the wait state indefinitely. The DMA controller asserts
dma_ack when it completes SrcBurstSize data transfers from/to the device. The device
should de-assert dma_req after detecting the assertion of dma_ack. The DMA controller
should de-assert dma_ack after detecting the de-assertion of dma_req . If an error is
encountered during the data transfers, the DMA controller will disable the channel without
asserting dma_ack.The error handling software should reset both the source and
destination of the DMA transfer to deassert dma_req.
Figure 9.2 Example of Hardware Handshaking
9.2.3.3. Chain Transfer
DMA provides the chain transfer function, with which multiple blocks of data can be
transferred consecutively without the intervention of the main processor.
Before a chain transfer is started, a linked list structure must be built to describe the data
blocks to move and the associated control setups. The first element of the list (the head of
the list) is described by the channel control registers. The rest of elements of the list are
specified by the linked list descriptors stored in the memory, where the linked list descriptor
holds the control values to load to the channel control registers to continue the data
transfer.The following figure shows an example of the linked list structure.
When the channel is enabled, the DMA controller will first transfer data according to the
channel control registers. After the data transfer completes, the DMA controller will
continue the data transfer by following the ChnLLPointer. The content of the linked list
descriptor pointed by ChnLLPointer will be loaded to the channel control registers if
ChnLLPointer is not zero. The loaded descriptor becomes the new head of the list and this
process repeats until the ChnLLPointer is zero.
Head of List 2'nd Element 3'rd Element 4'th Element

ChnCtrl Ctrl Ctrl Ctrl
ChnSrcAddr SrcAddr SrcAddr SrcAddr
ChnDstAddr DstAddr DstAddr DstAddr
ChnTranSize TranSize TranSize TranSize

ChnLLPoint
LLPointer LLPointer LLPointer(o)
er
Channel Control Registers Descriptors in Memory
Figure 9.3 Linked List Structure for Chain Transfers
When the terminal count interrupt (IntTCMask) of a channel is enabled, the DMA controller
will generate an interrupt and disable the channel when the data transfer for the head of
the list is done. If the ChnLLPointer is not zero, the channel control registers will be
preloaded with the next descriptor before the interrupt is generated. The interrupt handling
software could resume the chain transfer by just re-enabling the channel.
The following table shows the format of the linked list descriptor. The bit field definition of
each descriptor word is the same as the corresponding channel control register except the
channel enable bit, which is reserved in the linked list descriptor.
Name Offset Description Format
Ctrl 0x44+n*0x14 Channel control See DMA Register Map
SrcAddr 0x48+n*0x14 Source address See DMA Register Map
DstAddr 0x4c+n*0x14 Destination address See DMA Register Map
TranSize 0x50+n*0x14 Total transfer size See DMA Register Map
LLPointer 0x54+n*0x14 Linked list pointer See DMA Register Map
Table 9.2 Format of Linked List Descriptor
9.2.3.4. Data Order
DMA provides three address control modes: increment mode, decrement mode, and fixed
mode. At the increment mode, the address is increased after the DMA controller accesses
a data of the source/destination. At the decrement mode, the address is decreased after
the DMA controller accesses a data of the source/destination. At the fixed mode, the
address remains unchanged after the DMA controller accesses a data of the source/
destination.
When the address control mode of the source is the same as that of the destination, the
DMA controller maintains the same byte order of the data between the source and the
destination. When the address control mode of the source is opposite to that of the
destination, the data written to the destination will be in the reverse byte order of that read
from the source. The data order of the fixed mode is treated the same as that of the
increment mode. The following figures illustrate the byte order of the data at the destination
when the source address mode is increment, decrement, and fixed respectively.
d c 0xc
Destination: Increment b a 9 8 0x8

0x2 ~ 0xd
7 6 5 4 0x4
Source:Increment 3 2 0x0
0x2 ~ 0xd
f e d c 0xc 2 3 0xc
b a 9 8 0x8 Destination: decrement 4 5 6 7 0x8

0xd ~ 0x2
7 6 5 4 0x4 8 9 a b 0x4
3 2 1 0 0x0 c d 0x0
0xc
Destination: fixed 0x8

0x4
d c b a 0x4
0x0
Figure 9.4 Data Order at the Destination

when the Source Address Mode is the Increment Mode
2 3 0xc
Destination: Increment 4 5 6 7 0x8

0x2 ~ 0xd
8 9 a b 0x4
Destination: decrement
0xd ~ 0x2 c d 0x0
f e d c 0xc f e d c 0xc
b a 9 8 0x8 Destination: decrement b a 9 8 0x8

0xd ~ 0x2
7 6 5 4 0x4 7 6 5 4 0x4
3 2 1 0 0x0 3 2 1 0 0x0
0xc

0x4
2 3 4 5 0x4
0x0

when the Source Address Mode is the Decrement Mode
7 6 0xc
Destination: Increment 5 4 7 6 0x8

0x2 ~ 0xd
5 4 7 6 0x4
Destination: fixed 5 4 0x0

0x4
f e d c 0xc 4 5 0xc
b a 9 8 0x8 Destination: decrement 6 7 4 5 0x8

0xd ~ 0x2
7 6 5 4 0x4 6 7 4 5 0x4
3 2 1 0 0x0 6 7 0x0
0xc

0x4
7 6 5 4 0x4
0x0

when the Source Address Mode is the Fixed Mode
9.2.4. DMA Register Map
offset Name Description

0x04 NA Reserved
0x08 NA Reserved
0x0C NA Reserved
0x10 NA Reserved
0x14 NA Reserved
0x18 NA Reserved
0x1C NA Reserved
0x20 DMACTRL DMAC control register
0x24 NA Reserved
0x28 NA Reserved
0x2C NA Reserved
0x30 INTSTATUS Interrupt status register
0x34 CHEN Channel enable register
0x38 NA Reserved
0x3C NA Reserved
0x40 CHABORT Channel abort register
0x44+n*0x14 CHNCTRL Channel n control register
0x48+n*0x14 CHNSRCADDR Channel n source address register
0x4C+n*0x14 CHNDSTADDR Channel n destination address register
0x50+n*0x14 CHNTRANSIZE Channel n transfer size register
0x54+n*0x14 CHNLLPOINTER Channel n linked list pointer register
DMA Register Description
The following sections describe DMA registers in detail. The abbreviations for the Type
column are summarized below:
RO: read only
WO: write only
R/W: readable and writable
R/W1C: readable and write 1 to clear
DMAC Control Register (offset 0x20)

31:1 NA NA RESERVED NA
0 W 0x0 RESET Software reset control. Set this bit to 1 to
reset the DMA core and disable all channels.
Interrupt Status Register (offset 0x30)

This register contains the terminal count, error, and abort status. The terminal count status
of a channel is asserted when the channel encounters the terminal counter event. The
error/abort status of a channel is asserted when the channel encounters the error/abort
event. There is one bit of status for each channel and the status bit is zero when the
corresponding channel is not configured.
23:16 R/W 1C 0x0 TC The terminal count status of DMA channels,
one bit per channel. The terminal count status
is asserted when a channel transfer finishes
without abort or error event.
0=channel N has no terminal count status
1=channel N has terminal count status
15:8 R/W 1C 0x0 ABORT The abort status of channel, one bit per
channel.
The abort status is asserted when a channel
transfer is aborted.
0=channel N has no abort status
1=channel N has abort status
7:0 R/W 1C 0x0 ERROR The error status, one bit per channel.
The error status is asserted when a channel
transfer encounters the following error
events:
Bus error
Unaligned address
Unaligned transfer width
Reserved configuration
0=channel N has no error status
1=channel N has error status
Channel Enable Register (Offset 0x34)

The register shows the DMA channel enable status. The status fields only exist when the
corresponding channels are configured. This register is an alias of the Enable fields of all
ChnCtrl registers.
N:0 R 0x0 CHEN Alias of the Enable field of all ChnCtrl registers
Channel Abort Register (Offset 0x40)

The register controls the abortion of the DMA channel transfers, one-bit per channel. Write
1 to stop the current transfer of the corresponding channel. The abort bit is automatically
cleared by hardware after triggering the channel abort event.
N:0 W 0x0 CHABORT Write 1 to this field to stop the channel transfer.
The bits can only be set when the corresponding
channels are enabled. Otherwise, the writes will
be ignored for channels that are not enabled.
Channel n Control Register (Offset 0x44+n*0x14)

31:30 R/W NA RESERVED NA
29 R/W 0x0 PRIORITY Channel priority level.
0=lower priority
1=higher priority
24:22 R/W 0x0 SRCBURSTSI Source burst size. This field indicates the
ZE number
of transfers before DMA channel re-
arbitration.
Total byte of a burst is SrcBurstSize *
SrcWidth.
0x0: 1 transfer
0x1: 2 transfers
0x2: 4 transfers
0x3: 8 transfers
0x4: 16 transfers
0x5: 32 transfers
0x6: 64 transfers
0x7: 128 transfers
21:20 R/W 0x2 SRCWIDTH Source transfer width
0x0: byte transfer
0x1: half-word transfer
0x2: word transfer
0x3: reserved, setting the field with this
value
triggers error exception
19:18 R/W 0x2 DSTWIDTH Destination transfer width.
Both the total transfer byte and the total
burst
bytes should be aligned to the destination
transfer width; otherwise the error event will
be triggered.
For example, destination transfer width
should be set as byte transfer if total
transfer byte is not aligned to word or half-
word.
See SrcBurstSize field above for the
definition of total burst byte and section 3.12
for the definition of the total transfer bytes.
0x0: byte transfer
0x1: half-word transfer
0x2: word transfer
0x3: reserved, set the field as this value
triggers error exception
17 R/W 0x0 SRCMODE Source DMA handshake mode
0=normal mode
1=handshake mode
16 R/W 0x0 DSTMODE Destination DMA handshake mode
0=normal mode
1=handshake mode
15:14 R/W 0x0 SRCADDRCT Source address control
RL 0x0: increment address
0x1: decrement address
0x2: fixed address
value
triggers the error exception
13:12 R/W 0x0 DSTADDRCTR Destination address control
L 0x0: increment address
0x1: decrement address
0x2: fixed address
value
triggers the error exception
11:8 R/W 0x0 SRCREQSEL Source DMA request select. Select the
request/ack handshake pair that the source
device is connected to.
7:4 R/W 0x0 DSTREQSEL Destination DMA request select. Select the
request/ack handshake pair that the
destination device is connected to.
3 R/W 0x0 INTABTMASK Channel abort interrupt mask.
0=allow the abort interrupt to be triggered
1=disable the abort interrupt
2 R/W 0x0 INTERRMASK Channel error interrupt mask.
0=allow the error interrupt to be triggered
1=disable the error interrupt
1 R/W 0x0 INTTCMASK Channel terminal count interrupt mask
0=allow the terminal count interrupt to be
triggerd
1=disable the terminal count interrupt
0 R/W 0x0 ENABLE Channel enable bit
0x0: disable
0x1: enable
Channel n Source Address Register (Offset 0x48+n*0x14)

31:0 R/W 0x0 SRCADDR Source starting address. When a transfer
completes, its value is updated to the ending
address + sizeof(SrcWidth). This address
must be aligned to the source transfer size;
otherwise, an error event will be triggered.
Channel n Destination Address Register (Offset 0x4C+n*0x14)

31:0 R/W 0x0 DSTADDR Destination starting address. When a transfer
completes, its value is updated to the ending
address + sizeof(DstWidth). This address
must be aligned to the destination transfer
size; otherwise the error event will be
triggered.
Channel n Transfer Size Register (Offset 0x50+n*0x14)

21:0 R/W 0x0 TRANSIZE Total transfer size from source. The total
number of transferred bytes is TranSize *
SrcWidth. The value is updated to zero when
the DMA transfer is done. If a channel is
enabled with zero total transfer size, the error
event will be triggered and the transfer will be
terminated.
Channel n Linked List Pointer Register:(Offset 0x54+n*0x14)
31:2 R/W 0x0 LLPOINTE Pointer to the next block descriptor. The
R pointer must be word aligned.
9.3. Control SPI Interface
9.3.1. Introduction
The Serial Peripheral Interface (SPI) is used primarily for a synchronous serial
communication of host processor and peripherals. The SPI controller is Motorola SPI-
compatible interface. Up to two devices can be connected using two chip selects, data-in
(SPI_DO), data-out (SPI_DO) and clock (SPI_CLK) signals are common for all the two
devices. SPI interface can also be used to connect to SPI flash devices; commands such
as read/write are user configurable.
Following features are supported:

• Motorola SPI compatible 4 wire interface
• SPI Master Mode support only
• DMA read and write support. DMA reads can be maximum size of 65535 Bytes (64KB
-1)
• Command based read and writes
• Operating speed is software configurable
• Transparent read support for flash device
The AHB Master I/F transfers data from the SPI FIFO to system memory for SPI reads or
from system memory to the SPI FIFO for SPI writes. The CPU uses the AHB slave interface
to setup a SPI read or write transactions. The single buffered FIFO is used for data
transport through the AHB Master Interface. The same FIFO is used for both SPI reads
and SPI writes. When a transaction is completed, an interrupt can be generated, if enabled,
to signal the CPU that the requested transaction has completed.
For SPI devices that are less than 32-bit wide, the endianness of the SPI device needs to
be considered. Since data is sent MSB-first, when the SPI device is little-endian, this
module will internally swap the data bytes (for 8-bit devices) or half-words (for 16-bit
devices) before sending and after receiving data from the SPI device. SPI device
endianness is register configurable and programmed with the WIDTH field in the SPI
Configuration Register. Frame work below indicates the bit order sent for a specific SPI
device configuration:
AHB BUS
AHB MASTER INTERFACE AHB SLAVE INTERFACE
FIFO
DATA ENDIN CONTROL REG
SHIFT REGISTER SPI INTERFACE
SPI BUS
Figure 9.7 Specific SPI Device Configuration
9.3.4. SFLASH Address Map
SPI address is mapped to transparent read space. Below is the SPI address map:
Address Range Description
0x5000 0000 to 0x50FF FFFF(un-cacheable) Transparent read space
(physical address)
0x0000 0000 to 0x00FF FFFF Remap address space
(cacheable/un-cacheable)
0x5100 0000 to 0x51FF FFFF SPI control register space
9.3.5. SFLASH Register Map

0x00000 SPI_INTR_STATUS SPI Interrupt Status Register
0X00004 SPI_RAW_INTR_STATUS SPI Raw Interrupt Status Register
0X00008 SPI_INTR_MASK SPI Interrupt Mask register
0X0000C SPI_COMMAND SPI Command Register
0X00010 SPI_COMMAND_DATA0_REG SPI command data0 register
0X00014 SPI_COMMAND_DATA1_REG SPI command data1 register
0X00018 SPI_READ0_REG SPI Read0 Register
0X0001C SPI_READ1_REG SPI Read1 Register
0X00020 SPI_ADDRESS_REG SPI Address Register
0X00024 SPI_READ_OPCODE_REG SPI Read Opcode Register
0X00028 SPI_CONFIGURATION_0 SPI Configuration Register 0
0X0002C SPI_CS_CONFIGURATION_0 SPI CS Configuration Register 0
0X00030 SPI_CONFIGURATION_1 SPI Configuration Register 1
0X00034 SPI_CS_CONFIGURATION_1 SPI CS Configuration Register 1
SPI_INTR_STATUS address offset: 0x000

31:1 N/A 0x0 RESERVED reserved
0 R 0x0 SPI_CMD_DONE SPI command done
SPI_RAW_INTR_STATUS address offset: 0x004

0 RW 0x0 SPI_RAW_INTR_ SPI command done interruption (internal
STATUS interrupt value before mask). Set when
the SPI command is complete.
Writing 1 to clear the interrupt Status.
SPI_INTR_MASK address offset: 0x008

0 RW 0x0 SPI_CMD_DONE_ SPI command done interrupt mask.
MASK When 1, allows the interrupt to assert the
interrupt.
SPI_COMMAND address offset: 0x00c

31:12 RW 0x0 DATA_BYTES This field specifies the number of data
bytes to transfer after the Command
Data bits have been sent.
Valid values are 0-65535.
For a Read command, if this field is not a
multiple of 4, zeros will be padded before
data is written to system memory.
This value is decremented during the
SPI transaction until it reaches 0.
11:5 RW 0x0 CMD_BITS This field specifies the number of bits of
the Command Data to send.
Valid values are 0-64.
This value is decremented during the
SPI transaction until it reaches 0.
Note that the 64 command data bits are
defined in 2 32-bitregisters.
The first 32 command data bits are sent
from the spi_command_data0_reg
register, the next 32 bits from the
spi_command_data1_reg register.
4 RW 0x0 KEEP_CS CS keep enable.
0: Disable.
1: Enable.
3 RW 0x0 DATA_2_LANE_E 2 data lane mode enable, only available
N when spi_if_mode is set to 3 wire mode
1
0: Disable
1: Enable
2 RW 0x0 CHIP_SELECT Chip Select.
0: CS0
1: CS1
1:0 RW 0x0 COMMAND Read/write command.
This field is self-clearing after the SPI
transition has completed.
0x0: NOP
0x1: Read. Data is transferred to
Memory after the Command Data bits
are sent
0x2: Write. Data is transferred to the SPI
device after the Command Data bits are
sent.
SPI_COMMAND_DATA0_REG address offset: 0x010

31:0 RW 0x0 COMMAND_DATA This is the command data which is sent
for the first 32 SPI clock cycles,
depending on the CMD_BITS field. It is
sent MSB first (data is left-shifted out of
bit31).This value is maintained during the
SPI transaction.
SPI_COMMAND_DATA1_REG address offset: 0x014

31:0 RW 0x0 COMMAND_DATA This is the command data which is sent
for the first 32 SPI clock cycles,
depending on the CMD_BITS field. It is
sent MSB first (data is left-shifted out of
bit31).This value is maintained during the
SPI transaction.
SPI_READ_DATA0_REG address offset: 0x018

31:0 RW 0x0 READ_DATA0 This register holds data that is captured
during the first 32 SPI clock cycles. It is
captured MSB first(data is left-shifted in
from bit 0). Unused leading bits will be 0.
spi_read_data1_reg address offset: 0x01c

31:0 RW 0x0 READ_DATA1 This register holds data that is captured
during the first 32 SPI clock cycles. It is
captured MSB first(data is left-shifted in
from bit 0). Unused leading bits will be 0.
SPI_ADDRESS_REG address offset: 0x020

31:0 RW 0x0 ADDRESS This register holds the system memory
address for data transfer. It is
incremented by 4 as data is read from
system memory (in the case of a Write
command), or as data is written to
system memory(in the case of a Read
command). The lower two bits of this
register are always 0, in order to force
word alignment.
SPI_READ_OPCODE_REG address offset: 0x024

15:8 RW 0x3b CS1_OPCODE This register holds the OPCODE which
is used to read from a Serial Flash
device when a Transparent Read occurs
in the CS1 address space
7:0 RW 0x3b CS0_OPCODE This register holds the OPCODE which
is used to read from a Serial Flash
device when a Transparent Read occurs
in the CS0 address space
SPI_CONFIGURATION_0 address offset: 0x028

31:24 N/A 0x0 RESEVED reserved
23 RW 0x0 LCD_RD_EN 0x0: flash read and write, lcd write
0x1: lcd read
22:21 RW 0x0 RGB_MODE 0x0: flash, RGB565 1-wire/2-wire data-
lane
0x1: RGB666 1-wire/2-wire data-lane
20:18 RW 0x0 LCD_SPI_CTRL 0x0: flash-mode;
0x1: RGB565/RGB888 3-wire, 1-wire
data-lane
data-lane
0x3: RGB666 3-wire, 1-wire data-
lane/RGB565 3-wire, 2-wire data-lane
0x5: RGB888 3-wire, 2-wire data-lane
(only valid for SFLASH2)
17:16 RW 0x0 WIDTH Width of the data reads/writes.
This field causes data to be properly
written to devices which are less than
32-bits wide in little-endian system. Big-
endian systems should use the 32-bit
data setting.
00: 8-bit data
01: 16-bit data
1X: 32-bit data
Note: 0x1 for RGB565;
0x2 for RGB666 and RGB888
15 N/A 0x0 RESERVED reserved
14 RW 0x0 FE_DLY_SAMPLE Falling edge delayed sampling.
1: sample SPI_DI on falling edge of
delayed sampling clock (SPI_CLK_DLY).
internal sampling clock (SPI_CLK).
Enabling this bit will allow higher
frequency operation.
If set, the dly_sample[13:12] must beset
to 1 or greater. This is only valid for SPI
modes 0 and3. For modes 1 and 2,
these bits must be set to 0.
13:12 RW 0x0 DLY_SAMPLE Delayed Sampling, the number of
REF_CLKs after the falling edge of
SPI_CLK to sample SPI_DI.
Setting these bits will allow higher
frequency operation. If
fe_dly_sample[14] is set, this field must
be set to 1 or greater. This is only valid
for SPI modes 0 and 3. For modes 1 and
2, these bits must be set to 0.
10 RW 0x0 BP_ CLOCK_DIV Bypass clock divider
9 RW 0x0 CPOL Clock polarity.
0: The clock is low during idle times, and
each clock pulse consists of a rising
edge followed by a falling edge.
1: The clock is high during idle times,
and each clock pulse consists of a falling
edge followed by a rising edge.
8 RW 0x0 CPHA Clock phase.
0: Input data is clocked on first edge of
each clock pulse.
1: Input data is clocked on the second
edge of each clock pulse.
7:0 RW 0x2 CLOCK_DIV This register is the divider for the system
clock and to generate the SPI clock.
Only even values should be programmed
in order to keep a 50% duty cycle clock.
The minimum value of this register is 2.
SPI_CS_CONFIGURATION_0 address offset: 0x02c

31:24 RW 0x0a CS_RECOVER Chip Select Recover time. This is the
number of system cycles that must pass
after the chip select is de-asserted
before the same or any other chip select
can be asserted.
23:16 RW 0x0a CS_HOLD Chip Select Hold time. This is the
number of system clock cycles between
the last clock and the de-assertion of the
chip select.
15:8 RW 0x0a CS_SETUP Chip Select Setup time. This is the
the assertion of the chip select and the
first clock pulse.
0 RW 0x0 CS_POL Chip Select Polarity.
0: Chip select is active low.
1: Chip select is active high
SPI_CONFIGURATION_1 address offset: 0x030

23 RW 0x0 LCD_RD_EN 0x0: flash read and write, lcd write
0x1: lcd read
22:21 RW 0x0 RGB_MODE 0x0: flash, RGB565 1-wire/2-wire data-
lane
20:18 RW 0x0 LCD_SPI_CTRL 0x0: flash-mode;
data-lane
data-lane
0x5: RGB888 3-wire, 2-wire data-lane
17:16 RW 0x0 WIDTH Width of the data reads/writes.
This field causes data to be properly
written to devices which are less than 32-
bits wide in little-endian system. Big-
endian systems should use the 32-bit
data setting.
00: 8-bit data
01: 16-bit data
1X: 32-bit data
Note: 0x1 for RGB565;
0x2 for RGB666 and RGB888
14 RW 0x0 FE_DLY_SAMPL Falling edge delayed sampling.
E 1: sample SPI_DI on falling edge of
delayed sampling clock (SPI_CLK_DLY).
internal sampling clock (SPI_CLK).
Enabling this bit will allow higher
frequency operation.
If set, the dly_sample[13:12] must beset
to 1 or greater. This is only valid for SPI
modes 0 and3. For modes 1 and 2, these
bits must be set to 0.
13:12 RW 0x0 DLY_SAMPLE Delayed Sampling, the number of
REF_CLKs after the falling edge of
SPI_CLK to sample SPI_DI. Setting
these bits will allow higher frequency
operation. If fe_dly_sample[14] is set,
this field must be set to 1 or greater. This
is only valid for SPI modes 0 and 3. For
modes 1 and 2, these bits must be set to
0.
11 N/A 0x0 RESEVED reserved
10 RW 0x0 BP_ CLOCK_DIV Bypass clock divider
9 RW 0x0 CPOL Clock polarity.
0: The clock is low during idle times, and
each clock pulse consists of a rising
edge followed by a falling edge.
1: The clock is high during idle times,
and each clock pulse consists of a falling
edge followed by a rising edge.
8 RW 0x0 CPHA Clock phase.
0: Input data is clocked on first edge of
each clock pulse.
1: Input data is clocked on the second
edge of each clock pulse.
7:0 RW 0x2 CLOCK_DIV This register is the divider for the system
clock and to generate the SPI clock. Only
even values should be programmed in
order to keep a 50% duty cycle clock.
The minimum value of this register is 2.
SPI_CS_CONFIGURATION_1 address offset: 0x034

31:24 RW 0x0a CS_RECOVER Chip Select Recover time. This is the
number of system cycles that must pass
after the chip select is de-asserted
before the same or any other chip select
can be asserted.
23:16 RW 0x0a CS_HOLD Chip Select Hold time. This is the
the last clock and the de-assertion of the
chip select.
15:8 RW 0x0a CS_SETUP Chip Select Setup time. This is the
the assertion of the chip select and the
first clock pulse.
0 RW 0x0 CS_POL Chip Select Polarity.
0: Chip select is active low.
1: Chip select is active high
9.3.6. SFLASH Software Program Guide
9.3.6.1. Read ID
In order to read the ID of the flash device, the SPI Master sends the 8- bit Read-ID
command; then the flash sends back the 24-bit ID value (total of 32 bits are transferred).
Hence the number of command bits for this transaction will be 32; the number of data bytes
will be 0. The ID value will be available on ReadData0 register.
• Write the SPI Command Data0 register with the Read-ID command (0x9f); please
remember the command is transmitted MSB first; hence write 0x9f000000 (SPI
Command Data1 register is not used for this transaction).
• Write the SPI Command Register with the following details: Number of command bits
= 32, Number of data bytes = 0, Keep_CS = 0, Chip_select = Required Chip select
number (example 0), Command= Read i.e. 1.
• Wait until the command completes. One way to do this is by polling the
spi_raw_intr_status bit in the SPI Raw Interrupt Status Register.Another option is to
use the interrupt.
• Read the ID Value from SPI Read0 register (bits [23:0]). The data is captured MSB
first i.e., left shifted from bit 0, so the LSB will always be at 0.
9.3.6.2. Read Status Register
The Read-Status-Register command can be issued after initiating an erase or write

operation to check the status of that operation. The SPI Master sends the 8-bit command,
and then the flash sends back the 8-bit status value. Thus a total of 16 bits are transferred.
Hence the number of command bits for this transaction will be 16; the number of data bytes
will be 0. The Status value will be available on the lower 8-bits of the Read Data0 register.
• Write the SPI Command Data0 register with the Read-Status command (0x05); please
remember the command is transmitted MSB first; hence write 0x05000000 (SPI
Command Data1 register is not used for this transaction).
• Write the SPI Command Register with the following details:
• Number of command bits = 16, Number of data bytes = 0, Keep_CS = 0,
Chip_select = Required Chip select number (example 0), Command= Read i.e. 1.
spi_raw_intr_status bit in the SPI Raw Interrupt Status Register.Another option is to
use the interrupt.
• Read the Status Value from SPI Read0 register (bits [7:0]). The data is captured MSB
first i.e., left shifted from bit 0, so the LSB will always be at 0.
9.3.6.3. DMA Write Operation
For DMA write operation, only a maximum of Page Size number of bytes supported by the
flash can be written at a time. The Page Write or Page Program command (8-bits) is sent
along with the 24-bit start flash address; this is followed by the required number of data
bytes. Thus the number of command bits should be set to 32 and the number of data bytes
is set to the required number.
• Perform a Sector Erase operation if the flash supports only Page Program command;
if it supports Page Write then there is no need to do a separate Erase command.
• Send Write enable command to the flash.
• Write the SPI Command Data0 register with the Page Program (Or Page Write)
command and the 24-bit start address in flash; please remember the command is
transmitted MSB first; hence for example if the start address in flash is 0, then write
0x02000000 to do a page program. (SPI Command Data1 register is not used for this
transaction).
• Set the DMA Source Address in the SPI Address Register.
• Number of command bits=32, Number of data bytes=N (required number),
Keep_CS=0, Chip_select=Required Chip select number (example0), Command
= Write i.e. 2.
spi_raw_intr_status bit in the SPI Raw Interrupt Status Register. Another option is to
use the interrupt.
• Use the Read-Status-Register command to find out when the Write operation is
completed by flash.
9.3.6.4. DMA Read Operation
For DMA Read operation, the whole flash can be read using a single command. Normal
Read command (0x03) can be used only up-to a certain frequency (example 20 MHz for
M25P128); above that frequency the Fast Read command (0x0b) should be used. When
the Normal Read command is used the SPI Master sends the 8-bit read command along
with a 24-bit start flash address. Thus the number of command bits will be 32 for normal
read command. When the Fast Read command is used the SPI Master sends the 8-bitFast-
read command along with a 24-bit start flash address; the flash device returns a dummy
byte before starting to return valid data. Hence the number of command bits for Fast-read
command will be 40 bits.
• Write the SPI Command Data0 register with the Normal Read command (0x03) or the
Fast-Read command (0x0b) based on the SPI clock frequency, along with the 24-bit
start flash address; please remember the command is transmitted MSB first; hence
for example if the start address in flash is 0, then write 0x0b000000 to do a fast read.
Write 0x00000000 to SPI Command Data1 register for fast read to make sure the
MOSI line does not toggle during the dummy byte interval this is safer.
• Set the DMA Destination Address in the SPI Address Register.
• Number of command bits=32 for normal read or 40 for Fast read, Number of data
bytes=N (required number), Keep_CS=0, Chip_select =Required Chip select
number (example 0), Command = Read i.e.1.
spi_raw_intr_status bit in the SPI Raw Interrupt Status Register. Another option is to
use the interrupt.
• The data will be available in the system memory starting from address DMA
Destination Address.
9.4. GPIO
9.4.1. Introduction
OM6621Ex has GPIOs which can connect to various signal interfaces. The following figure
shows the basic structure of an I/O Port bit.
Figure 9.8 Basic structure of a standard I/O Port Bit
• OM6621EM: 23 general-purpose I/O GPIOs (max)

• OM6621ED: 16 general-purpose I/O GPIOs (max)
The digital GPIO pads can be configured to set direction, enable pull-up/pull-down resistors
and enable output retention. GPIOs can also be read or written by firmware for applications
that need direct access, by using the GPIOx registers.
Subject to the specific hardware characteristics of each I/O port listed in the datasheet,
each port bit of the General Purpose IO (GPIO) Ports, can be individually configured by
software in several modes:
• Input floating
• Input pull-up
• Input-pull-down
• Output open-drain
• Output push-pull
• Open-drain, pull up
9.4.3.1. External Interrupt
All ports have external interrupt capability. To use external interrupt lines, the port must be
configured in input mode. And it can be set to trigger in a variety of ways through the
software configuration register.
• Falling edge
• Rising edge
• Both edge
• High level
• Low level
• Disable trigger
9.4.3.2. Input Configuration
When the I/O Port is programmed as Input:

• The Output Buffer is disabled.
• The Schmitt Trigger Input is activated.
• The weak pull-up and pull-down resistors are activated or not depending on input
configuration (pull-up, pull-down or floating).
• The data present on the I/O pin is sampled into the Input Data register.
• A read access to the Input Data register obtains the I/O State.
错误!未找到引用源。The following figure shows the Input Configuration of the I/O Port
bit.
Figure 9.9 Input Floating/Pull up/Pull down Configurations
9.4.3.3. Output Configuration
When the I/O Port is programmed as Output:

• The Output Buffer is enabled:
• Open Drain Mode: A “0” in the Output register activates the N-MOS while a “1” in
the Output register leaves the port in Hi-Z (the P-MOS is never activated).
• Push-Pull Mode: A “0” in the Output register activates the N-MOS while a “1” in
the Output register activates the P-MOS.
• The Schmitt Trigger Input is activated.
• The weak pull-up and pull-down resistors are disabled.
• The data present on the I/O pin is sampled into the Input Data register.
• A read access to the Input Data register gets the I/O state in open drain mode.
• A read access to the Output Data register gets the last written value in Push-Pull mode.
The following figure shows the Output configuration of the I/O Port bit.
Figure 9.10 Output Configuration
9.4.3.4. Analog Configuration
When the I/O Port is programmed as Analog configuration:

• The Output Buffer is disabled.
• The Schmitt Trigger Input is deactivated providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt Trigger is forced to a constant value (0).
• The weak pull-up and pull-down resistors are disabled.
• Read access to the Input Data register gets the value “0”.
The following figure shows the high impedance-analog configuration of the I/O Port bit.
Figure 9.11 High Impedance-analog Configuration
9.4.4. Electrical Specification

VIH Input high voltage 0.7xVAVDD VAVDD V
VIL Input low voltage VSS 0.3xVAVDD V
Current at 0.3xVAVDD, output
set low, VAVDD=3.3V
IOL,H
gpio_drv_ctrl=0 10.4 mA
set low, VAVDD=1.8V
IOL,L
set high, VAVDD=3.3V
IOH,H
gpio_drv_ctrl=0 8 mA
set high, VAVDD=1.8V
IOH,L
Pull-up resistance
gpio_pl_ctrl[1:0]=00 4 kΩ
RPU gpio_pl_ctrl[1:0]=01 10 kΩ
gpio_pl_ctrl[1:0]=10 300 kΩ
gpio_pl_ctrl[1:0]=11 2 MΩ
RPD Pull-down resistance 200 kΩ
Table 9.3 Electrical Specification
9.4.5. GPIO Register Map

0x00000 DATA Data
0X00004 DATAOUT Data output latch
0X00010 OUTENSET Output enable set
0X00014 OUTENCLR Output enable clear
0X00018 ALTFUNCSET Alternative function set
0X0001c ALTFUNCCLR Alternative function set
0X00020 INTENSET Interrupt enable set
0X00024 INTENCLR Interrupt enable clear
0X00028 INTTYPESET Interrupt type set
0X0002c INTTYPECLR Interrupt type clear
0X00030 INTPOLSET Interrupt polarity set
0X00034 INTPOLCLR Interrupt polarity clear
0X00038 INTSTATUS Interrupt status
0x00040 INTBOTHSET Interrupt type1 set
0x00044 INTBOTHCLR Interrupt type1 clear
0x01000-0x13FC MASKBYTE0 Byte 0 masked access
0x01400-0x17FC MASKBYTE1 Byte 1 masked access
0x01800-0x1BFC MASKBYTE2 Byte 2 masked access
0x01c00-0x1FFC MASKBYTE3 Byte 3 masked access
DATA address offset: 0x00000

31:0 RW N/A DATA Read Sampled at pin.
Write To data output register.
DATAOUT address offset: 0x00004

31:0 RW 0x0 DATAOUT Data output Register value:
Read Current value of data output register.
Write To data output register.
OUTENSET address offset: 0x00010

31:0 RW 0x0 OUTENSET Output enable set:
Write
1 Set the output enable bit.
0 No effect.
Read back
0 Indicates the signal direction as input.
1 Indicates the signal direction as output
OUTENCLR address offset: 0x00014

31:0 RW 0x0 OUTENCLR Output enable clear:
Write
1 Clears the output enable bit.
0 No effect.
Read back
0 Indicates the signal direction as input.
1 Indicates the signal direction as output
ALTFUNCSET address offset: 0x00018

31:0 RW 0x0 ALTFUNCS Alternative function set:
ET Write
1 Sets the ALTFUNC bit.
0 No effect.
Read back
0 For I/O.
1 For an alternate function.
ALTFUNCCLR address offset: 0x0001C

31:0 RW 0x0 ALTFUNCC Alternative function clear:
LR Write
1 Clears the ALTFUNC bit.
0 No effect.
Read back
0 For I/O.
1 For an alternate function
INTENSET address offset: 0x00020

31:0 RW 0x0 INTENSET Interrupt enable set:
Write
1 Sets the enable bit.
0 No effect.
Read back
0 Interrupt disabled.
1 Interrupt enabled
INTENCLR address offset: 0x00024
31:0 RW 0x0 INTENCLR Interrupt enable clear:
Write
1 Clear the enable bit.
0 No effect.
Read back
0 Interrupt disabled.
1 Interrupt enabled
INTTYPESET address offset: 0x00028

31:0 RW 0x0 INTTYPESE Interrupt type set:
T Write
1 Sets the interrupt type bit.
0 No effect.
Read back
0 For LOW or HIGH level.
1 For falling edge or rising edge
INTTYPECLR address offset: 0x0002c

31:0 RW 0x0 INTTYPECL Interrupt type clear:
R Write
1 Clears the interrupt type bit.
0 No effect.
Read back
0 For LOW or HIGH level.
1 For falling edge or rising edge.
INTPOLSET address offset: 0x00030

31:0 RW 0x0 INTPOLSET Polarity-level, edge IRQ configuration:
Write
1 Sets the interrupt polarity bit.
0 No effect.
Read back
0 For LOW level or falling edge.
1 For HIGH level or rising edge.
INTPOLCLR address offset: 0x00034

31:0 RW 0x0 INTPOLCLR Polarity-level, edge IRQ configuration:
Write
1 Clears the interrupt polarity bit.
0 No effect.
Read back
0 For LOW level or falling edge.
1 For HIGH level or rising edge.
INTSTATUS address offset: 0x00038

31:0 RW 0x0 INTSTATUS Write one to clear interrupt request:
Write IRQ status clear Register.
Write:
1 To clear the interrupt request.
0 No effect.
Read back IRQ status Register
INTTYPE1SET address offset: 0x00040

31:0 RW 0x0 INTTYPE1S Interrupt type1 set:
ET Write
1 if the corresponding bit of INTTYPE SET is
also 1, both falling edge and rising edge
triggers interrupt; else no effect
0 No effect.
Read back
0 double edge detect disable
1 double edge detect enable
INTTYPE1CLR address offset: 0x00044

31:0 RW 0x0 INTTYPE1C Interrupt type1 clear:
LR Write
1 Clears the interrupt type1 bit.
0 No effect.
Read back
0 double edge detect disable.
1 double edge detect enable.
MASKBYTE0 address offset: 0x01000-0x013FC

7:0 RW 0x0 MASKBYTE BYTE0 masked access.
0 Bits[9:2] of the address value are used as
enable bit mask for the access:
[7:0] Data for BYTE0 access, with bits[9:2] of
address value used as enable mask for each
bit
MASKBYTE1 address offset: 0x01400-0x017FC

bit
MASKBYTE2 address offset: 0x01800-0x01BFC

bit
MASKBYTE3 address offset: 0x01C00-0x01FFC

bit
9.5. UART1
9.5.1. Introduction
The uart is a programmable Universal Asynchronous Receiver/Transmitter (UART). This

component is an AMBA 2.0-compliant Advanced Peripheral Bus (APB) slave device and is
part of the family of design ware synthesizable components .
The uart has been modeled after the industry-standard 16550. However, the register
address space has been relocated to 32-bit data boundaries for APB bus implementation.
It can be configured, synthesized, and verified using the Onmicro core Consultant GUI to
produce RTL. The uart is used for serial communication with a peripheral, modem (data
carrier equipment, DCE) or data set. Data is written from a master (CPU) over the APB bus
to the UART and it is converted to serial form and transmitted to the destination device.
Serial data is also received by the UART and stored for the master (CPU) to read back.
The uart contains registers to control the character length, baud rate, parity
generation/checking, and interrupt generation. Although there is only one interrupt output
signal (intr) from the uart, there are several prioritized interrupt types that can be
responsible for its assertion. Each of the interrupt types can be separately enabled/
disabled with the control registers.
• AMBA APB interface allows easy integration into AMBA SOC implementations
• Configurable parameters for the following:
• APB data bus widths of 8, 16 and 32
• Additional DMA interface signals for compatibility with design ware DMA interface
• DMA interface signal polarity
• Transmit and receive FIFO depth is 16
• Use of two clocks (pclk and sclk) instead of one (pclk)
• IrDA 1.0 SIR mode support with up to 115.2Kbaud data rate and a pulse duration
(width) as follows: width = 3/16 × bit period as specified in the IrDA physical layer
specification
• IrDA 1.0 SIR low-power reception capabilities
• Baud clock reference output signal
• Clock gate enable output(s) used to indicate that the TX and RX pipeline is clear
(no data) and no activity has occurred for more than one character time, so clocks
may be gated
• FIFO access mode (for FIFO testing) so that the receive FIFO can be written by
the master and the transmit FIFO can be read by the master
• Additional FIFO status registers
• Shadow registers to reduce software overhead and also include a software
programmable reset
• Auto Flow Control mode as specified in the 16750 standard
• Loop back mode that enables greater testing of Modem Control and Auto Flow
Control features (Loop back support in IrDA SIR mode is available)
• Transmitter Holding Register Empty (THRE) interrupt mode
• Busy functionality
• Ability to set some configuration parameters in instantiation
• Configuration identification registers present
• Functionality based on the 16550 industry standard, as follows:
• Programmable character properties, such as number of data bits per character
(5-8), optional
• parity bit (with odd or even select) and number of stop bits (1, 1.5 or 2)
• Line break generation and detection
• DMA signaling with two programmable modes
• Prioritized interrupt identification
• Programmable FIFO enable/disable
• Programmable serial data baud rate as calculated by the following:
• baud rate = (serial clock frequency)/(16× divisor)
• External read enable signal for RAM wake-up when using external RAMs
• Modem and status lines are independently controlled
• Complete RTL version
• Separate system resets for each clock domain to prevent metastability
9.5.3.1. UART(RS232) Serial Protocol
Because the serial communication between the UART and a selected device is
asynchronous, additional bits (start and stop) are added to the serial data to indicate the
beginning and end. Utilizing these bits allows two devices to be synchronized. This
structure of serial data — accompanied by start and stop bits—is referred to as a character,
as shown in the following figure.
One Character
Bit Time
Serial Data Start Data bits 5-8 Parity Stop 1,1.5,2
Figure 9.12 Serial Data Format

An additional parity bit can be added to the serial character. This bit appears after the last
data bit and before the stop bit(s) in the character structure in order to provide the UART
with the ability to perform simple error checking on the received data.
The UART Line Control Register (“LINE_CTRL” register) is used to control the serial
character characteristics. The individual bits of the data word are sent after the start bit,
starting with the least significant bit (LSB). These are followed by the optional parity bit,
followed by the stop bit(s), which can be 1, 1.5, or 2.
All the bits in the transmission (with exception to the half stop bit when 1.5 stop bits are
used) are transmitted for exactly the same time duration. This is referred to as a Bit Period
or Bit Time. One Bit Time equals 16 baud clocks. To ensure stability on the line the receiver
samples the serial input data at approximately the mid point of the Bit Time once the start
bit has been detected. As the exact number of baud clocks that each bit was transmitted
for is known, calculating the mid point for sampling is not difficult, that is every 16 baud
clocks after the mid point sample of the start bit. The following figure shows the sampling
points of the first couple of bits in a serial character.
N(divisor)
sclk
baudout_n(divisor of 1)
(N-2)clock cycles
2 clock cycles
baudout_n(divisor > 3)
Figure 9.13 Receiver Serial Data Sample Points
As part of the 16550 standard an optional baud clock reference output signal (baudout_n)
is supplied to provide timing information to receiving devices that require it. The baud rate
of the uart is controlled by the serial clock (sclk or pclk in a single clock implementation)
and the Divisor Latch Register (DLH and DLL).The following figure shows the timing
diagram for the baudout_n output for different divisor values.
Serial Data In Start Data Bit 0(LSB) Data Bit 1
8 16 16
Figure 9.14 Baud Clock Reference Timing Diagram
9.5.3.2. IrDA 1.0 SIR Protocol
The Infrared Data Association (IrDA) 1.0 Serial Infrared (SIR) mode supports bi-directional
data communications with remote devices using infrared radiation as the transmission
medium. IrDA 1.0 SIR mode specifies a maximum baud rate of 115.2K baud.
9.5.3.3. Attention
Information provided on IrDA SIR mode in this section assumes that the reader is fully
familiar with the IrDa Serial Infrared Physical Layer Specifications.
The data format is similar to the standard serial (sout and sin) data format. Each data
character is sent serially, beginning with a start bit, followed by 8 data bits, and ending with
at least one stop bit. Thus, the number of data bits that can be sent is fixed. No parity
information can be supplied and only one stop bit is used while in this mode. Trying to
adjust the number of data bits sent or enable parity with the Line Control Register (LCR)
has no effect. When the uart is configured to support IrDA 1.0 SIR it can be enabled with
Mode Control Register (MCR) bit 6. When the uart is not configured to support IrDA SIR
mode, none of the logic is implemented and the mode cannot be activated, reducing total
gate counts. When SIR mode is enabled and active, serial data is transmitted and received
on the sir_out_n and sir_in ports, respectively.
Transmitting a single infrared pulse signals a logic zero, while a logic one is represented
by not sending a pulse. The width of each pulse is 3/16ths of a normal serial bit time. Thus,
each new character begins with an infrared pulse for the start bit. However, received data
is inverted from transmitted data due to the infrared pulses energizing the photo transistor
base of the IrDA receiver, pulling its output low. This inverted transistor output is then fed
to the uart sir_in port, which then has correct UART polarity. The following figure shows
the timing diagram for the IrDA SIR data format in comparison to the standard serial format.
bit period
data bits
sout start stop
3/16 bit period

sir_out_n
sir_in
sin start stop
Figure 9.15 IrDA SIR Data Format

As detailed in the IrDA 1.0 SIR, the uart can be configured to support a low-power reception
mode. When the uart is configured in this mode, the reception of SIR pulses of 1.41
microseconds (minimum pulse duration) is possible, as well as nominal 3/16 of a normal
serial bit time. Using this low-power reception mode requires programming the Low Power
Divisor Latch (LPDLL/LPDLH) registers. It should be noted that for all sclk frequencies
greater than or equal to 7.37MHz (and obey the requirements of the Low Power Divisor
Latch registers), pulses of 1.41us are detectable. However, there are several values of sclk
that do not allow the detection of such a narrow pulse and these are as follows:
Low Power Divisor Latch Register Min Pulse Width for
SCLK
Value Detection*
1.84MHz 1 3.77uS
3.69MHz 2 2.086uS
5.53MHz 3 1.584uS
* 10% has been added to the internal pulse width signal to cushion the effect of pulse
reduction due to the synchronization and data integrity logic so that a pulse slightly
narrower than these may be detectable.
Table 9.4 Detection of SCLK values for narrow pulses is not allowed
When IrDA SIR mode is enabled, the uart operation is similar to when the mode is disabled,
with one exception; data transfers can only occur in half-duplex fashion when IrDA SIR
mode is enabled. This is because the IrDA SIR physical layer specifies a minimum of 10ms
delay between transmission and reception. This 10ms delay must be generated by
software.
9.5.3.4. FIFO Support
The uart can be configured to implement FIFOs to buffer transmit and receive data. If FIFO
support is not selected, then no FIFOs are implemented and only a single receive data
byte and transmit data byte can be stored at a time in the RBR and THR. This implies a
16450-compatible mode of operation. In this mode most of the enhanced features are
unavailable.
In FIFO mode, the FIFOs can be selected to be either external customer-supplied FIFO
RAMs or internal design-ware D-flip-flop based RAMs (Onmicro_ram_r_w_s_dff). If the
configured FIFO depth is greater than 256, the FIFO memory selection is restricted to be
external. In addition, selection of internal memory restricts the Memory Read Port Type to
D-flip-flop based, Synchronous read port RAMs.
When external RAM support is chosen, either synchronous or asynchronous RAMs can be
used. Asynchronous RAM provides read data during the clock cycle that has the memory
address and read signals active, for sampling on the next rising clock edge. Synchronous
single stage RAM registers the data at the current address out and is not available until
the next clock cycle (second rising clock edge). The following figure shows the timing
diagram for both asynchronous and synchronous RAMs.
pclk
tx_ram_rd_addr A0
tx_ram_re_n
tx_ram_out(As ync Read Port) D0 D1
tx_ram_out(Sync Read Port) D0 D1
Figure 9.16 Timing for RAM Reads
Note: This timing diagram illustrated in the following figure assumes the RAM used has a
chip select port that is tied to an active value, therefore, the chip is always enabled. This is
why the second synchronous read data appears at the same cycle as the asynchronous
read data. That is, the address for the second read has been sampled along with the chip
select on an earlier edge. Once the output enabled (tx_ram_re_n) asserts the data, value
on the register output is seen on that same cycle.
Similarly, you can use synchronous RAM for writes, which registers the data at the current
address out.
The following figure shows the timing diagram for RAM writes.
pclk
tx_ram_wr_addr Addr0
tx_ram_we_n
tx_ram_in Data
Figure 9.17 Timing for RAM Writes

When FIFO support is selected, an optional programmable FIFO Access mode is available
for test purposes, which allows the receive FIFO to be written by the master and the
transmit FIFO to be read by the master. When FIFO Access mode is not selected, none of
the corresponding logic is implemented and the mode cannot be enabled, reducing overall
gate counts. When FIFO Access mode has been selected it can be enabled with the FIFO
Access Register (FAR[0]). Once enabled, the control portions of the transmit and receive
FIFOs are reset and the FIFOs are treated as empty.
Data can be written to the transmit FIFO as normal. However, no serial transmission occurs
in this mode (normal operation halted) and hence no data leave the FIFO. The data that
has been written to the transmit FIFO can be read back with the Transmit FIFO Read (TFR)
register, which when read gives the current data at the top of the transmit FIFO.
Similarly, data can be read from the receive FIFO as normal. Since the normal operation
of the uart is halted in this mode, data must be written to the receive FIFO so it may be
read back. Data is written to the receive FIFO with the Receive FIFO Write (RFW) register.
The upper two bits of the 10-bit register are used to write framing error and parity error
detection information to the receive FIFO. Setting bit RFW[9] to indicate a framing error
and RFW[8] to indicate a parity error. Although these bits can not be read back via the
Receive Buffer Register they can be checked by reading the Line Status Register and
checking the corresponding bits when the data in question is at the top of the receive FIFO.
9.5.3.5. Clock Support
The uart can be configured to have either one system clock (pclk) or two system clocks
(pclk and sclk). Having the second asynchronous serial clock (sclk) implemented
accommodates accurate serial baud rate settings, as well as APB bus interface
requirements. When using a single system clock, the system clock settings available for
accurate baud rates are greatly restricted.
When a two clocks design is chosen, a synchronization module is implemented for
synchronization of all control and data across the two system clock boundaries. The RTL
diagram for the data synchronization module is shown in the Figure 6.18. The data
synchronization module can have pending data capability. The timing diagram shown in
the Figure 6.19 shows this process.
The arrival of new source domain data is indicated by the assertion of start. Since data is
now available for synchronization the process is started and busy status is set. If start is
asserted while busy and pending data capability has been selected, the new data is stored.
When no longer busy the synchronization process starts on the stored pending data.
Otherwise, the busy status is removed when the current data has been synchronized to
the destination domain and the process continues. If only one clock is implemented, all
synchronization logic is absent and signals are simply passed through this module.
Data_in Pending 1
Data Source Clock Data Data_out
Data 0 Register Register
Register
Edge Sync Sync Acknowledge

Start Detection Reg.2 Reg.1
Level Sync.
Stores the
request for Data
Available Sync Sync Edge
new writes Toggle Reg.1 Reg.2 Detection
while busy Register Data Available Toggle
so that Level Sync.
Logic
pending data
Busy
can be Register
sync’ed once
current data Delay Data_rdy
sync’ing is Pending
Register
Register
complete.
Figure 9.18 RTL Diagram of Data Synchronization Module
start
busy
pending
data_avail_togg
finish
Figure 9.19 Timing Diagram for Data Synchronization Module
Full synchronization handshake takes place on all signals that are “data synchronized”. All
signals that are “level synchronized” are simply passed through two destination clock
registers. Both synchronization types incur additional data path latencies. However, this
additional latency has no negative affect on received or transmitted data, other than to limit
the serial clock (sclk) to being no faster than four-times the pclk clock for back-to-back
serial communications with no idle assertion.
A serial clock faster than four-times the pclk signal does not leave enough time for a
complete incoming character to be received and pushed into the receiver FIFO. However,
in most cases, the pclk signal is faster than the serial clock and this should never be an
issue. There is also slightly more time required after initial serial control register
programming, before serial data can be transmitted or received.
The serial clock modules must have time to see new register values and reset their
respective state machines. This total time is guaranteed to be no more than eight clock
cycles of the slower of the two system clocks. Therefore, no data should be transmitted or
received before this maximum time expires, after initial configuration.
In systems where only one clock is implemented, there are no additional latencies.
9.5.3.6. Interrupts
The assertion of the uart interrupt output signal (intr) occurs whenever one of the several
prioritized interrupt types are enabled and active. The following interrupt types can be
enabled with the IER register:
• Configurable parameters for the following:
• Receiver Error
• Receiver Data Available
• Character Timeout (in FIFO mode only)
• Transmitter Holding Register Empty at/below threshold (in Programmable THRE
interrupt mode)
• Modem Status
• Busy Detect Indication
9.5.3.7. Auto Flow Control
The uart can be configured to have a 16750-compatible Auto RTS and Auto CTS serial
data flow control mode available. If FIFOs are not implemented, then this mode cannot be
selected. When Auto Flow Control is not selected, none of the corresponding logic is
implemented and the mode cannot be enabled, reducing overall gate counts. When Auto
Flow Control mode has been selected it can be enabled with the Modem Control Register
(MCR[5]). The following figure shows a block diagram of the Auto Flow Control functionality.
uart1 uart2
Transmitter
Receiver sin
Receiver sout (Serial -to- Transmit
(Serial -to-
FIFO Parallel) FIFO
Parallel)
enable
Threshold Auto CTS

Detection rts_n cts_n
Auto RTS Flow
Flow Control
Control
rts
cts
Transmitter
sout sin Receiver
Transmit (Serial -to- Receiver
(Serial -to-
FIFO Parallel) FIFO
Parallel)
enable
Auto CTS Threshold

cts_n rts_n Detection
Flow Auto RTS
Control Flow
Control
rts
cts
Figure 9.20 Auto Flow Control Block Diagram

Auto RTS – Becomes active when the following occurs:
• Auto Flow Control is selected during configuration
• FIFOs are implented
• RTS (MCR[1] bit and MCR[5]bit are both set)
• FIFOs are enabled (FCR[0]) bit is set)
• SIR mode is disabled (MCR[6] bit is not set)
When Auto RTS is enabled (active), the rts_n output is forced inactive (high) when the
receiver FIFO level reaches the threshold set by FCR[7:6]. When rts_n is connected to the
cts_n input of another UART device, the other UART stops sending serial data until the
receiver FIFO has available space (until it is completely empty).
The selectable receiver FIFO threshold values are: 1, ¼, ½, and “2 less than full”. Since
one additional character may be transmitted to the uart after rts_n has become inactive
(due to data already having entered the transmitter block in the other UART), setting the
threshold to “2 less than full” allows maximum use of the FIFO with a safety zone of one
character.
Once the receiver FIFO becomes completely empty by reading the Receiver Buffer
Register (RBR), rts_n again becomes active (low), signaling the other UART to continue
sending data. It is important to note that even if everything else is selected and the correct
MCR bits are set, if the FIFOs are disabled through FCR[0] or the UART is in SIR mode
(MCR[6] is set to one), Auto Flow Control is also disabled. When Auto RTS is not
implemented or disabled, rts_n is controlled solely by MCR[1]. The following figure shows
a timing diagram of Auto RTS operation.
This character
was received because rts_n was not detected before next
character entered the sending-UART's transmitter
sin start Character T stop start Character

CharacterT+1
T+1 stop
rts_n
RX FIFO Read 11 22 33 T T+1

T=Receiver FIFO Threshold Value
Figure 9.21 Auto RTS Timing

This character was received because rts_n was not detected before next character entered
the sending-UART's transmitter T=Receiver FIFO Threshold Value Auto CTS – becomes
active when the following occurs:
• Auto Flow Control is selected during configuration
• FIFOs are implemented
• AFCE (MCR[5] bit is set)
• FIFOs are enabled through FIFO Control Register FCR[0] bit
• SIR mode is disabled (MCR[6] bit is not set)
When Auto CTS is enabled (active), the uart transmitter is disabled whenever the cts_n
input becomes inactive (high). This prevents overflowing the FIFO of the receiving UART.
If the cts_n input is not inactivated before the middle of the last stop bit, another character
is transmitted before the transmitter is disabled. While the transmitter is disabled, the
transmitter FIFO can still be written to, and even overflowed.
Therefore, when using this mode, the following happens:
• The UART status register can be read to check if the transmit FIFO is full (USR[1] set
to zero),
• The current FIFO level can be read via the TFL register, or
• The Programmable THRE Interrupt mode must be enabled to access the “FIFO full”
status via the Line Status Register (LSR).
When using the “FIFO full” status, software can poll this before each write to the Transmitter
FIFO. See “Programmable THRE Interrupt for details. When the cts_n input becomes
active (low) again, transmission resumes. It is important to note that even if everything else
is selected, if the FIFOs are disabled via FCR[0], Auto Flow Control is also disabled. When
Auto CTS is not implemented or disabled, the transmitter is unaffected by cts_n. A Timing
Diagram showing Auto CTS operation can be seen in the following figure.
sout start Data Bits stop start Data Bits stop start Data Bits stop
Disabled
cts_n
Figure 9.22 Auto CTS Timing
9.5.3.8. Programmable THRE Interrupt
The UART can be configured for a Programmable TX_HDG_EMPTY Interrupt mode in

order to increase system performance; if FIFOs are not implemented, then this mode
cannot be selected.
• When Programmable TX_HDG_EMPTY Interrupt mode is not selected, none of the
logic is implemented and the mode cannot be enabled, reducing the overall gate
counts.
• When Programmable TX_HDG_EMPTY Interrupt mode is selected, it can be enabled
using the Interrupt Enable Register (INT_EN[7]).
When FIFOs and TX_HDG_EMPTY mode are implemented and enabled, the
TX_HDG_EMPTY Interrupts and dma_tx_req_n are active at, and below, a programmed
transmitter FIFO empty threshold level, as opposed to empty, as shown in the flowchart in
the following figure.
CLEAR INTR
For the THRE interrupt to be
controlled as shown here, the
following must be true:
- FIFO_MODE != NONE FIFO LEVEL>TX Y
- THRE_MODE == Enabled Empty Trigger?
- FIFOs enabled (FCR[0]==1)
- THRE mode enabled (IER[7] == 1)
N
THRE Interrupt N
Enabled?
Y
Under the condition that
there are no other pending SET INTR
interrupts, the interrupt
signal (intr) is asserted
FIFO LEVEL>TX N
Empty Trigger?
Y
Figure 9.23 Flowchart of Interrupt Generation
for Programmable THRE Interrupt Mode
The threshold level is programmed into FIFO_CTRL[5:4]. Available empty thresholds are:
empty, 2, ¼ , ½ . Selection of the best threshold value depends on the system's ability to
start a new transmission sequence in a timely manner. However, one of these thresholds
should be optimal for increasing system performance by preventing the transmitter FIFO
from running empty. For threshold setting details, refer to 10.7.4.6 FIFO_CTRL.
In addition to the interrupt change, the Line Status Register (LINE_STAT[5]) also switches
from indicating that the transmitter FIFO is empty to the FIFO being full. This allows
software to fill the FIFO for each transmit sequence by polling LINE_STAT[5] before writing
another character. The flow then allows the transmitter FIFO to be filled whenever an
interrupt occurs and there is data to transmit, rather than waiting until the FIFO is
completely empty. Waiting until the FIFO is empty causes a reduction in performance
whenever the system is too busy to respond immediately. Further system efficiency is
achieved when this mode is enabled in combination with Auto Flow Control.
Even if everything else is selected and enabled, if the FIFOs are disabled using the
FIFO_CTRL[0] bit, the Programmable TX_HDG_EMPTY Interrupt mode is also disabled.
When not selected or disabled, TX_HDG_EMPTY interrupts and the LSR[5] bit function
normally, signifying an empty TX_HDG or FIFO. The flowchart of THRE interrupt
generation when not in programmable THRE interrupt mode is shown in the following figure.
CLEAR INTR
For the THRE interrupt to be
controlled as shown here, one or
more of the following must be true:
- FIFO_MODE == NONE Y
- THRE_MODE == Disabled TX FIFO EMPTY?
- FIFOs disabled (FCR[0]==0)
- THRE mode disabled (IER[7] == 0)
N
THRE Interrupt N
Enabled?
Y
Under the condition that
there are no other pending SET INTR
interrupts, the interrupt
signal (intr) is asserted
TX FIFO Not Empty N

or IIR Read?
Y
Figure 9.24 Flowchart of Interrupt generation
when nor in Programmable THRE Interrupt Mode
9.5.3.9. Clock Gate Enable
The uart can be configured to have a clock gate enable output. When the clock enable
option is not selected, none of the logic is implemented, reducing the overall gate counts.
When the clock gate enable option is selected the clock gate enable signal(s)
(uart_lp_req_pclk for single clock implementations or uart_lp_req_pclk, uart_lp_req_sclk
for two clock implementations) is used to indicate that the transmit and receive pipeline is
clear (no data), no activity has occurred, and the modem control input signals have not
changed in more than one character time (the time taken to TX/RX a character) so clocks
may be gated. (A character is made up of: start bit + data bits + parity (optional) + stop
bit(s)). It is an indication that the UART is inactive, so clocks may be gated to put the device
in a low power (lp) mode. Therefore, the following must be true for at least one character
time for the assertion of the clock gate enable signal(s) to occur:
• No data in the RBR (in non-FIFO mode) or the RX FIFO is empty (in FIFO mode)
• No data in the THR (in non-FIFO mode) or the TX FIFO is empty (in FIFO mode)
• sin/sir_in and sout/sir_out_n are inactive (sin/sir_in are kept high and sout is high or
sir_out_n is low) indicating no activity
• No change on the modem control input signals
Note: the clock gate enable assertion does not occur in the following modes of operation:
• Loop-back mode
• FIFO access mode
• When transmitting a break
For example, assume a uart that is configured to have a single clock (pclk) and is
programmed to transmit and receive characters of 7 bits (1 start bit, 5 data bits and 1 stop
bit) and the baud clock divisor is set to 1. Therefore, the uart_lp_req_pclk signal is asserted
if the transmit and receive pipeline is clear, no activity has occurred and the modem control
input signals have not changed for 112 (7 × 16) pclk cycles. The following figure illustrates
this example .
16
cycles
pclk
sin stop
sout
busy(FSR[0])
baud_clk_cnt_Internal 0 1 2 110 111 0 1
uart_Ip_req
Figure 9.25 Clock Gate Enable Timing

When either of the signals sin or sir_in goes low, or a write to any of the registers is
performed, or the modem control input signals have changed when the uart is in low power
(sleep) mode, the clock gate enable signal(s) are de-asserted (as the assertion criteria are
no longer met) so that the clock(s) is resumed. The time taken for the clock(s) to resume
is important in the prevention of receive data synchronization problems. This is due to the
fact that the uart RX block samples at the mid-point of each bit period (after approximately
8 baud clocks) in UART (RS323) mode and then every 16 baud clocks after that for a baud
divisor of 1 that is 16 sclks (which for a single clock implementation is 16 pclks). Thus, if 8
or more sclk periods pass before the serial clock starts up again, the UART may get out of
sync with the serial data it is receiving. That is, the receiver may sample into the second
bit period and if it is still zero, think this is the start bit and so on. Therefore, to avoid this
problem the clock should be resumed within 5 clock periods of the baud clock, which is the
same as sclk if the baud divisor is set to one. This is worst case. If the divisor is greater, it
gives a greater number of sclk cycles available before the clock must resume. This means
a sample point at the 13 baud clock (at the latest) out of the 16 that is transmitted for each
bit period of the character in non-SIR mode.
The following figure shows the timing diagram that illustrates the previous scenario. This
problem is magnified in SIR mode as the pulse width is only 3/16 of a bit period (3 baud
clocks, which for a divisor of 1 is 3 sclks). Hence, it could be missed completely. The clocks
must resume before 3 baud clock periods elapse. If the first character received while in
sleep mode is used purely for wakeup reasons and the actual character value is
unimportant, this may not be a problem at all.
Actual Latest sample
Clock(s) resume midpoint sample point point
after 2 bclk periods
bclk(=sclk when div.=1)
sin
uart_Ip_req
Figure 9.26 Resuming Clock(s) After Low Power Mode Timing

When the uart is configured to have two clocks, if the timing of the received signal is not
affected by the synchronization problem, then the minimum time to receive a character, if
the baud divisor is 1, is 112 sclks (1 start bit + 5 data bits + 1 stop bit = 7 × 16 =112).
Therefore, the pclk must be available before 112 sclk cycles pass so that the received
character can be synchronized over to the pclk domain and stored in the RBR (in non-FIFO
mode) or the RX FIFO (in FIFO mode).
9.5.4. UART1 Register Map
Offset RW Reset Name Description

0x0000 R 0x0 RBR Receive Buffer Register
Dependencies:LCR[7]bit = 0
W 0x0 THR Transmit Holding Register
Dependencies:LCR[7]bit = 0
R/W 0x0 DLL Divisor Latch (Low)
Dependencies: LCR[7] bit = 1
0x0004 R/W 0x0 DLH Divisor Latch (High)
R/W 0x0 IER Interrupt Enable Register
0x0008 R 0x01 IIR Interrupt Identification Register
W 0x0 FCR FIFO Control Register
0x000C R/W 0x0 LCR Line Control Register
0x0010 R/W 0x0 MCR Modem Control Register
0x0014 R 0x60 LSR Line Status Register
0x0018 R 0x0 MSR Modem Status Register
0X001C R/W 0x0 SCR Scratchpad Register
0x0020 R/W 0x0 LPDLL Low Power Divisor Latch (Low)
Register
0x0024 R/W 0x0 LPDLH Low Power Divisor Latch (High)
Register
0x0028 ISO7816_CTRL0 ISO7816 Control Register
(only valid in UART1)
0x002C ISO7816_CTRL1 ISO7816 Control Register
(only valid in UART1)
0x0030- R 0x0 SRBR Shadow Receive Buffer Register
-0x006C Dependencies: LCR[7] bit = 0
W 0x0 STHR Shadow Transmit Holding
Register
0x0070 R/W 0x0 FAR FIFO Access Register
0x0074 R 0x0 TFR Transmit FIFO Read
0x0078 W 0x0 RFW Receive FIFO Write
0x007C R 0x6 USR UART Status Register
0x0080 R 0x0 TFL Transmit FIFO Level
Width: FIFO_ADDR_WIDTH + 1
0x0084 R 0x0 RFL Receive FIFO Level
Width: FIFO_ADDR_WIDTH + 1
0x0088 W 0x0 SRR Software Reset Register
0x008C R/W 0x0 SRTS Shadow Request to Send
0x0090 R/W 0x0 SBCR Shadow Break Control Register
0x0094 R/W 0x0 SDMAM Shadow DMA Mode
0x0098 R/W 0x0 SFE Shadow FIFO Enable
0x009C R/W 0x0 SRT Shadow RCVR Trigger
0x00A0 R/W 0x0 STET Shadow TX Empty Trigger
0x00A4 R/W 0x0 HTX Halt TX
0x00A8 W 0x0 DMASA DMA Software Acknowledge
0x00AC-
0x00F0
0x00F4 R Configuration- CPR Component Parameter Register
dependent
0x00F8 R See the UCV UART Component Version
Releases table
in the AMBA 2
release notes.
0x00FC R 0x44570110 CTR Component Type Register
RBR address offset: 0x0000

7:0 R 0x0 RBR Data byte received on the serial input port (sin) in
UART mode, or the serial infrared input (sir_in) in
infrared mode. The data in this register is valid only
if the Data Ready (DR) bit in the Line Status
Register (LCR) is set.
If in non-FIFO mode (FIFO_MODE == NONE) or
FIFOs are disabled (FCR[0] set to zero), the data in
the RBR must be read before the next data arrives,
otherwise it is overwritten, resulting in an over-run
error.
If in FIFO mode (FIFO_MODE != NONE) and FIFOs
are enabled (FCR[0] set to one), this register
accesses the head of the receive FIFO. If the
receive FIFO is full and this register is not read
before the next data character arrives, then the data
already in the FIFO is preserved, but any incoming
data are lost and an overrun error occurs.
THR address offset: 0x0000

7:0 W 0x0 THR Data to be transmitted on the serial output port
(sout) in UART mode or the serial infrared output
(sir_out_n) in infrared mode. Data should only be
written to the THR when the THR Empty (THRE) bit
(LSR[5]) is set.
If in non-FIFO mode or FIFOs are disabled (FCR[0]
= 0) and THRE is set, writing a single character to
the THR clears the THRE. Any additional writes to
the THR before the THRE is set again causes the
THR data to be overwritten.
If in FIFO mode and FIFOs are enabled (FCR[0] =
1) and THRE is set, x number of characters of data
may be written to the THR before the FIFO is full.
The number x (default=16) is determined by the
value of FIFO Depth that you set during
configuration. Any attempt to write data when the
FIFO is full results in the write data being lost.
DLH address offset: 0x0004

7:0 RW 0x0 DLH Upper 8-bits of a 16-bit, read/write, Divisor Latch
register that contains the baud rate divisor for the
UART.
The output baud rate is equal to the serial clock (pclk
if one clock design, sclk if two clock design
(CLOCK_MODE == Enabled)) frequency divided by
sixteen times the value of the baud rate divisor, as
follows: baud rate = (serial clock freq) / (16 * divisor).
Note that with the Divisor Latch Registers (DLL and
DLH) set to zero, the baud clock is disabled and no
serial communications occur. Also, once the DLH is
set, at least 8 clock cycles of the slowest uart clock
should be allowed to pass before transmitting or
receiving data.
DLL address offset: 0x0000

7:0 RW 0x0 DLL Lower 8 bits of a 16-bit, read/write, Divisor Latch
register that contains the baud rate divisor for the
UART.
The output baud rate is equal to the serial clock (pclk
if one clock design, sclk if two clock design
(CLOCK_MODE == Enabled)) frequency divided by
sixteen times the value of the baud rate divisor, as
follows: baud rate = (serial clock freq) / (16 * divisor).
Note that with the Divisor Latch Registers (DLL and
DLH) set to zero, the baud clock is disabled and no
serial communications occur. Also, once the DLL is
set, at least 8 clock cycles of the slowest uart clock
should be allowed to pass before transmitting or
receiving data.
IER address offset: 0x0004
7 RW 0x0 PTIME This is used to enable/disable the generation of
THRE Interrupt
0 = disabled
1 = enabled
3 RW 0x0 EDSSI Enable Modem Status Interrupt. This is used to
enable/disable the generation of Modem Status
Interrupt. This is the fourth highest priority interrupt.
0 = disabled
1 = enabled
2 RW 0x0 ELSI Enable Receiver Line Status Interrupt. This is used
to enable/disable the generation of Receiver Line
Status Interrupt. This is the highest priority interrupt
0 = disabled
1 = enabled
1 RW 0x0 ETBEI Enable Transmit Holding Register Empty Interrupt.
This is used to enable/disable the generation of
Transmitter Holding Register Empty Interrupt. This
is the third highest priority interrupt.
0 = disabled
1 = enabled
0 RW 0x0 ERBFI Enable Received Data Available Interrupt. This is
used to enable/disable the generation of Received
Data Available Interrupt and the Character Timeout
Interrupt (if in FIFO mode and FIFOs enabled).
These are the second highest priority interrupts.
0 = disabled
1 = enabled
IIR address offset: 0x0008

7:6 R 0x0 FIFOSE FIFOs Enabled. This is used to indicate whether
the FIFOs are enabled or disabled.
00 = disabled
11 = enabled
3:0 R 0x1 IID Interrupt ID. This indicates the highest priority
pending interrupt which can be one of the following
types
0000 = modem status
0001 = no interrupt pending
0010 = THR empty
0100 = received data available
0110 = receiver line status
0111 = busy detect
1100 = character timeout
FCR address offset: 0x0008

7:6 W 0x0 RT RCVR Trigger. This is used to select the trigger
level in the receiver FIFO at which the Received
Data Available Interrupt is generated. In auto flow
control mode it is used to determine when the
rts_n signal is de-asserted. For details on DMA
support, The following trigger levels are supported:
00 = 1 character in the FIFO
01 = FIFO/4 full
10 = FIFO/2 full
11 = FIFO 2 less than full
5:4 W 0x0 TET TX Empty Trigger. This is used to select the empty
threshold level at which the THRE Interrupts are
generated when the mode is active. For details on
DMA support, The following trigger levels are
supported:
00 = FIFO empty
01 = 2 characters in the FIFO
10 = FIFO/4 full
11 = FIFO/2 full
3 W 0x0 DMAM DMA Mode. For details on DMA support,
0 = mode 0;
1 = mode 1
2 W 0x0 XFIFOR XMIT FIFO Reset. This resets the control portion
of the transmit FIFO and treats the FIFO as empty.
This bit is 'self-clearing'.
1 W 0x0 RFIFOR RCVR FIFO Reset. This resets the control portion
of the receive FIFO and treats the FIFO as empty.
This bit is 'self-clearing'.
0 W 0x0 FIFOE FIFO Enable. This enables/disables the transmit
(XMIT) and receive (RCVR) FIFOs.Whenever the
value of this bit is changed both the XMIT and
RCVR controller portion of FIFOs is reset.
LCR address offset: 0x000C
7 RW 0x0 DLAB Divisor Latch Access Bit. This bit is used to enable
reading and writing of the Divisor Latch register (DLL
and DLH) to set the baud rate of the UART.
6 RW 0x0 BC Break Control Bit.This is used to cause a break
condition to be transmitted to the receiving device. If
set to one the serial output is forced to the spacing
(logic 0) state. When not in Loop back Mode, as
determined by MCR[4], the sout line is forced low
until the Break bit is cleared. If SIR_MODE ==
Enabled and active (MCR[6] set to one) the sir_out_n
line is continuously pulsed. When in Loop back
Mode, the break condition is internally looped back to
the receiver and the sir_out_n line is forced low.
4 RW 0x0 EPS Even Parity Select.If UART_16550_COMPATIBLE
== NO, then write able only when UART is not busy
(USR[0] is zero); otherwise always writable, always
readable. This is used to select between even and
odd parity, when parity is enabled (PEN set to one).
If set to one, an even number of logic 1s is
transmitted or checked. If set to zero, an odd number
of logic 1s is transmitted or checked.
0 = mode 0
1 = mode 1
3 RW 0x0 PEN Parity Enable.If UART_16550_COMPATIBLE == NO,
then writable only when UART is not busy (USR[0] is
zero); otherwise always writable, always readable.
This bit is used to enable and disable parity
generation and detection in transmitted and received
serial character respectively
0 = parity disabled
1 = parity enabled
2 RW 0x0 STOP Number of stop bits.
If UART_16550_COMPATIBLE == NO, then write
able only when UART is not busy (USR[0] is zero);
otherwise always writable, always readable. This is
used to select the number of stop bits per character
that the peripheral transmits and receives. If set to
zero, one stop bit is transmitted in the serial data.
If set to one and the data bits are set to 5 (LCR[1:0]
set to zero) one and a half stop bits is transmitted.
Otherwise, two stop bits are transmitted. Note that
regardless of the number of stop bits selected, the
receiver checks only the first stop bit.
0 = 1 stop bit
1 = 1.5 stop bits (DLS==0)
1 = 2 stop bits (DLS!=0)
1:0 RW 0x0 DLS Data Length Select
This is used to select the number of data bits per
character that the peripheral transmits and receives.
The number of bit that may be selected areas
follows:
00 = 5 bits
01 = 6 bits
10 = 7 bits
11 = 8 bits
MCR address offset: 0x0010

6 RW 0x0 SIRE SIR Mode Enable.
0 = disable
1 = enable
5 RW 0x0 AFCE Auto Flow Control Enable.
0 = Auto Flow Control Mode disabled
1 = Auto Flow Control Mode enabled
4 RW 0x0 LB Loop Back Bit. This is used to put the UART into a
diagnostic mode for test purposes.
If operating in UART mode (SIR_MODE != Enabled
or not active, MCR[6] set to zero), data on the sout
line is held high, while serial data output is looped
back to the sin line, internally. In this mode all the
interrupts are fully functional. Also, in loop back
mode, the modem control inputs (dsr_n, cts_n, ri_n,
dcd_n) are disconnected and the modem control
outputs (dtr_n, rts_n, out1_n, out2_n) are looped
back to the inputs, internally.
If operating in infrared mode (SIR_MODE ==
Enabled AND active, MCR[6] set to one), data on the
sir_out_n line is held low, while serial data output is
inverted and looped back to the sir_in line.
3 RW 0x0 OUT2 OUT2. This is used to directly control the user-
designated Output2 (out2_n) output. The value
written to this location is inverted and driven out on
out2_n, that is:
0 = out2_n de-asserted (logic 1)
1 = out2_n asserted (logic 0)
2 RW 0x0 OUT1 OUT1. This is used to directly control the user-
designated Output1 (out1_n) output. The value
out1_n, that is:
0 = out1_n de-asserted (logic 1)
1 = out1_n asserted (logic 0)
1 RW 0x0 RTS Request to Send. This is used to directly control the
Request to Send (rts_n) output. The Request To
Send (rts_n) output is used to inform the modem or
data set that the UART is ready to exchange data.
When Auto RTS Flow Control is not enabled (MCR[5]
set to zero), the rts_n signal is set low by
programming MCR[1] (RTS) to a high.In Auto Flow
Control, AFCE_MODE == Enabled and active
(MCR[5] set to one) and FIFOs enable (FCR[0] set to
one), the rts_n output is controlled in the same way,
but is also gated with the receiver FIFO threshold
trigger (rts_n is inactive high when above the
threshold). The rts_n signal is de-asserted when
MCR[1] is set low.
Note that in Loop back mode (MCR[4] set to one),
the rts_n output is held inactive high while the value
of this location is internally looped back to an input.
0 RW 0x0 DTR Data Terminal Ready. This is used to directly control
the Data Terminal Ready (dtr_n) output. The value
dtr_n, that is:
0 = dtr_n de-asserted (logic 1)
1 = dtr_n asserted (logic 0)
LSR address offset: 0x0014

7 R 0x0 RFE Receiver FIFO Error bit.This bit is only relevant when
FIFO_MODE != NONE AND FIFOs are enabled
(FCR[0] set to one). This is used to indicate if there is
at least one parity error, framing error, or break
indication in the FIFO.
0 = no error in RX FIFO
1 = error in RX FIFO
6 R 0x1 TEMT Transmitter Empty bit. If in FIFO mode
(FIFO_MODE != NONE) and FIFOs enabled (FCR[0]
set to one), this bit is set whenever the Transmitter
Shift Register and the FIFO are both empty. If in non-
FIFO mode or FIFOs are disabled, this bit is set
whenever the Transmitter Holding Register and the
Transmitter Shift Register are both empty.
5 R 0x1 THRE Transmit Holding Register Empty bit.If
THRE_MODE_USER == Disabled or THRE mode is
disabled (IER[7] set to zero) and regardless of
FIFO's being implemented/enabled or not, this bit
indicates that the THR or TX FIFO is empty.
This bit is set whenever data is transferred from the
THR or TX FIFO to the transmitter shift register and
no new data has been written to the THR or TX
FIFO. This also causes a THRE Interrupt to occur, if
the THRE Interrupt is enabled. If
THRE_MODE_USER == Enabled AND
FIFO_MODE != NONE and both modes are active
(IER[7] set to one and FCR[0] set to one
respectively), the functionality is switched to indicate
the transmitter FIFO is full, and no longer controls
THRE interrupts, which are then controlled by the
FCR[5:4] threshold setting.
4 R 0x0 BI Break Interrupt bit. This is used to indicate the
detection of a break sequence on the serial input
data.
If in UART mode (SIR_MODE == Disabled), it is set
whenever the serial input, sin, is held in a logic '0'
state for longer than the sum of start time + data bits
+ parity + stop bits.
If in infrared mode (SIR_MODE == Enabled), it is set
whenever the serial input, sir_in, is continuously
pulsed to logic '0' for longer than the sum of start
time + data bits + parity + stop bits. A break condition
on serial input causes one and only one character,
consisting of all zeros, to be received by the UART.
In the FIFO mode, the character associated with the
break condition is carried through the FIFO and is
revealed when the character is at the top of the
FIFO.
Reading the LSR clears the BI bit. In the non-FIFO
mode, the BI indication occurs immediately and
persists until the LSR is read.
3 R 0x0 FE Framing Error bit.This is used to indicate the
occurrence of a framing error in the receiver. A
framing error occurs when the receiver does not
detect a valid STOP bit in the received data.
In the FIFO mode, since the framing error is
associated with a character received, it is revealed
when the character with the framing error is at the
top of the FIFO.
When a framing error occurs, the UART tries to
resynchronize. It does this by assuming that the error
was due to the start bit of the next character and
then
continues receiving the other bit i.e. data, and/or
parity and stop. It should be noted that the Framing
Error (FE) bit (LSR[3]) is set if a break interrupt has
occurred, as indicated by Break Interrupt (BI) bit
(LSR[4]).
0 = no framing error
1 =framing error
2 R 0x0 PE Parity Error bit.This is used to indicate the
occurrence of a parity error in the receiver if the
Parity Enable (PEN) bit (LCR[3]) is set.
In the FIFO mode, since the parity error is associated
with a character received, it is revealed when the
character with the parity error arrives at the top of the
FIFO.
It should be noted that the Parity Error (PE) bit
(LSR[2]) is set if a break interrupt has occurred, as
indicated by Break Interrupt (BI) bit (LSR[4]).
0 = no parity error
1 = parity error
1 R 0x0 OE Overrun error bit.This is used to indicate the
occurrence of an overrun error.
This occurs if a new data character was received
before the previous data was read.
In the non-FIFO mode, the OE bit is set when a new
character arrives in the receiver before the previous
character was read from the RBR. When this
happens, the data in the RBR is overwritten. In the
FIFO mode, an overrun error occurs when the FIFO
is full and a new character arrives at the receiver.
The data in the FIFO is retained and the data in the
receive shift register is lost.
0 = no overrun error
1 = overrun error
0 R 0x0 DR Data Ready bit. This is used to indicate that the
receiver contains at least one character in the RBR
or the receiver FIFO.
0 = no data ready
1 = data ready
MSR address offset: 0x0018
7 R 0x0 DCD Data Carrier Detect.This is used to indicate the current
state of the modem control line dcd_n. This bit is the
complement of dcd_n. When the Data Carrier Detect
input (dcd_n) is asserted it is an indication that the
carrier has been detected by the modem or data set.
0 = dcd_n input is de-asserted (logic 1)
1 = dcd_n input is asserted (logic 0)
6 R 0x0 RI Ring Indicator. This is used to indicate the current
state of the modem control line ri_n. This bit is the
complement of ri_n. When the Ring Indicator input
(ri_n) is asserted it is an indication that a telephone
ringing signal has been received by the modem or
data set.
0 = ri_n input is de-asserted (logic 1)
1 = ri_n input is asserted (logic 0)
5 R 0x0 DSR Data Set Ready.This is used to indicate the current
state of the modem control line dsr_n. This bit is the
complement of dsr_n. When the Data Set Ready input
(dsr_n) is asserted it is an indication that the modem
or data set is ready to establish communications with
the OM_uart.
0 = dsr_n input is de-asserted (logic 1)
1 = dsr_n input is asserted (logic 0)
4 R 0x0 CTS Clear to Send.This is used to indicate the current state
of the modem control line cts_n. This bit is the
complement of cts_n. When the Clear to Send input
(cts_n) is asserted it is an indication that the modem or
data set is ready to exchange data with the OM_uart.
0 = cts_n input is de-asserted (logic 1)
1 = cts_n input is asserted (logic 0)
3 R 0x0 DDCD Delta Data Carrier Detect.This is used to indicate that
the modem control line dcd_n has changed since the
last time the MSR was read.
0 = no change on dcd_n since last read of MSR
1 = change on dcd_n since last read of MSR
Reading the MSR clears the DDCD bit. In Loop back
Mode (MCR[4] = 1), DDCD reflects changes on
MCR[3] (Out2).
Note, if the DDCD bit is not set and the dcd_n signal is
asserted (low) and a reset occurs (software or
otherwise), then the DDCD bit is set when the reset is
removed if the dcd_n signal remains asserted.
2 R 0x0 TERI Trailing Edge of Ring Indicator.This is used to indicate
that a change on the input ri_n (from an active-low to
an inactive-high state) has occurred since the last time
the MSR was read.
0 = no change on ri_n since last read of MSR
1 = change on ri_n since last read of MSR
1 R 0x0 DDSR Delta Data Set Ready.This is used to indicate that the
modem control line dsr_n has changed since the last
time the MSR was read.
0 = no change on dsr_n since last read of MSR
1 = change on dsr_n since last read of MSR
Reading the MSR clears the DDSR bit. In Loop back
Mode (MCR[4] = 1), DDSR reflects changes on
MCR[0] (DTR).
Note, if the DDSR bit is not set and the dsr_n signal is
otherwise), then the DDSR bit is set when the reset is
removed if the dsr_n signal remains asserted.
0 R 0x0 DCTS Delta Clear to Send.This is used to indicate that the
modem control line cts_n has changed since the last
time the MSR was read.
0 = no change on cts_n since last read of MSR
1 = change on cts_n since last read of MSR
Reading the MSR clears the DCTS bit. In Loop back
Mode (MCR[4] = 1), DCTS reflects changes on
MCR[1] (RTS).
Note, if the DCTS bit is not set and the cts_n signal is
otherwise), then the DCTS bit is set when the reset is
removed if the cts_n signal remains asserted.
SCR address offset: 0x001C

31:8 N/A 0x0 N/A Reserved and read as zero
7:0 RW 0x0 Scratchpad This register is for programmers to use as a
Register temporary storage space. It has no defined
purpose in the OM_uart.
LPDLL address offset: 0x0020
7:0 RW 0x0 LPDLL This register makes up the lower 8-bits of a 16-bit,
read/write, Low Power Divisor Latch register that
contains the baud rate divisor for the UART,which
must give a baud rate of 115.2K. This is required for
SIR Low Power (minimum pulse width) detection at
the receiver. If UART_16550_COMPATIBLE == No,
then this register may only be accessed when the
DLAB bit (LCR[7]) is set and the UART is not busy
(USR[0] is zero); otherwise this register may be
accessed only when the DLAB bit (LCR[7]) is set.
The output low-power baud rate is equal to the
serial clock (sclk) frequency divided by sixteen
times the value of the baud rate divisor, as follows:
Low power baud rate = (serial clock frequency)/(16*
divisor)
Therefore, a divisor must be selected to give a baud
rate of 115.2K.
NOTE: When the Low Power Divisor Latch registers
(LPDLL and LPDLH) are set to 0, the low-power
baud clock is disabled and no low-power pulse
detection (or any pulse detection) occurs at the
receiver. Also, once the LPDLL is set, at least eight
clock cycles of the slowest uart clock should be
allowed to pass before transmitting or receiving
data.
LPDLH address offset: 0x0024

7:0 RW 0x0 LPDLL This register makes up the upper 8-bits of a 16-bit,
read/write, Low Power Divisor Latch register that
contains the baud rate divisor for the UART,which
must give a baud rate of 115.2K. This is required for
SIR Low Power (minimum pulse width) detection at
the receiver. If UART_16550_COMPATIBLE == No,
then this register may only be accessed when the
DLAB bit (LCR[7]) is set and the UART is not busy
(USR[0] is zero); otherwise this register may be
accessed only when the DLAB bit (LCR[7]) is set.
The output low-power baud rate is equal to the
serial clock (sclk) frequency divided by sixteen
times the value of the baud rate divisor, as follows:
Low power baud rate = (serial clock frequency)/(16*
divisor)
Therefore, a divisor must be selected to give a baud
rate of 115.2K.
NOTE: When the Low Power Divisor Latch registers
(LPDLL and LPDLH) are set to 0, the low-power
baud clock is disabled and no low-power pulse
detection (or any pulse detection) occurs at the
receiver. Also, once the LPDLH is set, at least eight
clock cycles of the slowest uart clock should be
allowed to pass before transmitting or receiving
data.
ISO7816_CTRL0 address offset: 0x0028

12 R 0x0 tx_done TX is done
11:4 RW 0x0 sample sample_dly is used to adjust the sample timing of
_dly SIN
3 RW 0x0 retrans_ parity error re-trans enable
en
2 RW 0x0 trx_oen 0: TX
1: RX
1 RW 0x0 nack_e noack is enable
nable
0 RW 0x0 iso7816 ISO7816 is enable
_en
ISO7816_CTRL1 address offset: 0x002C

15:8 R 0x0 tx_perr_cnt tx parity error counter
7:0 R 0x0 rx_perr_cnt rx parity error counter
SRBR address offset: 0x0030--0x006C

7:0 R 0x0 SRBR This is a shadow register for the RBR and has been
allocated sixteen 32-bit locations so as to
accommodate burst accesses from the master. This
register contains the data byte received on the serial
input port (sin) in UART mode or the serial infrared
input (sir_in) in infrared mode. The data in this
register is valid only if the Data Ready (DR) bit in the
Line status Register (LSR) is set.
If in non-FIFO mode (FIFO_MODE == NONE) or
FIFOs are disabled (FCR[0] set to zero), the data in
the RBR must be read before the next data arrives,
otherwise it is overwritten, resulting in an overrun
error.
If in FIFO mode (FIFO_MODE != NONE) and FIFOs
are enabled (FCR[0] set to one), this register
accesses the head of the receive FIFO. If the receive
FIFO is full and this register is not read before the
next data character arrives, then the data already in
the FIFO are preserved, but any incoming data is
lost. An overrun error also occurs.
STHR address offset: 0x0030--0x006C

7:0 W 0x0 STHR This is a shadow register for the THR and has been
allocated sixteen 32-bit locations so as to
accommodate burst accesses from the master. This
register contains data to be transmitted on the serial
output port (sout) in UART mode or the serial infrared
output (sir_out_n) in infrared mode. Data should only
be written to the THR when the THR Empty (THRE)
bit (LSR[5]) is set.
If in non-FIFO mode or FIFOs are disabled (FCR[0]
set to zero) and THRE is set, writing a single
character to the THR clears the THRE. Any additional
writes to the THR before the THRE is set again
causes the THR data to be overwritten.
If in FIFO mode and FIFOs are enabled (FCR[0] set
to one) and THRE is set, x number of characters of
data may be written to the THR before the FIFO is
full. The number x (default=16) is determined by the
value of FIFO Depth that you set during
configuration. Any attempt to write data when the
FIFO is full results in the write data being lost.
FAR address offset: 0x0070

0 RW 0x0 FIFO Writes have no effect when FIFO_ACCESS ==
Access No, always readable. This register is use to
Register enable a FIFO access mode for testing, so that
the receive FIFO can be written by the master
and the transmit FIFO can be read by the master
when FIFOs are implemented and enabled.
When FIFOs are not implemented or not enabled
it allows the RBR to be written by the master and
the THR to be read by the master.
0 = FIFO access mode disabled
1 = FIFO access mode enabled
Note, that when the FIFO access mode is
enabled/disabled, the control portion of the
receive FIFO and transmit FIFO is reset and the
FIFOs are treated as empty.
TFR address offset: 0x0074

7:0 R 0x0 Transmit Transmit FIFO Read. These bits are only valid
FIFO when FIFO access mode is enabled (FAR[0] is
Read set to one).
When FIFOs are implemented and enabled,
reading this register gives the data at the top of
the transmit FIFO. Each consecutive read pops
the transmit FIFO and gives the next data value
that is currently at the top of the FIFO.
When FIFOs are not implemented or not
enabled, reading this register gives the data in
the THR.
RFW address offset: 0x0078

9 W 0x0 RFFE Receive FIFO Framing Error. These bits are only
valid when FIFO access mode is enabled
(FAR[0] is set to one). When FIFOs are
implemented and enabled, this bit is used to
write framing error detection information to the
receive FIFO. When FIFOs are not implemented
or not enabled, this bit is used to write framing
error detection information to the RBR.
8 W 0x0 RFPE Receive FIFO Parity Error. These bits are only
implemented and enabled, this bit is used to
write parity error detection information to the
receive FIFO.
When FIFOs are not implemented or not
enabled, this bit is used to write parity error
detection information to the RBR.
7:0 W 0x0 RFWD Receive FIFO Write Data. These bits are only
implemented and enabled, the data that is written
to the RFWD is pushed into the receive FIFO.
Each consecutive write pushes the new data to
the next write location in the receive FIFO. When
FIFOs are not implemented or not enabled, the
data that is written to the RFWD is pushed into
the RBR.
USR address offset: 0x007C

4 R 0x0 RFF Receive FIFO Full.This bit is only valid when
FIFO_STAT == YES. This is used to indicate that
the receive FIFO is completely full.
0 = Receive FIFO not full
1 = Receive FIFO Full
3 R 0x0 RFNE Receive FIFO Not Empty.This bit is only valid
when FIFO_STAT == YES. This is used to
indicate that the receive FIFO contains one or
more entries.
0 = Receive FIFO is empty
1 = Receive FIFO is not empty
2 R 0x1 TFE Transmit FIFO Empty.This bit is only valid when
the transmit FIFO is completely empty.
0 = Transmit FIFO is not empty
1 = Transmit FIFO is empty
1 R 0x1 TFNF Transmit FIFO Not Full.This bit is only valid when
the transmit FIFO in not full.
0 = Transmit FIFO is full
1 = Transmit FIFO is not full
0 R 0x0 BUSY UART Busy.This bit is valid only when
UART_16550_COMPATIBLE == NO and
indicates that a serial transfer is in progress, ;
when cleared, indicates that the uart is idle or
inactive.
0 = uart is idle or inactive
1 = uart is busy (actively transferring data)
TFL address offset: 0x0080

4:0 R 0x0 TFL Transmit FIFO Level. This is indicates the
number of data entries in the transmit FIFO.
RFL address offset: 0x0084

4:0 R 0x0 RFL Receive FIFO Level. This is indicates the number
of data entries in the receive FIFO.
SRR address offset: 0x0088

2 W 0x0 XFR XMIT FIFO Reset.
This is a shadow register for the XMIT FIFO
Reset bit (FCR[2]). This can be used to remove
the burden on software having to store previously
written FCR values (which are pretty static) just
to reset the transmit FIFO. This resets the control
portion of the transmit FIFO and treats the FIFO
as empty. This also de-asserts the DMA TX
request and single signals when additional DMA
handshaking signals are selected (DMA_EXTRA
== YES).
Note that this bit is 'self-clearing'. It is not
necessary to clear this bit.
1 W 0x0 RFR RCVR FIFO Reset.
This is a shadow register for the RCVR FIFO
Reset bit (FCR[1]). This can be used to remove
the burden on software having to store previously
written FCR values (which are pretty static) just
to reset the receive FIFO This resets the control
portion of the receive FIFO and treats the FIFO
as empty. This also de-asserts the DMA RX
request and single signals when additional DMA
handshaking signals are selected (DMA_EXTRA
== YES).
Note that this bit is 'self-clearing'. It is not
0 W 0x0 UR UART Reset.
This asynchronously resets the uart and
synchronously removes the reset assertion.For a
two clock implementation both pclk and sclk
domains are reset.
SRTS address offset: 0x008C

0 RW 0x0 SRTS Shadow Request to Send.
This is a shadow register for the RTS bit
(MCR[1]), this can be used to remove the burden
of having to performing a read-modify-write on
the MCR. This is used to directly control the
Request to Send (rts_n) output. The Request To
Send (rts_n) output is used to inform the modem
or data set that the uart is ready to exchange
data.
When Auto RTS Flow Control is not enabled
(MCR[5] = 0), the rts_n signal is set low by
programming MCR[1] (RTS) to a high.
In Auto Flow Control, AFCE_MODE == Enabled
and active (MCR[5] = 1) and FIFOs enable
(FCR[0] = 1), the rts_n output is controlled in the
same way, but is also gated with the receiver
FIFO threshold trigger (rts_n is inactive high
when above the threshold).
Note that in Loopback mode (MCR[4] = 1), the
rts_n output is held inactive-high while the value
of this location is internally looped back to an
input.
SBCR address offset: 0x0090

0 RW 0x0 SBCR Shadow Break Control Bit.
This is a shadow register for the Break bit
(LCR[6]), this can be used to remove the burden
of having to performing a read modify write on
the LCR. This is used to cause a break condition
to be transmitted to the receiving device.
If set to one the serial output is forced to the
spacing (logic 0) state. When not in Loopback
Mode, as determined by MCR[4], the sout line is
forced low until the Break bit is cleared.
If SIR_MODE == Enabled and active (MCR[6] =
1) the sir_out_n line is continuously pulsed.
When in Loopback Mode, the break condition is
internally looped back to the receiver.
SDMAM address offset: 0x0094

0 RW 0x0 SDMAM Shadow DMA Mode.
This is a shadow register for the DMA mode bit
(FCR[3]). This can be used to remove the
burden of having to store the previously written
value to the FCR in memory and having to mask
this value so that only the DMA Mode bit gets
updated. This determines the DMA signaling
mode used for the dma_tx_req_n and
dma_rx_req_n output signals when additional
DMA handshaking signals are not selected
(DMA_EXTRA == NO).
0 = mode 0
1 = mode 1
SFE address offset: 0x0098

0 RW 0x0 SFE Shadow FIFO Enable.
This is a shadow register for the FIFO enable bit
(FCR[0]). This can be used to remove the
this value so that only the FIFO enable bit gets
updated.This enables/disables the transmit
(XMIT) and receive (RCVR) FIFOs. If this bit is
set to zero (disabled) after being enabled then
both the XMIT and RCVR controller portion of
FIFOs are reset.
SRT address offset: 0x009C

1:0 RW 0x0 SRT Shadow RCVR Trigger.
This is a shadow register for the RCVR trigger
bits (FCR[7:6]).This can be used to remove the
this value so that only the RCVR trigger bit gets
updated.
This is used to select the trigger level in the
receiver FIFO at which the Received Data
Available Interrupt is generated. It also
determines when the dma_rx_req_n signal is
asserted when DMA Mode (FCR[3]) = 1. The
following trigger levels are supported:
00 = 1 character in the FIFO
01 = FIFO ¼ full
10 = FIFO ½ full
11 = FIFO 2 less than full
STET address offset: 0x00A0

1:0 RW 0x0 STET Shadow TX Empty Trigger.
This is a shadow register for the TX empty
trigger bits (FCR[5:4]). This can be used to
remove the burden of having to store the
previously written value to the FCR in memory
and having to mask this value so that only the
TX empty trigger bit gets updated.
This is used to select the empty threshold level
at which the THRE Interrupts are generated
when the mode is active. The following trigger
levels are supported:
00 = FIFO empty
01 = 2 characters in the FIFO
10 = FIFO ¼ full
11 = FIFO ½ full
Dependencies: Writes have no effect when
THRE_MODE_USER = = Disabled.
HTX address offset: 0x00A4

0 RW 0x0 HTX This register is used to halt transmissions for
testing, so that the transmit FIFO can be filled by
the master when FIFOs are implemented and
enabled.
0 = Halt TX disabled
1 = Halt TX enabled
Note, if FIFOs are implemented and not enabled,
the setting of the halt TX register has no effect
on operation.
Dependencies: Writes have no effect when
FIFO_MODE == None.
DMASA address offset: 0x00A8
0 W 0x0 DMASA This register is use to perform a DMA software
acknowledge if a transfer needs to be terminated
due to an error condition. For example, if the
DMA disables the channel, then the uart should
clear its request. This causes the TX request, TX
single, RX request and RX single signals to de-
assert. Note that this bit is 'self-clearing'. It is not
CPR address offset: 0x00F4

23:16 R 0x0 FIFO_MO 0x00 = 0
DE 0x01 = 16
0x02 = 32
to
0x80 = 2048
0x81- 0xff = reserved
15:14 R 0x0 N/A Reserved and read as zero
13 R 0x0 DMA_EXT 0 = FALSE
RA 1 = TRUE
12 R 0x0 UART_AD 0 = FALSE
D_ENCOD 1 = TRUE
ED_PARA
MS
11 R 0x0 SHADOW 0 = FALSE
1 = TRUE
10 R 0x0 FIFO_STA 0 = FALSE
T 1 = TRUE
9 R 0x0 FIFO_ACC 0 = FALSE
ESS 1 = TRUE
8 R 0x0 ADDITION 0 = FALSE
AL_FEAT 1 = TRUE
7 R 0x0 SIR_LP_M 0 = FALSE
ODE 1 = TRUE
6 R 0x0 SIR_MOD 0 = FALSE
E 1 = TRUE
5 R 0x0 THRE_MO 0 = FALSE
DE 1 = TRUE
4 R 0x0 AFCE_MO 0 = FALSE
DE 1 = TRUE
1:0 R 0x0 APB_DATA 00 = 8 bits
_WIDTH 01 = 16 bits
10 = 32 bits
11 = reserved
UCV address offset: 0x00F8

31:0 R See the releases UART ASCII value for each number in the
table in the Component version, followed by *. For example
AMBA 2 release Version 32_30_31_2A represents the version
notes. 2.01*
CTR address offset: 0x00FC

31:0 R 0x445 Peripheral This register contains the peripherals
70110 ID identification code.
9.6. UART0
9.6.1. Introduction
The uart provides a flexible full-duplex synchronous/asynchronous receiver/transmitter. It

can operate in three asynchronous modes. The uart can reserve new data in the receive
register until the completion of the 2nd transfer.
9.6.2. Operating Mode
9.6.2.1. Mode1
In mode 1 the uart operates as asynchronous transmitter/receiver with 8 data bits and
programmable baud rate. Depending on the setting of baud_rate_reg of
BAUD_RATE_CTRL_0 or setting uart timer register baud rate by TIML_CTRL and
TIMH_CTRL register. Additionally the baud rate can be doubled with the use of the
Baud_rate_sel bit of the BAUD_RATE_CTRL_1 register.
Transmission is started by writing to the THR register. The o_uart_sda pin outputs data.
The first bit transmitted is a start bit (always 0), then 8 bits of data proceed, after which a
stop bit (always 1) is transmitted.
The i_uart_sda inputs data. When reception starts, the uart synchronizes with the falling
edge detected at pin i_uart_sda. Input data are available after completion of the reception
in the RBR register, and the value of stop bit is available as the stop_bit_sel in the
UART_CTRL register. During the reception, the stop_bit_sel and RBR should be hold.
9.6.2.2. Mode2
In mode 2 the uart operates as asynchronous transmitter/receiver with 9 data bits and baud
rate fixed to uart_clk/32 or uart_clk/64, depending on the setting of Baud_rate_sel bit of
the BAUD_RATE_CTRL_1 register. Transmission is started by writing to the THR register.
The o_uart_sda pin outputs data. The first bit transmitted is a start bit (always 0), then 9
bits of data proceed where the 9th is taken from bit tx_bit8_sel of the UART_CTRL register,
after which a stop bit (always 1) is transmitted.
The i_uart_sda pin inputs data. When reception starts, the uart synchronizes with the falling
edge detected at i_uart_sda. Input data are available after completion of the reception in
the RBR register, and the 9th bit is available as the rx_bit8_sel in the UART_CTRL register.
During the reception, the RBR and rx_bit8_sel remain unchanged until the completion.
9.6.2.3. Mode3
The only difference between Mode 2 and Mode 3 is that in Mode 3 either internal baud rate
generator or Timer 1 can be used to specify the baud rate.
In mode 3 the uart operates as asynchronous transmitter/ receiver with 9 data bits and
programmable baud rate. Depending on the setting of baud_rate_reg of baud_rate_ctrl_0
register, either Timer 1 overflow or TIML_CTRL and TIMH_CTRL baud rate generator is
used. Additionally the baud rate can be doubled with the use of the Baud_rate_sel bit of
the baud_rate_ctrl_1 register.
Transmission is started by writing to the THR register. The o_uart_sda pin outputs data.
The first bit transmitted is a start bit (always 0), then 9 bits of data proceed where the 9th
is taken from bit tx_bit8_sel of the UART_CTRL register, after which a stop bit (always 1)
is transmitted.
The i_uart_sda pin inputs data. When reception starts, the uart synchronizes with the falling
edge detected at pin i_uart_sda. Input data are available after completion of the reception
in the RBR register, and the 9th bit is available as the rx_bit8_sel in the UART_CTRL
register. During the reception, the RBR and rx_bit8_sel remain unchanged until the
completion.
9.6.2.4. The Serial Port0 Multiprocessor Communication
The feature of receiving 9 bits in Modes 2 and 3 of Serial Interface 0 can be used for
multiprocessor communication.
When the mc_en bit of the UART_CTRL register is set, the receive interrupt is generated
only when the 9th received bit (rx_bit8_sel in the UART_CTRL) is 1. Otherwise, no interrupt
is generated upon reception.
To utilize this feature to multiprocessor communication, the slave processors have their
mc_en bit set to 1. The master processor transmits the slave’s address, with the 9th bit set
to 1, causing reception interrupt in all of the slaves. The slave processors’ software
compares the received byte with their network address. If there is a match, the addressed
slave clears its mc_en flag and the rest of the message is transmitted from the master with
the 9th bit set to 0. The other slaves keep their mc_en set to 1 so that they ignore the rest
of the message sent by the master.
9.6.3. UART0 Register Map

0x0000 CON Control Register
0x0004 BUF Data Buffer
0x0040 RELL Baud Rate Generator Reload Register (low-order byte)
Baud Rate Generator Reload Register (high-order
0x0044 RELH
byte)
0x0400 PCON Power Control Register
0x0404 ADCON Baud Rate Select register
UART_CTRL address offset: 0x0000

(The CON register controls the function of UART0/UART2.)
9 R/W 0x0 TXEN Tx interrupt enable register
8 R/W 0x0 RXEN Rx interrupt enable register
Model select register
01:Mode1,8-bit uart, band
rate=((2^smod)*pclk/64)*(2^10-rel)，rel is
the contents of TIM registers (TIMH,TIML)
10:Mode2,9-bit uart, In mode 2,the UART
7:6 R/W 0x0 MODE operates as asynchronous
transmitter/receiver with 9 data bits and baud
rate fixed to uart_clk/32 or uart_clk /64,
depending on the setting of Baud_rate_sel
bit of the BAUD_RATE_CTRL_1 register. .
11:Mode3,8-bit uart,band rate variable
Multiprocessor communication enable
5 R/W 0x0 MC_EN
control register
Serial reception enable
If set HIGH serial reception at uart is
4 RW 0x0 SRX_EN
enabled. Otherwise serial reception at uart is
disabled.
Transmitter bit 8
This bit is used while transmitting data
through uart in Modes 2 and 3. The state of
3 RW 0x0 TX_BIT8_SEL this bit corresponds with the state of the 9th
transmitted bit (e.g. parity check or
multiprocessor communication). It is
controlled by software.
Received bit 8
This bit is used while receiving data through
UART in Modes 2 and 3. It reflects the state
2 R/W 0x0 RX_BIT8_SEL of the 9th received bit.
In Mode 1, if multiprocessor communication
is enabled (sm20 = 0), this bit is the stop bit
that was received
Transmit interrupt flag
It indicates completion of a serial
1 R/W 0x0 TX_INT
transmission at UART.
It is at the beginning of a stop bit in all
modes. It must be cleared by software.
Receive interrupt flag
It is set by hardware after completion of a
0 R/W 0x0 RX_INT serial reception at UART.
It is in the middle of a stop bit in all modes.
It must be cleared by software.
THR_CTRL address offset: 0x0004

Writing data to this register sets data in
serial output buffer and starts the
7:0 R/W 0x0 THR transmission through UART. Reading from
the BUF reads data from the serial receive
buffer.
TIML address offset: 0x0040

UART Reload Register is used for UART
baud rate generation. Only 10 bits are used.
7:0 R/W 0xD9 TIML
8 bits from the RELL as lower bits and 2 bits
from the TIMH as higher bits.
TIMH address offset: 0x0044

UART Reload Register is used for UART
baud rate generation. Only 10 bits are used.
7:0 R/W 0x03 TIMH
8 bits from the TIML as lower bits and 2 bits
from the TIMH as higher bits.
BAUD_RATE_CTRL_1 address offset: 0x0400

UART baud rate select (baud rate double)(in
0 R/W 0x03 SMOD
mode1 and mode3)
BAUD_RATE_CTRL_0 address offset: 0x0404

Uart baud rate select (in modes 1 and 3)
7:0 R/W 0x0 BD
When 1, additional internal baud rate
generator is used(need set to 1)
9.7. TIMER
9.7.1. Introduction
The advanced-control timers (TIM1) consist of a 16-bit auto-reload counter driven by a

programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM,
complementary PWM with dead-time insertion).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
TIM1 supports PWM output mode (only for channel0 ~ channel3), complementary output
mode (only for channel0 ~ channel2), complementary output mode with programmable
dead time (only for channel0 ~ channel2), and capture mode (only for channel0 ~
channel3), where channel3 does not support double edge capture mode.
TIM2’s channel 0 supports PWM mode, complementary output mode and dead time output
mode, and does not support capture mode.
TIM3 supports PWM mode (only for channel0 ~ channel3), complementary output
mode(only for channel0 ~ channel2), dead time output mode(only for channel0 ~ channel2),
and does not support capture mode.
• 16-bit up, down, up/down auto-reload counter.
• 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock
frequency either by any factor between 1 and 65535.
• Up to 4 independent channels for:
• Input Capture
• Output Compare
• PWM generation (Edge and Center-aligned Mode)
• One-pulse mode output
• Complementary outputs with programmable dead-time.
• Synchronization circuit to control the timer with external signals and to interconnect
several timers together
• Repetition counter to update the timer registers only after a given number of cycles of
the counter.
• Break input to put the timer’s output signals in reset state or in a known state.
• Interrupt/DMA generation on the following events:
• Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
• Trigger event (counter start, stop, initialization or count by internal/external trigger)
• Input capture
• Output compare
• Break input
• Supports incremental (quadrature) encoder
9.7.3.1. Block Diagram
Figure 9.27 Advanced control timer block diagram
9.7.3.2. Time-base Unit
The main block of the programmable advanced-control timer is a 16-bit counter with its
related auto-reload register. The counter can count up, down or both up and down. The
counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The time-base unit includes:
• Counter register (TIM_CNT)
• Prescaler register (TIM_PSC)
• Auto-reload register (TIM_ARR)
• Repetition counter register (TIM_RCR)
The auto-reload register is preloaded. Writing to or reading from the auto-reload register
accesses the preload register. The content of the preload register is transferred into the
shadow register permanently or at each update event (UEV), depending on the auto-reload
preload enable bit (ARPE) in TIM_CR1 register. The update event is sent when the counter
reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the
TIM_CR1 register. It can also be generated by software. The generation of the update
event is described in detailed for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enables bit (CEN) in TIM_CR1 register is set (refer also to the slave mode
controller description to get more details on counter enabling).
Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIM_CR1
register.
Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536.
It is based on a 16-bit counter controlled through a 16-bit register (in the TIM_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
The following figures give some examples of the counter behavior when the prescaler ratio
is changed on the fly:
CK_PSC
CNT_EN
CK_CNT
Counter Reg F7 F8 F9 FA FB FC 00 01 02 03
UEV
PSC Control Reg 0 1
PSC Buffer 0 1
PSC Counter 0 0 1 0 1 0 1 0 1
Write a new value in TIMx_PSC
Figure 9.28 Counter timing diagram
with prescaler division change from 1 to 2
CK_PSC
CNT_EN
CK_CNT
Counter Reg F7 F8 F9 FA FB FC 00 01
UEV
PSC Control Reg 0 3
PSC Buffer 0 3
PSC Counter 0 0 1 2 3 0 1 2 3
Write a new value in TIMx_PSC
Figure 9.29 Counter timing diagram

with prescaler division change from 1 to 4
9.7.3.3. Counter Modes
Upcounting mode
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIM_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after upcounting is
repeated for the number of times programmed in the repetition counter register (TIM_RCR).
Else the update event is generated at each counter overflow.
Setting the UG bit in the TIM_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIM_CR1 register.
This is to avoid updating the shadow registers while writing new values in the preload
registers. Then no update event occurs until the UDIS bit has been written to 0. However,
the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate
does not change). In addition, if the URS bit (update request selection) in TIM_CR1 register
is set, setting the UG bit generates an update event UEV but without setting the UIF flag
(thus no interrupt or DMA request is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIM_SR register) is set (depending on the URS bit):
• The repetition counter is reloaded with the content of TIM_RCR register,
• The auto-reload shadow register is updated with the preload value (TIM_ARR),
• The buffer of the prescaler is reloaded with the preload value (content of the TIM_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIM_ARR=0x36.
Figure 9.30 Counter timing diagram, internal clock divided by 1
Figure 9.33 Counter timing diagram, internal clock divided by N
Figure 9.34 Counter timing diagram, update event when ARPE = 0 (TIM_ARR not preloaded)
Figure 9.35 Counter timing diagram, update event when ARPE = 0 (TIM_ARR preloaded)
Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIM_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
If the repetition counter is used, the update event (UEV) is generated after downcounting
is repeated for the number of times programmed in the repetition counter register
(TIM_RCR). Else the update event is generated at each counter underflow.
Setting the UG bit in the TIM_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV update event can be disabled by software by setting the UDIS bit in TIM_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of
the prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIM_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt
or DMA request is sent). This is to avoid generating both update and capture interrupts
when clearing the counter on the capture event.
• The repetition counter is reloaded with the content of TIM_RCR register.
register).
• The auto-reload active register is updated with the preload value (content of the
TIM_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one.
frequencies when TIM_ARR=0x36.
CK_PSC
CNT_EN
CK_CNT
Counter Reg 05 04 03 02 01 00 36 35 34 33 32 31 30 2F
Counter underflow
UEV
UIF
CK_PSC
CNT_EN
CK_CNT
Counter Reg 0002 0001 0000 0036 0035 0034
Counter underflow
UEV
UIF
CK_PSC
CNT_EN
CK_CNT
Counter Reg 0001 0000 0036
Counter underflow
UEV
UIF
CK_PSC
CNT_EN
CK_CNT
Counter Reg 20 1F 00 36
Counter underflow
UEV
UIF
CK_PSC
CNT_EN
CK_CNT
Counter Reg 05 04 03 02 01 00 36 35 34 33 32 31 30 2F
Counter overflow
UEV
UIF
Auto-reload preload reg FF 36
Write a new value in TIMx_ARR
Figure 9.40 Counter timing diagram,

update event when repetition counter is not used
Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIM_ARR register) – 1, generates a counter overflow event, then counts from the auto-
reload value down to 1 and generates a counter underflow event. Then it restarts counting
from 0.
In this mode, the DIR direction bit in the TIM_CR1 register cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter
underflow or by setting the UG bit in the TIM_EGR register (by software or by using the
slave mode controller) also generates an update event. In this case, the counter restarts
counting from 0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in the TIM_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.
In addition, if the URS bit (update request selection) in TIM_CR1 register is set, setting the
UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt
or DMA request is sent). This is to avoid generating both update and capture interrupts
when clearing the counter on the capture event.
• The repetition counter is reloaded with the content of TIM_RCR register
register)
• The auto-reload active register is updated with the preload value (content of the
TIM_ARR register). Note that if the update source is a counter overflow, the auto-
reload is updated before the counter is reloaded, so that the next period is the
expected one (the counter is loaded with the new value).
frequencies.
CK_PSC
CNT_EN
CK_CNT
Counter Reg 04 03 02 01 00 01 02 03 04 05 06 05
Counter underflow
Counter overflow
UEV
UIF

internal clock frequency division factor is 1, TIMx_ARR=0x6
CK_PSC
CNT_EN
CK_CNT
Counter Reg 03 02 01 00 01 02 03
Counter underflow
UEV
UIF
Figure 9.42 Counter sequence diagram,

internal clock frequency division factor is 2
CK_PSC
CNT_EN
CK_CNT
Counter Reg 0034 0035 0036 0035
Counter overflow
UEV
UIF

internal clock frequency division factor of 4, TIMx_ARR=0x36
CK_PSC
CNT_EN
CK_CNT
Counter Reg 20 1F 00 36
Counter underflow
UEV
UIF
CK_PSC
CNT_EN
CK_CNT
Counter Reg 06 05 04 03 02 01 00 01 02 03 04 05 06 07
Counter underflow
UEV
UIF
Auto-reload preload reg FD 36
Auto-reload active reg FD 36

update event at ARPE=1(counter underflow)
CK_PSC
CNT_EN
CK_CNT
Counter Reg F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F
Counter overflow
UEV
UIF
Auto-reload preload reg FD 36
Auto-reload active reg FD 36

update event at ARPE=1(counter overflow)
9.7.3.4. Repetition Counter
Time-base unit describes how the update event (UEV) is generated with respect to the
counter overflows/underflows. It is actually generated only when the repetition counter has
reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIM_ARR auto-reload register, TIM_PSC prescaler register, but also TIM_CCRx
capture/compare registers in compare mode) every N counter overflows or underflows,
where N is the value in the TIM_RCR repetition counter register.
The repetition counter is decremented:
• At each counter overflow in upcounting mode,
• At each counter underflow in downcounting mode,
• At each counter overflow and at each counter underflow in center-aligned mode.
Although this limits the maximum number of repetition to 128 PWM cycles, it makes it
possible to update the duty cycle twice per PWM period. When refreshing compare
registers only once per PWM period in center-aligned mode, maximum resolution is 2*Tck,
due to the symmetry of the pattern.
The repetition counter is an auto-reload type; the repetition rate is maintained as defined
by the TIM_RCR register value (refer to the following figure). When the update event is
generated by software (by setting the UG bit in TIM_EGR register) or by hardware through
the slave mode controller, it occurs immediately whatever the value of the repetition
counter is and the repetition counter is reloaded with the content of the TIM_RCR register.
In center-aligned mode, for odd values of RCR, the update event occurs either on the
overflow or on the underflow depending on when the RCR register was written and when
the counter was started. If the RCR was written before starting the counter, the UEV occurs
on the overflow. If the RCR was written after starting the counter, the UEV occurs on the
underflow. For example, for RCR = 3, the UEV is generated on each 4th overflow or
underflow event depending on when RCR was written.
Figure 9.47 Update rate examples depending on mode and TIM_RCR register
9.7.3.5. Clock Selection
The counter clock can be provided by the following clock sources:

• Internal clock (CK_INT)
• External clock mode1: external input pin
• External clock mode2: external trigger input ETR
• Internal trigger inputs (ITRx): using one timer as prescaler for another timer
Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIM_CR1
register) and UG bits (in the TIM_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN
bit is written to 1, the prescaler is clocked by the internal clock CK_INT.
The following figure shows the behavior of the control circuit and the upcounter in normal
mode, without prescaler.
Figure 9.48 Control circuit in normal mode, internal clock divided by 1
External clock source mode 1
This mode is selected when SMS=111 in the TIM_SMCR register. The counter can count
at each rising or falling edge on a selected input.
TIMx_SMCR
TS[2:0]
ITRx 0xx or TI2F OR

TI1F Or Encoder
TI1_ED mode
100
External
TI1F_Rising TI1FP1 101
TRG I
clock
TI1 Edge 0 TI1FP2
mode 1
Filter 110 CK_PSC
Detector TI1F_Falling Externa
1 ETRF ETRF
l clock
111 mode 2
Internal
ICF[3:0] CK_INT clock
CC1P mode
TIMx_CCMR1 Internal clock
TIMx_CCER
ECE SMS[2:0]
TIMx_SMCR
Figure 9.49 TI1 external clock connection example
For example, to configure the upcounter to count in response to a rising edge on the TI1
input, use the following procedure:
• Configure channel 2 to detect rising edges on the TI1 input by writing CC2S = ‘01’ in
the TIM_CCMR1 register.
• Configure the input filter duration by writing the IC2F[3:0] bits in the TIM_CCMR1
register (if no filter is needed, keep IC2F=0000).
• Select rising edge polarity by writing CC2P=0 in the TIM_CCER register.
• Configure the timer in external clock mode 1 by writing SMS=111 in the TIM_SMCR
register.
• Select TI1 as the trigger input source by writing TS=110 in the TIM_SMCR register.
• Enable the counter by writing CEN=1 in the TIM_CR1 register.
Note: The capture prescaler is not used for triggering, so you don’t need to configure it.
When a rising edge occurs on TI1, the counter counts once and the TIF flag is set. The
delay between the rising edge on TI1 and the actual clock of the counter is due to the
resynchronization circuit on TI1 input.
TI2
TI1
CNT_EN
Counter clock=CK_CNT=CK_PSC
Counter Reg 34 35 36
TIF
Write TIF=0
Figure 9.50 Control circuit in external clock mode 1
External clock source mode 2
This mode is selected by writing ECE = 1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The following figure gives an overview of the external trigger input block.
or TI2F or
TI1F or Encoder
mode
External
TRGI
clock
mode 1
ETR CK_PSC
ETR pin 0 Divider ETRP Filter ETRF External
clock
1 /1,/2,/4,/8 fDTS downcounter mode 2
Internal
CK_INT clock
Internal clock mode
ETP ETPS[1:0] ETF[3:0]

TIMx_SMCR TIMx_SMCR TIMx_SMCR
ECE SMS[2:0]
Figure 9.51 External trigger input block
For example, to configure the upcounter to count each 2 rising edges on ETR, use the
following procedure:
• As no filter is needed in this example, write ETF[3:0] = 0000 in the TIM_SMCR register.
• Set the prescaler by writing ETPS[1:0] = 01 in the TIM_SMCR register
• Select rising edge detection on the ETR pin by writing ETP = 0 in the TIM_SMCR
register
• Enable external clock mode 2 by writing ECE = 1 in the TIM_SMCR register.
• Enable the counter by writing CEN = 1 in the TIM_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to
the resynchronization circuit on the ETRP signal.
FCK_INT
CNT_EN
ETR
ETRP
ETRF
Counter Reg 34 35 36
Figure 9.52 Control circuit in external clock mode 2
9.7.3.6. Capture/Compare Channels
Each Capture/Compare channel is built around a capture/compare register (including a

shadow register), an input stage for capture (with digital filter, multiplexing and prescaler)
and an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).
TI1F_ED
To the slave mode controller
TI1 TI1F_Rising
Filter TI1F Edge 0
fDTS TI1F_Falling
TI1FP1 01
downcounter Detector 1
TI1FP2 10 IC1 Divider IC1PS
/1,/2,/4,/8
ICF[3:0] CC1P/CC1NP TRC
TIMx_CCMR1 TIMx_CCER 11
From slave
TI4F_Rising mode controller
From channel 4 0
TI4F_Falling
1 CC1S[1:0] ICPS[1:0] CC1E
From channel 4
TIMx_CCMR1 TIMx_CCER
Figure 9.53 Capture/compare channel
(example: channel 1 input stage)
The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.
APB BUS
MCU peripheral interface

16 16
高低
S Write CCR1H
Read CCR1H Capture/compare preload Write in progress
S
Read in registers Write CCR1L
Read CCR1L Output R
R progress Capture mode
transter Compare transter CC1S[1]
CC1S[0]
Capture compare shadow OC1PE

CC1S[1]
OC1PE
register UEV
CC1S[0] Input From clock TIMx_CCMR1
mode Comparator reference unit
Capture
IC1PS
CNT>CCR1
CC1E
Counter
CNT=CCR1
CC1G
TIMx_EGR
Figure 9.54 Main circuit of capture/compare channel 1
To main mode
controller
ETR
0 Output OC4
CNT>CCR4 1 enable circuit
Output mode OC4_REF
CNT=CCR4 controller
CC4P
OC2M[2:0] TIM1_CCER
TIM1_CCMR2 CC4E TIM1_CCER
MOE OSSI TIM1_BDTR
OIS4 TIM1_CR2
Figure 9.55 Capture/compare the output portion of the channel (channel 4)

The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into
the preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
9.7.3.7. Input Capture Mode
In Input capture mode, the Capture/Compare Registers (TIM_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIM_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag
was already high, then the over-capture flag CCxOF (TIM_SR register) is set. CCxIF can
be cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIM_CCRx register. CCxOF is cleared when you write it to ‘0’.
The following example shows how to capture the counter value in TIM_CCR1 when TI1
input rises. To do this, use the following procedure:
• Select the active input: TIM_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIM_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIM_CCR1 register becomes read-only.
• Program the input filter duration you need with respect to the signal you connect to the
timer (when the input is one of the TIx (ICxF bits in the TIM_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at most 5 internal
clock cycles. We must program a filter duration longer than these 5 clock cycles. We
can validate a transition on TI1 when 8 consecutive samples with the new level have
been detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIM_CCMR1 register.
• Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in
the TIM_CCER register (rising edge in this case).
• Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIM_CCMR1 register).
• Enable capture from the counter into the capture register by setting the CC1E bit in
the TIM_CCER register.
• If needed, enable the related interrupt request by setting the CC1IE bit in the
TIM_DIER register, and/or the DMA request by setting the CC1DE bit in the TIM_DIER
register.
When an input capture occurs:

• The TIM_CCR1 register gets the value of the counter on the active transition.
• CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
• An interrupt is generated depending on the CC1IE bit.
• A DMA request is generated depending on the CC1DE bit.
• In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after
reading the flag and before reading the data.
Note: IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIM_EGR register.
9.7.3.8. PWM Input Mode
This mode is a particular case of input capture mode. The procedure is the same except:
• Two ICx signals are mapped on the same TIx input.
• These 2 ICx signals are active on edges with opposite polarity.
• One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.
For example, you can measure the period (in TIM_CCR1 register) and the duty cycle (in
TIM_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
• Select the active input for TIM_CCR1: write the CC1S bits to 01 in the TIM_CCMR1
register (TI1 selected).
• Select the active polarity for TI1FP1 (used both for capture in TIM_CCR1 and counter
clear): write the CC1P bit to ‘0’ (active on rising edge).
• Select the active input for TIM_CCR2: write the CC2S bits to 10 in the TIM_CCMR1
register (TI1 selected).
• Select the active polarity for TI1FP2 (used for capture in TIM_CCR2): write the CC2P
bit to ‘1’ (active on falling edge).
• Select the valid trigger input: write the TS bits to 101 in the TIM_SMCR register
(TI1FP1 selected).
• Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIM_SMCR register.
• Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIM_CCER register.
TI1
TIMx_CNT 0004 0000 0001 0002 0003 0004 0000
TIMx_CCR1 0004
TIMx_CCR2 0002
IC1 Capture IC2 Capture pulse width IC1 Capture period

IC2 Capture measurement measurement
Reset counter
Figure 9.56 PWM Input Mode Timing

Note: The PWM input mode can be used only with the TIM_CH1/TIM_CH2 signals due
to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller.
9.7.3.9. Forced Output Mode
In output mode (CCxS bits = 00 in the TIM_CCMRx register), each output compare signal
(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, you just need to write
101 in the OCxM bits in the corresponding TIM_CCMRx register. Thus OCXREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=0 (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIM_CCMRx
register.
Anyway, the comparison between the TIM_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the output compare mode section below.
9.7.3.10. Output Compare Mode
This function is used to control an output waveform or indicating when a period of time has
elapsed. When a match is found between the capture/compare register and the counter,
the output compare function:
• Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIM_CCMRx register) and the output polarity (CCxP
bit in the TIM_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.
• Sets a flag in the interrupt status register (CCxIF bit in the TIM_SR register).
• Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIM_DIER register).
• Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIM_DIER register, CCDS bit in the TIM_CR2 register for the DMA request selection).
The TIM_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIM_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used
to output a single pulse (in One Pulse mode).
Procedure:
• Select the counter clock (internal, external, prescaler).
• Write the desired data in the TIM_ARR and TIM_CCRx registers.
• Set the CCxIE bit if an interrupt request is to be generated.
• Select the output mode. For example:
• Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx
• Write OCxPE = 0 to disable preload register
• Write CCxP = 0 to select active high polarity
• Write CCxE = 1 to enable the output
• Enable the counter by setting the CEN bit in the TIM_CR1 register.
The TIM_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIM_CCRx
shadow register is updated only at the next update event UEV). A example is given in the
following figure.
Write B201h in the
CC1R register
TIM1_CNT 0039 003A 003B B200 B201
TIM1_CCR1 003A B201
OC1 REF=OC1
Match detected on CCR1

Interrupt generated if enabled
Figure 9.57 Output compare mode, toggle on OC1
9.7.3.11. PWM Mode
Pulse Width Modulation mode allows you to generate a signal with a frequency determined
by the value of the TIM_ARR register and a duty cycle determined by the value of the
TIM_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
TIM_CCMRx register. You must enable the corresponding preload register by setting the
OCxPE bit in the TIM_CCMRx register, and eventually the auto-reload preload register (in
upcounting or center-aligned modes) by setting the ARPE bit in the TIM_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, you have to initialize all the registers by setting the UG
bit in the TIM_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIM_CCER register. It
can be programmed as active high or active low. OCx output is enabled by a combination
of the CCxE, CCxNE, MOE, OSSI and OSSR bits (TIM_CCER and TIM_BDTR registers).
Refer to the TIM_CCER register description for more details.
In PWM mode (1 or 2), TIM_CNT and TIM_CCRx are always compared to determine
whether TIM_CCRx ≤ TIM_CNT or TIM_CNT ≤ TIM_CCRx (depending on the direction of
the counter).
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIM_CR1 register.
PWM edge-aligned mode

• Upcounting configuration
Upcounting is active when the DIR bit in the TIM_CR1 register is low. Refer to the
Upcounting mode.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF
is high as long as TIM_CNT < TIM_CCRx else it becomes low. If the compare value in
TIM_CCRx is greater than the auto-reload value (in TIM_ARR) then OCxREF is held at ‘1’.
If the compare value is 0 then OCxRef is held at ‘0’.
The following figure shows some edge-aligned PWM waveforms in an example where
TIM_ARR=8.
Counter register 0 1 2 3 4 5 6 7 8 0 1
OCxREF
CCRx=4
CCxIF
OCxREF
CCRx=8
CCxIF
OCxREF
CCRx>8 ‘1’
CCxIF
‘0’
CCRx=0 OCxREF
CCxIF
Figure 9.58 Edge-aligned PWM waveforms (ARR=8)

• Downcounting configuration
Downcounting is active when DIR bit in TIMx_CR1 register is high.
In PWM mode 1, the reference signal OCxRef is low as long as TIM_CNT > TIM_CCRx
else it becomes high. If the compare value in TIM_CCRx is greater than the auto-reload
value in TIM_ARR, then OCxREF is held at ‘1’. 0% PWM is not possible in this mode.
PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIM_CR1 register are different from
‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals).
The compare flag is set when the counter counts up, when it counts down or both when it
counts up and down depending on the CMS bits configuration. The direction bit (DIR) in
the TIM_CR1 register is updated by hardware and must not be changed by software. Refer
to the Center-aligned mode (up/down counting).
The following figure shows some center-aligned PWM waveforms in an example where:
• TIM_ARR=8,
• PWM mode is the PWM mode 1,
• The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIM_CR1 register.
Counter register 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1
OCxREF
CCRx=4
CMS=01
CCxIF
CMS=10
CMS=11
OCxREF
CCRx=7
CMS=10 or 11
CCxIF
‘1’
CCRx=8 OCxREF CMS=01
CCxIF CMS=10
‘1’
CMS=11
CCRx>8 OCxREF CMS=01
CCxIF CMS=10
‘0’ CMS=11
OCxREF
CCRx=0 CMS=01
CCxIF CMS=10
CMS=11
Figure 9.59 Center-aligned PWM waveforms (ARR=8)
Hints on using center-aligned mode

• When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR
bit in the TIM_CR1 register. Moreover, the DIR and CMS bits must not be changed at
the same time by the software.
• Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
• The direction is not updated if you write a value in the counter that is greater than
the auto-reload value (TIM_CNT>TIM_ARR). For example, if the counter was
counting up, it continues to count up.
• The direction is updated if you write 0 or write the TIM_ARR value in the counter
but no Update Event UEV is generated.
• The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIM_EGR register) just before starting the counter and not
to write the counter while it is running.
9.7.3.12. Complementary Outputs and Dead-time Insertion
The advanced-control timers (TIM1&TIM3) can output complementary signal and manage
the switching-off and the switching-on instants of the output.
This time is generally known as dead-time and you have to adjust it depending on the
devices you have connected to the outputs and their characteristics (intrinsic delays of
level shifter, delays due to power switches...)
User can select the polarity of the outputs (main output OCx or complementary OCxN)
independently for each output. This is done by writing to the CCxP and CCxNP bits in the
TIM_CCER register.
The complementary signals OCx and OCxN are activated by a combination of several
control bits: the CCxE and CCxNE bits in the TIM_CCER register and the MOE, OISx,
OISxN, OSSI and OSSR bits in the TIM_BDTR and TIM_CR2 registers. In particular, the
dead-time is activated when switching to the IDLE state (MOE falling down to 0).
Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if
the break circuit is present. There is one 10-bit dead-time generator for each channel. From
a reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN
are active high:
• The OCx output signal is the same as the reference signal except for the rising edge,
which is delayed relative to the reference rising edge.
• The OCxN output signal is the opposite of the reference signal except for the rising
edge, which is delayed relative to the reference falling edge.
If the delay is greater than the width of the active output (OCx or OCxN) then the
corresponding pulse is not generated.
The following figures show the relationships between the output signals of the dead-time
generator and the reference signal OCxREF. (we suppose CCxP = 0, CCxNP = 0, MOE=1,
CCxE = 1 and CCxNE = 1 in these examples)
OCx REF
OCx
Delay Delay
OCxN
Figure 9.60 Complementary output with dead-time insertion
OCx REF
OCx
Delay
OCxN
Figure 9.61 Dead-time waveforms with delay greater than the negative pulse
Figure 9.62 Dead-time waveforms with delay greater than the positive pulse
The dead-time delay is the same for each of the channels and is programmable with the
DTG bits in the TIMx_BDTR register.
Re-directing OCxREF to OCx or OCxN
In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx
output or to OCxN output by configuring the CCxE and CCxNE bits in the TIM_CCER
register.
This allows you to send a specific waveform (such as PWM or static active level) on one
output while the complementary remains at its inactive level. Other alternative possibilities
are to have both outputs at inactive level or both outputs active and complementary with
dead-time.
Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and
becomes active as soon as OCxREF is high. For example, if CCxNP=0 then
OCxN=OCxRef. On the other hand, when both OCx and OCxN are enabled
(CCxE=CCxNE=1) OCx becomes active when OCxREF is high whereas OCxN is
complemented and becomes active when OCxREF is low.
9.7.3.13. Using the Break Function
When using the break function, the output enable signals and inactive levels are modified
according to additional control bits (MOE, OSSI and OSSR bits in the TIM_BDTR register,
OISx and OISxN bits in the TIM_CR2 register). In any case, the OCx and OCxN outputs
cannot be set both to active level at a given time.
The break source can be either the break input pin or a clock failure event, generated by
the Clock Security System (CSS), from the Reset Clock Controller.
When exiting from reset, the break circuit is disabled and the MOE bit is low. You can
enable the break function by setting the BKE bit in the TIM_BDTR register. The break input
polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can
be modified at the same time. When the BKE and BKP bits are written, a delay of 1 APB
clock cycle is applied before the writing is effective. Consequently, it is necessary to wait
1 APB clock period to correctly read back the bit after the write operation.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIM_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you
must insert a delay (dummy instruction) before reading it correctly. This is because you
write the asynchronous signal and read the synchronous signal.
When a break occurs (selected level on the break input):

• The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state
or in reset state (selected by the OSSI bit). This feature functions even if the MCU
oscillator is off.
• Each output channel is driven with the level programmed in the OISx bit in the
TIM_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable
output else the enable output remains high.
• When complementary outputs are used:
• The outputs are first put in reset state inactive state (depending on the polarity).
This is done asynchronously so that it works even if no clock is provided to the
timer.
• If the timer clock is still present, then the dead-time generator is reactivated in
order to drive the outputs with the level programmed in the OISx and OISxN bits
after a dead-time. Even in this case, OCx and OCxN cannot be driven to their
active level together. Note that because of the resynchronization on MOE, the
dead-time duration is a bit longer than usual (around 2 tim_clk clock cycles).
• If OSSI=0 then the timer releases the enable outputs else the enable outputs
remain or become high as soon as one of the CCxE or CCxNE bits is high.
• The break status flag (BIF bit in the TIM_SR register) is set. An interrupt can be
generated if the BIE bit in the TIM_DIER register is set. A DMA request can be sent if
the BDE bit in the TIM_DIER register is set.
• If the AOE bit in the TIM_BDTR register is set, the MOE bit is automatically set again
at the next update event UEV. This can be used to perform a regulation, for instance.
Else, MOE remains low until you write it to ‘1’ again. In this case, it can be used for
security and you can connect the break input to an alarm from power drivers, thermal
sensors or any security components.
Note: The break inputs are acting on level. Thus, the MOE cannot be set while the break
input is active (neither automatically nor by software). In the meantime, the status flag BIF
cannot be cleared.
The break can be generated by the BRK input which has a programmable polarity and an
enable bit BKE in the TIM_BDTR Register.
In addition to the break input and the output management, a write protection has been
implemented inside the break circuit to safeguard the application. It allows you to freeze
the configuration of several parameters (dead-time duration, OCx/OCxN polarities and
state when disabled, OCxM configurations, break enable and polarity). You can choose
from 3 levels of protection selected by the LOCK bits in the TIM_BDTR register. The LOCK
bits can be written only once after an MCU reset.
The following figure shows an example of behavior of the outputs in response to a break.
Break(MOE )
OCx REF
OCx CCxP=0,OISx=1
OCx CCxP=0,OISx=0
OCx CCxP=1,OISx=1
OCx CCxP=1,OISx=0
OCx Delay Delay Delay
OCxN
(CCxE=1,CCxP=0,OISx=0,CCxNE=1,CCxNP=0,OISxN=1)
OCx
Delay Delay Delay
OCxN
Delay
OCx
OCxN
OCx
Dela
y
OCxN
OCx
OCxN
(CCxE=1,CCxP=0,CCxNE=0,CCxNP=0,OISx=OISxN=0 or OISx=OISxN=1)
Figure 9.63 Output behavior in response to a break
9.7.3.14. Clearing the OCxREF Signal on an External Event
The OCxREF signal for a given channel can be driven Low by applying a High level to the
ETRF input (OCxCE enable bit of the corresponding TIM_CCMRx register set to ‘1’). The
OCxREF signal remains Low until the next update event, UEV, occurs.
This function can only be used in output compare and PWM modes, and does not work in
forced mode.
For example, the OCxREF signal) can be connected to the output of a comparator to be
used for current handling. In this case, the ETR must be configured as follow:
• The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIM_SMCR
register set to ‘00’.
• The external clock mode 2 must be disabled: bit ECE of the TIM_SMCR register set
to ‘0’.
• The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be
configured according to the user needs.
The following figure shows the behavior of the OCxREF signal when the ETRF Input
becomes High, for both values of the enable bit OCxCE. In this example, the timer TIM is
programmed in PWM mode.
（CCRx）
counter(CNT)
ETRF
OCxREF
(OCxCE=`0`)
OCxREF
(OCxCE=`1`)
OCREF_CLR OCREF_CLR
becomes high still high
Figure 9.64 Clearing TIMx OCxREF
9.7.3.15. 6-step PWM Generation
When complementary outputs are used on a channel, preload bits are available on the
OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the
COM commutation event. Thus you can program in advance the configuration for the next
step and change the configuration of all the channels at the same time. COM can be
generated by software by setting the COM bit in the TIM_EGR register or by hardware (on
TRGI rising edge).
A flag is set when the COM event occurs (COMIF bit in the TIM_SR register), which can
generate an interrupt (if the COMIE bit is set in the TIM_DIER register) or a DMA request
(if the COMDE bit is set in the TIM_DIER register).
The following figure describes the behavior of the OCx and OCxN outputs when a COM
event occurs, in 3 different examples of programmed configurations.
counter(CNT) （CCRx）
OCxREF
Write COM to 1
COM event
CCxE=1
CCxNE=0 write OCxM to 100 CCxE=1
OCxM=100(forced CCxNE=0
inactive) OCxM=100
Example 1
OCxN
CCxE=1 Write CCxNE to 1

CCxNE=0 And OCxM to 101 CCxE=0
inactive) OCxM=101
OCx
OCxN
CCxE=1 Write CCxNE to 0
CCxNE=0 And OCxM to 100 CCxE=1
inactive) OCxM=100
Example 3
OCxN
Figure 9.65 step generation, COM example (OSSR=1)
9.7.3.16. One-pulse Mode
One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. You select One-pulse
mode by setting the OPM bit in the TIM_CR1 register. This makes the counter stop
automatically at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration
must be:
• In upcounting: CNT < CCRx < ARR (in particular, 0 < CCRx)
• In downcounting: CNT > CCRx
T12
OC1REF
OC1
Counte
TIM1_ARR
TIM1_CCR1
tDELAY tPULSE
0
f
Figure 9.66 Example of one pulse mode

For example you may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
• Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIM_CCMR1 register.
• TI2FP2 must detect a rising edge, write CC2P=’0’ in the TIM_CCER register.
• Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’
in the TIM_SMCR register.
• TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIM_SMCR register
(trigger mode).
The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
• The tDELAY is defined by the value written in the TIM_CCR1 register.
• The tPULSE is defined by the difference between the auto-reload value and the
compare value (TIM_ARR - TIM_CCR1).
• Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare
match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload
value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIM_CCMR1
register. You can optionally enable the preload registers by writing OC1PE=’1’ in the
TIM_CCMR1 register and ARPE in the TIM_CR1 register. In this case you have to
write the compare value in the TIM_CCR1 register, the auto-reload value in the
TIM_ARR register, generate an update by setting the UG bit and wait for external
trigger event on TI2. CC1P is written to ‘0’ in this example.
In our example, the DIR and CMS bits in the TIM_CR1 register should be low.
You only want 1 pulse, so you write ‘1’ in the OPM bit in the TIM_CR1 register to stop the
counter at the next update event (when the counter rolls over from the auto-reload value
back to 0).
Particular case: OCx fast enable

In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the
TIM_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.
9.7.3.17. Encoder Interface Mode
To select Encoder Interface mode write SMS=‘001’ in the TIM_SMCR register if the counter
is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and SMS=’011’
if it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIM_CCER
register. When needed, you can program the input filter as well.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to the
following table. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1
and TI2 after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIM_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence
the counter counts up or down, the DIR bit in the TIM_CR1 register is modified by hardware
accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in
the TIM_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you
must configure TIM_ARR before starting. in the same way, the capture, compare, prescaler,
repetition counter, trigger output features continue to work as normal. Encoder mode and
External clock mode 2 are not compatible and must not be selected together.
In this mode, the counter is modified automatically following the speed and the direction of
the incremental encoder and its content, therefore, always represents the encoder’s
position. The count direction correspond to the rotation direction of the connected sensor.
The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the
same time.
Level on opposite signal TI1FP1 signal TI2FP2 signal
Active edge
(TI1FP1 for TI2, TI2FP2 for TI1) Rising Falling Rising Falling
Counting on High Down Up No count No count
TI1 only Low Up Down No count No count
Counting on High No count No count Up Down
TI2 only Low No count No count Down Up
Counting on High Down Up Up Down
TI1 and TI1 Low Up Down Down Up
Table 9.5 Counting direction versus encoder signals
An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoder’s
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
The following figure gives an example of counter operation, showing count signal
generation and direction control. It also shows how input jitter is compensated where both
edges are selected. This might occur if the sensor is positioned near to one of the switching
points. For this example we assume that the configuration is the following:
• CC1S=’01’ (TIM_CCMR1 register, TI1FP1 mapped on TI1).
• CC2S=’01’ (TIM_CCMR2 register, TI1FP2 mapped on TI2).
• CC1P=’0’ (TIM_CCER register, TI1FP1 non-inverted, TI1FP1=TI1).
• CC2P=’0’ (TIM_CCER register, TI1FP2 non-inverted, TI1FP2= TI2).
• SMS=’011’ (TIM_SMCR register, both inputs are active on both rising and falling
edges).
• CEN=’1’ (TIM_CR1 register, Counter enabled).
Figure 9.67 Example of counter operation in encoder interface mode
9.7.3.18. Timer Input XOR Function
The TI1S bit in the TIM_CR2 register, allows the input filter of channel 1 to be connected
to the output of a XOR gate, combining the three input pins TIM_CH1, TIM_CH2 and
TIM_CH3.
The XOR output can be used with all the timer input functions such as trigger or input
capture.
9.7.3.19. Interfacing with Hall Sensors
This is done using the advanced-control timers (TIM1 or TIM3) to generate PWM signals
to drive the motor and another timer TIM referred to as “interfacing timer” in the following
figure. The “interfacing timer” captures the 3 timer input pins (CC1, CC2, CC3) connected
through a XOR to the TI1 input channel (selected by setting the TI1S bit in the TIM_CR2
register).
The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus,
each time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a
time base triggered by any change on the Hall inputs.
On the “interfacing timer”, capture/compare channel 1 is configured in capture mode,
capture signal is TRC. The captured value, which corresponds to the time elapsed between
2 changes on the inputs, gives information about motor speed.
The “interfacing timer” can be used in output mode to generate a pulse which changes the
configuration of the channels of the advanced-control timer (TIM1 or TIM3) (by triggering
a COM event). The TIM1 timer is used to generate PWM signals to drive the motor. To do
this, the interfacing timer channel must be programmed so that a positive pulse is
generated after a programmed delay (in output compare or PWM mode). This pulse is sent
to the advanced control timer (TIM1 or TIM3) through the TRGO output.
Example: you want to change the PWM configuration of your advanced-control timer TIM1
after a programmed delay each time a change occurs on the Hall inputs connected to one
of the TIM timers.
• Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the
TIM_CR2 register to ‘1’,
• Program the time base: write the TIM_ARR to the max value (the counter must be
cleared by the TI1 change. Set the prescaler to get a maximum counter period longer
than the time between 2 changes on the sensors,
• Program the channel 1 in capture mode (TRC selected): write the CC1S bits in the
TIM_CCMR1 register to ‘01’. You can also program the digital filter if needed,
• Program the channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to
‘111’ and the CC2S bits to ‘00’ in the TIM_CCMR1 register,
• Select OC2REF as trigger output on TRGO: write the MMS bits in the TIM_CR2
register to ‘101’,
In the advanced-control timer TIM1, the right ITR input must be selected as trigger input,
the timer is programmed to generate PWM signals, the capture/compare control signals
are preloaded (CCPC=1 in the TIM_CR2 register) and the COM event is controlled by the
trigger input (CCUS=1 in the TIM_CR2 register). The PWM control bits (CCxE, OCxM) are
written after a COM event for the next step (this can be done in an interrupt subroutine
generated by the rising edge of OC2REF). The following figure describes this example.
Figure 9.68 Example of hall sensor interface
9.7.3.20. TIM and External Trigger Synchronization
The TIM timer can be synchronized with an external trigger in several modes: Reset mode,
Gated mode and Trigger mode.
Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIM_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIM_ARR, TIM_CCRx) are updated.
In the following example, the upcounter is cleared in response to a rising edge on TI1 input:
• Configure the channel 1 to detect rising edges on TI1. Configure the input filter
duration (in this example, we don’t need any filter, so we keep IC1F=0000). The
capture prescaler is not used for triggering, so you don’t need to configure it. The
CC1S bits select the input capture source only, CC1S = 01 in the TIM_CCMR1 register.
Write CC1P=0 in TIM_CCER register to validate the polarity (and detect rising edges
only).
• Configure the timer in reset mode by writing SMS=100 in TIM_SMCR register. Select
TI1 as the input source by writing TS=101 in TIM_SMCR register.
• Start the counter by writing CEN=1 in the TIM_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIM_SR register) and an interrupt request, or a DMA request
can be sent if enabled (depending on the TIE and TDE bits in TIM_DIER register).
The following figure shows this behavior when the auto-reload register TIM_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
TI1
UG
Counter reg 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03
TIF
Figure 9.69 Control circuit in reset mode
Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input. In the following
example, the upcounter counts only when TI1 input is low:
• Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S=01 in TIM_CCMR1 register. Write CC1P=1
in TIM_CCER register to validate the polarity (and detect low level only).
• Configure the timer in gated mode by writing SMS=101 in TIM_SMCR register. Select
• Enable the counter by writing CEN=1 in the TIM_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon
as TI1 becomes high. The TIF flag in the TIM_SR register is set both when the counter
starts or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
TI1
CNT_EN
Counter reg 30 31 32 33 34 35 36 37 38
TIF
Write TIF=0
Figure 9.70 Control circuit in gated mode
Slave mode: Trigger mode

The counter can start in response to an event on a selected input.
In the following example, the upcounter starts in response to a rising edge on TI2 input:
• Configure the channel 2 to detect rising edges on TI2. Configure the input filter
duration (in this example, we don’t need any filter, so we keep IC2F=0000). The
capture prescaler is not used for triggering, so you don’t need to configure it. The
CC2S bits are configured to select the input capture source only, CC2S=01 in
TIM_CCMR1 register. Write CC2P=1 in TIM_CCER register to validate the polarity
(and detect low level only).
• Configure the timer in trigger mode by writing SMS=110 in TIM_SMCR register.
Select TI2 as the input source by writing TS=110 in TIM_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and
the TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
TI2TI1
CNT_EN
Counter reg 34 35 36 37 38
TIF
Figure 9.71 Control circuit in trigger mode

Slave mode: external clock mode 2 + trigger mode
The external clock mode 2 can be used in addition to another slave mode (except external
clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock
input, and another input can be selected as trigger input (in reset mode, gated mode or
trigger mode). It is recommended not to select ETR as TRGI through the TS bits of
TIM_SMCR register.
In the following example, the upcounter is incremented at each rising edge of the ETR
signal as soon as a rising edge of TI1 occurs:
• Configure the external trigger input circuit by programming the TIM_SMCR register as
follows:
• ETF = 0000: no filter
• ETPS = 00: prescaler disabled
• ETP = 0: detection of rising edges on ETR and ECE=1 to enable the external
clock mode 2
• Configure the channel 1 as follows, to detect rising edges on TI:
• IC1F = 0000: no filter.
• The capture prescaler is not used for triggering and does not need to be
configured.
• CC1S = 01 in TIM_CCMR1 register to select only the input capture source
• CC1P = 0 in TIM_CCER register to validate the polarity (and detect rising edge
only).
• Configure the timer in trigger mode by writing SMS=110 in TIM_SMCR register. Select
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts
on ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.
TI1
CEN/CNT_EN
ETR
Counter reg 34 35 36
TIF
Figure 9.72 Control circuit in external clock mode2 + trigger mode
9.7.3.21. TIM Synchronization
The TIM timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
The following figure presents an overview of the trigger selection and the master mode
selection blocks.
Using one timer as prescaler for the another
Figure 9.73 Master/Slave timer example
For example, you can configure Timer 1 to act as a prescaler for Timer 2. To do this:
• Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each
update event UEV. If you write MMS=010 in the TIM1_CR2 register, a rising edge is
output on TRGO1 each time an update event is generated.
• To connect the TRGO1 output of Timer 1 to Timer 2, Timer 2 must be configured in
slave mode using ITR1 as internal trigger. You select this through the TS bits in the
TIM2_SMCR register (writing TS=000).
• Then you put the slave mode controller in external clock mode 1 (write SMS=111 in
the TIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the
periodic Timer 1 trigger signal (which correspond to the timer 1 counter overflow).
• Finally both timers must be enabled by setting their respective CEN bits (TIM_CR1
register).
Note: If OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to
clock the counter of timer 2.
Using one timer to enable another timer

In this example, we control the enable of Timer 2 with the output compare 1 of Timer 1.
Refer to Figure 6.71 for connections. Timer 2 counts on the divided internal clock only
when OC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the
prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).
• Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIM1_CR2 register).
• Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).
• Configure Timer 2 to get the input trigger from Timer 1 (TS=000 in the TIM2_SMCR
register).
• Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).
• Enable Timer 2 by writing ‘1’ in the CEN bit (TIM2_CR1 register).
• Start Timer 1 by writing ‘1’ in the CEN bit (TIM1_CR1 register).
Note: The counter 2 clock is not synchronized with counter 1, this mode only affects the
Timer 2 counter enable signal.
Figure 9.74 Gating timer 2 with OC1REF of timer 1

The Timer 2 counter and prescaler are not initialized before being started. So they start
counting from their current value. It is possible to start from a given value by resetting both
timers before starting Timer 1. You can then write any value you want in the timer counters.
The timers can easily be reset by software using the UG bit in the TIM_EGR registers.
In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts
from 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both
timers. Timer 2 stops when Timer 1 is disabled by writing ‘0’ to the CEN bit in the TIM1_CR1
register:
• Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIM1_CR2 register).
• Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).
register).
• Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).
• Reset Timer 1 by writing ‘1’ in UG bit (TIM1_EGR register).
• Reset Timer 2 by writing ‘1’ in UG bit (TIM2_EGR register).
• Initialize Timer 2 to 0xE7 by writing ‘0xE7’ in the timer 2 counter (TIM2_CNTL).
• Enable Timer 2 by writing ‘1’ in the CEN bit (TIM2_CR1 register).
• Stop Timer 1 by writing ‘0’ in the CEN bit (TIM1_CR1 register).
Figure 9.75 Gating timer 2 with Enable of timer 1

Using one timer to start another timer
In this example, we set the enable of Timer 2 with the update event of Timer 1. Timer 2
starts counting from its current value (which can be non-zero) on the divided internal clock
as soon as the update event is generated by Timer 1.
When Timer 2 receives the trigger signal its CEN bit is automatically set and the counter
counts until we write ‘0’ to the CEN bit in the TIM2_CR1 register. Both counter clock
frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).
• Configure Timer 1 master mode to send its UEV as trigger output (MMS=010 in the
TIM1_CR2 register).
• Configure the Timer 1 period (TIM1_ARR registers).
register).
• Configure Timer 2 in trigger mode (SMS=110 in TIM2_SMCR register).
Figure 9.76 Triggering timer 2 with update of timer 1
As in the previous example, you can initialize both counters before starting counting. The
following figure shows the behavior with the same configuration as in Figure 6.74 but in
trigger mode instead of gated mode (SMS=110 in the TIM2_SMCR register).
Figure 9.77 Triggering timer 2 with Enable of timer 1
Using one timer as prescaler for another timer
For example, you can configure Timer 1 to act as a prescaler for Timer 2. To do this:
• Configure Timer 1 master mode to send its Update Event (UEV) as trigger output(MMS
= 010 in the TIM1_CR2 register). then it outputs a periodic signal on each counter
overflow.
• Configure the Timer 1 period (TIM1_ARR registers).
• Configure Timer 2 to get the input trigger from Timer 1 (TS = 000 in the TIM2_SMCR
register).
• Configure Timer 2 in external clock mode 1 (SMS = 111 in TIM2_SMCR register).
Starting 2 timers synchronously in response to an external trigger

In this example, we set the enable of timer 1 when its TI1 input rises, and the enable of
Timer 2 with the enable of Timer 1. To ensure the counters are aligned, Timer 1 must be
configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer
2):
• Configure Timer 1 master mode to send its Enable as trigger output (MMS = 001 in
the TIM1_CR2 register).
• Configure Timer 1 slave mode to get the input trigger from TI1 (TS = 100 in the
TIM1_SMCR register).
• Configure Timer 1 in trigger mode (SMS = 110 in the TIM1_SMCR register).
• Configure the Timer 1 in Master/Slave mode by writing MSM = ‘1’ (TIM1_SMCR
register).
• Configure Timer 2 to get the input trigger from Timer 1 (TS = 000 in the TIM2_SMCR
register).
• Configure Timer 2 in trigger mode (SMS = 110 in the TIM2_SMCR register).
When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously
on the internal clock and both TIF flags are set.
Note: In this example both timers are initialized before starting (by setting their respective
UG bits). Both counters start from 0, but you can easily insert an offset between them by
writing any of the counter registers (TIM_CNT). You can see that the master/slave mode
insert a delay between CNT_EN and CK_PSC on timer 1.
Figure 9.78 Triggering timer 1 and 2 with timer 1 TI1 input
9.7.3.22. Debug Mode
When the micro-controller enters debug mode (Cortex-M33 core halted), the TIM counter
either continues to work normally or stops, depending on DBG_TIM_STOP configuration
bit in DBG module.
9.7.4. TIMER Register Map
9.7.4.1. Timer0 Register Map

Base Address: 0x400c0000
0x0000 TIM_CR1 Timer control register 1
0x0008 TIM_SMCR Timer slave mode control register
0x000c TIM_DIER Timer DMA/interrupt enable register
0x0010 TIM_SR Timer status register
0x0014 TIM_EGR Timer event generation register
0x0018 TIM_CCMR1 Timer capture/compare mode register1
0x001c TIM_CCMR2 Timer capture/compare mode register2
0x0020 TIM_CCER Timer capture/compare enable register
0x0024 TIM_CNT Timer counter
0x0028 TIM_PSC Timer prescaler
0x002c TIM_ARR Timer auto-reload register
0x0030 TIM_RCR Timer reperepetition counter register
0x0034 TIM_CCR1 Timer capture/compare register1
0x003c TIM_CCR3 Timer capture/compare register3
0x0044 TIM_BDTR Timer break and dead-time register
0x0048 TIM_DCR Timer dma control register
0x004c TIM_DMAR Timer dma address for full transfer
TIM_CR1 address offset: 0x0000

9:8 RW 0x0 CKD[1:0] Clock division
This bit-field indicates the division ratio between
the timer clock (tCK_INT) frequency and the
dead-time and sampling clock (tDTS )used by the
dead-time generators and the digital filters
(ETR, TIx)
00: tDTS =tCK_INT
01: tDTS =2*tCK_INT
10: tDTS =4*tCK_INT
11: Reserved, do not program this value
7 RW 0x0 ARPE Auto-reload preload enable
0: TIM_ARR register is not buffered
1: TIM_ARR register is buffered
6:5 RW 0x0 CMS Center-aligned mode selection
00: Edge-aligned mode. The counter counts up
or down depending on the direction bit (DIR).
01: Center-aligned mode 1. The counter counts
up and down alternatively. Output compare
interrupt flags of channels are set only when the
counter is counting down.
counter is counting up.
interrupt flags of channels are set both when the
counter is counting up or down.
4 RW 0x0 DIR Direction
0: Counter used as upcounter
1: Counter used as downcounter
Note: This bit is read only when the timer is
configured in Center-aligned mode or Encoder
mode
3 RW 0x0 OPM One pulse mode
0: Counter is not stopped at update event
1: Counter stops counting at the next update
event (clearing the bit CEN)
2 RW 0x0 URS Update request source
This bit is set and cleared by software to select
the UEV event sources.
0: Any of the following events generate an
update interrupt or DMA request if enabled.
These events can be:
⚫ Counter overflow/underflow
⚫ Setting the UG bit
⚫ Update generation through the slave mode
controller
1: Only counter overflow/underflow generates an
update interrupt or DMA request if enabled.
1 RW 0x0 UDIS Update disable
This bit is set and cleared by software to
enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is
generated by one of the following events:
⚫ Counter overflow/underflow
⚫ Setting the UG bit
⚫ Update generation through the slave mode
controller
Buffered registers are then loaded with their
preload values.
1: UEV disabled. The Update event is not
generated, shadow registers keep their value
(ARR, PSC, CCRx). However the counter and
the prescaler are reinitialized if the UG bit is
set or if a hardware reset is received from the
slave mode controller.
0 RW 0x0 CEN Counter enable
0: Counter disabled
1: Counter enabled
Note: External clock, gated mode and encoder
mode can work only if the CEN bit has been
previously set by software. However trigger
mode can set the CEN bit automatically by
hardware

14 RW 0x0 OIS4 Output Idle state 4 (OC4 output)
0: OC4=0 (after a dead-time if OC4N is
implemented) when MOE=0
13 RW 0x0 OIS3N Output Idle state 3 (OC3N output)
0: OC3N=0 after a dead-time when MOE=0
Note: This bit can not be modified as long as
LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIM_BDTR register)
LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIM_BDTR register).
7 RW 0x0 TI1S TI1 selection
0: The TIM_CH1 pin is connected to TI1 input
1: The TIM_CH1, CH2 and CH3 pins are
connected to the TI1 input (XOR combination)
6:4 RW 0x0 MMS Master mode selection
These bits allow to select the information to be
sent in master mode to slave timers for
synchronization (TRGO). The combination is as
follows:
000: Reset - the UG bit from the TIM_EGR
register is used as trigger output (TRGO). If the
reset is generated by the trigger input (slave
mode controller configured in reset mode) then
the signal on TRGO is delayed compared to the
actual reset.
001: Enable - the Counter Enable signal
CNT_EN is used as trigger output (TRGO). It is
useful to start several timers at the same time or
to control a window in which a slave timer is
enable. The Counter Enable signal is generated
by a logic OR between CEN control bit and the
trigger input when configured in gated mode.
When the Counter Enable signal is controlled by
the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see
the MSM bit description in TIM_SMCR register).
010: Update - The update event is selected as
trigger output (TRGO). For instance a master
timer can then be used as a prescaler for a slave
timer.
011: Compare Pulse - The trigger output send a
positive pulse when the CC1IF flag is to be set
(even if it was already high), as soon as a
capture or a compare match occurred. (TRGO).
100: Compare - OC1REF signal is used as
trigger output (TRGO)
3 RW 0x0 CCDS Capture/compare DMA selection
0: CC DMA request sent when CC event occurs
1: CC DMA requests sent when update event
occurs
2 RW 0x0 CCUS Capture/compare control update selection
0: When capture/compare control bits are
preloaded (CCPC=1), they are updated by
setting the COMG bit only
setting the COMG bit or when an rising edge
occurs on TRGI
Note: This bit acts only on channels that have a
complementary output.
0 RW 0x0 CCPC Capture/compare preloaded control
0: CCE, CCNE and OCM bits are not preloaded
1: CCE, CCNE and OCM bits are preloaded,
after having been written, they are updated only
when a commutation event (COM) occurs
(COMG bit set or rising edge detected on TRGI,
depending on the CCUS bit).
Note: This bit acts only on channels that have a
complementary output
TIM_SMCR address offset: 0x0008

15 RW 0x0 ETP External trigger polarity
This bit selects whether ETR or ETR is used for
trigger operations
0: ETR is non-inverted, active at high level or
rising edge.
1: ETR is inverted, active at low level or falling
edge.
14 RW 0x0 ECE External clock enable
This bit enables External clock mode 2.
0: External clock mode 2 disabled
1: External clock mode 2 enabled.
Note: 1: Setting the ECE bit has the same effect
as selecting external clock mode 1 with TRGI
connected to ETRF (SMS=111 and TS=111).
2: It is possible to simultaneously use external
clock mode 2 with the following slave modes:
reset mode, gated mode and trigger mode.
Nevertheless, TRGI must not be connected to
ETRF in this case (TS bits must not be 111).
3: If external clock mode 1 and external clock
mode 2 are enabled at the same time, the
external clock input is ETRF.
13:12 RW 0x0 ETPS[1:0] External trigger prescaler
External trigger signal ETRP frequency must be
at most 1/4 of TIMCLK frequency. A prescaler
can be enabled to reduce ETRP frequency. It is
useful when inputting fast external clocks.
00: Prescaler OFF
01: ETRP frequency divided by 2
11:8 RW 0x0 ETF[3:0] External trigger filter
This bit-field then defines the frequency used to
sample ETRP signal and the length of the
digital filter applied to ETRP. The digital filter is
made of an event counter in which N events
are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS
0001: fSAMPLING = fCK_INT , N=2
0100: fSAMPLING = fDTS /2, N=6
1110: ffSAMPLING = fDTS /32, N=6
7 RW 0x0 MSM Master/slave mode
0: No action
1: The effect of an event on the trigger input
(TRGI) is delayed to allow a perfect
synchronization between the current timer and
its slaves (through TRGO). It is useful if we want
to synchronize several timers on a single
external event
6:4 RW 0x0 TS[2:0] Trigger selection
This bit-field selects the trigger input to be used
to synchronize the counter.
000: Internal Trigger 0 (ITR0)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
Note: These bits must be changed only when
they are not used (e.g. when SMS=000) to avoid
wrong edge detection at the transition.
2:0 RW 0x0 SMS Slave mode selection
When external signals are selected the active
edge of the trigger signal (TRGI) is linked to the
polarity selected on the external input (see Input
Control register and Control Register
description.
000: Slave mode disabled - if CEN = ‘1’ then the
prescaler is clocked directly by the internal
clock.
001: Encoder mode 1 - Counter counts up/down
on TI2FP2 edge depending on TI1FP1 level.
on TI1FP1 edge depending on TI2FP2 level.
on both TI1FP1 and TI2FP2 edges depending
on the level of the other input.
100: Reset Mode - Rising edge of the selected
trigger input (TRGI) re-initializes the counter and
generates an update of the registers.
101: Gated Mode - The counter clock is enabled
when the trigger input (TRGI) is high. The
counter stops (but is not reset) as soon as the
trigger becomes low. Both start and stop of the
counter are controlled.
110: Trigger Mode - The counter starts at a
rising edge of the trigger TRGI (but it is not
reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of
the selected trigger (TRGI) clock the counter.
Note: The gated mode must not be used if
TI1F_ED is selected as the trigger input
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for
each transition on TI1F, whereas the gated
mode checks the level of the trigger signal.
TIM_DIER address offset: 0x000c
14 RW 0x0 TDE Trigger DMA request enable
0: Trigger DMA request disabled
1: Trigger DMA request enabled
13 RW 0x0 COMDE COM DMA request enable
0: COM DMA request disabled
1: COM DMA request enabled
12 RW 0x0 CC4DE Capture/Compare 4 DMA request enable
0: CC4 DMA request disabled
1: CC4 DMA request enabled
8 RW 0x0 UDE Update DMA request enable
0: Update DMA request disabled
1: Update DMA request enabled
7 RW 0x0 BIE Break interrupt enable
0: Break interrupt disabled
1: Break interrupt enabled
6 RW 0x0 TIE Trigger interrupt enable
0: Trigger interrupt disabled
1: Trigger interrupt enabled
5 RW 0x0 COMIE COM interrupt enable
0: COM interrupt disabled
1: COM interrupt enabled
4 RW 0x0 CC4IE Capture/Compare 4 interrupt enable
0: CC4 interrupt disabled
1: CC4 interrupt enabled
0 RW 0x0 UIE Update interrupt enable
0: Update interrupt disabled
1: Update interrupt enabled
TIM_SR address offset: 0x0010
12 RW 0x0 CC4OF Capture/Compare 4 over capture flag
Note: refer to CC1OF description
This flag is set by hardware only when the
corresponding channel is configured in input
capture mode. It is cleared by software by
writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in
TIM_CCR1 register while CC1IF flag was
already set
7 RW 0x0 BIF Break interrupt flag
This flag is set by hardware as soon as the
break input goes active. It can be cleared by
software if the break input is not active.
0: No break event occurred.
1: An active level has been detected on the
break input.
6 RW 0x0 TIF Trigger interrupt flag
This flag is set by hardware on trigger event
(active edge detected on TRGI input when the
slave mode controller is enabled in all modes but
gated mode. It is set when the counter starts or
stops when gated mode is selected. It is cleared
by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
5 RW 0x0 COMIF COM interrupt flag
This flag is set by hardware on COM event
(when Capture/compare Control bits - CCxE,
CCxNE, OCxM - have been updated). It is
cleared by software.
0: No COM event occurred.
1: COM interrupt pending.
4 RW 0x0 CC4IF Capture/Compare 4 interrupt flag
Note: refer to CC1IF description
If channel CC1 is configured as output:
This flag is set by hardware when the counter
matches the compare value, with some
exception in center-aligned mode (refer to the
CMS bits in the TIM_CR1 register description). It
is cleared by software.
0: No match.
1: The content of the counter TIM_CNT matches
the content of the TIM_CCR1 register.
When the contents of TIM_CCR1 are greater
than the contents of TIM_ARR, the CC1IF bit
goes high on the counter overflow (in upcounting
and up/down-counting modes) or underflow (in
downcounting mode)
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is
cleared by software or by reading the
TIM_CCR1 register.
0: No input capture occurred
1: The counter value has been captured in
TIM_CCR1 register (An edge has been detected
on IC1 which matches the selected polarity)
0 RW 0x0 UIF Update interrupt flag
This bit is set by hardware on an update event. It
0: No update occurred.
1: Update interrupt pending. This bit is set by
hardware when the registers are updated:
⚫ At overflow or underflow regarding the
repetition counter value (update if repetition
counter = 0) and if the UDIS=0 in the TIM_CR1
register.
⚫ When CNT is reinitialized by software using
the UG bit in TIM_EGR register, if URS=0 and
UDIS=0 in the TIM_CR1 register.
⚫ When CNT is reinitialized by a trigger event,
if URS=0 and UDIS=0 in the TIM_CR1 register.
TIM_EGR address offset: 0x0014

7 W 0x0 BG Break generation
This bit is set by software in order to generate an
event, it is automatically cleared by hardware.
0: No action
1: A break event is generated. MOE bit is
cleared and BIF flag is set. Related interrupt or
DMA transfer can occur if enabled.
6 W 0x0 TG Trigger generation
0: No action
1: The TIF flag is set in TIM_SR register. Related
interrupt or DMA transfer can occur if enabled.
5 W 0x0 COMG Capture/Compare control update generation
This bit can be set by software, it is
automatically cleared by hardware
0: No action
1: When CCPC bit is set, it allows to update
CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels having a
complementary output.
4 W 0x0 CC4G Capture/Compare 4 generation
Note: refer to CC1G description
0: No action
1: A capture/compare event is generated on
channel 1:
CC1IF flag is set, Corresponding interrupt or
DMA request is sent if enabled.
The current value of the counter is captured in
TIM_CCR1 register. The CC1IF flag is set,
the corresponding interrupt or DMA request is
sent if enabled. The CC1OF flag is set if the
CC1IF flag was already high.
0 W 0x0 UG Update generation
automatically cleared by hardware.
0: No action
1: Reinitialize the counter and generates an
update of the registers. Note that the prescaler
counter is cleared too (anyway the prescaler
ratio is not affected). The counter is cleared if
the center-aligned mode is selected or if DIR=0
(upcounting), else it takes the auto-reload value
(TIM_ARR) if DIR=1 (downcounting).
TIM_CCMR1 address offset: 0x0018 (Output compare mode)

The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.
15 RW 0x0 OC2CE Output Compare 2 clear enable
14:12 RW 0x0 OC2M Output Compare 2 mode
11 RW 0x0 OC2PE Output Compare 2 preload enable
10 RW 0x0 OC2FE Output Compare 2 fast enable
9:8 RW 0x0 CC2S Capture/Compare 2 Selection
This bit-field defines the direction of the channel
(input/output) as well as the used input.
00: CC2 channel is configured as output
01: CC2 channel is configured as input, IC2 is
mapped on TI2
mapped on TI1
mapped on TRC. This mode is working only if an
internal trigger input is selected through the TS
bit (TIM_SMCR register)
Note: CC2S bits are writable only when the
channel is OFF (CC2E = ‘0’ in TIM_CCER)
0: OC1Ref is not affected by the ETRF Input
1: OC1Ref is cleared as soon as a High level is
detected on ETRF input
These bits define the behavior of the output
reference signal OC1REF from which OC1 and
OC1N are derived. OC1REF is active high
whereas OC1 and OC1N active level depends
on CC1P and CC1NP bits.
000: Frozen - The comparison between the
output compare register TIM_CCR1 and the
counter TIM_CNT has no effect on the
outputs.(this mode is used to generate a timing
base).
001: Set channel 1 to active level on match.
OC1REF signal is forced high when the counter
TIM_CNT matches the capture/compare register
1 (TIM_CCR1).
010: Set channel 1 to inactive level on match.
OC1REF signal is forced low when the counter
TIM_CNT matches the capture/compare register
1 (TIM_CCR1).
011: Toggle - OC1REF toggles when TIM_CNT
= TIM_CCR1.
100: Force inactive level - OC1REF is forced
low.
101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In upcounting, channel 1 is
active as long as TIM_CNT<TIM_CCR1 else
inactive. In downcounting, channel 1 is inactive
(OC1REF=‘0’) as long as TIM_CNT>TIM_CCR1
else active (OC1REF=’1’).
111: PWM mode 2 - In upcounting, channel 1 is
inactive as long as TIM_CNT<TIM_CCR1 else
active. In downcounting, channel 1 is active as
long as TIM_CNT>TIM_CCR1 else inactive.
Note1: These bits can not be modified as long
as LOCK level 3 has been programmed (LOCK
bits in TIM_BDTR register) and CC1S=’00’ (the
channel is configured in output).
Note2: In PWM mode 1 or 2, the OCREF level
changes only when the result of the comparison
changes or when the output compare mode
switches from “frozen” mode to “PWM” mode.
0: Preload register on TIM_CCR1 disabled.
TIM_CCR1 can be written at anytime, the new
value is taken in account immediately.
1: Preload register on TIM_CCR1 enabled.
Read/ Write operations access the preload
register. TIM_CCR1 preload value is loaded in
the active register at each update event.
Note1: These bits can not be modified as long
as LOCK level 3 has been programmed (LOCK
bits in TIM_BDTR register) and CC1S=’00’ (the
Note2: The PWM mode can be used without
validating the preload register only in one pulse
mode (OPM bit set in TIM_CR1 register). Else
the behavior is not guaranteed.
This bit is used to accelerate the effect of an
event on the trigger in input on the CC output.
0: CC1 behaves normally depending on counter
and CCR1 values even when the trigger is ON.
The minimum delay to activate CC1 output when
an edge occurs on the trigger input is 5 clock
cycles.
1: An active edge on the trigger input acts like a
compare match on CC1 output. Then, OC is set
to the compare level independently from the
result of the comparison. Delay to sample the
trigger input and to activate CC1 output is
reduced to 3 clock cycles. OCFE acts only if the
channel is configured in PWM1 or PWM2 mode.
mapped on TI1
mapped on TI2
internal trigger input is selected through TS bit
(TIM_SMCR register)
channel is OFF (CC1E = ‘0’ in TIM_CCER).
TIM_CCMR1 address offset: 0x0018 (Input capture mode)

15:12 RW 0x0 IC2F Input capture 2 filter
11:10 RW 0x0 IC2PSC Input capture 2 prescaler
mapped on TI2
mapped on TI1
(TIM_SMCR register)
This bit-field defines the frequency used to
sample TI1 input and the length of the digital
filter applied
to TI1. The digital filter is made of an event
counter in which N events are needed to
validate a transition on the output:
0000: No filter, sampling is done at fDTS
This bit-field defines the ratio of the prescaler
acting on CC1 input (IC1). The prescaler is reset
as soon as CC1E=’0’ (TIM_CCER register).
00: no prescaler, capture is done each time an
edge is detected on the capture input
01: capture is done once every 2 events
mapped on TI1
mapped on TI2
(TIM_SMCR register)
TIM_CCMR2 address offset: 0x001c (Output compare mode)

mapped on TI4
mapped on TI3
(TIM_SMCR register)
mapped on TI3
mapped on TI4
(TIM_SMCR register)
TIM_CCMR2 address offset: 0x001c (Input capture mode)

mapped on TI4
mapped on TI3
(TIM_SMCR register)
mapped on TI3
mapped on TI4
(TIM_SMCR register)
TIM_CCER address offset: 0x0020

13 RW 0x0 CC4P Capture/Compare 4 output polarity
Note: refer to CC1P description
12 RW 0x0 CC4E Capture/Compare 4 output enable
Note: refer to CC1E description
11 RW 0x0 CC3NP Capture/Compare 3 complementary output
polarity
Note: refer to CC1NP description
10 RW 0x0 CC3NE Capture/Compare 3 complementary output
enable
Note: refer to CC1NE description
polarity
Note: refer to CC1NP description
enable
Note: refer to CC1NE description
polarity
0: OC1N active high.
1: OC1N active low.
Note: This bit is not writable as soon as LOCK
level 2 or 3 has been programmed (LOCK bits in
TIM_BDTR register) and CC1S=”00” (the
enable
0: Off - OC1N is not active. OC1N level is then
function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1E bits.
1: On - OC1N signal is output on the
corresponding output pin depending on MOE,
OSSI, OSSR, OIS1, OIS1N and CC1E bits.
CC1 channel configured as output:
0: OC1 active high
1: OC1 active low
CC1 channel configured as input:
This bit selects whether IC1 or IC1 is used for
trigger or capture operations.
0: non-inverted: capture is done on a rising edge
of IC1. When used as external trigger, IC1
is non-inverted.
1: inverted: capture is done on a falling edge of
IC1. When used as external trigger, IC1 is
inverted.
Note: This bit is not writable as soon as LOCK
level 2 or 3 has been programmed (LOCK bits in
TIM_BDTR register).
CC1 channel configured as output:
0: Off - OC1 is not active. OC1 level is then
function of MOE, OSSI, OSSR, OIS1, OIS1N
and CC1NE bits.
1: On - OC1 signal is output on the
corresponding output pin depending on MOE,
OSSI, OSSR, OIS1, OIS1N and CC1NE bits.
CC1 channel configured as input:
This bit determines if a capture of the counter
value can actually be done into the input
capture/compare register 1 (TIM_CCR1) or not.
0: Capture disabled.
1: Capture enabled.
Control bits Output states

MOE OSSI OSSR CCxE CCxNE OCx outpput state OCxN output state
output disabled (not driven by output disabled (not driven by
0 0 0 the timer) the timer)
1 X
OCx = 0, OCx_EN = 0 OCxN = 0, OCxN_EN = 0
0 0 1 output disabled (not driven by OCxREF + Polarity
the timer) OCxN = OCxREF xor CCxNP,
OCx = 0, OCx_EN = 0 OCxN_EN = 1
OCxREF + Polarity output disabled (not driven by
0 1 0 OCx = OCxREF xor CCxP, the timer)
OCx_EN = 1 OCxN = 0, OCxN_EN = 0
Complementary to OCREF
OCREF + Polarity + dead
(not OCREF) + Polarity + dead
0 1 1 time
time
OCx_EN = 1
OCxN_EN = 1
output disabled (not driven by
output disabled (not driven by
the timer)
1 0 0 the timer)
OCxN = CCxNP, OCxN_EN =
OCx = CCxP, OCx_EN = 0
0
off-state (output enabled with OCxREF + Polarity
1 0 1 inactive state) OCxN = OCxREF xor CCxNP,
OCx = CCxP, OCx_EN = 1 OCxN_EN = 1
off-state (output enabled with
OCxREF + Polarity
inactive state)
1 1 0 OCx = OCxREF xor CCxP,
OCxN = CCxNP, OCxN_EN =
OCx_EN = 1
1
Complementary to OCREF
OCREF + Polarity + dead
(not OCREF) + Polarity + dead
1 1 1 time
time
OCx_EN = 1
OCxN_EN = 1
0 0 0 output disabled (not driven by the timer)
0 0 1 Asynchronously: OCx = CCxP, OCx_EN = 0, OCxN = CCxNP,
0 1 0 OCxN_EN = 0
0 1 1 Then if the clock is present: OCx = OISx and OCxN = OISxN
after a dead time, assuming that OISx and OISxN do not
1 0 0
correspond to OCX and OCxN both in active state
1 X
1 0 1 off-state (output enabled with inactive state)
1 1 0 Asynchronously: OCx = CCxP, OCx_EN = 1, OCxN = CCxNP,
OCxN_EN = 1
Then if the clock is present: OCx = OISx and OCxN = OISxN
1 1 1
after a dead time, assuming that OISx and OISxN do not
correspond to OCX and OCxN both in active state
Table 9.6 Output control bits for complementary OCx and OCxN channels
with brake function
Note 1: When both outputs of a channel are not used (CCxE = CCxNE = 00), the OISx,
OISxN, CCxP and CCxNP bits must be kept cleared.
Note 2: The state of the external I/O pins connected to the complementary OCx and OCxN
channels depends on the OCx and OCxN channel state and the GPIO and AFIO registers.
TIM_CNT address offset: 0x0024
15:0 RW 0x0 CNT Counter value
TIM_PSC address offset: 0x0028

15:0 RW 0x0 PSC Prescaler value
The counter clock frequency (CK_CNT) is equal
to fCK_PSC / (PSC[15:0] + 1).
PSC contains the value to be loaded in the
active prescaler register at each update event
(including when the counter is cleared through
UG bit of TIM_EGR register or through trigger
controller when configured in “reset mode”)
TIM_ARR address offset: 0x002c

15:0 RW 0x0 ARR Prescaler value
ARR is the value to be loaded in the actual auto-
reload register.
The counter is blocked while the auto-reload
value is null.
TIM_RCR address offset: 0x0030

7:0 RW 0x0 REP Repetition counter value
These bits allow the user to set-up the update
rate of the compare registers (i.e. periodic
transfers from preload to active registers) when
preload registers are enable, as well as the
update interrupt generation rate, if this interrupt
is enable.
Each time the REP_CNT related downcounter
reaches zero, an update event is generated and
it restarts counting from REP value. As
REP_CNT is reloaded with REP value only at
the repetition update event U_RC, any write to
the TIMx_RCR register is not taken in account
until the next repetition update event.
It means in PWM mode (REP+1) corresponds
to:
⚫ the number of PWM periods in edge-
aligned mode
⚫ the number of half PWM period in center-
aligned mode
TIM_CCR1 address offset: 0x0034

15:0 RW 0x0 CCR1 Capture/Compare 1 value
CCR1 is the value to be loaded in the actual
capture/ compare 1 register (preload value).
It is loaded permanently if the preload feature is
not selected in the TIM_CCMR1 register (bit
OC1PE). Else the preload value is copied in the
active capture/ compare 1 register when an
update event occurs.
The active capture/compare register contains
the value to be compared to the counter
TIM_CNT and signaled on OC1 output.
CCR1 is the counter value transferred by the
last input capture 1 event (IC1)

last input capture 2 event (IC2).
TIM_CCR3 address offset: 0x003c


TIM_BDTR address offset: 0x0044

15 RW 0x0 MOE Main output enable
This bit is cleared asynchronously by hardware
as soon as the break input is active. It is set by
software or automatically depending on the AOE
bit. It is acting only on the channels which are
configured in output.
0: OC and OCN outputs are disabled or forced
to idle state.
1: OC and OCN outputs are enabled if their
respective enable bits are set (CCxE, CCxNE in
TIM_CCER register).
14 RW 0x0 AOE Automatic output enable
0: MOE can be set only by software
1: MOE can be set by software or automatically
at the next update event (if the break input is not
be active)
LOCK level 1 has been programmed (LOCK bits
in TIM_BDTR register).
13 RW 0x0 BKP Break polarity
0: Break input BRK is active low
1: Break input BRK is active high
LOCK level 1 has been programmed (LOCK bits
in TIM_BDTR register).
Note: Any write operation to this bit takes a
delay of 1 APB clock cycle to become effective.
12 RW 0x0 BKE Break enable
0: Break inputs (BRK and CCS clock failure
event) disabled
1: Break inputs (BRK and CCS clock failure
event) enabled
Note: This bit cannot be modified when LOCK
level 1 has been programmed (LOCK bits in
TIM_BDTR register).
Note: Any write operation to this bit takes a
delay of 1 APB clock cycle to become effective.
11 RW 0x0 OSSR Off-state selection for Run mode
This bit is used when MOE=1 on channels
having a complementary output which are
configured as outputs. OSSR is not
implemented if no complementary output is
implemented in the timer.
0: When inactive, OC/OCN outputs are disabled
(OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are enabled
with their inactive level as soon as CCxE=1 or
CCxNE=1. Then, OC/OCN enable output
signal=1
Note: This bit can not be modified as soon as
the LOCK level 2 has been programmed (LOCK
bits in TIM_BDTR register).
10 RW 0x0 OSSI Off-state selection for Idle mode
This bit is used when MOE=0 on channels
configured as outputs.
0: When inactive, OC/OCN outputs are disabled
(OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are forced
first with their idle level as soon as CCxE=1 or
CCxNE=1. OC/OCN enable output signal=1)
Note: This bit can not be modified as soon as
the LOCK level 2 has been programmed (LOCK
bits in TIM_BDTR register.
9:8 RW 0x0 LOCK Lock configuration
These bits offer a write protection against
software errors.
00: LOCK OFF - No bit is write protected.
01: LOCK Level 1 = DTG bits in TIM_BDTR
register, OISx and OISxN bits in TIM_CR2
register and BKE/BKP/AOE bits in TIM_BDTR
register can no longer be written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity
bits (CCxP/CCxNP bits in TIM_CCER register,
as long as the related channel is configured in
output through the CCxS bits) as well as OSSR
and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control
bits (OCxM and OCxPE bits in TIM_CCMRx
registers, as long as the related channel is
configured in output through the CCxS bits) can
no longer be written.
Note: The LOCK bits can be written only once
after the reset. Once the TIM_BDTR register
has been written, their content is frozen until the
next reset.
7:0 RW 0x0 DTG Dead-time generator setup
This bit-field defines the duration of the dead-
time inserted between the complementary
outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg
=tDTS .
DTG[7:5]=10x => DT=(64+DTG[5:0])x tdtg with
Tdtg = 2x tDTS .
DTG[7:5]=110 => DT=(32+DTG[4:0])x tdtg with
Tdtg = 8x tDTS .
DTG[7:5]=111 => DT=(32+DTG[4:0])x tdtg with
Tdtg = 16x tDTS .
Example if TDTS =125ns (8MHz), dead-time
possible values are:
0 to 15875ns by 125ns steps,
16 us to 31750ns by 250ns steps,
32 us to 63us by 1 us steps,
64 us to 126 us by 2 us steps
Note: This bit-field can not be modified as long
as LOCK level 1, 2 or 3 has been programmed
(LOCK bits in TIM_BDTR register
TIM_DCR address offset: 0x0048

12:8 RW 0x0 DBL DMA burst length
This 5-bit vector defines the number of DMA
transfers (the timer detects a burst transfer
when a read or a write access to the
TIM_DMAR register address is performed).
the TIM_DMAR address)
00000: 1 transfer
00001: 2 transfers
00010: 3 transfers
to
10001: 18 transfers
Example: Let us consider the following transfer:
DBL = 7 bytes & DBA = TIM2_CR1.
⚫ If DBL = 7 bytes and DBA = TIM2_CR1
represents the address of the byte to be
transferred, the address of the transfer
should be given by the following equation:
(TIM_CR1 address) + DBA + (DMA index),
where DMA index = DBL
In this example, 7 bytes are added to (TIM_CR1
address) + DBA, which gives us the address
from/to which the data will be copied. In this
case, the transfer is done to 7 registers starting
from the following address: (TIM_CR1 address)
+ DBA
According to the configuration of the DMA Data
Size, several cases may occur:
⚫ If you configure the DMA Data Size in half-
words, 16-bit data will be transferred to
each of the 7 registers.
⚫ If you configure the DMA Data Size in
bytes, the data will also be transferred to 7
registers: the first register will contain the
first MSB byte, the second register, the first
LSB byte and so on. So with the transfer
Timer, you also have to specify the size of
data transferred by DMA.
4:0 RW 0x0 DBA DMA base address
This 5-bits vector defines the base-address for
DMA transfers (when read/write access are
done through the TIM_DMAR address). DBA is
defined as an offset starting from the
address of the TIM_CR1 register.
00000: TIM_CR1,
00001: TIM_CR2,
00010: TIM_SMCR,
...
TIM_DMAR address offset: 0x004c

15:0 RW 0x0 DMAB DMA register for burst accesses
A read or write operation to the DMAR register
accesses the register located at the address
(TIM_CR1 address) + (DBA + DMA index) x 4
where TIM_CR1 address is the address of the
control register 1, DBA is the DMA base address
configured in TIM_DCR register, DMA index is
automatically controlled by the DMA transfer,
and ranges from 0 to DBL (DBL configured in
TIM_DCR).

0x001c TIM_CCER Timer capture/compare enable register
0x0028 TIM_ARR Timer auto-reload register
0x002c TIM_RCR Timer reperepetition counter register

9:8 RW 0x0 CKD Clock division
dead-time and sampling clock (tDTS)used by the
1 RW 0x0 UDIS Update disable,
0: Counter disabled
1: Counter enabled

8 RW 0x0 OIS1 OIS1: Output Idle state 1 (OC1 output)
occurs
setting
the COMG bit only
setting
the COMG bit or when an rising edge occurs on
TRGI
1: CCE, CCNE and OCM bits are preloaded

trigger operations
rising edge.
edge.
13:12 RW 0x0 ETPS External trigger prescaler
11:8 RW 0x0 ETF External trigger filter
6:4 RW 0x0 TS Trigger selection


1: Update interrupt pending.

0: No action
channel 1:
0: No action
update of the registers.


polarity
enable



reload register.






0x001c TIM_CCMR2 Timer capture/compare mode register2
0x0020 TIM_CCER Timer capture/compare enable register
0x002c TIM_ARR Timer auto-reload register
0x0030 TIM_RCR Timer reperepetition counter register
0x003c TIM_CCR3 Timer capture/compare register3

9:8 RW 0x0 CKD Clock division
dead-time and sampling clock (tDTS)used by the
1 RW 0x0 UDIS Update disable,
0: Counter disabled
1: Counter enabled

occurs
setting
the COMG bit only
setting
the COMG bit or when an rising edge occurs on
TRGI
1: CCE, CCNE and OCM bits are preloaded

trigger operations
rising edge.
edge.
13:12 RW 0x0 ETPS External trigger prescaler
11:8 RW 0x0 ETF External trigger filter
6:4 RW 0x0 TS Trigger selection


1: Update interrupt pending.

0: No action
channel 4
0: No action
channel 3
0: No action
channel 2
0: No action
channel 1
0: No action
update of the registers

TIM_CCMR2 address offset: 0x001c (Output compare mode)


polarity
enable
polarity
enable
polarity
enable


reload register.



TIM_CCR3 address offset: 0x003c





9.8. GPADC
9.8.1. Introduction
The OM6621Ex is equipped with a high-speed low power 12-bit general purpose Analog-
to-Digital Converter (GPADC). It can operate in unipolar (single ended) mode.
• 12-bit dynamic ADC with 8 us conversion time

• Maximum sampling rate 500k sample/s
• Single-ended input
• 8x single-ended external input channels
• Battery monitoring function
• Temperature monitoring function
• Offset and gain calibration
• Support voltage input range: 0.3V~(VBAT-0.3)V
VTEMP ADC
VBAT
GPIO[2]
GPIO[3]
GPIO[8]
GPIO[9] MUX Buffer
GPIO[10]
GPIO[11]
GPIO[12] ADC
PGA
GPIO[13] Core
VCM
Figure 9.79 Block Diagram

The analog MUX selects the input voltages to detect the temperature, supply voltage, and
external voltage.

VAVDD Main analog supply 1.8 3.6 V
VIN Input range 0.3 VAVDD-0.3
IADC Current consumption uA
FSAMPLE throughput rate 125/250/500 ksps
DNL Differential non-linearity <1 LSB
INL Integral non-linearity <1 LSB
Effective number of bits
FSAMPLE=125ksps 10.97 bits
ENOB
Signal to noise + distortion ratio
FSAMPLE=125ksps 67.8 dB
SNDR
THD Total harmonic distortion -71.7 dB
VOS Offset error (Calibrated)
GE Gain error %
Table 9.7 GPADC Specifications
9.8.5. GPADC Register Map

0x0000 INTR Raw interrupt write 1 to clear
0x0004 INTR MASK Interrupt mask
0x0008 DLY _CFG dly counter register
0x0010 ADC_CFG0 Adc status register
0x0014 ADC_CFG1 Adc work mode register
0x0018 ADC_CFG2 Channel register
0x0020 ADC_SW_TRIG Sw trigger register
0x0030 CH_0_CFG Channel 0 register
0x003c CH_3_CFG Channel 3 register
0x004c CH_7_CFG Channel 7 register
0x0060 VOS_TEMP_REG Vos_temp register
0x0068 CH_0_DATA Channel 0 output data
0x006c CH_1_DATA Channel 1 output data
0x00B0 CH DMA DATA Output data in DMA mode
0x00B4 DMA CNS Dma control and status
INTR address offset: 0x0000

12 RW 0x0 OVR Interrupt over sampling status
Read 1: data invalid
Read 0: data valid
Write 1: clear
11 RW 0x0 EOA Interrupt eoa status
Read 1: end of all conversion
Write 1: clear
10 RW 0x0 EOS Interrupt eos status
Read 1: end of single sequence conversion
Write 1: clear
9 RW 0x0 EOC_9 Interrupt eoc_9 status
Read 1: end of channel 9 conversion
Write 1: clear
8 RW 0x0 EOC_8 Interrupt eoc_8 status, 1 eoc_8 intr and write
1 clear
1 clear
1 clear
1 clear
1 clear
1 clear
1 clear
1 clear
1 clear
INTR_MASK address offset: 0x0004
31:13 RW 0x0 INTR reserved
RESERVED
REG
12 RW 0x0 OVR_MSK Interrupt ovr mask,
0: masked
1: enable
11 RW 0x0 EOA_MSK Interrupt eoa mask,
0: masked
1: enable
10 RW 0x0 EOS_MSK Interrupt eos mask,
0: masked
1: enable
9 RW 0x0 EOC_9_MSK Interrupt eoc_9 mask,
0: masked
1: enable
0: masked
1: enable
0: masked
1: enable
0: masked
1: enable
0: masked
1: enable
0: masked
1: enable
0: masked
1: enable
0: masked
1: enable
0: masked
1: enable
0: masked
1: enable
DLY_CFG address offset: 0x0008
23:16 RW 0x14 ORB_DLY Delay time from one channel to another
channel
0x00:
0xFF:
Step:
15:8 RW 0x50 PD_DLY_MAX Delay time from power down mode to normal
work mode
0x00:
0xFF:
Step:
7:0 RW 0x50 CFG_CHG_DLY Delay time from suspend mode to normal
work mode
0x00:
0xFF:
Step:
ADC_CFG0 address offset: 0x0010

31:13 R 0x0 N/A reserved
12 R 0x0 ADC_SUSPEN Read suspend mode status:
D 0: other status
1: suspend mode
4 W 0x0 ADC_STOP Stop adc and return to IDLE_PD
Write 1: clear the adc_start status
3:2 RW 0x0 N/A Reserved
1 R 0x0 ADC_MODE adc_mode
0: auadc
1: gpadc
0 RW 0x0 ADC_START Start the adc sfsm
Write 1: start

31:24 RW 0x20 DIGI_CLK_FRE div clk_gated for the wait counter
Q 0x00:
0xFF:
Step:
23 RW 0x0 N/A reserved
22:20 RW 0x4 AVG_CFG number of 1<<avg_cfg gpadc_out summed
then averaged
0x00:
0xFF:
Step:
14:13 RW 0x0 GP_BIT_SEL Sample cycles:
01: 32 cycles
10: 64 cycles
11: 128 cycles
Note: 00 no define
12 RW 0x0 DMA_EN DMA enable control
0: disable
1: enable
11:8 RW 0x0 TRIG_HW_SEL Select trigger source
4’b0000:ext_trigger = timer1_toggle[0]
4’b0100:ext_trigger = timer2_toggle
4’b1100:ext_trigger = timer1_ext
Default:ext_trigger = 1’b0
6 RW 0x0 TRIG_RES Triger resolution
0:per channel
1:per sequence
5:4 RW 0x0 TRIG MODE Select the trigger source
01:ext_trigger pedge
10:ext_trigger nedge
11:ext_trigger pedge || ext_trigger nedge
Default:adc_sw_trig_wr || sw_trigger_true
2 RW 0x0 AUTO_PD2 After whole sequence, return to status below:
1: power down mode
0: suspend mode
1 RW 0x0 AUTO_DELAY the ch ready and data not fetched, will block
ch after it
0: disable
1: enable
0 RW 0x0 AUTO_PD1 Per channel power down after trigger
1: power down
0: power on

31:16 RW 0x1 SEQ_LIFE The numbers of sequence
0:
10:1 RW 0x10 SEQ_VECT Channel enable,
1: enable
0:disable
Seq_vect[*] :CH_*_enable
0 RW 0x0 SCANDIR Ch sequence order,
1: incr mode from 0 to 10
0:decr mode from 10 to 0
ADC_SW_TRIG address offset: 0x0020

31 RW 0x0 SW_TRIGGER_ The trigger is always true
TRUE
CH_0_CFG address offset: 0x0030

1:0 RW 0x0 SEL_GP_VERF 01: 1.25V
Note: 00/10/11 no define

1:0 RW 0x0 SEL_GP_VERF The same with CH_0_CFG
CH_3_CFG address offset: 0x003c



CH_7_CFG address offset: 0x004c



VOS_TEMP_REG address offset: 0x0060

27 RW 0x1 PD_GP_TEMP_ Temperature detection power control
GEN 0: power up
1: power down
26:24 RW 0x5 TEMP_SEL
000: 20℃
to
111: 27℃
CH_0_DATA address offset: 0x0068

15:0 RW 0x0 CH_0_DATAL adc out data in ch_0
CH_1_ DATA address offset: 0x006C

CH_2_ DATA address offset: 0x0070







CH_DMA_ DATA address offset: 0x00B0

31:0 RW 0x0 CH_DMA_DATA adc out data in dma mode
DMA_CNS address offset: 0x00B4

7:4 RW 0x0 CH_ID_DMA The active channel in dma mode
1:0 R 0x0 DFSM Dma fsm only read for debug
9.9. I2S
9.9.1. Introduction
The I2S is designed to be used in systems that process digital audio signals, such as:
• A/D and D/A converters
• digital signal processors
• error correction for compact disc and digital recording
• digital filters
• digital input/output interfaces
The Inter-IC Sound (I2S) Bus is a simple three-wire serial bus protocol developed by Philips
to transfer stereo audio data. The bus only handles the transfer of audio data; hence control
and sub-coding signals need to be transferred separately using a different bus protocol
(such as I2C).
• I2S transmitter and/or receiver based on the Philips I2S serial protocol
• one stereo channel for transmitter and another for receiver
• Full duplex communication due to the independence of transmitter and receiver
• Slave mode of operation
• Audio data resolutions of 24 bits
• FIFO depth is 16
• Programmable FIFO thresholds level
The I2S bus can only handle audio data transmissions; sub-coding and controls are
handled by another device, such as an I2C. The I2S protocol requires three wires—data
(sd), word select (ws), and serial clock (sclk)—keeping the design simple and the pin count
minimal. However, I2S are configured to have one channel for transmit or receive
operations.
The component operating as a slave, I2S responds to externally generated sclk and ws
signals. An external sclk and an inverted version of sclk need to be supplied to the device
via input signals sclk and sclk_n. I2S supports the standard I2S frame format for
transmitting and receiving data —the MSB of aword is sent one sclk cycle after a word
select change.
9.9.3.1. I2S Enable
You must enable the I2S component before any data can be received or transmitted into
the FIFO.
To enable the component, set the I2S Enable (IEN) bit of the I2S Enable Register (IER) to
1. When you disable.The device, it acts as a global disable. To disable I2S, set IER[0] to 0.
After disable, the following events occur:
• TX and RX FIFO are cleared, and read/write pointers are reset;
• Any data in the process of being transmitted or received is lost;
• All other programmable enables (such as transmitter/receiver block enables and
TX/RX channel enables) in the component are overridden;
As I2S is configured as a slave, ws is externally supplied. On reset, the IER[0] is set to 0
(disable).
9.9.3.2. I2S_TX as Transmitter
The I2S_TX are configured to support up to one stereo I2S_TX transmit (TX) channel. The
channel only operate in slave mode. By default, I2S_TX is configured in slave mode only.
Stereo data pairs (such as, left and right audio data) written to a TX channel via the APB
bus are shifted out serially on the appropriate serial data out line (sdo). The shifting is timed
with respect to the serial clock (sclk) and the word select line (ws).
The following figure illustrates the basic usage flow for I2S_TX.
Software Flow
IDLE
Enable
IER[0]=1
TX DMA Yes
enable?
No
Fill TX FIFOs
by writing data to Enable
LTHR and RTHR Transmitter block
until filled ITER[0]=1
Enable Fill TX FIFO

Transmitter by writing data
block ITER[0]=1 Via TXDMA
Figure 9.80 Basic Usage Flow – I2S as Transmitter
9.9.3.3. Transmitter Block Enable
The I2S_TX Transmitter Enable Register (ITER) globally turns on and off TX channel.To
enable the transmitter block, set ITER[0] to 1.To disable the block, set ITER[0] to 0.
When the transmitter block is disabled, the following events occur:
• Outgoing data is lost and the channel output are held low;
• Data in the TX FIFO are preserved and the FIFO can be written to;
• Any previous programming (like changes in word size, threshold levels, and so on) of
the TX channel is preserved;
• The TX channel enable are overridden.
When the transmitter block is enabled, if there is data in the TX FIFO, the channel resumes
transmission on the next left stereo data cycle (such as when the ws line goes low).
When the block is disabled, you can perform any of the following procedures:
• Program (or further program) TX channel registers
• Flush the TX FIFO by programming the Transmitter FIFO Reset bit of the Transmitter
FIFO Flush Register (TXFFR[0] = 1)
• Flush the channel’s TX FIFO by programming the Transmit Channel FIFO
Reset(TXCHFR) bit of the Transmit FIFO Flush Register (TFF [0] = 1)
On reset, the ITER[0] is set to 0 (disable) .
9.9.3.4. Transmit Channel Enable
The transmit channel has enable/disable that can be set to allow the reprogramming of
the channel and to flush the channel’s TX FIFO while other TX channel are transmitting.
This enable/disable is controlled by bit 0 of the Transmitter Enable Register (TER).When
a TX channel is disabled, the following occurs:
• Outgoing stereo data is lost;
• Channel output is held low;
• Data in the TX FIFO is preserved, and the FIFO can be written to;
• Any previous programming of the TX channel’s registers is preserved, and the
registers can be further reprogrammed.
When a TX channel is disabled, you can flush the channel’s TX FIFO by programming the
Transmit Channel FIFO Reset (TXCHFR) bit of the Transmit FIFO Flush (TFF [0] = 1).
When the TX channel is enabled, if there is data in the TX FIFO, the channel resumes
transmission on the next left stereo data cycle (such as, when the ws line goes low).On
reset, the TFF [0] is set to 1 (enable).
9.9.3.5. Transmit Channel FIFO
The Transmit Channel has two FIFO banks for left and right stereo data. The FIFO is
configured with depths of 16 bits. The FIFO width is determined by the “Maximum Audio
Resolution – Transmit Channel”.
There are several ways to clear the TX FIFO and reset the read/write pointers as described
as follows;
• on reset
• by disabling I2s (IER[0] = 0)
• by flushing the transmitter block (TXFFR[0] = 1)
• by flushing an individual TX channel (TFF [0] = 1)
You must disable the transmitter block/channel before the transmitter block and individual
channel FIFO can be flushed.
The TX FIFO Empty Threshold Trigger Level sets the default trigger threshold level for the
TX FIFO. The trigger level is set to4. When this level is reached, a transmit channel empty
interrupt is generated. This level can be reprogrammed during operation by writing to the
Transmit Channel Empty Trigger (TXCHET) bits of the Transmit FIFO Configuration
Register (TFCR [3:0],).
You must disable the TX channel prior to changing the trigger level.
9.9.3.6. Transmit Channel Interrupts
All interrupts in I2S_TX is configured as active high. THE I2S_TX channel generates two
interrupts: TX FIFO Empty and Data Overrun.
• TX FIFO Empty interrupt – This interrupt is asserted when the empty trigger threshold
level for the TX FIFO is reached. When this interrupt is included on the I/O, it appears
on the outputs tx_emp_ intr. A TX FIFO Empty interrupt is cleared by writing data to
the TX FIFO to bring its level above the empty trigger threshold level for the channel.
• Data Overrun interrupt –This interrupt is asserted when an attempt is made to write to
a full TX FIFO (any data being written is lost while data in the FIFO is preserved).
When this interrupt is included on the I/O, it appears on the outputs tx_or_ intr. A Data
Overrun interrupt is cleared by reading the Transmit Channel Overrun (TXCHO) bit [0]
of the Transmit Overrun Register (TOR).
The interrupt status of any TX channel can be determined by polling the Interrupt Status
Register (ISR). The TXFE bit [4] indicates the status of the TX FIFO Empty interrupt, while
the TXFO bit [5] indicates the status of the Data Overrun interrupt.
Both the TX FIFO Empty and Data Overrun interrupts can be masked off by writing a 1 in
the Transmit Empty Mask (TXFEM) and Transmit Overrun Mask (TXFOM) bits of the
Interrupt Mask Register (IMR), respectively. This prevents the interrupts from driving their
output lines, however, the ISR always shows the current status of the interrupts regardless
of any masking.
9.9.3.7. Writing to a Transmit Channel
The stereo data pairs to be transmitted by a TX channel are written to the TX FIFO via the
Left Transmit Holding Register (LTHR) and the Right Transmit Holding Register (RTHR).
All stereo data pairs must be written using the following two stage process:
• Write left stereo data to LTHR.
• Write right stereo data to RTHR.
Note: You must write stereo data to the device in this order, otherwise, the interrupt and
status lines values will be invalid, and the left/right stereo pairs might be transmitted out of
sync.
When TX DMA is enabled (I2S_TX_DMA = 1), data to be transmitted by TX channels are
written to the TX FIFO via the TXDMA register rather than through LTHR and RTHR. Data
is written cyclically through all enabled TX channel starting from the lowest-numbered
enabled channel. After a stereo data pair is transmitted, the component will point to the
next enabled channel.
The following example describes the behavior of the TXDMA register for a component that
has been configured with the Transmit channels, where Channel are enabled. Order of
transmitted data:
• Ch0 — Left Data
• Ch0 — Right Data
• Ch0 — Right Data, and so on
The RTXDMA register resets TXMDA to the lowest-enabled Channel. The RTXDMA
register can be written to at any stage of the TXDMA transmit cycle; however, it has no
effect when the component is in the middle of a stereo pair transmit.
The following example describes the operation of this register for a system with four
Transmit channels, where all the channels are enabled.
Order of transmitted data
• RTXDMA Reset
• RTXDMA Reset — No effect (read not complete)
• RTXDMA Reset
When I2S_TX is enabled, if the TX FIFO is empty and data is not written to the FIFO before
the next left cycle, the channel output zeros for a full frame (left and right cycle).
Transmission only commences if there is data in the TX FIFO prior to the transition to the
left data cycle. In other words, if the start of the frame is missed, the channel output idles
until the next available frame.
Note:Data should only be written to the FIFO when it is not full. Any attempt to write to a
full FIFO results in that data being lost and a Data Overrun interrupt being generated.
9.9.3.8. I2S_RX as Receiver
I2S_RX is configured to support to four stereo I2S receive (RX) channel. This channel can
operate only in slave mode. Stereo data pairs (such as, left and right audio data) are
received serially from a data input line (sdi). These data words are stored in RX FIFO until
they are read via the APB bus. The receiving is timed with respect to the serial clock (sclk)
and the word select line (ws). By default, I2S_RX is configured with one receive
channel.The following figure illustrates the basic usage flow for I2S_RX when it acts as a
receiver.
Software Flow
IDLE
Enable
IER[0]=1
Enable
Receiver block
IRER[0]=1
Read ISR[0]
when bit goes high
default trigger level
has been reached
RX DMA
Enabled?
Read contents of
Read contents of
LRBR/RRBR
LRBR and RRBR
via RXDMA
No
Yes
Figure 9.81 Basic Usage Flow – I2S_RX as Receiver
Receiver Block Enable

The Receiver Block Enable (RXEN) bit of the I2S Receiver Enable Register (IRER)
enables/disables all configured RX channel. To enable the receiver block, set IRER[0] to
‘1’. To disable the block, set this bit to ‘0’.
When the receiver block is disabled, the following events occur:
• Incoming data is lost;
• Data in the RX FIFO is preserved and the FIFO can be read;
• Any previous programming (such as changes in word size, threshold level, and so on)
of the RX channels is preserved;
• Any individual RX channel enable is overridden. Enabling the channel resumes
receiving on the next left stereo data cycle (for instance, when ws goes low).
When the block is disabled, you can perform any of the following procedures:
• Program (or further program) the RX channel registers;
• Flush the RX FIFO by programming the Receiver FIFO Reset (RXFR) bit of the
Receiver FIFO Flush Register (RXFFR[0] = 1);
• Flush an individual channel’s RX FIFO by programming the Receive Channel FIFO
Reset (RXCHFR) bit of the Receive FIFO Flush Register (RFF [0] = 1).
On reset, IRER[0] is set to 0 (disable).
Receive Channel Enable

The I2S_ RX channel has enable/disable that can be set to allow programming of the
channel and to clear the channel’s RX FIFO while other RX channel are still receiving data.
This enable/disable is controlled by bit 0 of the Receiver Enable Register (RER [0]). When
the I2S_RX channel is disabled, the following occurs:
• Incoming data is lost;
• Data in the RX FIFO is preserved;
• FIFO can be read;
• Previous programming of the RX channel is preserved;
• RX channel can be further programmed.
When the RX channel or block is disabled, you can flush the channel’s RX FIFO by writing
1 in bit 0 of the Receive FIFO Flush Register (RFF). When the channel is enabled, it
resumes receiving on the next left stereo data cycle (for instance. when ws line goes low).
On reset, the RFF[0] is set to 1 (enable).
Receive Channel FIFO

The Receive Channel has two FIFO banks for left and right stereo data. The FIFO can be
configured with depth of 16 bits. The FIFO width is determined by the data resolution for
the channel.
The RX FIFO can be cleared and the read/write pointers reset in a number ways, as
described as follows:
• on reset
• by disabling I2S_RX (IER[0] = 0)
• by flushing the receiver block (RXFFR[0] = 1)
• by flushing an individual RX channel (RFF[0] = 1)
Before you flush the receiver block or channel, you must disable the receiver block or
channel.
The RX FIFO Data Available Level parameter (I2S_RX_FIFO_THRE) sets the default data
available trigger level for the RX FIFO. When this level is reached, a RX channel data
available interrupt is generated. The valid values are 0 to FIFO_DEPTH–1, which
correspond to trigger levels of 1 to FIFO_DEPTH (for example,default Trigger Level =4).
This level can be reprogrammed during operation via the Receive Channel Data Trigger
(RXCHDT) bits of the Receive FIFO Configuration Register (RFCR [3:0]). The RX channel
needs to be disabled prior to any changes in the trigger level.
Receive Channel Interrupts

All interrupts in I2S_RX are configured as active high , The RX channel generates two
interrupts: RX FIFO Data Available and Data Overrun.
• RX FIFO Data Available interrupt – This interrupt is asserted when the trigger level for
the RX FIFO is reached. When this interrupt is included on the I/O, it appears on the
outputs rx_da_ intr. This interrupt is cleared by reading data from the RX FIFO until its
level drops below the data available trigger level for the channel.
• Data Overrun interrupt – This interrupt is asserted when an attempt is made to write
received data to a full RX FIFO (any data being written is lost while data in the FIFO
is preserved). When this interrupt is included on the I/O, it appears on the outputs
rx_or_ intr. This interrupt is cleared by reading the Receive Channel Overrun (RXCHO)
bit [0] of the Receive Overrun Register (ROR).
The interrupt status of any RX channel can be determined by polling the Interrupt Status
Register (ISR). The RXDA bit [0] indicates the status of the RX FIFO Data Available
interrupt; the RXFO bit [1] indicates the status of the RX FIFO Data Overrun interrupt.
Both the Receive Empty Threshold and Data Overrun interrupts can be masked by writing
a 1 in the Receive Empty Threshold Mask (RDM) and Receive Overrun Mask (ROM) bits
of the Interrupt Mask Register (IMR), respectively. This prevents the interrupts from driving
their output lines, however, the ISR always shows the current status of the interrupts
regardless of any masking.
Reading from a Receive Channel

The stereo data pairs received by the RX channel are written to the left and right RX FIFO.
This FIFO can be read via the Left Receive Buffer Register (LRBR) and the Right Receive
Buffer Register (RRBR. All stereo data pairs must be read using the following two-stage
process:
• Read the left stereo data from LRBR.
• Read the right stereo data from RRBR.
When RX DMA is enabled (I2S_RX_DMA = 1), data can be read from RX FIFO via the
RXDMA register rather than through LRBR and RRBR. The RXDMA register cyclically
accesses the RX FIFO of all enabled RX channel similarly to the TXDMA register.
The RRXDMA register resets the RXDMA read cycle. This register provides the same
functionality as the RTXDMA register, but targets RXDMA instead.
Receive Channel Audio Data Resolution

The RX channel is designed with a maximum audio data resolution24. The RX channel
can be programmed during operation to any supported audio data resolution that is less
than 24.
For example,as the RX Channel is initially configured with a 24-bit audio resolution, it can
be programmed to support resolutions of 12 16, 20, or 24 bits. However. Any other
resolution values are considered invalid. Additionally, if the channel is programmed with an
invalid audio resolution, the RX channel defaults to 24.
This programming ensures that the LSB of the received data is placed in the LSB position
of the RX FIFO if the resolution of the data being received is reduced. Changes to the
resolution are programmed via the Word Length (WLEN) bits of the Receive Configuration
registers (RCR[3:0]). The channel must be disabled prior to any resolution changes.
The RX channel also supports unknown data resolutions. If the received word is greater
than the configured channel resolution, the least significant bits are ignored. If the received
word is less than the configured/programmed channel resolution, the least significant bits
are padded with zeros.
On reset or if an invalid resolution is selected, the RX channel’s audio data resolution
defaults back to the initial parameter setting 24.
9.9.4. I2S Register Map
9.9.4.1. I2S_TX Register Map

I2s Enable Register
0x00000 IER
Reset Value: 0x0
I2S Transmitter Block Enable Register
0X00008 ITER
Reset Value: 0x0
Transmitter Block FIFO Register
0X00018 TXFFR
Reset Value: 0x0
LTHR Left Transmit Holding Register
0X00020
Reset Value: 0x0
RTHR Right Transmit Holding Register
0X00024
Reset Value: 0x0
Transmit Enable Register
0X0002C TER
Reset Value: 0x1
Transmit Configuration Register
0X00034 TCR
Reset Value: Configuration Dependent
Interrupt Status Register
0X00038 ISR
Reset Value: 0x10
IMR Interrupt Mask Register
0X0003C
Reset Value: 0x33
Transmit Overrun Register
0X00044 TOR
Reset Value: 0x0
TFCR Transmit FIFO Configuration Register
0X0004C
Transmit FIFO Flush
0X00054 TFF
Reset Value: 0x0
Transmitter Block DMA Register
0X001C8 TXDMA
Reset Value: 0x00
Reset Transmitter Block DMA Register
0X001CC RTXDMA
Reset Value: 0x00

4 RW 0x0 SINGLE_EN Single track enable
1: enable
0: disable
0 RW 0x0 IEN I2S_TX global enable, a disable on this bit
overrides any other block enables and
flushes all FIFO.
1: enable
0: disable
ITER address offset: 0x0008

0 RW 0x0 TXEN I2S_TX Transmitter enable
1: enable transmitter
0: disable transmitter
TXFFR address offset: 0x0018

0 W 0x0 TXFFR Transmitter FIFO Reset. Writing a 1 to this
register flushes all the TX FIFO
(this is a self clearing bit).
The Transmitter Block must be disabled prior
to writing this bit.
LTHR address offset: 0x0020

31:0 W 0x0 LTHR The left stereo data to be transmitted serially
through the transmit output is written through
this register.
RTHR address offset: 0x0024

31:0 W 0x0 RTHR The right stereo data to be transmitted
serially through the transmit output is written
through this register.
TER address offset: 0x002C

0 RW 0x0 TXCHEN Transmit channel enable. On enable, the
channel begins transmitting on the next left
stereo cycle.
0: Disable
1: Enable
TCR address offset: 0x0034

2:0 RW 0x0 WLEN These bits are used to program the data
resolution of the transmitter and ensures the
MSB of the data is transmitted first.
000 = Ignore word length
001 = 12-bit resolution
ISR address offset: 0x0038

5 R 0x0 TXFO Status of Data Overrun interrupt for the TX
channel. Attempt to write to full TX FIFO.
0: TX FIFO write valid
1: TX FIFO write overrun
4 R 0x0 TXFE Status of Transmit Empty Trigger interrupt.
TX FIFO is empty.
1: trigger level reached
0: trigger level not reached
IMR address offset: 0x003C

5 RW 0x1 TXFOM Masks TX FIFO Overrun interrupt.
1: masks interrupt
0: unmasks interrupt
4 RW 0x1 TXFEM Masks TX FIFO Empty interrupt.
1: masks interrupt
TOR address offset: 0x0044

0 R 0x0 TXCHO Read this bit to clear the TX FIFO Data
Overrun interrupt.
0: TX FIFO write valid
1: TX FIFO write overrun
TFCR address offset: 0x004C

3:0 RW 0x0 TXCHET Transmit Channel Empty Trigger. These bits
program the trigger level in the TX FIFO at
which the Empty Threshold Reached
Interrupt is generated.
Trigger Level = TXCHET
TFF address offset: 0x0054

0 W 0x0 TXCHFR Transmit Channel FIFO Reset.
Writing a 1 to this register flushes TX FIFO.
(This is a self clearing bit.)
TXDMA address offset: 0x01C8

31:0 W 0x0 TXDMA Transmitter Block DMA Register.
This register can be used to cycle repeatedly
through the enabled Transmit channels to
allow writing of stereo data pairs.
RTXDMA address offset: 0x01CC

0 W 0x0 RTXDMA Reset Transmitter Block DMA Register.
Writing a 1 to this self-clearing register resets
the TXDMA register.
9.9.4.2. I2S_RX Register Map

I2s Enable Register
0x00000 IER
Reset Value: 0x0
I2S Receiver Block Enable Register
0X00004 IRER
Reset Value: 0x0
RXFFR Receiver Block FIFO Register
0X00014
Reset Value: 0x0
Left Receiver Buffer
0X00020 LRBR
Reset Value: 0x0
Right Receiver Buffer
0X00024 RRBR
Reset Value: 0x0
Receiver Enable Register
0X00028 RER
Reset Value: 0x1
RCR Receiver Configuration Register
0X00030
Interrupt Status Register
0X00038 ISR
Reset Value: 0x10
Interrupt Mask Register
0X0003C IMR
Reset Value: 0x33
Receive Overrun Register
0X00040 ROR
Reset Value: 0x0
Receive FIFO Configuration Register
0X00048 RFCR
Receive FIFO Flush
0X00050 RFF
Reset Value: 0x0
Receiver Block DMA Register
0X001C0 RXDMA
Reset Value: 0x00
Reset Receiver Block DMA Register
0X001C4 RRXDMA
Reset Value: 0x00

4 RW 0x0 SINGLE_EN Single track enable
1: enable
0: disable
0 RW 0x0 IEN I2S_RX global enable, a disable on this bit
overrides any other block enables and
flushes all FIFO.
1: enable
0: disable
IRER address offset: 0x0004

0 RW 0x0 RXEN I2S_RX Receiver enable
1: enable receiver
0: disable receiver
RXFFR address offset: 0x0014

0 W 0x0 RXFFR Receiver FIFO Reset. Writing a 1 to this
register flushes all the RX FIFO
(this is a self clearing bit). The Receiver
Block must be disabled prior to writing this
bit.
LRBR address offset: 0x0020

31:0 R 0x0 LRBR The left stereo data received serially from
the receive channel input is read through this
register
RRBR address offset: 0x0024

31:0 R 0x0 RRBR The right stereo data received serially from
the receive channel input is read through this
register.
RER address offset: 0x0028

0 RW 0x1 RXCHEN Receive channel enable. On enable, the
channel begins receiving on the next left
stereo cycle
0: Disable
1: Enable
RCR address offset: 0x0030

2:0 RW 0x0 WLEN These bits are used to program the desired
data resolution of the receiver
and enables the LSB of the incoming left (or
right) word to be placed in the
LSB of the LRBR (or RRBR) register.
000 = Ignore word length
ISR address offset: 0x0038

1 R 0x0 RXFO Status of Data Overrun interrupt for the RX
channel. Incoming data lost due to a full
RX FIFO.
0: RX FIFO write valid
1: RX FIFO write overrun
0 R 0x0 RXDA Status of Receive Data Available interrupt.
RX FIFO data available.
1: trigger level reached
0: trigger level not reached
IMR address offset: 0x003C

1 RW 0x1 RXFOM Masks RX FIFO Overrun interrupt.
1: masks interrupt
0 RW 0x1 RXDAM Masks RX FIFO Data Available interrupt.
1: masks interrupt
ROR address offset: 0x0040

0 R 0x0 RXCHO Read this bit to clear the RX FIFO Data
Overrun interrupt.
0: RX FIFO write valid
1: RX FIFO write overrun
RFCR address offset: 0x0048
3:0 RW 0x0 RXCHDT These bits program the trigger level in the
RX FIFO at which the Received Data
Available interrupt is generated.
RFF address offset: 0x0050

0 W 0x0 RXCHFR Receive Channel FIFO Reset. Writing a 1 to
this register flushes an individual RX FIFO.
(This is a self clearing bit.)
RXDMA address offset: 0x01C0

31:0 R 0x0 RXDMA Receiver Block DMA Register. Used to cycle
repeatedly through the enabled receive
channels, reading stereo data pairs.
RRXDMA address offset: 0x01C4

0 W 0x0 RRXDMA Reset Receiver Block DMA Register. Writing
a 1 to this self-clearing register resets the
RXDMA register.
9.10. Audio
9.10.1. Introduction
The OM6621Ex has an audio PGA and ADC inside. The structure is as shown below, the
PGA has a differential input, which can be switched from GPIO[2,3]. The PGA gain varies
from PGA GAIN -3 to +30db (3db step).
C1
auref
auref ldo_2.8V aldo_1.2V
biasgen VT/R
GPIO2 + -
pga adc
GPIO3 - +
Audio
digital
clkgen
Figure 9.82 Audio Block Diagram

Resolution 24 bits
FSAMPLE Output sample rate 8 32 kHz
Fin=1kHz, BW=20Hz~20kHz
SNDR 93.5 dB
A-weighted, 0.8Vrms input
Fin=1kHz, BW=20Hz~20kHz
SNDR 95.5 dB
A-weighted, 1mVrms input
DGAIN Digital Gain with 0.5dB resolution -50 24.5 dB
AGAIN Analog Gain with 3dB resolution -3 30 dB
Table 9.8 Electrical Specification
9.10.3. Audio Register Map

0x0000 ADC_CTRL Audio ADC control
0x0078 ADC_VOL_CTRL ADC volume control
0x00c0 ADC_GAIN_READ ADC internal gain read
0x00c4 ADC_CLK_CTRL_1 ADC clock control register 1
0x00c8 ADC_CLK_CTRL_2 ADC clock control register 2
0x00cc ADC_CLK_CTRL_3 ADC clock control register 3
0x00dc ADC_INT_STATUS ADC interrupt status
0x00e0 ADC_INT_CTRL ADC interrupt control
0x00fc IF_CTRL Interface control
0x0100 ADC_ANA_CTRL_1 ADC analog control register 1
0x0104 ADC_ANA_CTRL_2 ADC analog control register 2
ADC_CTRL address offset: 0x0000

18 RW 0x0 ADC_CIC_SEL adc cic filter selection
1: use 4-order cic
0: use 3-order cic
17 RW 0x0 ADC_ANTI_CLIP 1: when output is clipping, the gain
decreased automatically
16 RW 0x0 ADC_INPUT_INV 1: adc input is inverted
10:8 RW 0x1 ADC_SR sample rate control
100: sample rate = 8k
7 RW 0x0 ADC_24B_EN adc output 24bit enable
1: Enable
0: Disable
6:4 RW 0x0 ADC_CIC_GAIN cic filter gain
0: 0dB
1: 2dB
2: 3.5dB
3,4: 6dB
5: 8dB
6: 9.5dB
7: 12dB
3 RW 0x1 ADC_DC_EN dc offset enable
1: dc offset is enable
0: dc offset is disable
2 RW 0x0 DMIC_EN DMIC mode enable
1: digital mic as input
0: analog mic as input
1 RW 0x0 ADC_SW_RESET_ ADC digital filter soft reset
X 0: reset
0 RW 0x0 ADC_EN ADC digital filter enable
1: enable
0: disable
ADC_VOL_CTRL address offset: 0x0078

31:28 N/A 0x1 ADC_UNMUTE_RA the volume adjust rate in unmute
TE process
adjust rate = 2^(adc_unmute_rate)*fs
24 RW 0x1 ADC_VOL_UPDATE ladcvol take effect only update while
adc_vol_update=1
15:8 RW 0x64 LADCVOL the volume control, 0.5dB/step
7:4 RW 0x1 ADC_MUTE_RATE the volume adjust rate in mute process
adjust rate = 2^(adc_mute_rate)*fs
2 RW 0x0 ADC_MUTE_BYPAS 1: mute and unmute mechanism is
S bypass, volume is only controlled by
ladcvol
1 RW 0x1 ADCUNMU 1: gain gradually increased from 0 to
ladcvol
0 RW 0x0 ADCMU 1: gain gradually decreased to 0
ADC_GAIN_READ address offset: 0x00c0

7:0 R 0x64 ADC_GAIN_READ adc gain control read out (read only)
ADC_CLK_CTRL_1 address offset: 0x00c4

6 RW 0x0 DMIC_CLK_CTRL 0: output dmic_clk,
1: output dmic_clk_n
5 RW 0x0 DMIC_CLK_SEL 0: dmic_clk= 2MHz,
1: dmic_clk= 3.2MHz
4 RW 0x0 CLK_32K_EN 0: clk_32k for adc is gating
3 RW 0x0 I2S_RXCLK_RSTN_ i2s_rx clock reset, low active
REG
2 RW 0x0 I2S_TXCLK_RSTN_ i2s_tx clock reset, low active
REG
1 RW 0x0 ADC_CLK_EN_REG adc clock enable, active high
0 RW 0x0 ADC_RSTN_REG adc reset, active low
ADC_CLK_CTRL_2 address offset: 0x00c8

24 R 0x0 I2S_TX_SCLK_DON i2s_tx_sclk ready flag
E
20:12 RW 0x19 I2S_TX_HIGH_NUM the high pulse of i2s_tx_ws
8 RW 0x0 I2S_TX_ODD i2s_tx_ws cofiguration:
0: high pulse=low pulse,
1: low pulse=high pulse-1
7 RW 0x1 I2S_TX_DIV_EN 1: i2s_tx_sclk divider is enable
6 RW 0x1 I2S_TX_DIV_SEL 0: i2s_tx_sclk = 16MHz,
1: i2s_tx_sclk=16M/i2s_tx_div_coeff
5:0 RW 0x14 I2S_TX_DIV_COEF i2s_tx_sclk divider, greater than 2
F
ADC_CLK_CTRL_3 address offset: 0x00cc

24 R 0x0 I2S_RX_SCLK_DO i2s_rx_sclk ready flag
NE
20:12 RW 0x19 I2S_RX_HIGH_NUM the high pulse of i2s_rx_ws
8 RW 0x0 I2S_RX_ODD i2s_rx_ws cofiguration:
0: high pulse=low pulse,
1: low pulse=high pulse-1
7 RW 0x1 I2S_RX_DIV_EN 1: i2s_rx_sclk divider is enable
6 RW 0x1 I2S_RX_DIV_SEL 0: i2s_rx_sclk = 16MHz,
1: i2s_rx_sclk=16M/i2s_rx_div_coeff
5:0 RW 0x14 I2S_RX_DIV_COEF i2s_rx_sclk divider, greater than 2
F
ADC_INT_STATUS address offset: 0x00dc
6 RW 0x0 AUDIO_OFF_INT audio power off complete interrupt,
write 1 to clear the interrupt
5 RW 0x0 AUDIO_ON_INT audio power on complete interrupt,
write 1 to clear the interrupt
4 R 0x0 ADC_INTT all interrupts are OR
3 R 0x0 ADC_UNMUTE_INT adc unmute interrupt
2 R 0x0 ADC_MUTE_INT adc mute interrupt
1 R 0x0 ADC_OUTL_CLIP_I adc output clipping interrupt status
NT
0 RW 0x0 ADC_SIGNAL_LAR adc large signal interrupt status,
GE_INT write 1 to clear the interrupt
ADC_INT_CTRL address offset: 0x00e0

6 RW 0x1 AUDIO_OFF_INT_MAS 1: audio off int is mask
K
5 RW 0x1 AUDIO_ON_INT_MASK 1: audio on int is mask
3 RW 0x1 ADC_UNMUTE_INT_MA 1: adc unmute interrupt mask
SK
2 RW 0x1 ADC_MUTE_INT_MASK 1: adc mute interrupt mask
1 RW 0x1 ADC_CLIP_INT_MASK 1: adc clip int is mask and clear
0 RW 0x1 ADC_SIGNAL_LARGE_I 1: interrupt is mask (the interrupt
NT_IM indicates adc signal is large)
IF_CTRL address offset: 0x00fc

7 RW 0x0 I2S_TXCLK_MST_INV 1: pinmux output i2s_txclk_n
0: pinmux output i2s_txclk
6 RW 0x0 I2S_RXCLK_MST_INV 1: pinmux output i2s_rxclk_n
0: pinmux output i2s_rxclk
5 RW 0x1 I2S_TX_MS_SEL 1: i2s tx clock and ws is generated
by adc
0: i2s tx clock and ws is input from
gpio
4 RW 0x1 I2S_RX_MS_SEL 1: i2s rx clock and ws is generated
by adc
0: i2s rx clock and ws is input from
gpio
3 RW 0x0 I2S_TX_CNT_EN 1: i2s_tx counter is enable (counter
value is read in ADC_AMP_CTRL)
2 RW 0x0 I2S_CON_CTRL 0: adc connected to i2s;
1: adc and i2s connected to gpio
1 RW 0x0 TRANSMIT_EN enable data transmitor to i2s
interface
0 RW 0x0 RECEIVE_EN enable data receiver from i2s
interface
ADC_ANA_CTRL_1 address offset: 0x0100

31:8 N/A N/A N/A reserved
7:4 RW 0x1 au_pga_gain pga gain control
ADC_ANA_CTRL_2 address offset: 0x0104

24 RW 0x0 adc_mode 0: auadc mode
1: gpadc mode
14 RW 0x1 auldo28mod 2.8V LDO output voltage
0=1.6v,
1=2.8v
13:12 RW 0x1 ctrl_au_auldo28 2.8V DRV LDO output adjust;
9.11. I2C
The I2C bus is a two-wire serial interface, consisting of a serial data line (SDA) and a serial
clock (SCL).
These wires carry information between the devices connected to the bus. Each device is
recognized by a unique address and can operate as either a “transmitter” or “receiver,”
depending on the function of the device. Devices can also be considered as masters or
slaves when performing data transfers. A master is a device that initiates a data transfer
on the bus and generates the clock signals to permit that transfer. At that time, any device
addressed is considered a slave.
• Two-wire I2C serial interface – consists of a serial data line (SDA) and a serial clock
(SCL)
• Two speeds:
• Standard mode (100Kb/s)
• Fast mode (400Kb/s)
• Master or slave I2C operation
• 7-bit or 10-bit addressing
• 7-bit or 10-bit combined format transfers
• Bulk transmit mode
• Transmit and receive buffers
• Interrupt or polled-mode operation
• DMA handshaking interface compatible with the dmac handshaking interface
• Add a bullet point here for programmable SDA hold time (tHD;DAT)
The I2C requires external hardware components as support in order to be compliant in an
I2C system. The descriptions are detailed later in this document.
It must also be noted that the I2C should only be operated either as (but not both):
• A master in an I2C system and programmed only as a Master
• A slave in an I2C system and programmed only as a Slave
9.11.3.1. I2CBus Terms
The following terms relate to how the role of the I2C device and how it interacts with other
I2C devices on the bus.
• Transmitter – the device that sends data to the bus. A transmitter can either be a
device that initiates the data transmission to the bus (a master-transmitter) or
responds to a request from the master to send data to the bus (a slave-transmitter).
• Receiver – the device that receives data from the bus. A receiver can either be a
device that receives data on its own request (a master-receiver) or in response to a
request from the master (a slave-receiver).
• Master – the component that initializes a transfer (START command), generates the
clock (SCL) signal and terminates the transfer (STOP command). A master can be
either a transmitter or a receiver.
• Slave – the device addressed by the master. A slave can be either receiver or
transmitter.These concepts are illustrated in the following figure.
Master Slave
SDA
Transmitter Receiver
SCL
Master Slave
SDA
Receiver Transmitter
SCL
Figure 9.83 Master/Slave and Transmitter/Receiver Relationships
• Multi-master – the ability for more than one master to co-exist on the bus at the same
time without collision or data loss.
• Arbitration – the predefined procedure that authorizes only one master at a time to
take control of the bus.
• Synchronization – the predefined procedure that synchronizes the clock signals
provided by two or more masters.
• SDA – data signal line (Serial Data)
• SCL – clock signal line (Serial Clock)
9.11.3.2. Bus Transfer Terms
The following terms are specific to data transfers that occur to/from the I2C bus.
• START (RESTART) – data transfer begins with a START or RESTART condition. The
level of the SDA data line changes from high to low, while the SCL clock line remains
high. When this occurs, the bus becomes busy.
Note: START and RESTART conditions are functionally identical.
• STOP – data transfer is terminated by a STOP condition. This occurs when the level
on the SDA data line passes from the low state to the high state, while the SCL clock
line remains high. When the data transfer has been terminated, the bus is free or idle
once again. The bus stays busy if a RESTART is generated instead of a STOP
condition.
9.11.3.3. I2C Behavior
The I2C can be controlled via software to be either:

• An I2C master only, communicating with other I2C slaves; OR
• An I2C slave only, communicating with one more I2C masters.
The master is responsible for generating the clock and controlling the transfer of data. The
slave is responsible for either transmitting or receiving data to/from the master. The
acknowledgement of data is sent by the device that is receiving data, which can be either
a master or a slave. As mentioned previously, the I2C protocol also allows multiple masters
to reside on the I2C bus and uses an arbitration procedure to determine bus ownership.
Each slave has a unique address that is determined by the system designer. When a
master wants to communicate with a slave, the master transmits a START/RESTART
condition that is then followed by the slave’s address and a control bit (R/W) to determine
if the master wants to transmit data or receive data from the slave. The slave then sends
an acknowledge (ACK) pulse after the address.
If the master (master-transmitter) is writing to the slave (slave-receiver), the receiver gets
one byte of data.
This transaction continues until the master terminates the transmission with a STOP
condition. If the master is reading from a slave (master-receiver), the slave transmits
(slave-transmitter) a byte of data to the master, and the master then acknowledges the
transaction with the ACK pulse. This transaction continues until the master terminates the
transmission by not acknowledging (NACK) the transaction after the last byte is received,
and then the master issues a STOP condition or addresses another slave after issuing a
RESTART condition. This behavior is illustrated in the following figure.
P or R
SDA MSB LSB ACK ACK
from receiver from receiver
SCL S 1 2 7 8 9 1 2 3-8
3-8 9 R or P
or
R
START or Byte Complete SCL held low STOP AND
RESTART Interrupt within while servicing RESTART
Condition Slave interrupts Condition
Figure 9.84 Data Transfer on The I2C Bus
The I2C is a synchronous serial interface. The SDA line is a bidirectional signal and
changes only while the SCL line is low, except for STOP, START, and RESTART
conditions. The output drivers are open-drain or open-collector to perform wire-AND
functions on the bus. The maximum number of devices on the bus is limited by only the
maximum capacitance specification of 400pF. Data is transmitted in byte packages.
Note:Putting data into the FIFO generates a START,and emptying the FIFO generates a
STOP.
START and STOP Generation

When operating as an I2C master, putting data into the transmit FIFO causes the I2c to
generate a START condition on the I2C bus.Allowing the transmit FIFO to empty causes
the I2c to generate a STOP condition on the I2C bus. When operating as a slave, the I2c
does not generate START and STOP conditions, as per the protocol.However,if a read
request is made to the I2c, it holds the SCL line low until read data has been supplied to it.
This stalls the I2C bus until read data is provided to the slave I2c,or the I2c slave is disabled
by writing a 0 to IC_ENABLE.
Combined Formats
The I2C supports mixed read and write combined format transactions in both 7-bit and 10-
bit addressing modes.
The I2C does not support mixed address and mixed address format—that is, a 7-bit
address transaction followed by a 10-bit address transaction or vice versa—combined
format transactions.
To initiate combined format transfers, IC_CON.IC_RESTART_EN should be set to 1. With
this value set and operating as a master, when the I2c completes an I2C transfer, it checks
the transmit FIFO and executes the next transfer. If the direction of this transfer differs from
the previous transfer, the combined format is used to issue the transfer. If the transmit
FIFO is empty when the current I2C transfer completes, a STOP is issued and the next
transfer is issued following a START condition.
9.11.3.4. I2C Protocols
START and STOP Conditions

When the bus is idle, both the SCL and SDA signals are pulled high through external pull-
up resistors on the bus. When the master wants to start a transmission on the bus, the
master issues a START condition.
This is defined to be a high-to-low transition of the SDA signal while SCL is 1.When the
master wants to terminate the transmission, the master issues a STOP condition.This is
defined to be a low-to-high transition of the SDA line while SCL is 1. The following figure
shows the timing of the START and STOP conditions.When data is being transmitted on
the bus, the SDA line must be stable when SCL is 1.
SDA
SCL
Change of Data Data line Stable Change of Data P

S
Allowed Data Valid Allowed
Stop Condition
Start Condition
Figure 9.85 START and STOP Condition

Note: The signal transitions for the START/STOP conditions, as depicted in Figure 6.83,
reflect those observed at the output signals of the Master driving the I2C bus.Care should
be taken when observing the SDA/SCL signals at the input signals of the Slave(s), because
unequal line delays may result in an incorrect SDA/SCL timing relationship.
Addressing Slave Protocol

There are two address formats: the 7-bit address format and the 10-bit address format.
7-bit Address Format

During the 7-bit address format, the first seven bits (bits 7:1) of the first byte set the slave
address and the LSB bit (bit 0) is the R/W bit as shown in the following figure. When bit 0
(R/W) is set to 0, the master writes to the slave. When bit 0 (R/W) is set to 1, the master
reads from the slave.
MSB LSB
S A6 A5 A4 A3 A2 A1 A0 R/W ACK
sent by slave
Slave Address
S = START condition R/W= Read/Write Pulse
ACK = Acknowledge
Figure 9.86 7-bit Address Format
10-bit Address Format

During 10-bit addressing,two bytes are transferred to set the 10-bit address.The transfer
of the first byte contains the following bit definition. The first five bits (bits 7:3) notify the
slaves that this is a 10-bit transfer followed by the next two bits (bits 2:1), which set the
slaves address bits 9:8, and the LSB bit (bit 0) is the R/W bit. The second byte transferred
sets bits 7:0 of the slave address. The following figure shows the 10-bit address format,
and the following table defines the special purpose and reserved first byte addresses.
S ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
Reserved for 10-bit sent by slave sent by slave

Address
S = START condition
R/W = Read/Write Pulse
ACK = Acknowledge
Figure 9.87 10-bit Address Format
Slave Address R/W Bit Description

General Call Address. I2c places the data in the receive
0000 000 0
buffer and issues a General Call interrupt.
0000 000 1 START byte.
0000 001 X CBUS address. I2c ignores these accesses.
0000 010 X Reserved.
0000 011 X Reserved.
0000 1XX X High-speed master code.
1111 1XX X Reserved.
1111 0XX X 10-bit slave addressing.
Table 9.9 I2C Definition of Bits in First Byte
I2C does not restrict you from using these reserved addresses. However, if you use these
reserved addresses, you may run into incompatibilities with other I2C components.
Transmitting and Receiving Protocol

The master can initiate data transmission and reception to/from the bus, acting as either a
master-transmitter or master-receiver. A slave responds to requests from the master to
either transmit data or receive data to/from the bus, acting as either a slave-transmitter or
slave-receiver, respectively.
Master-Transmitter and Slave-Receiver

All data is transmitted in byte format, with no limit on the number of bytes transferred per
data transfer.
After the master sends the address and R/W bit or the master transmits a byte of data to
the slave, the slave-receiver must respond with the acknowledge signal (ACK). When a
slave-receiver does not respond with an ACK pulse, the master aborts the transfer by
issuing a STOP condition. The slave must leave the SDA line high so that the master can
abort the transfer.
If the master-transmitter is transmitting data as shown in the following figure, then the
slave-receiver responds to the master-transmitter with an acknowledge pulse after every
byte of data is received.
Figure 9.88 Master-Transmitter Protocol
Master-Receiver and Slave-Transmitter

If the master is receiving data as shown in the following figure, then the master responds
to the slave-transmitter with an acknowledge pulse after a byte of data has been received,
except for the last byte. This is the way the master-receiver notifies the slave-transmitter
that this is the last byte. The slave-transmitter relinquishes the SDA line after detecting the
No Acknowledge (NACK) so that the master can issue a STOP condition.
When a master does not want to relinquish the bus with a STOP condition, the master can
issue a RESTART condition. This is identical to a START condition except it occurs after
the ACK pulse. Operating in master mode, the I2C can then communicate with the same
slave using a transfer of a different direction.
Note: The I2C must be completely disabled - if I2C_DYNAMIC_TAR_UPDATE = 0 - or
inactive on the serial port - if I2C_DYNAMIC_TAR_UPDATE = 1 - before the target slave
address register (IC_TAR) can be reprogrammed.
Figure 9.89 Master-Receiver Protocol
START BYTE Transfer Protocol

The START BYTE transfer protocol is set up for systems that do not have an on-board
dedicated I2C hardware module. When the I2C is addressed as a slave, it always samples
the I2C bus at the highest speed supported so that it never requires a START BYTE transfer.
However, when I2C is a master, it supports the generation of START BYTE transfers at the
beginning of every transfer in case a slave device requires it. This protocol consists of
seven zeros being transmitted followed by a 1, as illustrated in the following figure. This
allows the processor that is polling the bus to under-sample the address phase until 0 is
detected. Once the micro-controller detects a 0, it switches from the under sampling rate
to the correct rate of the master.
Figure 9.90 START BYTE Transfer
The START BYTE procedure is as follows:

• Master generates a START condition.
• Master transmits the START byte (0000 0001).
• Master transmits the ACK clock pulse. (Present only to conform with the byte handling
format used on the bus)
• No slave sets the ACK signal to 0.
• Master generates a RESTART (R) condition.
A hardware receiver does not respond to the START BYTE because it is a reserved
address and resets after the RESTART condition is generated.
Multiple Master Arbitration

The I2C bus protocol allows multiple masters to reside on the same bus. If there are two
masters on the same I2C-bus, there is an arbitration procedure if both try to take control of
the bus at the same time by generating a START condition at the same time. Once a
master (for example, a micro-controller) has control of the bus, no other master can take
control until the first master sends a STOP condition and places the bus in an idle state.
Arbitration takes place on the SDA line, while the SCL line is 1. The master, which transmits
a 1 while the other master transmits 0, loses arbitration and turns off its data output stage.
The master that lost arbitration can continue to generate clocks until the end of the byte
transfer. If both masters are addressing the same slave device, the arbitration could go into
the data phase.
Upon detecting that it has lost arbitration to another master, the I2C will stop generating
SCL (ic_clk_oe).
The following figure illustrates the timing of when two masters are arbitrating on the bus.
Figure 9.91 Multiple Master Arbitration
Arbitration is not allowed between the following conditions:

• A RESTART condition and a data bit
• A STOP condition and a data bit
• A RESTART condition and a STOP condition
Note: Slaves are not involved in the arbitration process.
Clock Synchronization
When two or more masters try to transfer information on the bus at the same time, they
must arbitrate and synchronize the SCL clock. All masters generate their own clock to
transfer messages. Data is valid only during the high period of SCL clock. Clock
synchronization is performed using the wired-AND connection to the SCL signal. When the
master transitions the SCL clock to 0, the master starts counting the low time of the SCL
clock and transitions the SCL clock signal to 1 at the beginning of the next clock period.
However, if another master is holding the SCL line to 0, then the master goes into a HIGH
wait state until the SCL clock line transitions to 1.
All masters then count off their high time, and the master with the shortest high time
transitions the SCL line to 0. The masters then counts out their low time and the one with
the longest low time forces the other master into a HIGH wait state. Therefore, a
synchronized SCL clock is generated, which is illustrated in the following figure. Optionally,
slaves may hold the SCL line low to slow down the timing on the I2C bus.
Figure 9.92 Multi-Master Clock Synchronization
Operation Modes
This section provides information on operation modes.
Note:It is important to note that the I2C should only be set to operate as an I2C Master, or
I2C Slave, but not both simultaneously. This is achieved by ensuring that bit 6
(IC_SLAVE_DISABLE) and 0 (IC_MASTER_MODE) of the IC_CON register are never set
to 0 and 1, respectively.
Slave Mode Operation

Initial Configuration
To use the I2C as a slave, perform the following steps:
• Disable the I2C by writing a ‘0’ to bit 0 of the IC_ENABLE register.
• Write to the IC_SAR register (bits 9:0) to set the slave address.This is the address to
which the I2C responds.
• Write to the IC_CON register to specify which type of addressing is supported (7- or
10-bit by setting bit 3). Enable the I2C in slave-only mode by writing a ‘0’ into bit 6
(IC_SLAVE_DISABLE) and a ‘0’ to bit 0 (MASTER_MODE).
Note: Slaves and masters do not have to be programmed with the same type of addressing
7-bit or10-bit address. For instance, a slave can be programmed with 7-bit addressing and
a master with 10-bit addressing, and vice versa.
Enable the I2C by writing a ‘1’ in bit 0 of the IC_ENABLE register.
Note: Depending on the reset values chosen, steps 2 and 3 may not be necessary because
the reset values can be configured. For instance, if the device is only going to be a master,
there would be no need to set the slave address because you can configure I2C to have
the slave disabled after reset and to enable the master after reset. The values stored are
static and do not need to be reprogrammed if the I2C is disabled.
Slave-Transmitter Operation for a Single Byte

When another I2C master device on the bus addresses the I2C and requests data, the I2C
acts as a slave-transmitter and the following steps occur:
• The other I2C master device initiates an I2C transfer with an address that matches the
slave address in the IC_SAR register of the I2C.
• The I2C acknowledges the sent address and recognizes the direction of the transfer
to indicate that it is acting as a slave-transmitter.
• The I2C asserts the RD_REQ interrupt (bit 5 of the IC_RAW_INTR_STAT register)
and holds the SCL line low. It is in a wait state until software responds.
If the RD_REQ interrupt has been masked, due to IC_INTR_MASK[5] register
(M_RD_REQ bit field) being set to 0, then it is recommended that a hardware and/or
software timing routine be used to instruct the CPU to perform periodic reads of the
IC_RAW_INTR_STAT register.
• Reads that indicate IC_RAW_INTR_STAT[5] (R_RD_REQ bit field) being set to 1
must be treated as the equivalent of the RD_REQ interrupt being asserted.
• Software must then act to satisfy the I2C transfer.
• The timing interval used should be in the order of 10 times the fastest SCL clock period
the I2C can handle. For example, for 400 kb/s, the timing interval is 25us.
Note:The value of 10 is recommended here because this is approximately the amount of
time required for a single byte of data transferred on the I2C bus.
• If there is any data remaining in the TX FIFO before receiving the read request, then
the I2C asserts a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register) to
flush the old data from the TX FIFO.
Note: Because the I2C’s TX FIFO is forced into a flushed/reset state whenever a TX_ABRT
event occurs, it is necessary for software to release the I2C from this state by reading the
IC_CLR_TX_ABRT register before attempting to write into the TX FIFO. See register
IC_RAW_INTR_STAT for more details.
If the TX_ABRT interrupt has been masked,due to of IC_INTR_MASK[6] register
(M_TX_ABRT bit field) being set to 0, then it is recommended that re-using the timing
routine (described in the previous step), or a similar one, be used to read the
IC_RAW_INTR_STAT register.
• Reads that indicate bit 6 (R_TX_ABRT) being set to 1 must be treated as the
equivalent of the TX_ABRT interrupt being asserted.
• There is no further action required from software.
• The timing interval used should be similar to that described in the previous step for the
IC_RAW_INTR_STAT[5] register.
• Software writes to the IC_DATA_CMD register with the data to be written (by writing
a ‘0’ in bit8).
• Software must clear the RD_REQ and TX_ABRT interrupts (bits 5 and 6, respectively)
of the IC_RAW_INTR_STAT register before proceeding.
If the RD_REQ and/or TX_ABRT interrupts have been masked, then clearing of the
IC_RAW_INTR_STAT register will have already been performed when either the
R_RD_REQ or R_TX_ABRT bit has been read as 1.
• The I2C releases the SCL and transmits the byte.
• The master may hold the I2C bus by issuing a RESTART condition or release the bus
by issuing a STOP condition.
Slave-Receiver Operation for a Single Byte

When another I2C master device on the bus addresses the I2C and is sending data, the
I2C acts as a slave-receiver and the following steps occur:
• The other I2C master device initiates an I2C transfer with an address that matches the
I2C’s slave address in the IC_SAR register.
• The I2C acknowledges the sent address and recognizes the direction of the transfer
to indicate that the I2C is acting as a slave-receiver.
• I2C receives the transmitted byte and places it in the receive buffer.
Note: If the RX FIFO is completely filled with data when a byte is pushed, then an overflow
occurs and the I2C continues with subsequent I2C transfers. Because a NACK is not
generated, software must recognize the overflow when indicated by the I2C (by the
R_RX_OVER bit in the IC_INTR_STAT register) and take appropriate actions to recover
from lost data. Hence, there is a real time constraint on software to service the RX FIFO
before the latter overflow as there is no way to reapply pressure to the remote transmitting
master. You must select a deep enough RX FIFO depth to satisfy the interrupt service
interval of their system.
I2C asserts the RX_FULL interrupt (IC_RAW_INTR_STAT[2] register). If the RX_FULL
interrupt has been masked, due to setting IC_INTR_MASK[2] register to 0 or setting
IC_TX_TL to a value larger than 0, then it is recommended that a timing routine (described
in “Slave-Transmitter Operation for a Single Byte” on page 40) be implemented for periodic
reads of the IC_STATUS register. Reads of the IC_STATUS register, with bit 3 (RFNE) set
at 1, must then be treated by software as the equivalent of the RX_FULL interrupt being
asserted.
• Software may read the byte from the IC_DATA_CMD register (bits 7:0).
• The other master device may hold the I2C bus by issuing a RESTART condition or
release the bus by issuing a STOP condition.
Slave-Transfer Operation For Bulk Transfers

In the standard I2C protocol, all transactions are single byte transactions and the
programmer responds to a remote master read request by writing one byte into the slave’s
TX FIFO. When a slave (slave-transmitter) is issued with a read request (RD_REQ) from
the remote master (master-receiver), at a minimum there should be at least one entry
placed into the slave-transmitter’s TX FIFO. I2C is designed to handle more data in the TX
FIFO so that subsequent read requests can take that data without raising an interrupt to
get more data. Ultimately, this eliminates the possibility of significant latencies being
incurred between raising the interrupt for data each time had there been a restriction of
having only one entry placed in the TX FIFO.
This mode only occurs when I2C is acting as a slave-transmitter. If the remote master
acknowledges the data sent by the slave-transmitter and there is no data in the slave’s TX
FIFO, the I2C holds the I2C SCL line low while it raises the read request interrupt (RD_REQ)
and waits for data to be written into the TX FIFO before it can be sent to the remote master.
If the RD_REQ interrupt is masked, due to bit 5 (M_RD_REQ) of the IC_INTR_STAT
register being set to 0, then it is recommended that a timing routine be used to activate
periodic reads of the IC_RAW_INTR_STAT register. Reads of IC_RAW_INTR_STAT that
return bit 5 (R_RD_REQ) set to 1 must be treated as the equivalent of the RD_REQ
interrupt referred to in this section.
The RD_REQ interrupt is raised upon a read request, and like interrupts, must be cleared
when exiting the interrupt service handling routine (ISR). The ISR allows you to either write
1 byte or more than 1 byte into the TX FIFO. During the transmission of these bytes to the
master, if the master acknowledges the last byte. then the slave must raise the RD_REQ
again because the master is requesting for more data.
If the programmer knows in advance that the remote master is requesting a packet of n
bytes, then when another master addresses I2C and requests data, the TX FIFO could be
written with n number bytes and the remote master receives it as a continuous stream of
data. For example, the I2C slave continues to send data to the remote master as long as
the remote master is acknowledging the data sent and there is data available in the TX
FIFO. There is no need to hold the SCL line low or to issue RD_REQ again.
If the remote master is to receive n bytes from the I2C but the programmer wrote a number
of bytes larger than n to the TX FIFO, then when the slave finishes sending the requested
n bytes, it clears the TX FIFO and ignores any excess bytes.
The the I2C generates a transmit abort (TX_ABRT) event to indicate the clearing of the TX
FIFO in this example. At the time an ACK/NACK is expected, if a NACK is received, then
the remote master has all the data it wants. At this time, a flag is raised within the slave’s
state machine to clear the leftover data in the TX FIFO. This flag is transferred to the
processor bus clock domain where the FIFO exists and the contents of the TX FIFO is
cleared at that time.
Master Mode Operation

Initial Configuration
The initial configuration procedure for Master Mode Operation depends on the
configuration parameter I2C_DYNAMIC_TAR_UPDATE. When set to “Yes” (1), the target
address and address format can be changed dynamically without having to disable I2C.
This parameter only applies to when I2C is acting as a master because the slave requires
the component to be disabled before any changes can be made to the address.
The procedures are very similar and are only different with regard to where the
IC_10BITADDR_MASTER bit is set (either bit 4 of IC_CON register or bit 12 of IC_TAR
register).
To use the I2C as a master perform the following steps:
• Disable the I2C by writing 0 to the IC_ENABLE register.
• Write to the IC_CON register to set the maximum speed mode supported for slave
operation (bits 2:1) and to specify whether the I2C starts its transfers in 7/10 bit
addressing mode when the device is a slave (bit 3).
• Write to the IC_TAR register the address of the I2C device to be addressed. It also
indicates whether a General Call or a START BYTE command is going to be
performed by I2C. The desired speed of the I2c master-initiated transfers, either 7-bit
or 10-bit addressing.
• Only applicable for high-speed mode transfers. Write to the ic_hs_maddr register the
desired master code for the I2C. The master code is programmer-defined.
• Enable the I2C by writing a 1 in the IC_ENABLE register.
• Now write the transfer direction and data to be sent to the IC_DATA_CMD register. If
the IC_DATA_CMD register is written before the I2C is enabled, the data and
commands are lost as the buffers are kept cleared when I2C is not enabled.
Note: For multiple I2C transfers, perform additional writes to the TX FIFO such that the TX
FIFO does not become empty during the I2C transaction. If the TX FIFO is completely
emptied at any stage, then further writes to the TX FIFO results in an independent I2C
transaction.
Dynamic IC_TAR Update

The I2C supports dynamic updating of the IC_TAR (bits 9:0) and ic_10bit addr_master (bit
12) bit fields of the IC_TAR register. In order to perform a dynamic update of the IC_TAR
register. You can dynamically write to the IC_TAR register provided the following
conditions are met:
• I2C is not enabled (IC_ENABLE=0);
• I2Cis enabled (IC_ENABLE=1);
• I2C is not engaged in any Master (tx,rx) operation (IC_STATUS[5]=0);
• I2C is enabled to operate in Master mode (IC_CON[0]=1);
• And there are no entries in the TX FIFO (IC_STATUS[2]=1).
Master Transmit and Master Receive

The I2C supports switching back and forth between reading and writing dynamically. To
transmit data, write the data to be written to the lower byte of the I2C Rx/Tx Data Buffer
and Command Register (IC_DATA_CMD). The CMD bit [8] should be written to 0 for I2C
write operations. Subsequently, a read command may be issued by writing “don’t cares” to
the lower byte of the IC_DATA_CMD register, and a 1 should be written to the CMD bit.
The I2C master continues to initiate transfers as long as there are commands present in
the transmit FIFO. If the transmit FIFO becomes empty, the I2C inserts a STOP condition
after completing the current transfers.
Disabling I2C
The register IC_ENABLE_STATUS is added to allow software to unambiguously
determine when the hardware has completely shut down in response to the IC_ENABLE
register being set from 1 to 0. Only one register is required to be monitored, as opposed to
monitoring two registers (IC_STATUS and IC_RAW_INTR_STAT) which is a requirement
for I2C.
IC_CLK Frequency Configuration

When the I2C is configured as a master, the *CNT registers must be set before any I2C
bus transaction can take place in order to ensure proper I/O timing. The *CNT registers
are:
• IC_SS_SCL_HCNT
• IC_SS_SCL_LCNT
• IC_FS_SCL_HCNT
• IC_FS_SCL_LCNT
Note: It is not necessary to program any of the *CNT registers if the I2C is enabled to
operate only as an I2C slave, since these registers are used only to determine the SCL
timing requirements for operation as an I2C master.
Minimum High and Low Counts

When the I2C operates as an I2C master, in both transmit and receive transfers:
• Minimum value that can be programmed in the *_LCNT registers is 8
• Minimum value allowed for the *_HCNT registers is 6
The minimum value of 8 for the *_LCNT registers is due to the time required for the I2C to
drive SDA after a negative edge of SCL.
The minimum value of 6 for the *_HCNT register is due to the time required for the I2C to
sample SDA during the high period of SCL.
The I2C adds one cycle to the programmed *_LCNT value in order to generate the low
period of the SCL clock. This is due to the counting logic for SCL low counting to
(*_LCNT+1).
The I2C adds eight cycles to the programmed *_HCNT value in order to generate the high
period of the SCL clock. This is due to the following factors:
• The counting logic for SCL high counts to (*_HCNT+1).
• The digital filtering applied to the SCL line incurs a delay of four ic_clk cycles. This
filtering includes metastability removal and a 2-out-of-3 majority vote processing on
SDA and SCL edges.
• Whenever SCL is driven 1 to 0 by the I2C - that is, completing the SCL high time—an
internal logic latency of three ic_clk cycles is incurred.
Consequently, the minimum SCL low time of which the I2C is capable is nine (9) ic_clk
periods (8+1), while the minimum SCL high time is fourteen (14) ic_clk periods (6+1+4+3).
Minimum IC_CLK Frequency

This section describes the minimum ic_clk frequencies that the I2C supports for each
speed mode, and the associated high and low count values. It should be noted that these
limits apply to the I2C in both master and slave modes. The limits for slave mode are
required so that the I2C does not break the Thd;dat maximum I2C protocol timing
requirement.
Standard and Fast Modes
This section details how to derive a minimum ic_clk value for standard and fast modes of
the I2C.
Although the following method shows how to do fast mode calculations, you can also use
the same method in order to do calculations for standard mode.
Given conditions and calculations for the minimum I2C ic_clk value in fast mode:
• Fast mode has data rate of 400kb/s; implies SCL period of 1/400khz = 2.5us
• Minimum hcnt value of 14 as a seed value; IC_HCNT_FS = 14
• Protocol minimum SCL high and low times:
• MIN_SCL_LOWtime_FS = 1300ns
• MIN_SCL_HIGHtime_FS = 600ns
The following table lists the minimum ic_clk values for all modes with standard and fast
count values.
SCL SCL Low SCL SCL SCL High SCL
Speed Ic_clkfreq
Low Program Low High Program High
Mode (MHz)
Count Value Time Count Value Time
SS 2.7 13 12 4.7μs 14 6 5.2μs
FS 12.0 16 15 1.33μs 14 6 1.16μs
Table 9.10 ic_clk in Relation to High and Low Counts
Note: The IC_*_SCL_LCNT and IC_*_SCL_HCNT registers are programmed using the
SCL low and high program values in Table 6.9, which are calculated using SCL low count
minus 1, and SCL high counts minus 8, respectively.
Calculating High and Low Counts

The calculations below show how to calculate SCL high and low counts for each speed
mode in the I2C. For the calculations to work, the ic_clk frequencies used must not be less
than the minimum ic_clk frequencies specified in Table 6.9.
The ic_clk period must not specify a clock of a lower frequency than required for all
supported speed modes. It is possible that the automatically calculated values may result
in a baud rate higher than the maximum rate specified by the protocol. If this happens,
either the low or high count values can be scaled up to reduce the baud rate.
SDA Hold Time

The I2C protocol specification requires 300ns of hold time on the SDA signal (tHD;DAT) in
standard and fast speed modes.
Board delays on the SCL and SDA signals can mean that the hold-time requirement is met
at the I2C master, but not at the I2C slave (or vice-versa). As each application will
encounter differing board delays, the I2C contains a software programmable register
(IC_SDA_HOLD) to enable dynamic adjustment of the SDA hold-time.
The IC_SDA_HOLD register can be used to alter the timing of the generated SDA
(ic_data_oe) signal by the I2C. Each value in the IC_SDA_HOLD register represents a unit
of one ic_clk period.
When the I2C is operating in Master Mode, the minimum tHD:DAT timing is one ic_clk
period.
Therefore, even when IC_SDA_HOLD has a value of zero, the I2C will drive SDA
(ic_data_oe) one ic_clk cycle after driving SCL (ic_clk_oe) to logic 0. For all other values
of IC_SDA_HOLD, the following is true:
• Drive on SDA (ic_data_oe) will occur IC_SDA_HOLD ic_clk cycles after driving SCL
(ic_clk_oe) to logic0.
When the I2C is operating in Slave Mode, the minimum tHD:DAT timing is eight ic_clk
periods.
This delay is to allow for synchronization and filtering on the SCL (ic_clk_in) sample.
Therefore, even when IC_SDA_HOLD has a value less than 8, the I2C will drive SDA
(ic_data_oe) eight ic_clk cycles after SCL (ic_clk_in) has transitioned to logic 0. For all
other values of IC_SDA_HOLD, the following is true:
• Drive on SDA (ic_data_oe) will occur IC_SDA_HOLD ic_clk cycles after SCL (ic_clk_in)
has transitioned to logic 0.
If different SDA hold times are required for different speed modes, the IC_SDA_HOLD
register must be reprogrammed when the speed mode is being changed. The
IC_SDA_HOLD register cab be programmed only when the I2C is disabled (IC_ENABLE
= 0).
The following figure shows the tHD:DAT timing generated by the I2C operating in Master
Mode when IC_SDA_HOLD = 3.
Figure 9.93 I2C Master Implementing tHD;
9.11.4. I2C Register Map

0x0000 I2C_CON I2C control
0x0004 I2C_TAR I2C target address
0x0008 I2C_SAR I2C slave address
0x000C I2C_HS_MADDR I2C HS Master Mode Code Address
0x0010 I2C_DATA_CMD I2C Rx/Tx Data Buffer and Command
0x0014 I2C_SS_SCL_HCNT Standard speed I2C Clock SCL High
Count
0x0018 I2C_SS_SCL_LCNT Standard speed I2C Clock SCL Low
Count
0x001C I2C_FS_SCL_HCNT Fast speed I2C Clock SCL High Count
0x0020 I2C_FS_SCL_LCNT Fast speed I2C Clock SCL Low Count
0x002C I2C_INTR_STAT I2C Interrupt Status
0x0030 I2C_INTR_MASK I2C Interrupt Mask
0x0034 I2C_RAW_INTR_STAT I2C Raw Interrupt Status
0x0038 I2C_RX_TL I2C Receive FIFO Threshold
0x003C I2C_TX_TL I2C Transmit FIFO Threshold
0x0040 I2C_CLR_INTR Clear Combined and Individual
Interrupts
0x0044 I2C_CLR_RX_UNDER Clear RX_UNDER Interrupt
0x0048 I2C_CLR_RX_OVER Clear RX_OVER Interrupt
0x004C I2C_CLR_TX_OVER Clear TX_OVER Interrupt
0x0050 I2C_CLR_RD_REQ Clear RD_REQ Interrupt
0x0054 I2C_CLR_TX_ABRT Clear TX_ABRT Interrupt
0x0058 I2C_CLR_RX_DONE Clear RX_DONE Interrupt
0x005C I2C_CLR_ACTIVITY Clear ACTIVITY Interrupt
0x0060 I2C_CLR_STOP_DET Clear STOP_DET Interrupt
0x0064 I2C_CLR_START_DET Clear START_DET Interrupt
0x0068 I2C_CLR_GEN_CALL Clear GEN_CALL Interrupt
0x006C I2C_ENABLE I2C Enable
0x0070 I2C_STATUS I2C Status register
0x0074 I2C_TXFLR Transmit FIFO Level Register
0x0078 I2C_RXFLR Receive FIFO Level Register
0x007C I2C_SDA_HOLD SDA hold time length register
0x0080 I2C_TX_ABRT_SOURCE I2C Transmit Abort Status Register
0x0084 I2C_SLV_DATA_NACK_ONLY Generate SLV_DATA_NACK
0x0088 I2C_DMA_CR DMA Control Register for transmit and
receive handshaking interface
0x008C I2C_DMA_TDLR DMA Transmit Data Level
0x0090 I2C_DMA_RDLR DMA Receive Data Level
0x0094 I2C_SDA_SETUP I2C SDA Setup Register
0x0098 I2C_ACK_GENERAL_CALL I2C ACK General Call Register
0x009C I2C_ENABLE_STATUS I2C Enable Status Register
0x00a0 I2C_CON1 I2C control
0x00b0 I2C_TIMEOUT I2C timeout control
0x00b4 I2C_CLR_TIME_OUT I2C timeout interrupt clear
I2C_CON address offset: 0x0000

6 RW 0x1 IC_SLAVE_DI This bit controls whether I2C has its slave
S disabled
0: slave is enable
1: slave is disable
5 RW 0x1 IC_RESTART Determines whether RESTART conditions
may be sent when acting as a master
0: disable
1: enable
4 R 0x1 MASTER_10 When acting as a master, the i2c responds
BIT only to 10-bit address
3 RW 0x1 SLAVE_10BI When acting as a slave, this bit controls
T whether the i2c responds to 7- or 10-bit
addresses.
0: 7-bit addressing
1: 10-bit addressing
2:1 RW 0x2 SPEED These bits control at which speed the I2C
operates
1: standard mode (100Kb/s)
2: fast mode (400Kb/s)
0 RW 0x1 MASTER_M This bit controls whether the master is
ODE enabled.
0: master disabled
1: master enabled
I2C_TAR address offset: 0x0004

12 RW 0x1 MASTER_10 This bit controls whether the i2c starts its
BIT_SEL transfers in 7- or 10-bit addressing mode
when acting as a master.
0: 7-bit addressing
1: 10-bit addressing
11 RW 0x0 SPECIAL This bit indicates whether software performs a
General Call or START BYTE command.
0: ignore bit 10 GC_OR_START and use
IC_TAR normally
1: perform special I2C command as specified
in GC_OR_START bit
10 RW 0x0 GC_OR_STA If bit 11 (SPECIAL) is set to 1, then this bit
RT indicates whether a General Call or START
byte command is to be performed by the i2c
0: General Call Address
1: START BYTE
9:0 RW 0x55 IC_TAR This is the target address for any master
transaction
I2C_SAR address offset: 0x0008

9:0 RW 0x55 IC_SAR The IC_SAR holds the slave address when
the I2C is operating as a slave. For 7-bit
addressing, only IC_SAR[6:0] is used.
I2C_HS_MADDR address offset: 0x000c

2:0 RW 0x1 IC_HS_MAR This bit field holds the value of the I2C HS
mode master code.
I2C_DATA_CMD address offset: 0x0010

8 RW 0x0 CMD This bit controls whether a read or a write is
performed. This bit does not control the
direction when the i2c acts as a slave. It
controls only the direction when it acts as a
master.
1 = Read
0 = Write
7:0 RW 0x0 DAT This register contains the data to be
transmitted or received on the I2C bus.
I2C_SS_SCL_HCNT address offset: 0x0014

15:0 RW 0x190 I2C_SS_SCL_ This register sets the SCL clock high-period
HCNT count
for standard speed.
I2C_SS_SCL_LCNT address offset: 0x0018

15:0 RW 0x1d6 I2C_SS_SCL_ This register sets the SCL clock low-period
LCNT count
for standard speed.
I2C_FS_SCL_HCNT address offset: 0x001c

15:0 RW 0x3c I2C_FS_SCL_ This register sets the SCL clock high-period
HCNT count
for fast speed.
I2C_FS_SCL_LCNT address offset: 0x0020

15:0 RW 0x82 I2C_FS_SCL_ This register sets the SCL clock low-period
LCNT count
for fast speed.
I2C_INTR_STAT address offset: 0x002c

12 R 0x0 R_TIME_OUT Set time out interrupt when i2c bus no
response for a user defined time
11 R 0x0 R_GEN_CALL Set only when a General Call address is
received and it is acknowledged
10 R 0x0 R_START_DE Indicates whether a START or RESTART
T condition has occurred
9 R 0x0 R_STOP_DET Indicates whether a STOP condition has
occurred
8 R 0x0 R_ACTIVITY This bit captures I2C activity and stays set until
it is cleared
7 R 0x0 R_RX_DONE When the I2C is acting as a slave-transmitter,
this bit is set to 1 if the master does not
acknowledge a transmitted byte
6 R 0x0 R_TX_ABRT This bit indicates if an I2C transmitter, is unable
to complete the actions on the contents of the
transmit FIFO.
5 R 0x0 R_RD_REQ This bit is set to 1 when another I2C master is
attempting to read data from one I2C slave
4 R 0x0 R_TX_EMPTY This bit is set to 1 when the transmit buffer is at
or below the threshold value
3 R 0x0 R_TX_OVER Set during transmit if the transmit buffer is filled
to the threshold value
2 R 0x0 R_RX_FULL Set when the receive buffer reaches or goes
above the threshold value
1 R 0x0 R_RX_OVER Set if the receive buffer is completely filled
0 R 0x0 R_RX_UNDER Set if the processor attempts to read the
receive
buffer when it is empty
I2C_INTR_MASK address offset: 0x0030

12 RW 0x0 M_TIME_OUT TIME_OUT interrupt mask
11 RW 0x1 M_GEN_CALL GEN_CALL interrupt mask
10 RW 0x1 M_START_DE START_DET interrupt mask
T
9 RW 0x1 M_STOP_DET STOP_DET interrupt mask
8 RW 0x1 M_ACTIVITY ACTIVITY interrupt mask
7 RW 0x1 M_RX_DONE RX_DONE interrupt mask
6 RW 0x1 M_TX_ABRT TX_ABRT interrupt mask
5 RW 0x1 M_RD_REQ RD_REQ interrupt mask
4 RW 0x1 M_TX_EMPTY TX_EMPTY interrupt mask
3 RW 0x1 M_TX_OVER TX_OVER interrupt mask
2 RW 0x1 M_RX_FULL RX_FULL interrupt mask
1 RW 0x1 M_RX_OVER RX_OVER interrupt mask
0 RW 0x1 M_RX_UNDER RX_UNDER interrupt mask
I2C_RAW_INTR_STAT address offset: 0x0034

12 R 0x0 TIME_OUT TIME_OUT raw interrupt status
11 R 0x0 GEN_CALL GEN_CALL raw interrupt status
10 R 0x0 START_DET START_DET raw interrupt status
9 R 0x0 STOP_DET STOP_DET raw interrupt status
8 R 0x0 ACTIVITY ACTIVITY raw interrupt status
7 R 0x0 RX_DONE RX_DONE raw interrupt status
6 R 0x0 TX_ABRT TX_ABRT raw interrupt status
5 R 0x0 RD_REQ RD_REQ raw interrupt status
4 R 0x0 TX_EMPTY TX_EMPTY raw interrupt status
3 R 0x0 TX_OVER TX_OVER raw interrupt status
2 R 0x0 RX_FULL RX_FULL raw interrupt status
1 R 0x0 RX_OVER RX_OVER raw interrupt status
0 R 0x0 RX_UNDER RX_UNDER raw interrupt status
I2C_RX_TL address offset: 0x0038

7:0 RW 0x0 RX_TL Receive FIFO Threshold Level
I2C_TX_TL address offset: 0x003c

7:0 RW 0x0 TX_TL Transmit FIFO Threshold Level
I2C_CLR_INTR address offset: 0x0040

0 R 0x0 CLR_INTR Read this register to clear the combined
interrupt, all individual interrupts
I2C_CLR_RX_UNDER address offset: 0x0044

0 R 0x0 CLR_RX_UND Read this register to clear the RX_UNDER
ER interrupt
I2C_CLR_RX_OVER address offset: 0x0048

0 R 0x0 CLR_RX_OVE Read this register to clear the RX_OVER
R interrupt
I2C_CLR_TX_OVER address offset: 0x004c

0 R 0x0 CLR_TX_OVE Read this register to clear the TX_OVER
R interrupt
I2C_CLR_RD_REQ address offset: 0x0050

0 R 0x0 CLR_RD_REQ Read this register to clear the RD_REQ
interrupt
I2C_CLR_TX_ABRT address offset: 0x0054

0 R 0x0 CLR_TX_ABR Read this register to clear the TX_ABRT
T interrupt
I2C_CLR_RX_DONE address offset: 0x0058

0 R 0x0 CLR_RX_DON Read this register to clear the RX_DONE
E interrupt
I2C_CLR_ACTIVITY address offset: 0x005c

0 R 0x0 CLR_ACTVITY Read this register to clear the ACTIVITY
interrupt
I2C_STOP_DET address offset: 0x0060

0 R 0x0 CLR_STOP_D Read this register to clear the STOP_DET
ET interrupt
I2C_START_DET address offset: 0x0064

0 R 0x0 CLR_START_ Read this register to clear the START_DET
DET interrupt
I2C_GEN_CALL address offset: 0x0068

0 R 0x0 CLR_GEN_CA Read this register to clear the GEN_CALL
LL interrupt
I2C_ENABLE address offset: 0x006c

0 RW 0x0 ENABLE Controls whether the i2c is enabled.
0: Disables i2c (TX and RX FIFOs are held in
an erased state)
1: Enables i2c
I2C_STATUS address offset: 0x0070

6 R 0x0 SLV_ACTIVITY Slave FSM Activity Status
0: Slave FSM is in IDLE state
1: Slave FSM is not in IDLE state
5 R 0x0 MST_ACTIVIT Master FSM Activity Status
Y 0: Master FSM is in IDLE state
1: Master FSM is not in IDLE state
4 R 0x0 RFF Receive FIFO Completely Full.
0: Receive FIFO is not full
1: Receive FIFO is full
3 R 0x0 RFNE Receive FIFO Not Empty
0: Receive FIFO is empty
1: Receive FIFO is not empty
2 R 0x1 TFE Transmit FIFO Completely Empty
0: Transmit FIFO is not empty
1: Transmit FIFO is empty
1 R 0x1 TFNF Transmit FIFO Not Full
0: Transmit FIFO is full
1: Transmit FIFO is not full
0 R 0x0 ACTIVITY I2C Activity Status.
I2C_TXFLR address offset: 0x0074

5:0 R 0x0 TXFLR Transmit FIFO Level. Contains the number of
valid data entries in the transmit FIFO.
I2C_RXFLR address offset: 0x0078

5:0 R 0x0 RXFLR Receive FIFO Level. Contains the number of
valid data entries in the receive FIFO.
I2C_STA_HOLD address offset: 0x007c

15:0 RW 0x1 I2C_SDA_HOL Sets the required SDA hold time
D
I2C_TX_ABRT_SOURCE address offset: 0x0080

15 R 0x0 ABRT_SLVRD 1: When I2C slave is requested to transmit
_INTX data to a master and user writes a 1 in CMD
(bit 8) of IC_DATA_CMD register.
14 R 0x0 ABRT_SLV_A 1: Slave lost the bus while transmitting data to
RBLOST a remote master
13 R 0x0 ABRT_SLVFL 1: Slave has received a read command and
USH_TXFIFO some data exists in the TX FIFO so the slave
issues a TX_ABRT interrupt to flush old data
in TX FIFO.
12 R 0x0 ARB_LOST 1: I2C has lost arbitration
11 R 0x0 ABRT_MASTE 1: User tries to initiate a Master operation with
R_DIS the Master mode disabled.
10 R 0x0 ABRT_10B_R 1: The restart is disabled and the master
D_NORSTRT sends a read command in 10-bit addressing
mode.
9 R 0x0 ABRT_SBYTE 1: The restart is disabled and the user is trying
_NORSTRT to send a START Byte
8 R 0x0 N/A reserved
7 R 0x0 ABRT_SBYTE 1: Master has sent a START Byte and the
_ACKDET START Byte was acknowledged
6 R 0x0 N/A reserved
5 R 0x0 ABRT_GCALL 1: i2c in master mode sent a General Call but
_READ the user programmed byte following the
General Call is a read
4 R 0x0 ABRT_GCALL 1: i2c in master mode sent a General Call and
_NOACK no slave on the bus acknowledged the
General Call.
3 R 0x0 ABRT_TXDAT 1: This is a master-mode only bit. Master has
A_NOACK received an acknowledgement for the
address, but when it sent data following the
address, it did not receive an acknowledge
from the remote slave
2 R 0x0 ABRT_10ADD 1: Master is in 10-bit addressing mode and the
R2_NOACK second 10-bit address byte was not
acknowledged by any slave.
1 R 0x0 ABRT_10ADD 1: Master is in 10-bit addressing mode and the
R1_NOACK first 10-bit address byte was not
acknowledged by any slave.
0 R 0x0 ABRT_7B_AD 1: Master is in 7-bit addressing mode and the
DR_NOACK address sent was not acknowledged by any
slave.
I2C_SLV_DATA_NACK_ONLY address offset: 0x0084

0 RW 0x0 NACK Generate NACK.
This NACK generation only occurs when i2c is
a slave-receiver.
1 = generate NACK after data byte received
0 = generate NACK/ACK normally
I2C_DMA_CR address offset: 0x0088

1 RW 0x0 TDMAE Transmit DMA Enable.
This bit enables/disables the transmit FIFO
DMA channel.
0 = Transmit DMA disabled
1 = Transmit DMA enabled
0 RW 0x0 RDMAE Receive DMA Enable.
This bit enables/disables the receive FIFO
DMA channel.
0 = Receive DMA disabled
1 = Receive DMA enabled
I2C_DMA_TDLR address offset: 0x008c

7:0 RW 0x0 DMATDL Transmit Data Level. This bit field controls the
level at which a DMA request is triggered
I2C_DMA_RDLR address offset: 0x0090

7:0 RW 0x0 DMARDL Receive Data Level.
This bit field controls the level at which a DMA
request is triggered
I2C_SDA_SETUP address offset: 0x0094

7:0 RW 0x64 SDA_SETUP SDA setup time
I2C_ACK_GENERAL_CALL address offset: 0x0098

0 RW 0x1 ACK_GEN_CA ACK General Call.
LL When set to 1, i2c responds with a ACK (by
asserting ic_data_oe) when it receives a
General Call. When set to 0, the i2c does not
generate General Call interrupts.
I2C_ENABLE_STATUS address offset: 0x009C

2 R 0x0 SLV_RX_DAT Slave Received Data Lost.
A_LOST
1 R 0x0 SLV_DIS_IN_ Slave Disabled While Busy (Transmit,
BUSY Receive).
0 R 0x0 I2C_EN ic_en Status.
I2C_CON1 address offset: 0x00A0

31 W 0x0 I2C_EN_CLR Write 1 to clear i2c_en, self clear
25:24 RW 0x0 TRIG_SRC_E Trigger source edge select:
DGE_SEL 0: pos-edge
1: neg-edge
3: both edge
23:20 RW 0x0 TRIG_SRC_S Trigger source select
EL
16 W 0x0 RD_DATA_NU Write 1 to update RD_DATA_NUM, self clear
M_UPDATE
13 RW 0x0 I2C_EN_EXT_ 1: I2C_EN_EXT enable
MASK 0: I2C_EN_EXT masked
12 RW 0x0 I2C_RX_EN 1: I2C RX
0: I2C TX
11:0 RW 0x0 RD_DATA_NU I2C read byte numbers
M
I2C_TIMEOUT address offset: 0x00B0

31 RW 0x0 I2C_EN_TIME I2C timeout interrupt enable
OUT
30:0 RW 0x0 I2C_TIMEOUT The timeout interrupt trigger level
_CNT
I2C_CLR_TIME_OUT address offset: 0x00B4

0 R 0x0 CLR_TIME_O Read this register to clear the TIME_OUT
UT interrupt
9.12. EFUSE
EFUSE controller can be burn the EFUSE mem ip and read EFUSE mem ip transparently;
The EFUSE controller in OM6621Ex is connected to the system APB bus;
• One byte of data can be burned at a time, and burst burning operation is not supported;
• The data in EFUSE mem ip is all 0 by default, and the burning process is the
process of writing the silent bit to 1;
• The software can read EFUSE mem transparently through APB bus;
• EFUSE memory offset address: 0x000~0x01F;
• EFUSE register offset address: 0xF00~0xFFF;
• Burning speed: the single bit burning speed is about 1bit/12us. Since the AVDD needs
30us pull up time for each byte burning, the actual single bit burning speed will be
greater than 1bit/12us; (For example, when burning 0xff, the total time is about 8 *
12us + 30us, and the single bit burning speed is about 8 * 12 + 30/8 = 16us).
9.12.2.1. Operation Process
Burning process:
Assuming the EFUSE working clock is 32mhz, burn the quantity 0x34 to the second byte
of EFUSE mem;
1) Set the burning configuration register:
avdd_tim_cfg>10us/ (1/32 MHz) =0x160
T_sp_pgm > 100ns/31.25ns=4;
T_sp_pg_avdd > 1us/31.25ns=35=0x23;
T_pgm = 10us/31.25ns=320=0x140;
T_aen = T_pgm +1.9us/31.25ns=320+60=0x180;
T_sp_a > 50ns/31.25ns=2;
So, set register value:
*(0xF08) =0x000002e0;
*(0xF18) =0x00040023;
*(0xF1c) =0x01400180;
*(0xF20) =0x00000002;
2) Set the read configuration register:
T_sr_rd > 100ns/31.25ns=4;
T_sr_a > 10ns/31.25ns=1;
T_aen_rd > (T_rd +35ns)/31.25ns=4;
T_rd > 40ns/31.25ns=2;
So, set register value:
*(0xF24) =0x04010402;
3) Set program_en=1;
4) Set program address=0x1;
5) Set Program data=0x34;
6) Set Program_start=1;
7) Wait Program_start=0 Indicates that burning is completed.
9.12.3. Typical Parameter Configuration
EFUSE work clk freq

64MHz 32MHz
(apb_clk)
Program config0 0x0008_0046 0x0004_0023
Program config1 0x0280_0300 0x0140_017C
Program config2 0x0000_0004 0x0000_0002
read config 0x0701_0603 0x0401_0302
Avdd config(5.5us) 0x160 0x0B0
Table 9.11 Typical Parameter Configuration
9.12.3.1. Program Mode
See the following figure and table for timing requirements for program mode.
Figure 9.94 Timing Diagram for Program Mode
Value
Paremeter Symbol Uint
Min Typ Max
Burning time TPGM 9000 10000 11000 ns
Address enable cycle time TAEN TPGM + 1900 ns
Address to AEN setup time TSP_A 50 - ns
Address hold time from AEN THP_A 50 - ns
PGMEN signal to AEN setup ns
TSP_PGM 100
time
AEN to PGMEN signal hold ns
THP_PGM 100
time
PDEN signal to AVDD setup ns
TSP_RD 150
time
AVDD to RDEN signal hold ns
THP_RD 150
time
AVDD to PGMEN setup time TSP_PG_AVDD 1000 ns
PGMEN to AVDD hold time THP_PG_AVDD 1000
Table 9.12 Timing Diagram for Program Mode
9.12.3.2. Read Mode
See the following figure and table for timing requirements for program mode.
Figure 9.95 Timing Diagram for Read Mode
Value
Paremeter Symbol Uint
Min Typ Max
Read time TRD 40 ns
Address enable cycle time TAEN TRD + 35 ns
Address to AEN setup time TSR_A 10 - ns
AEN to Address hold time THR_A 10 - ns
DVDD to RDEN setup time TSR_DVDD 150 ns
RDEN to DVDD hold time THR_DVDD 150 ns
RDEN signal to AEN setup ns
TSR_RD 100
time
Output data steady time with ns
TSQ 45
0 loading
Output data hold time TSQ_H 0 ns
AEN to RDEN signal hold ns
THR_RD 100
time
Table 9.13 ACDD/DVDD Timing
Figure 9.96 Timing Change
enb_EFUSE_dvdd_pwrsw [1:0] is used to control the DVDD startup process. According to

the timing change in the figure above, this timing control is completed by the PMU hardware;
The DVDD will not be closed after it is turned on until the PSO is powered off.
9.12.4. EFUSE Register Map

0xF00 PROG_EN Program enable
0xF04 PROG_START Program start
0xF08 AVDD_TIM_CFG AVDD Timing configuration
0xF0C PROG_ADDR Program address
0xF10 PROG_DATA Program data
0xF18 PROG_CFG0 Program configuration0
0xF1C PROG_CFG1 Program configuration1
0xF20 PROG_CFG2 Program configuration2
0xF24 READ_CFG read configuration
0xF28 INTERRUPT interrupt configuration
0xF2C STATUS EFUSE controller status
PROG_EN address offset: 0xF00

0 RW 0x1 PROGRAM_EN Burn enable:
1: enable
0: disable
PROG_START address offset: 0xF04

0 R0W 0x0 PROGRAM_STA Burn start:
RT Setup Program_start=1 start burning,
Read Program_start=0 means the burning
is completed;
AVDD_TIM_CFG address offset: 0xF08

15:0 RW 0x160 AVDD_TIM_CFG AVDD 2.5v pull-up timing control:
AVDD 2.5v pull-up time needs to be
greater than 30us, avdd_tim_cfg is the
number of EFUSE clocks corresponding to
10us; For example, the EFUSE clock is
32mhz, 10us/(1/32MHz) = 0x140;
So avdd_tim_cfg Fill in the value slightly
greater than 0x160
PROG_ADDR address offset: 0xF0C

8:0 RW 0x0 PROGRAM Burn address, from 0 to 31
ADDRESS
PROG_DATA address offset: 0xF10

7:0 RW 0x0 PROGRAM DATA Burn data
PROG_CFG0 address offset: 0xF18
31:16 R/W 0x04 T_SP_PGM T_sp_pgm and T_hp_pgm (>100ns);
T_sp_pgm: PGMEM signal to AEN setup
time;
T_hp_pgm: AEN signal to PGMEM setup
time;
15:0 R/W 0x23 T_SP_PG_AVDD T_sp_pg_avdd and T_hp_pg_avdd
(>1000ns);
T_sp_pgm: AVDD signal to PGMEM setup
time;
T_hp_pgm: PGMEM signal to AVDD setup
time;
PROG_CFG1 address offset: 0xF1C

31:16 R/W 0x140 T_PGM T_pgm: burning time (9000ns~11000ns)
15:0 R/W 0x180 T_AEN T_aen address enable cycle time
(T_pgm+1900ns)
PROG_CFG2 address offset: 0xF20

15:0 R/W 0x02 T_SP_A T_sp_a and T_hp_a(>50ns)
T_sp_a: address signal to AEN setup time;
T_hp_a: AEN signal to address setup time;
RAED_CFG address offset: 0xF24

31:24 R/W 0x04 T_SR_RD T_sr_rd and T_hr_rd (>100ns)
T_sr_rd: RDEN signal to AEN setup time;
T_hr_rd: AEN signal to RDEN setup time;
23:16 R/W 0x01 T_SR_A T_sr_a and T_hr_a (>10ns)
T_sr_a: address signal to AEN setup time;
T_hr_a: AEN signal to address setup time;
15:8 R/W 0x04 T_AEN_RD T_aen for read address enable cycle time
(>T_rd +35ns)
7:0 R/W 0x02 T_RD Read time(>40ns)
INTERRUPT address offset: 0xF28

2 R 0x0 EFUSE_INT 1: EFUSE interrupt happen;
0: no EFUSE interrupt
1 R0/ 0x0 EFUSE_INT_CL Interrupt clear, write 1 clear interrupt, read
W R return 0
0 R/W 0x0 EFUSE_INT_EN EFUSE interrupt enable
1: enable
0: disable
STATUS address offset: 0xF2C

11:8 R 0x3 CTRL STATE EFUSE controller state for debug
3 R 0x0 ERR_SET_REA 1: read parameter config error, T_aen_rd<
D (T_sr_a+T_rd)
0: no error
2 R0/ 0x0 ERR_SET_PRO 1: program parameter config error,
W G T_pgm > T_aen
0: no error
1 N/A N/A reserved
0 R READY EFUSE controller state
1: idle (standby)
0: busy (program state)
9.13. IR
IR transceiver is an analog block, which can drive IR LED by TX, and can translate the IR
LED sense current to digital signal.
The PWM output driving capability can be adjusted by setting value of IR_PWMDRV, and
the sensitivity of RX block by IR_SENSE[1:0].
9.13.2.1. Enable PWM
Register PWM_EN (offset address 0x00) [0] serves to enable PWM via writing “1” for bit0.
9.13.2.2. Set PWM Clock
IR_clk is from main_clk, the frequency of IR_clk can be set use CPM register
CPM_IRTX_CFG. For detail, see CPM chapter.
9.13.2.3. PWM Waveform, Polarity and Output Inversion
Each PWM channel has independent counter and 2 status including “Count” and
“Remaining”. Count and Remaining status form a signal frame.
9.13.2.4. Waveform of Signal Frame
When PWM is enabled, first PWM enters count status and outputs High level signal by
default. When PWM counter reaches cycles set in register PWM_TCMP (offset address
0x10) / PWM_TCMP_SHADOW (0x18), PWM enters Remaining status and outputs Low
level till PWM cycle time configured in register PWM_TMAX (offset address 0x14) /
PWM_TMAX0_SHADOW (0x1c) expires.
Figure 9.97 Signal Frame

An interruption will be generated at the end of each signal frame if enabled via register
PWM_INT_MASK (address 0x2c [2:0]).
9.13.2.5. Invert PWM Output
PWM output could be inverted independently via register PWM_INV (offset address
0x08[0]). When the inversion bit is enabled, waveform of the corresponding PWM channel
will be inverted completely.
9.13.2.6. Polarity for Signal Frame
By default, PWM outputs high level at count status and Low level at Remaining status.
When the corresponding polarity bit is enabled via register PWM_POLARITY (offset
address 0x0c [0]), PWM will output Low level at count status and High level at remaining
status.
Figure 9.98 PWM Output Waveform Chart
9.13.3. PWM Mode
9.13.3.1. Select PWM Mode
PWM supports two modes, including IR mode (normal mode, default) and IR FIFO mode.
Register PWM_MODE (offset address 0x04) serves to select PWM mode.
9.13.3.2. IR Mode
Offset address 0x04 [1:0] should be set as 2b’00 to select PWM IR mode.
In this mode, specified number of frames is defined as one pulse group. During IR mode,
PWM output waveform could also be changed freely via WM_TCMP, PWM_TMAX and
PWM_PNUM. New configuration for PWM_TCMP, PWM_TMAX and PWM_PNUM will
take effect in the next pulse group.
To stop IR mode and complete current pulse group, IR mode can disable directly via
PWM_EN (offset 0x00[0]), PWM output will turn Low immediately despite of current pulse
group. After each signal frame/pulse group is finished, PWM cycle done interrupt flag bit
(0x30[2])/PWM pnum interrupt flag bit (0x30[0]) will be automatically set to 1b’1. A frame
interruption/Pnum interruption will be generated (if enabled by setting address 0x2c
[2]/0x2c [0] as 1b’1).
Figure 9.99 IR Mode
9.13.3.3. IR FIFO Mode
IR FIFO mode is designed to allow IR transmission of long code patterns without the
continued intervention of MCU, and it is designed as a selectable working mode on PWM.
The IR carrier frequency is divided down from the system clock and can be configured as
any normal IR frequencies, e.g. 36 kHz, 38 kHz, 40 kHz or 56 kHz.
Offset address 0x04[1:0] should be set as 2b’01 to select PWM IR FIFO mode.
An element (“FIFO CFG Data”) is defined as basic unit of IR waveform, and written into
FIFO. This element consists of 16 bits, including:
• bit [13:0] defines PWM pulse number of current group.
• bit [14] determines duty cycle and period for current PWM pulse group.
• 0: use configuration of TCMP and TMAX in 0x10~0x14.
• 1: use configuration of TCMP_SHADOW and TMAX_SHADOW in 0x18~0x1c.
• bit [15] determines whether current PWM pulse group is used as carrier, i.e. whether
PWM will output pulse (1) or low level (0).
User should use FIFO_DATA_ENTRY in 0x3c to write the 16-bit “FIFO CFG Data” into
FIFO by byte or half word or word.
• To write by byte, user should successively write 0x3c, 0x3d, 0x3e and 0x3f.
• To write by half word, user should successively write 0x3c and 0x3e.
• To write by word, user should write 0x3c.
FIFO depth is 16 words. User can read the register FIFO_SR in 0x44 to view FIFO
empty/full status and check FIFO data number.
Figure 9.100 IR Format Examples
When “FIFO CFG Data” is configured in FIFO and PWM is enabled via PWM_EN (address
0x00), the configured waveforms will be output from PWM in sequence. As long as FIFO
doesn’t overflow, user can continue to add waveforms during IR waveforms sending
process, and long IR code that exceeds the FIFO depth can be implemented this way. After
all waveforms are sent, FIFO becomes empty, PWM will be disabled automatically.
The FIFO_CLR register (offset address 0x48[0]) serves to clear data in FIFO. Writing 1b’1
to this register will clear all data in the FIFO. Note that the FIFO can only be cleared when
not in active transmission.
Example 1:
Suppose Mark carrier (pulse) frequency1 (F1) = 40 kHz, duty cycle 1/3
Mark carrier (pulse) frequency2 (F2) = 50 kHz, duty cycle 1/2
Space carrier (low level) frequency (F3) = 40 kHz
If user wants to make PWM send waveforms in following format (PWM CLK = 24 MHz):
Burst(20[F1]), i.e. 20 F1 pulses
Burst(30[F2])
Burst(50[F1]) ,
Burst(50[F2]),
Burst(20[F1],10[F3]),
Burst(30[F2],10[F3])
Step 1: Set carrier F1 frequency as 40 kHz, set duty cycle as 1/3.
Set PWM_TMAX as 0x258 (i.e. 24 MHz/40 kHz = 600 = 0x258).
Since duty cycle is 1/3, set PWM_TCMP as 0xc8 (i.e. 600/3 = 200 = 0xc8).
Set carrier F2 frequency as 50 kHz, set duty cycle as 1/2.
Set PWM_TMAX_SHADOW as 0x1e0 (i.e. 24 MHz/50kHz = 480 = 0x1e0).
Since duty cycle is 1/2, set PWM_TCMP_SHADOW as 0xf0 (i.e. 480/2 = 240 = 0xf0).
Step 2: Generate “FIFO CFG Data” sequence.
Burst (20[F1]): {[15]: 1’b1, [14]: 1’b0, [13:0]: ’d20} = 0x8014.
Burst (30[F2]): {[15]: 1’b1, [14]: 1’b1, [13:0]: ’d30} = 0xc01e.
Burst (50[F1]): {[15]: 1’b1, [14]: 1’b0, [13:0]: ’d50} = 0x8032.
Burst (50[F2]): {[15]: 1’b1, [14]: 1’b1, [13:0]:’d50} = 0xc032.
Burst (20[F1], 10[F3]): {[15]: 1’b1, [14]: 1’b0, [13:0]: ’d20} = 0x8014,
{[15]: 1’b0, [14]: 1’b0, [13:0]: ’d10} = 0x000a.
Burst (30[F2],10[F3]): {[15]: 1’b1, [14]: 1’b1, [13:0]: ’d30} = 0xc01e,
{[15]:1’b0, [14]: 1’b0, [13:0]: ’d10} = 0x000a.
Step 3: After set PWM_EN =1, user should write “FIFO CFG Data” into IR FIFO.
DATA0: 0xc01e_8014 (little endian)
DATA1: 0xc032_8032
DATA2: 0x000a_8014
DATA3: 0x000a_c01e
After all waveforms are sent, FIFO becomes empty, PWM will be disabled automatically
(address 0x00[0] is automatically cleared). The FIFO mode stop interrupt flag bit (address
0x30[1]) will be automatically set as 1b’1. If the interrupt is enabled by setting
PWM_INT_MASK (address 0x2c [1]) as 1b’1, a FIFO mode stop interrupt will be generated.
User needs to write 1b’1 to the flag bit to manually clear it.
Example 2:
Suppose carrier frequency is 38 kHz, system clock frequency is 24 MHz, duty cycle is 1/3,
and the format of IR code to be sent is shown as below:
1) Preamble waveform: 9 ms carrier + 4.5 ms low level.
2) Data 1 waveform: 0.56 ms carrier + 0.56 ms low level.
3) Data 0 waveform: 0.56 ms carrier + 1.69 ms low level.
4) Repeat waveform: 9 ms carrier + 2.25 ms low level + 0.56 ms carrier. Repeat waveform
duration is 11.81 ms, interval between two adjacent repeat waveforms is 108 ms.
5) End waveform: 0.56 ms carrier.
User can follow the steps below to configure related registers:
Step 1: Set carrier frequency as 38 kHz, set duty cycle as 1/3.
Set PWM_TMAX as 0x277 (i.e. 24 MHz/38 kHz = 631 = 0 x 277).
Since duty cycle is 1/3, set PWM_TCMP as 0xd2 (i.e. 631/3 = 210 = 0xd2).
Step 2: Generate “FIFO CFG Data” sequence.
Preamble waveform:
9ms carrier: {[15]:1’b1, [14]:1’b0, [13:0]: 9*38=’d 342=14’h 156} = 0x8156
4.5ms low level: {[15]:1’b0, [14]:1’b0, [13:0]: 4.5*38=’d 171=14’h ab} = 0x00ab
Data 1 waveform:
0.56ms carrier: {[15]:1’b1, [14]:1’b0, [13:0]: 0.56*38=’d 21=14’h 15} = 0x8015
0.56ms low level: {[15]:1’b0, [14]:1’b0, [13:0]: 0.56*38 = ’d 21 = 14’h 15} = 0x0015
Data 0 waveform:
0.56ms carrier: {[15]:1’b1, [14]:1’b0, [13:0]: 0.56*38 = ’d 21 = 14’h 15} = 0x8015
Repeat waveform:
9ms carrier: {[15]:1’b1, [14]:1’b0, [13:0]: 9*38 = ’d 342 = 14’h 156} = 0x8156
0.56ms carrier: {[15]:1’b1, [14]:1’b0, [13:0]: 0.56*38 = ’d 21 = 14’h 15} = 0x8015
108ms -11.81ms =96.19ms low level:
{[15]:1’b0, [14]:1’b0, [13:0]: 96.19*38 = ’d 3655 = 14’h e47} = 0x0e47
End waveform:
0.56ms carrier: {[15]:1’b1, [14]:1’b0, [13:0]: 0.56*38 = ’d 21 = 14’h 15} = 0x8015
Step 3: Write “IR CFG Data” into IR FIFO.
If user want PWM to send IR waveform in following format:
Preamble+0x5a+Repeat+End
Preamble: 0x8156, 0x00ab
0x5a = 8’b01011010
Data 0: 0x8015, 0x0040
Data 1: 0x8015, 0x0015
Data 0: 0x8015, 0x0040
Data 1: 0x8015, 0x0015
Data 1: 0x8015, 0x0015
Data 0: 0x8015, 0x0040
Data 1: 0x8015, 0x0015
Data 0: 0x8015, 0x0040
Repeat: 0x8156, 0x0056, 0x8015, 0x0e47
End: 0x8015.
After set PWM_EN =1, user needs to write the configuration information above into IR
FIFO, as shown below:
0x00ab_8156 (Preamble) (little endian)
0x0040_8015 (Data 0)
0x0015_8015 (Data 1)
0x0040_8015 (Data 0)
0x0015_8015 (Data 1)
0x0015_8015 (Data 1)
0x0040_8015 (Data 0)
0x0015_8015 (Data 1)
0x0040_8015 (Data 0)
0x0056_8156 (Repeat)
0x0e47_8015 (Repeat)
0x8015 (End)
After all waveforms are sent, FIFO becomes empty, PWM will be disabled automatically
(address 0x00[0] is automatically cleared). The FIFO mode stop interrupt flag bit (address
0x30[1]) will be automatically set as 1b’1. If the interrupt is enabled by setting
PWM_MASK1 (address 0x2c [1]) as 1b’1, a FIFO mode stop interrupt will be generated.
User needs to write 1b’1 to the flag bit to manually clear it.
9.13.3.4. PWM Interrupt
There are 4 interrupt sources from PWM function.

After each signal frame, PWM will generate a frame-done IRQ (Interrupt Request) signal.
In IR mode, PWM will generate a Pnum IRQ signal after completing a pulse group. In IR
FIFO mode, PWM will generate a FIFO mode count IRQ signal when the FIFO_NUM value
is less than the FIFO_NUM_LVL, and will generate a FIFO mode stop IRQ signal after
FIFO becomes empty.. To enable various PWM interrupt sources, PWM_INT_MASK
(address 0x2c [2:0]) and FIFO_CNT_INT_MASK (address 0x34[1:0]) should be set as 1b’1
correspondingly. Interrupt status can be cleared via register PWM_INT_ST (address
0x30[2:0]) and FIFO_CNT_INT_ST (address 0x38[1:0]).
9.13.4. Port Description
The analog block of IR, which can drive IR LED by TX, and can translate the IR LED sense
current to digital signal. The PWM output driving capability can be adjusted by setting value
of IR_PWMDRV, and the sensitivity of RX block by IR_SENSE [1:0]
Figure 9.101 BLOCK Diagram of Analog
9.13.5. IR TX Register Map
Offset Reg Name Description
0x00 PWM_EN PWM enable
0x04 PWM_MODE mode select
0x08 PWM_INV PWM output invert configuration
0x0c PWM_POLARITY Signal frame polarity
0x10 PWM_TCMP PWM's high time or low time (if polarity [0]
=1)
0x14 PWM_TMAX PWM's cycle time
0x18 PWM_TCMP_SHADOW PWM's high time or low time (if polarity [0]
=1), if shadow bit (fifo data [14]) is 1’b1 in ir
fifo mode
0x1c PWM_TMAX_SHADOW PWM's cycle time, if shadow bit (fifo data
[14]) is 1’b1 in ir fifo mode
0x20 PWM_PNUM PWM Pulse number IR mode
0x24 PWM_CNT PWM cnt value
0x28 PWM_PULSE_CNT PWM pulse cnt value
0x2c PWM_INT_MASK PWM INT mask
0x30 PWM_INT_ST PWM INT status
0x34 FIFO_CNT_INT_MASK PWM fifo mode fifo cnt configuration
0x38 FIFO_CNT_INT_ST FIFO mode INT status
0x3c FIFO_DATA_ENTRY Use in IR fifo mode
0x40 FIFO_NUM_LVL FIFO number int trigger level
0x44 FIFO_SR FIFO status
0x48 FIFO_CLR FIFO clear
PWM_EN address offset: 0x00

0 RW 0x0 PWM_EN 0: disable PWM
1: enable PWM
PWM_MODE address offset: 0x04

1:0 RW 0x0 mode select
00: pwm IR normal mode
01: pwm IR FIFO mode
PWM_INV address offset: 0x08

0 RW 0x0 PWM output invert enable
0: not invert PWM output
1: invert PWM output
PWM_POLARITY address offset: 0x0C

0 RW 0x0 Signal frame polarity
0: high level first
1: low level first
PWM_TCMP address offset: 0x10

15:0 RW 0x0 PWM's high time or low time (if polarity [0]
=1)
PWM_TMAX address offset: 0x14

15:0 RW 0x0 PWM's cycle time
PWM_TCMP_SHADOW address offset: 0x18

15:0 RW 0x555 PWM's high time or low time (if polarity [0]
5 =1), if shadow bit (fifo data [14]) is 1’b1 in ir
fifo mode
PWM_TMAX_SHADOW address offset: 0x1C

15:0 RW 0x0 PWM's cycle time, if shadow bit (fifo data
[14]) is 1’b1 in ir fifo mode
PWM_PNUM address offset: 0x20

13:0 RW 0x0 PWM Pulse number IR mode
PWM_CNT address offset: 0x24

15:0 R 0x0 PWM cnt value
PWM_PULSE_CNT address offset: 0x28
15:0 R 0x0 PWM pulse cnt value
PWM_INT_MASK address offset: 0x2C

2 RW 0x0 PWM frame int mask
0: disable
1: Enable
1 RW 0x0 reserved
0 RW 0x0 PWM Pnum int mask
0: disable
1: Enable
PWM_INT_ST address offset: 0x30

2 RW 0x0 PWM cycle done int
(PWM_CNT==PWM_TMAX)
(write 1 to clear)
1 RW 0x0 reserved
0 RW 0x0 PWM pnum int (have sent PNUM pulses,
PWM_NCNT ==PWM_PNUM)
(write 1 to clear)
FIFO_CNT_INT_MASK address offset: 0x34

1 RW 0x0 PWM fifo mode fifo empty int mask
0: disable
1: Enable
0 RW 0x0 PWM fifo mode fifo cnt int mask
0: disable
1: Enable
FIFO_CNT_INT_ST address offset: 0x38

1 RW 0x0 fifo mode fifo empty int (write 1 to clear)
0 RW 0x0 fifo mode cnt int, when FIFO_NUM
(0x44[3:0]) is less than FIFO_NUM_LVL
(0x40[3:0]) (write 1 to clear)
FIFO_DATA_ENTRY address offset: 0x3C
31:0 RW 0x0 Use in ir fifo mode
FIFO_NUM_LVL address offset: 0x40

3:0 RW 0x0 FIFO number int trigger level
FIFO_SR address offset: 0x44

5 R 0x0 FIFO FULL
4 R 0x1 FIFO EMPTY
3:0 R 0x0 FIFO DATA NUM (byte)
FIFO_CLR address offset: 0x48

0 W1 0x0 write 1 to clear data in FIFO
9.13.6. IR RX Register Map
Offset Reg Name Description

0x78 IR_RX_CFG IR RX configuration
IR_RX_CFG address offset: 0x400A0078

8 RW 0x0 IR_TX_IN_ME IR_TX_IN control enable
7 RW 0x0 IR_TX_IN_MO IR_TX_IN control value
6 RW 0x0 IR_TEST_EN IR test signal output enable signal
0: disable
1: disable
5:4 RW 0x0 IR_SENSE RX current sensitivity control.
00: > 4uA
01: > 8uA
10: > 16uA
11: > 32uA
3:2 RW 0x0 IRRX_CH_SE IR RX input channel select signal
L 00: timer0 ch1
01: timer0 ch2
10: timer0 ch3
11: timer0 ch4
1 RW 0x0 IRRX_EN IR RX input enable signal
0: disable
1: enable
0 RW 0x0 IR_PDB_RX RX power down control signal.
0: power down
1: power on
10. Communication Subsystem
10.1. Supported Features
OM6621Ex on-chip Bluetooth system compliant with Bluetooth standard 5.1.
10.2. Radio Transceiver
The Radio Transceiver implements the RF part of the Bluetooth Low Energy protocol.
Together with the Bluetooth 5.1 PHY layer, this provides a reliable wireless communication.
All RF blocks are supplied by on-chip low-drop out-regulators (LDO’s). The Bluetooth LE
radio comprises the Receiver, Transmitter, Synthesizer, RX/TX combiner block, and
Biasing LDO’s.
Baseband
PA TX Filter
Modulator
RF Synthesizer
Baseband
ANT LNA RX Filter
Demodulator
Figure 10.1 RF Block Diagram
10.2.1. Bluetooth Radio Receiver
The OM6621Ex receiver is a low IF down conversion architecture. The RF signal passes
first through an integrated transformer, which is shared between receiver and transmitter.
The transformer drives a differential variable-gain LNA, which amplifies the signal before it
passes through a low-IF down conversion mixer stage. Following the mixer is a third-order
complex BPF, which performs channel selection and image rejection. The IF signal is then
digitized by two SAR ADCs before further signal processing in the digital domain.
10.2.2. Bluetooth Radio Transmitter
The OM6621Ex transmitter is a direct modulating architecture. The digital base-band

signals directly modulate VCO and divider of PLL, which is called two-point modulation.
After a 3-stage B-class power amplifier, the radio signal is output through antenna.
10.2.3. Frequency Synthesizer
The OM6621Ex Frequency synthesizer is fully integrated sigma delta fractional-N PLL to
lock the VCO to a reference crystal oscillator. The synthesizer uses several integrated
linear regulators for better isolation to the blocks respectively.
10.3. Bluetooth Baseband Unit
The BLE (Bluetooth Low Energy) core is a qualified Bluetooth 5.1 baseband controller
compatible with Bluetooth Smart specification and it is in charge of packet encoding/
decoding and frame scheduling.
• All device classes support (Broadcaster, Central, Observer, Peripheral)

• All packet types (Advertising / Data / Control)
• Encryption (AES / CCM)
• Bit stream processing (CRC, Whitening)
• Frequency Hopping calculation
• Low power modes supporting 32.768kHz
FILTER BT DEMOD DETECTOR
RF TIMING BT LINK
RADIO RECOVERY LAYER
FSK
MODULATION
Figure 10.2 OM6621Ex BT Baseband
10.4. Performance
10.4.1. BLE Receiver Performance
[Supply Voltage = 3.3V @ 25℃]

Parameter Min Typ Max Unit
Sensitivity, uncoded data at 1Ms/s -97 dBm
Sensitivity, uncoded data at 2Ms/s -94 dBm
Maximum received signal - -1.5 dBm
C/I co-channel Sensitivity, uncoded data at 1Ms/s - 3.5 dB
C/I co-channel Sensitivity, uncoded data at 2Ms/s 3.8 dB
F = F0+1MHz, uncoded data at 1Ms/s - - -28 dB
F = F0 -1MHz, uncoded data at 1Ms/s - - -16 dB
F = F0-2MHz, uncoded data at 1Ms/s
- - -30 dB
(Image)
Adjacent channel F = F0+3MHz, uncoded data at 1Ms/s - - -32 dB

selectivity C/I F = F0-3MHz, uncoded data at 1Ms/s - - -32 dB
Note: F = F0+2MHz, uncoded data at 2Ms/s - - -30 dB
F0=2440MHz F = F0 -2MHz, uncoded data at 2Ms/s - - -15 dB
F = F0-4MHz, uncoded data at 2Ms/s
- - -30 dB
(Image)
F = F0-6MHz, uncoded data at 2Ms/s - - -37 dB
Table 10.1 OM6621Ex BLE Receiver Architecture
Note: Spur channels may have extra degradation due to clock interference at 2416,
2432,
2448, 2464, 2480MHz.
10.4.2. BLE Transmitter Performance
[Supply Voltage = 3.3V @ 25℃]
Ma
Parameter Min Typ Unit
x
RF power control range -20 - 7 dBm
RF power range control resolution 1 dB
ACP F = F0±2MHz - - dBm
Note: F0=2440MHz F = F0±>3MHz - - dBm
∆f1avg maximum modulation
225 250 275 kHz
(uncoded data at 1Ms/s)
∆f1avg maximum modulation
450 500 550 kHz
(uncoded data at 2Ms/s)
∆f2max maximum modulation 100
(uncoded data at 1Ms/s) %
∆f2max maximum modulation 100
(uncoded data at 2Ms/s) %
∆f2avg/∆f1avg (uncoded data at 1Ms/s) 0.84
∆f2avg/∆f1avg (uncoded data at 2Ms/s)
Frequency Accuracy (uncoded data at 1Ms/s) 4.37 kHz
Frequency Accuracy (uncoded data at 2Ms/s) 3.74 kHz
Frequency Offset (uncoded data at 1Ms/s) -8.41 KHz
Frequency Offset (uncoded data at 2Ms/s) -7.2 KHz
Frequency Drift (uncoded data at 1Ms/s) -12.74 KHz
Frequency Drift (uncoded data at 2Ms/s) -10.2 KHz
KHz/50u
Frequency Drift rate (uncoded data at 1Ms/s) -9.73
s
KHz/50u
Frequency Drift rate (uncoded data at 2Ms/s) -7.83
s
Initial Frequency Drift (uncoded data at
-3.94 KHz
1Ms/s)
Initial Frequency Drift (uncoded data at
-6.23 KHz
2Ms/s)
2nd harmonic distortion -60 dBm
3rd harmonic distortion - -60 dBm
Table 10.2 OM6621Ex BLE Transceiver Architecture
11. Application Circuit
Figure 11.1 OM6621EM Circuit Diagram
Figure 11.2 OM6621ED Circuit Diagram
Figure 11.3 OM6621EG Circuit Diagram
12. Package Information
The OM6621EM has the QFN32 package, the information is as below:
Figure 12.1 OM6621EM QFN32 package
MILLMETER
SYMBOL
MIN NOM MAX
A 0.80 0.85 0.90
A1 0 0.02 0.05
b 0.15 0.20 0.25
c 0.18 0.20 0.25
D 3.90 4.00 4.10
D2 2.65 2.70 2.75
e 0.40BSC
Nd 2.80BSC
E 3.90 4.00 4.10
E2 2.65 2.70 2.75
Ne 2.80BSC
K 0.25Ref
L 0.35 0.40 0.45
h 0.40 0.45 0.50
R 0.08 0.10 0.15
aaa 0.10
bbb 0.10
ccc 0.05
Table 12.1 OM6621EM QFN32 package
The OM6621ED has the QFN24 package, the information is as below:
Figure 12.2 OM6621ED QFN24 package
SYMBOL MIN NOM MAX
TOTAL THICKNESS A 0.8 0.85 0.9
STAND OFF A1 0 0.02 0.05
MOLD THICKNESS A2 --- 0.65 ---
L/F THICKNESS A3 0.203 REF
LEAD WIDTH b 0.2 0.25 0.3
X D 4 BSC
BODY SIZE
Y E 4 BSC
LEAD PITCH e 0.5 BSC
X D2 2.6 2.7 2.8
EP SIZE
Y E2 2.6 2.7 2.8
LEAD LENGTH L 0.3 0.4 0.5
LEAD TIP TO EXPOSED PAD EDGE K 0.25 REF
PACKAGE EDGE TOLERANCE aaa 0.1
MOLD FLATNESS ccc 0.1
COPLANARITY eee 0.08
bbb 0.1
LEAD OFFSET
ddd 0.05
EXPOSED PAD OFFSET fff 0.1
Table 12.2 OM6621ED QFN24 package
The OM6621EG has the QFN48 package, the information is as below:
MILLMETER
SYMBOL
MIN NOM MAX
A 0.80 0.85 0.90
A1 0 0.02 0.05
b 0.15 0.20 0.25
c 0.18 0.20 0.23
D 5.90 6.00 6.10
D2 4.10 4.20 4.30
e 0.40BSC
Ne 4.40BSC
Nd 4.40BSC
E 5.90 6.00 6.10
E2 4.10 4.20 4.30
L 0.35 0.40 0.45
h 0.30 0.35 0.40
13. Ordering Information
OM6621Ex offers devices below for different application requirement.

Product MOQ MPQ
Part No. Type Package Size Packing Status
series (PCS) (PCS)
4*4mm
OM6621EM QFN-32 Tape/Reel 3000 3000 MP
0.4mm Pitch
4*4mm
OM6621Ex OM6621ED QFN-24 Tape/Reel 3000 3000 MP
0.5mm Pitch
6*6mm
OM6621EG QFN-48 Tape/Reel 3000 3000 CS
0.4mm Pitch
Table 13.1 OM6621Ex Ordering Information
14. Tape and Reel Information
14.1. Tape Orientation
General orientation of OM6621Ex package in the carrier tape.
Figure 14.1 OM6621Ex Tape Orientation
14.2. Tape and Reel Dimensions
Figure 14.2 OM6621EM/ED Tape and Reel Dimensions
Common Size:
Appearance Size / mm
E 1.75 ± 0.10
F 5.50 ± 0.05
P2 2.00 ± 0.10
D 1.55 ± 0.05
D1 1.500+ 0.25
P0 4.00 ± 0.10
10P0 40.00 ± 0.20
Table 14.1 OM6621EM/ED Common Size
Bag Size:
W 12.00 ± 0.30
P 8.00 ± 0.10
A0 4.30 ± 0.10
B0 4.30 ± 0.10
K0 1.10 ± 0.10
t 0.30 ± 0.05
Table 14.2 OM6621EM/ED Bag Size
Figure 14.3 OM6621EG Tape and Reel Dimensions
Common Size:
E 1.75 ± 0.10
F 7.50 ± 0.10
P2 2.00 ± 0.10
D 1.500+ 0.1
D1 1.50MIN
P0 4.00 ± 0.10
10P0 40.00 ± 0.20
Table 14.3 OM6621EG Common Size
Bag Size:
W 16.00 ± 0.30
P 12.00 ± 0.10
A0 6.30 ± 0.10
B0 6.30 ± 0.10
K0 1.40 ± 0.10
t 0.30 ± 0.05
Table 14.4 OM6621EG Bag Size
15. Glossary and Abbreviations
Name Description
ADC Analog to Digital Converter
AGC Automatic Gain Control
AON Always-on
APB Advanced Peripheral Bus
BB Base band
BLE Bluetooth Low Energy
BOD Brown-out Detector
IFS Inter Frame Spacing
LDO Low Dropout
LNA Low Noise Amplifier
LPD Low Power Domain
NVM Non-volatile memory
PLL Phase Locked Loop
PMU Power Management Unit
RNG RING Oscillator
SOC System-on-chip
TPMS Tire pressure monitor system
W1C Write 1 to clear
XO Crystal Oscillator
Typ Typical
SNR Signal to Noise Ratio
PA Power Amplifier
IRQ Interrupt Request
LSB Least Significant Bit
MSB Most Significant Bit
DFE Digital Front End
Table 15.1 Glossary and Abbreviations
16. Declaration of No Harmful Substances
This part is compliant with 2005/20/EC packaging directive, 1907/ 2006/ EC REACH
directive and the 2011/65/EU RoHS directive (Restrictions on the Use of Certain
Hazardous Substances in Electrical and Electronic Equipment), as amended by Directive
2015/863/EU.
This product also has the following attributes:
• Lead free
• Halogen Free (Chlorine, Bromine)
• SVHC Free
Sales and Service
Important Notice
The information provided herein by OnMicro is believed to be reliable; however, OnMicro
makes no warranties regarding the information and assumes no responsibility or liability
whatsoever for the use of the information. Customers should be aware that all information
contained herein is subject to change without notice. Unless explicitly specified, OnMicro
products are not warranted or authorized for use as critical components in medical, life-
saving, or life-sustaining applications, or other applications where a failure would cause
severe personal injury or death.

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OM6621Ex Bluetooth Low Energy Application

Table of Contents ................................................................................................................. 1

The OM6621Ex is a power-optimized true system-on-chip (SOC) solution for both

1.3. System Function Block Diagram

I-Cache RAM 4KB XTAL

QUAD-SPI I2S WATCHDOG

Figure 1.1 OM6621Ex block diagram

Figure 1.2 OM6621Ex applications

XTAL32M_P 4 OM6621EM 21 GPIO06/UART_RX

Figure 2.1 OM6621EM chip pin definition

XTAL32M_P 3 OM6621ED 16 GPIO05/UART_TX

Figure 2.2 OM6621ED chip pin definition

Figure 2.3 OM6621EG chip pin definition

2.4. Pin Description

Figure 3.1 Micro-controller Subsystem

3.1. MCU Debug

Serial Wire Debug (SWD) is used for debug.

3.2. Interrupts Vector

3.3. Electrical Specifications

3.3.1. Absolute Maximum Ratings

Parameter Min Typ Max Unit

3.3.2. Recommend Operating Conditions

Rating Min Typ Max Unit

3.3.3. ESD Characteristic

Parameter Condition Min Typ Max Unit

3.3.4. SFLASH Controller Characteristic

3.4. Module Address Mapping

Base Address Module

4.1. Memory Introduction

4.2. Memory Map

Figure 4.1 Memory Map

4.3. APB Address Space

5.1. Power Management

Figure 5.1 DC-DC Mode

Figure 5.2 LDO Mode

5.2. DC-DC Converter

Symbol Description Min Typ Max Unit

5.3. Digital LDO

5.5. Current Consumption

Symbol Description Min Typ Max Unit

5.5.2. CPU Running

Symbol Description Min Typ Max Unit

5.5.3. Radio Transmitting/Receiving

Symbol Description Min Typ Max Unit

Features of the OM6621E include:

6.1. Block Diagram

Figure 6.1 OM6621E block diagram

6.2. Function Description

6.2.1. Air Interface Data Rate

6.2.2. RF Channel Frequency

6.3.1. Packet Format

6.3.1.4. Packet Control Field (PCF)

6.3.1.6. CRC (Cyclic Redundancy Check)

7.2. Main Features

• Programmable free-running downcounter

7.3. Function Description

7.4. WDT Register Map

Offset Register Description

WDT_STATUS address offset: 0x0094

WDT_KR_CFG address offset: 0x00e8