Ram & Rom
Ram & Rom
Ram & Rom
It is known as temporary
memory
Eg: RAM (Random Access Memory )
Non - Volatile memory: This memory device does not require electric power to store the data. It is known
as Permanent memory
Eg: ROM (Read Only Memory )
• A Ram is a read/write random access memory it has both read and write capabilities
• Any storage location in ram can be accessed in any order to read or write. It is volatile memory. data are
lost if power is removed
• The above fig shows 32-bit RAM. It requires 5 address input lines , 8 data input and output lines and 2
control inputs (Read/write and chip select)
No of memory word is given RAM = 32
Word size = 8
Therefore, total no of bits: 32 x 8 =256 Bits
Working:
• Input is used to select required memory word for read write operation
• Chip select input is used to enable or disable the ram
̅̅̅̅)=0 chip is enabled , (𝐶𝑆
If (𝐶𝑆 ̅̅̅̅)=1 chip is disabled
• If R/W ̅ input is 1 read operation takes place. If R/W ̅ input is 0 write operation takes place.
• It is of 2 types:
1. Static Ram
2. Dynamic Ram
Problems:
A semiconductor memory chip is specified 2K x 8
1. How many bits can this bit store
2. How many address lines are required to access this chip
Above fig shows 32-bit ROM . It has 5 address input lines to select he required memory word, 8 data output
lines and 1control inputs ̅̅
𝐶𝑆̅̅ (chip select)
Working:
When ̅̅ ̅̅ (chip select) is 0 ,chip is enabled otherwise disable required memory word is selected by using 5
𝐶𝑆
address input lines read operations is performed
Types of ROM:
• Mask ROM
• Programmable ROM (PROM)
• Erasable Programmable ROM (EPROM)
• Electrically Erasable Programmable ROM (𝑬𝟐 PROM)
• Flash ROM
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Memory Expanding
Memory capacity can be expanded in two types namely:
1. Word size expansion
2. Memory word expansion
Working:
• Memory that can store 16 8- bit words and all we have ram chips that are arranged as 16 x 4 memories
with common I/O lines.
• We can combine 2 of these 16 x 4 chips to produce the desired memory the configuration is shown
above
• Each chip can store 16 (8-bit words) we are using each chip to store half word. In other words, Ram-1
stores the4 higher order bits of each of 16 word and Ram-2 stores 4 lower order bits .
• A full 8-Bit word is available at the Ram outputs connected to the data bus any of the 16 word is
selected by applying appropriate address code to the 4-line address line (A3,A2,A1,A0)
• To read R/W ̅ must be high and 𝐶𝑆 ̅̅̅̅ must be low. This causes Ram I/O lines to act as outputs .
• Ram-1 Places its selected 4- bit word on the upper 4 data bus lines . ram-2 places its selected 4-bit word
on the lower data bus lines .the data bus then contains 8-bit word.
• to write R/W ̅ must be low and ̅̅𝐶𝑆̅̅ must be low. This causes Ram I/O lines to act as inputs .
• the 8-bit word to be written is placed on the data bus by the CPU. The higher 4-bit is written into the
selected location of Ram-1 and lower 4-bit is written into the location of Ram-2.
Problem:
We want to combine several 2k x 8PROM to produce a total capacity of 8k x 8
1. How many PROM chips are needed.
2. How many address bus lines are required
2k x 8 PROMS
8k x 8
8 x 1024 = 8192
13
2 = 8192
Working:
• 16-byte data can be read or written into selected memory word from 2 chips
• 16- byte ram is expanded to 32-byte ram . for 32-byte ram 5 address lines are required for 16-byte ram 4
address lines are sufficient hence 4 address lines are made common to both memory chips
• 5th addressa4 is connected to chip select signal to Ram-1 and it is connected to Ram-2 through the
inverter
• R/W ̅ control input is made common to both chips with these connections two 16 byte Ram can be used
as 32 byte ram in which first 16 address outputs (00000 to 01111) to ram-1 is selected , for next 16
address inputs (10000 to 11111) Ram-2 is selected.
Implementation:
Working:
• A 16 x 4 Ram having 4 address lines and 4 data lines
• The expanded address is achieved by connecting the ̅̅ ̅̅ input to the 5th address bit as shown in above
𝐶𝑆
fig
• Input chip select is used as enable input common to both memories
• When the 5th address bit A4 is low, Ram-1 is selected and Ram-2 is disabled and the 5th lower order
address bit A0 to A3 access each of the address in Ram-1
• When the 5th address bit A4 is high, Ram-2 is enabled by low on the inverter output Ram-1 is disabled
and the 5th lower order address bit A0 to A3 access each of the ram to address
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