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EE2002 - Tutorial 1

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0% found this document useful (0 votes)
6 views

EE2002 - Tutorial 1

Uploaded by

227changpy
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Nanyang Technological University

School of Electrical and Electronic Engineering


EE2002 Analog Electronics

TUTORIAL 1
(With answers at the end)

1. Find an expression for vOUT as a function of vl and v2 in each of the op-amp


circuits of Fig.T1-1 and also determine the input resistance(s) with respect to
ground for each of the op-amp circuits. Assume op-amps used are ideal.

2. Consider an op-amp follower (i.e. the output is connected to the negative input)
powered by ±l5V supplies. The input voltage is set to 1V and the output feeds a
100 Ω resistive load RL to ground. With RL disconnected, the current IP from
VCC into the op-amp equals the current IN from the op-amp into VEE. The
op-amp used is assumed to be ideal. (Note: VCC is the positive supply voltage of
+15V and VEE is the negative supply voltage of -15V).

a) Draw a diagram of this circuit. Label the current IP and IN.


b) What is the difference between the power supply currents IP and IN when RL is
connected?
c) Find the additional power drawn from the power supplies when RL is
connected.

3. A high-gain op-amp circuit is formed by cascading two inverting amplifiers in


series. Both op-amps are connected to ±l5V power supplies. The first stage has
gain of 20. The cascade is to be designed so that the peak output voltage of the
second stage comes no closer than 1 V to either power supply voltage. If the input
is equal to a 25-mV peak sinusoid, what is the maximum permissible gain of the
second stage if its output is to remain within its allowed swing limits? Assume op-
amps used are ideal.

1
4. Find an expression for vOUT in the circuit shown in Fig Tl-2. Assume the op-amp
used is ideal.

Fig. T 1-2

5. An inverting amplifier with a gain of -10 is made from a non-ideal op-amp having
an input offset voltage of lmV. A sinusoidal input voltage of 0.1mV peak
amplitude is applied. What are the resulting ac and dc components of the output
voltage?

2
Partial Answers to Tutorial 1
1
(a) VOUT= 2v1 – v2
Rin1 = ∞
Rin2 = R
(b) VOUT= v1 +10 v2
Rin1 = 11R
Rin2 = 11R
(c) VOUT= -(10v1 +5 v2)
Rin1 = 10R
Rin2 = 20R
(d) VOUT= 10(v1 - v2)
Rin1 = 110R
Rin2 = 10R

2. (b) IP-IN = 10 mA
(c) The additional power drawn from VCC is
ÌP = 150 mW
No additional power is drawn from VEE , the negative supply.
3. The maximum permissible gain of the second stage is 28.

R5 + R4
4. v OUT = ( ) v IN
R4

2
5. v OUT = ∑ ( v OUT ) i = ( −1 sinωt + 11) mV
i =1

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