Module 5
Module 5
100003/CS500D
Microprocessors and Microcontrollers
Syllabus
● A microcontroller is available in
different word lengths like
microprocessors. 4 bit, 8 bit, 16 bit, 32
bit, 64 bit and 128 bit
microcontrollers are available today
Microcontroller vs Microprocessors
Microprocessors Microcontroller
Only have CPU in the chip. Have RAM, ROM and other peripherals along with
the CPU or processor.
Used in an application where the task is not predefined Designed for a specific task and once the program is
embed on MCU chip, it can’t be altered easily
Used where intensive processing is required like laptops, Used in many electronic appliances like washing
computers, mobiles etc. machine, microwave oven, timer, etc.
The microprocessors are run at higher clock speeds. High clock speed is not required.
Amount of memory required for the microprocessor is Amount of memory required is quite less compared
very large. to microprocessors.
• Instrumentation Applications
• Embedded devices
• RAM, ROM, I/O ports, one serial port and timers are all on-chip.
● B register or accumulator B is used along with the accumulator A for multiply and
divide operations.
● MUL A,B : multiplies 8 bit unsigned values in A and B and leaves the 16 bit result in
A (low byte) and B (high byte).
● DIV A,B : divides A by B, leaving the integer result in A and remainder in B.
● B register is bit-addressable.
Program Status Word (PSW)
Stack Pointer
● Stack pointer (SP) is an 8-bit register at address 81H.
● It contains the address of the data item currently on top of the stack.
● Stack operations include pushing data on the stack and popping data off the stack.
● Pushing increments SP before writing the data
● Popping from the stack reads the data and decrements the SP
● 8051 stack is kept in the internal RAM
● Depending on the initial value of the SP, stack can have different sizes
● Example: MOV SP,#5FH
● On 8051 this would limit the stack to 32 bytes since the uppermost address of on
chip RAM is 7FH.
PIN Description of 8051
• The 8051 is a 40 pin, Dual In
Line(DIP) package IC.
• Out of these 40 pins, 32 are
used for I/O. (Four 8-bit ports:
P0, P1, P2, and P4).
PSEN (Pin 29: Program Store For enabling the external program memory.
Enable) It will be connected to the external ROM memory chip.
This pin usually connects to an EPROM’s Output Enable
(OE) pin.
This is a logic low pin and during a fetch stage involving an
instruction stored in external memory, the pin will be pulsed
‘LOW’.
EA (Pin 31: External Access) If you need to connect to external ROM then this pin must
be tied LOW (0V).
This pin must be tied high (+5V) if the programs executes
from internal ROM
EA pin is for forcing the controller to use the external
program memory.
When it is connected to ground , controller will fetch data
from external memory.
PINs of 8051
Pin Description
I/O Ports The four ports P0, P1, P2, and P3.
Each port uses 8 pins.
All I/O pins are bi-directional.
Port 0 - P0 (pins 32-39) P0.0 (LSB) ~ P0.7 (MSB) - Also labelled as AD0 – AD7
Dual Purpose Port. Works as I/O or address lines
Lower order address lines / Data bus
Port 1 - P1 (pins 1-8) P1.0 (LSB) ~ P1.7 (MSB) – Dedicated I/O
For interfacing with external devices likes switches, LED
Port 2 – P2 (pins 21-28) P2.0 (LSB) ~ P2.7 (MSB) – Also labelled as A8 – A15
Dual Purpose Port. Works as I/O or address lines
Higher order address lines
Port 3 – P3 (pins 10-17) P3.0 (LSB) ~ P3.7(MSB)
Dual purpose, rarely used for I/O.
Used for functions related to special features of 8051
Reset Operation of 8051
● To reset the 8051, the RST pin must be held high for at least 2 machine cycles.
● This can be achieved upon power–up using an RC network.
● This is pin 9 of the IC and is used as the master reset for the 8051.
● In order for the 8051 to recognize that a reset has occurred, this pin must be brought
HIGH for at least two machine cycles.
● During normal operation, this pin must be at logic LOW.
8051 Memory Structure
● While most microprocessors implement a shared memory space for data and code
(programs), microcontrollers has limited memory and the program is usually stored in ROM.
● In the 8051, both code and data may be internal but they are stored in separate
memories,
namely the internal ROM and RAM.
● Expandable to a max of 64K code memory and 64K data memory using external memory.
● Internal Memory
○ Consists of on-chip ROM and on-chip data RAM.
○ On-chip RAM contains a rich arrangement of general purpose storage, bit addressable storage, register banks,
and special function registers.
○ In the 8051, the registers and input/output ports are memory mapped and accessible like any other memory location.
○ In the 8051, the stack resides within the internal RAM, rather than in external RAM.
8051 Memory Organization
8051 on chip Memory Allocation
RAM Memory Allocation
Stack in 8051
●The register used to access the stack
is called SP (stack pointer) register.
● These 32 bytes are divided into 4 banks of registers in which each bank has 8
registers, RO – R7.
● RAM locations from 0 to 7 are set aside for bank 0 of R0 – R7 where R0 is RAM
location 00H, R1 is RAM location 01H, R2 is location 02H, and so on, until memory
location 07H, which belongs to R7 of bank 0.
● The second bank of registers R0 – R7 starts at RAM location 08H and goes to location
0FH.
● The third bank of R0 – R7 starts at memory location 10H and goes to location 17H.
● Finally, RAM locations 18H to 1FH are set aside for the fourth bank of R0 – R7.
Register Banks in 8051 and their RAM Address
Special Function Registers in 8051
● 8051 has 21 special function registers (SFRs) at the top of internal RAM from address 80H
to FFH.
● Most of the addresses from 80H to FFH are not defined, except for 21 of them.
● Some SFR’s are both bit-addressable and byte addressable, depending on the instruction
accessing the register.
● All 8051 CPU registers, I/O ports, timers and other architecture components are
accessible in 8051 through SFRs
Special Function Registers in 8051
Name Function Name Function
A Accumulator Register SCON Serial Port Control
B Arithmetic
SBUF Serial Port data buffer
DPH Data Pointer High
SP Stack Pointer
DPL Data Pointer Low
IE Interrupt Enable TMOD Timer/Counter mode control
IP Interrupt Priority
TCON Timer/Counter control
P0 I/O Port Latch
TL0 Timer0 lower byte
P1 I/O Port Latch
P2 I/O Port Latch TH0 Timer0 higher byte
P3 I/O Port Latch
TL1 Timer1 lower byte
PCON Power Control
TH1 Timer1 higher byte
PSW Program Status Word
Interrupts of 8051
● The 8051 microcontroller can recognize five different events that cause the main
program to
interrupt from the normal execution.
● When an interrupt occurs, the microcontroller executes the interrupt service routine
so that
memory location corresponds to the interrupt that enables it.
● The Interrupt corresponding to the memory location is given in the interrupt vector
table.
Interrupt Vector Table of 8051
● Reset:
○ When the reset pin is activated, the 8051 jumps to address location 0000.
○ Two interrupts are set aside for the timers: one for Timer 0 and one for Timer 1.
○ Memory locations 000BH and 001BH in the interrupt vector table belong to Timer 0
and Timer 1, respectively.
● External hardware interrupts:
○ Two interrupts are set aside for hardware external hardware interrupts.
○ Pin numbers 12 (P3.2) and 13 (P3.3) in port 3 are for the external hardware interrupts INT0 and
INT1, respectively.
○ These external interrupts are also referred to as EX1 and EX2. Memory locations 0003H and
0013H in the interrupt vector table are assigned to INT0 and INT1, respectively.
○ Serial communication has a single interrupt that belongs to both receive and transmit.
● Since the 8051 has an 8-bit architecture, each 16-bit is accessed as two separate registers of
low byte and high byte.
● Timer0 Register:
○ 16 bit register and accessed as low byte and high byte.
○ The low byte is referred as a TL0 and the high byte is referred as TH0.
○ These registers can be accessed like any other registers.
● Timer1 Register:
○ 16 bit register
○ Split into two bytes, referred to as TL1 and TH1.
● TMOD (timer mode) Register:
○ This is an 8-bit register which is used by both timers 0 and 1 to set the various
timer modes.
○ In this TMOD register, lower 4 bits are set aside for timer0 and the upper 4 bits are
set aside for timer1.
○ In each case, the lower 2 bits are used to set the timer mode and upper 2 bits to
specify the operation.
● In upper or lower 4 bits, first bit is a GATE bit.
● Some timers do this by software, some by hardware, and some have both software and
hardware controls.
● The hardware way of starting and stopping the timer by an external source is achieved by
making GATE=1 in the TMOD register.
● When GATE=0, no external hardware is needed to start and stop the timers.
● The second bit is C/T bit and is used to decide whether a timer is used as a time delay
generator or an event counter.
● Mode 1- It is a 16-bit timer; therefore it allows values from 0000 to FFFFH to be loaded
into the timer’s registers TL and TH. After TH and TL are loaded with a 16-bit initial value,
the timer must be started.
● Mode0- Mode 0 is exactly same like mode 1 except that it is a 13-bit timer instead of 16-bit.
● Mode 2- It is an 8 bit timer that allows only values of 00 to FFH to be loaded into the
timer’s register TH. After TH is loaded with 8 bit value, the 8051 gives a copy of it to TL.
● Mode3- Mode 3 is also known as a split timer mode. It is different for Timer0 and Timer1.
When the Timer0 is working in mode 3, the TL0 will be used as an 8-bit timer/counter. It
will be controlled by the standard Timer0 control bits. The TH0 is used as an 8-bit timer
but not the counter. This is controlled by Timer1 Control bits. Timer1 is off.
8051 Serial Control Register (SCON)
● The Serial Control or SCON SFR is used to control the 8051 Microcontroller’s Serial Port.
● Using SCON, you can control the Operation Modes of the Serial Port, Baud Rate of the
Serial Port and Send or Receive Data using Serial Port.
● SCON Register also consists of bits that are automatically SET when a byte of data is
transmitted or received.
8051 Serial Data Buffer (SBUF)
● The Serial Buffer or SBUF register is used to hold the serial data while transmission or
reception.
● Register addressing
● Direct addressing
● Indirect addressing
8051 Addressing ● Immediate constant addressing
● Note: Abbreviated SFR names are defined in the “C8051F020.inc” header file
● Examples:
● MOV A, 020H Transfer the contents of RAM location 20H to the accumulator
Indirect Addressing Mode
● This mode uses a pointer to hold the effective address of the operand
● Only registers R0, R1 and DPTR can be used as the pointer registers
● The R0 and R1 registers can hold an 8-bit address, whereas DPTR can hold a 16-bit
address
● Examples:
● MOV @R0,A Store the content of accumulator into the memory location
pointed to by register R0. R0 could have an 8-bit address, such as 60H.
● MOVX A,@DPTR Transfer the contents from the memory location pointed to by
DPTR into the accumulator. DPTR could have a 16-bit address, such as 1234H.
Immediate Constant Addressing Mode
● This mode of addressing uses either an 8- or 16-bit constant value as the source
operand
● The destination register should hold the same data size which is specified by the
source operand
● Examples:
● ADD A, #030H Add 8-bit value of 30H to the 8 bit accumulator register.
● MOV DPTR, #0FE00H Move 16-bit data constant FE00H into the 16-bit Data Pointer
Register.
Relative Addressing Mode
● This mode of addressing is used with some type of jump instructions, like SJMP
(short jump) and conditional jumps like JNZ
● The destination address must be within -128 and +127 bytes from the current
instruction address because an 8-bit offset is used (28 = 256)
● Example:
● These are 2-byte instructions where the 11-bit absolute address is specified as the
operand
● The lower 11 bits are loaded from this instruction. So, the branch address must be
within the current 2K byte page of program memory (211 = 2048)
● Example:
● ACALL PORT_INIT PORT_INIT should be located within 2k bytes.
● PORT_INIT: MOV P0, #0FH PORT_INIT subroutine
Long Addressing Mode
● This mode of addressing is used with the LCALL and LJMP instructions
● It is a 3-byte instruction and the last 2 bytes specify a 16-bit destination location
where the program branches
● The program will always branch to the same location no matter where the program
was previously
● A 16-bit register (data pointer) holds the base address and the accumulator holds
an 8-bit displacement or index value
● The sum of these two registers forms the effective address for a JMP or MOVC
instruction
Indexed Addressing Mode
● Example:
● After the execution of the above instructions, the program will branch to address
1F08H (1F00H+08H) and transfer into the accumulator the data byte retrieved from
that location (from the look-up table)
● Divided into 5 functional
groups: