LM 5146
LM 5146
LM 5146
LM5146 100-V Synchronous Buck DC/DC Controller With Wide Duty Cycle Range
1 Features 2 Applications
• Functional Safety-Capable • Wireless infrastructure, cloud computing
– Documentation available to aid functional safety • Industrial motor drives, test and measurement
system design • Personal transport vehicle: electric bike
• Versatile synchronous buck DC/DC controller • Asset tracking and fleet management systems
– Wide input voltage range of 5.5 V to 100 V • Non-isolated PoE, IP cameras
– 150°C maximum junction temperature • Inverting buck-boost regulators
– 0.8-V reference with ±1% feedback accuracy 3 Description
– Adjustable output voltage from 0.8 V to 60 V
– 40-ns tON(min) for high VIN / VOUT ratio The LM5146 100-V synchronous buck controller
– 140-ns tOFF(min) for low dropout regulates from a high input voltage source or from an
– Lossless RDS(on) or shunt current sensing input rail subject to high-voltage transients, minimizing
– Optimized for CISPR 11 and CISPR 32 Class B the need for external surge suppression components.
EMI requirements A high-side switch minimum on-time of 40 ns gives
• Switching frequency from 100 kHz to 1 MHz large step-down ratios, enabling the direct step-down
– SYNC in and SYNC out capability conversion from a 48-V nominal input to low-voltage
– Selectable diode emulation or FPWM rails for reduced system complexity and solution cost.
• 7.5-V gate drivers for standard VTH MOSFETs The LM5146 continues to operate during input voltage
dips as low as 5.5 V, at nearly 100% duty cycle
– 14-ns adaptive dead-time control
if needed, making it an excellent choice for high-
– 2.3-A source and 3.5-A sink capability
performance industrial controls, robotics, datacom,
• Fast line and load transient response
and RF applications.
– Voltage-mode control with line feedforward
– High gain-bandwidth error amplifier Forced-PWM (FPWM) operation eliminates switching
• Inherent protection features for robust design frequency variation to minimize EMI, while
– Adjustable output voltage soft start user-selectable diode emulation lowers current
– Hiccup-mode overcurrent protection consumption at light-load conditions. The adjustable
– Input UVLO with hysteresis switching frequency as high as 1 MHz can be
– VCC and gate-drive UVLO protection synchronized to an external clock source to eliminate
– Precision enable input and open-drain PGOOD beat frequencies in noise-sensitive applications.
indicator for sequencing and control Device Information
– Thermal shutdown protection with hysteresis PART NUMBER PACKAGE(1) BODY SIZE (NOM)
• 20-pin VQFN package with wettable flanks
LM5146 VQFN (20) 4.50 mm × 3.50 mm
• Create a custom design using the LM5146 with
WEBENCH® Power Designer (1) For all available packages, see the orderable addendum at
the end of the data sheet.
VIN EN VIN
VOUT
VIN EN/UVLO Q1
SYNC In SYNCIN HO
PG RILIM
Typical Application Circuit and Efficiency Performance, VOUT = 12 V, FSW = 400 kHz
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5146
SNVSBV0A – JUNE 2021 – REVISED JUNE 2021 www.ti.com
Table of Contents
1 Features............................................................................1 8.4 Device Functional Modes..........................................25
2 Applications .................................................................... 1 9 Application and Implementation.................................. 27
3 Description.......................................................................1 9.1 Application Information............................................. 27
4 Revision History.............................................................. 2 9.2 Typical Applications.................................................. 36
5 Description (continued).................................................. 3 10 Power Supply Recommendations..............................46
6 Pin Configuration and Functions...................................4 11 Layout........................................................................... 47
6.1 Wettable Flanks.......................................................... 5 11.1 Layout Guidelines................................................... 47
7 Specifications.................................................................. 6 11.2 Layout Example...................................................... 50
7.1 Absolute Maximum Ratings ....................................... 6 12 Device and Documentation Support..........................51
7.2 ESD Ratings .............................................................. 6 12.1 Device Support....................................................... 51
7.3 Recommended Operating Conditions ........................7 12.2 Documentation Support.......................................... 52
7.4 Thermal Information ...................................................7 12.3 Receiving Notification of Documentation Updates..52
7.5 Electrical Characteristics ............................................8 12.4 Support Resources................................................. 52
7.6 Switching Characteristics .........................................10 12.5 Trademarks............................................................. 53
7.7 Typical Characteristics.............................................. 11 12.6 Electrostatic Discharge Caution..............................53
8 Detailed Description......................................................16 12.7 Glossary..................................................................53
8.1 Overview................................................................... 16 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram......................................... 16 Information.................................................................... 54
8.3 Feature Description...................................................17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (June 2021) to Revision A (June 2021) Page
• Updated functional safety link.............................................................................................................................1
5 Description (continued)
The LM5146 voltage-mode controller with line feedforward drives external high-side and low-side N-channel
power switches with robust 7.5-V gate drivers suitable for standard-threshold MOSFETs. Adaptively-timed gate
drivers with 2.3-A source and 3.5-A sink capability minimize body diode conduction during switching transitions,
reducing switching losses and improving thermal performance when driving MOSFETs at high input voltage and
high frequency. The LM5146 can be powered from the output of the switching regulator or another available
source, further improving efficiency.
A 180° out-of-phase clock output relative to the internal oscillator at SYNCOUT works well for cascaded or
multi-channel power supplies to reduce input capacitor ripple current and EMI filter size. Additional features of
the LM5146 include a configurable soft start, an open-drain power-good monitor for fault reporting and output
monitoring, monotonic start-up into prebiased loads, integrated VCC bias supply regulator and bootstrap diode,
external power supply tracking, precision enable input with hysteresis for adjustable line undervoltage lockout
(UVLO), hiccup-mode overload protection, and thermal shutdown protection with automatic recovery.
The LM5146 controller is offered in a 4.5-mm × 3.5-mm thermally enhanced, 20-pin VQFN package with
additional spacing for high-voltage pins and wettable flanks for optical inspection of solder joint fillets.
EN/UVLO
VIN
20
1
RT 2 19 SW
SS/TRK 3 18 HO
COMP 4 17 BST
FB 5 Exposed 16 NC
Pad
(EP)
AGND 6 15 EP
SYNCOUT 7 14 VCC
SYNCIN 8 13 LO
NC 9 12 PGND
10
11
PGOOD
ILIM
Figure 6-1. 20-Pin VQFN With Wettable Flanks in RGY Package (Top View)
7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature of –40℃ to +150℃ (unless otherwise noted).(1)
MIN MAX UNIT
VIN –0.3 100
SW –1 100
SW (20-ns transient) –5 100
ILIM –1 100
Input voltage V
EN/UVLO –0.3 100
VCC –0.3 14
FB, COMP, SS/TRK, RT –0.3 6
SYNCIN –0.3 14
BST –0.3 110
BST to VCC 100
BST to SW –0.3 14
Output voltage V
VCC to BST (20-ns transient) 7
LO (20-ns transient) –3
PGOOD –0.3 14
Operating junction temperature, TJ 150 °C
Storage temperture, Tstg –55 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) Recommended Operation Conditions are conditions under which the device is intended to be functional. For specifications and test
conditions, see Electrical Characteristics.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature
range unless otherwise stated. VVIN = 48 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated. (1) (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IPG-OH PGOOD high state leakage current VFB = 0.8 V, VPGOOD = 13 V 400 nA
OSCILLATOR
FSW1 Oscilator frequency – 1 RRT = 100 kΩ 100 kHz
FSW2 Oscillator frequency – 2 RRT = 25 kΩ 380 400 420 kHz
FSW3 Oscillator frequency – 3 RRT = 12.5 kΩ 780 kHz
SYNCHRONIZATION INPUT AND OUTPUT
FSYNC SYNCIN external clock frequency range % of nominal frequency set by RRT –20% 50%
VSYNC-IH SYNCIN input logic high 2 V
VSYNC-IL SYNCIN input logic low 0.8 V
RSYNC-IN SYNCIN input resistance VSYNCIN = 3 V 20 kΩ
Minimum high state or low state
TSYNCI-PW SYNCIN input minimum pulsewidth 50 ns
duration
VSYNCO-OH SYNCOUT high-state output voltage ISYNCOUT = –1 mA (sourcing current) 3 V
VSYNCO-OL SYNCOUT low-state output voltage ISYNCOUT = 1 mA (sinking current) 0.4 V
Delay from HO rising to SYNCOUT VSYNCIN = 0 V, TS = 1/FSW, FSW set by TS/2 –
TSYNCOUT ns
leading edge RRT 140
Delay from SYNCIN rising to HO
TSYNCIN 50% to 50% 150 ns
leading edge
GATE DRIVERS
RHO-UP HO high state resistance, HO to BST VBST – VSW = 7 V, IHO = –100 mA 1.5 Ω
RHO-DOWN HO low state resistance, HO to SW VBST – VSW = 7 V, IHO = 100 mA 0.9 Ω
RLO-UP LO high state resistance, LO to VCC VBST – VSW = 7 V, ILO = –100 mA 1.5 Ω
RLO-DOWN LO low state resistance, LO to PGND VBST – VSW = 7 V, ILO = 100 mA 0.9 Ω
VBST – VSW = 7 V, HO = SW, LO =
IHOH, ILOH HO, LO source current 2.3 A
AGND
IHOL, ILOL HO, LO sink current VBST – VSW = 7 V, HO = BST, LO = VCC 3.5 A
BOOTSTRAP DIODE AND UNDERVOLTAGE THRESHOLD
VBST-FWD Diode forward voltage, VCC to BST VCC to BST, BST pin sourcing 20 mA 0.75 0.9 V
BST to SW quiescent current, not
IQ-BST VSS/TRK = 0 V, VSW = 48 V, VBST = 54 V 80 µA
switching
VBST-UV BST to SW undervoltage detection VBST – VSW falling 3.4 V
VBST-HYS BST to SW undervoltage hysteresis VBST – VSW rising 0.42 V
PWM CONTROL
tON(min) Minimum controllable on-time VBST – VSW = 7 V, HO 50% to 50% 40 60 ns
tOFF(min) Minimum off-time VBST – VSW = 7 V, HO 50% to 50% 140 200 ns
DC100kHz FSW = 100 kHz, 6 V ≤ VVIN ≤ 60 V 98 99 %
Maximum duty cycle
DC400kHz FSW = 400 kHz, 6 V ≤ VVIN ≤ 60 V 90 94 %
RAMP valley voltage (COMP at 0% duty
VRAMP(min) 300 mV
cycle)
kFF PWM feedforward gain (VIN / VRAMP) 6 V ≤ VVIN ≤ 100 V 15 V/V
OVER CURRENT PROTECT (OCP) – VALLEY CURRENT LIMITING
IRS ILIM source current, RSENSE mode Low voltage detected at ILIM 90 100 110 µA
IRDSON ILIM source current, RDS-ON mode SW voltage detected at ILIM, TJ = 25°C 180 200 220 µA
IRDSONTC ILIM current tempco RDS-ON mode 4500 ppm/°C
IRSTC ILIM current tempco RSENSE mode 0 ppm/°C
VILIM-TH ILIM comparator threshold at ILIM –8 –2 3.5 mV
SHORT CIRCUIT PROTECTION (SCP) – DUTY CYCLE CLAMP
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 150°C junction temperature
range unless otherwise stated. VVIN = 48 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated. (1) (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Clamp offset voltage – no current 0.2 +
VCLAMP-OS COMP to duty cycle clamp voltage V
limiting VVIN/75
Clamp voltage with continuous current 0.3 +
VCLAMP-MIN Minimum clamp voltage V
limit VVIN/150
HICCUP MODE FAULT PROTECTION
Clock cycles with current limiting before
CHICC-DEL Hiccup mode activation delay 128 cycles
off-time activated
Clock cycles with no switching followed
CHICCUP Hiccup mode off time after activation 8192 cycles
by SS/TRK release
DIODE EMULATION / DCM OPERATION
ZCD threshold measured at SW pin 50
VZCD-SS Zero-cross detect (ZCD) soft-start ramp 0 mV
cycles after first HO pulse
ZCD threshold measured at SW pin
VZCD-DIS Zero-cross detect disable threshold 200 mV
1000 cycles after first HO pulse
VDEM-TH Diode emulation zero-cross threshold Measured at SW with VSW rising –5 0 5 mV
THERMAL SHUTDOWN
TSD Thermal shutdown threshold TJ rising 175 °C
TSD-HYS Thermal shutdown hysteresis 20 °C
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and
applied statistical process control.
(2) The junction temperature (TJ in ℃) is calculated from the ambient temperature (TA in ℃) and power dissipation (PD in Watts) as
follows: TJ = TA + (PD × RΘJA) where RΘJA (in ℃/W) is the package thermal impedance provided in Section 7.4.
100 100
95
95
90
90
Efficiency (%)
Efficiency (%)
85
80 85
Figure 7-1. Efficiency vs Load, CCM Figure 7-2. Efficiency vs Load, CCM
0.808 160
0.806 140
Min On-Time, Min Off-Time (ns)
0.804 120
Feedback Voltage (V)
0.802 100
0.8 80
0.798 60
0.796 40
0.794 20
tOFF(min) tON(min)
0.792 0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)
Figure 7-3. FB Voltage vs Junction Temperature Figure 7-4. tON(min) and tOFF(min) vs Junction
Temperature
40 2.2
40°C 25°C 125°C 150°C
VIN Shutdown Quiescent Current ( PA)
30 2
20 1.8
10 1.6
Figure 7-5. IQ-SHD vs Input Voltage Figure 7-6. IQ-STANDBY vs Input Voltage
2.2 4
Switching (mA)
VIN Operating Quiescent Current (mA)
3.75
2
3.5
3
1.6
2.75
Figure 7-7. IQ-OPERATING (Nonswitching) vs Input Figure 7-8. IQ-OPERATING (Switching) vs Input
Voltage Voltage
0.6 350
VIN Operating Quiescent Current (mA)
0.5 300
0.3 200
0.2 150
100
0.1
VCC = 8V 50
0 RDS-ON Mode
0 20 40 60 80 100 RSENSE Mode
Input Voltage (V) 0
-50 -25 0 25 50 75 100 125 150
VSW = 0 V VVCC = VBST = VILIM VFB = 0 V Junction Temperature (°C)
Figure 7-9. VIN Quiescent Current with External Figure 7-10. ILIM Current Source vs Junction
VCC Applied Temperature
25 5.2
20 5
VCC UVLO Threshold (V)
Deadtime (ns)
15 4.8
10 4.6
5 4.4
HO to LO Rising
LO to HO Falling
0 4.2
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)
VSW = 0 V Figure 7-12. VCC UVLO Thresholds vs Junction
Figure 7-11. Deadtime vs Junction Temperature Temperature
4 98
3.6 94
3.4 92
3.2 90
Rising Rising
Falling Falling
3 88
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)
Figure 7-13. BST UVLO Thresholds vs Junction Figure 7-14. PGOOD UVP Thresholds vs Junction
Temperature Temperature
110 1.3
PGOOD OVP Thresholds (V)
108 1.25
104 1.15
102 1.1
Rising
Falling
100 1.05
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)
Figure 7-15. PGOOD OVP Thresholds vs Junction Figure 7-16. EN/UVLO Threshold vs Junction
Temperature Temperature
0.5 1000
0.45 800
Switching Frequency (kHz)
EN Standby Threshold (V)
0.4 600
0.35 400
0.3 200
Rising
Falling
0.25 0
-50 -25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80 90 100
Junction Temperature (°C) RT Resistance (k:)
VSW = 0 V
420 1000
990
410
980
400
970
390
960 VIN = 6V
VIN = 6V
VIN = 48V VIN = 48V
VIN = 100V VIN = 100V
380 950
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (°C) Junction Temperature (°C)
RRT = 25 kΩ RRT = 10 kΩ
Figure 7-19. Oscillator Frequency vs Junction Figure 7-20. Oscillator Frequency vs Junction
Temperature Temperature
4 1.6
LO, HO Gate Driver Peak Current (A)
3.5
1.4
HO Gate Driver RDS(on) (:)
3
1.2
2.5
1
2
0.8
1.5
Source High State
Sink Low State
1 0.6
6 7 8 9 10 11 12 13 6 7 8 9 10 11 12 13
VCC Voltage (V) VCC Voltage (V)
Figure 7-21. Gate Driver Peak Current vs VCC Figure 7-22. HO Driver Resistance vs VCC Voltage
Voltage
1.6 8
7.5
1.4
LO Gate Driver RDS(on) (:)
7
1.2
6.5
1
6
0.8
5.5
High State
Low State 40°C 25°C 150°C
0.6 5
6 7 8 9 10 11 12 13 0 20 40 60 80 100
VCC Voltage (V) Input Voltage (V)
VSS/TRK = 0 V
Figure 7-23. LO Driver Resistance vs VCC Voltage Figure 7-24. VCC Voltage vs Input Voltage
7 8
40°C 25°C 125°C 150°C
6 7
6
5
VCC Voltage (V)
1 1
40°C 25°C 150°C
0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60
VCC Current (mA) VCC Current (mA)
VIN = 5.5 V VIN = 12 V
Figure 7-25. VCC vs ICC Characteristic Figure 7-26. VCC vs ICC Characteristic
1 10.6
BST Diode Forward Voltage (V)
10.4
0.9
10
0.7
9.8
0.6
9.6
VCC = 8V
0.5 9.4
0 10 20 30 40 50 -50 -25 0 25 50 75 100 125 150
BST Diode Forward Current (mA) Junction Temperature (°C)
Figure 7-27. BST Diode Forward Voltage vs Current Figure 7-28. SS/TRK Current Source vs Junction
Temperature
8 Detailed Description
8.1 Overview
The LM5146 is a 100-V synchronous buck controller with all of the functions necessary to implement a high-
efficiency step-down power supply. The output voltage range is from 0.8 V to 60 V. The voltage-mode control
architecture uses input feedforward for excellent line transient response over a wide VIN range. Voltage-mode
control supports the wide duty cycle range for high input voltage and low dropout applications as well as when
a high-voltage conversion ratio (for example, 10-to-1) is required. Current sensing for cycle-by-cycle current limit
can be implemented with either the low-side FET RDS(on) or a current sense resistor. The operating frequency
is programmable from 100 kHz to 1 MHz. The LM5146 drives external high-side and low-side NMOS power
switches with robust 7.5-V gate drivers suitable for standard threshold MOSFETs. Adaptive dead-time control
between the high-side and low-side drivers minimizes body diode conduction during switching transitions. An
external bias supply can be connected to the VCC pin to improve efficiency in high-voltage applications. A
user-selectable diode emulation feature enables DCM operation for improved efficiency and lower dissipation at
light-load conditions.
8.2 Functional Block Diagram
VIN VCC
7.5 V LDO +
REGULATOR VCC
± 7.5 V
UVLO
VCC ENABLE ± BST
SHUTDOWN
+ VVCC-UV
0.4 V +
EN/UVLO ± ENABLE
LOGIC BST_UV
1.2 V
±
+ 5 µs STANDBY ³1´ D R
± FILTER +
VSW +
VBST-UV
CL Q
kFF*VIN THERMAL
HYSTERESIS
SHUTDOWN
COMP ±
PGND
ERROR
AMP
FB ±
115 mV
± +
0.8 V +
+
+
±
+ ZERO CROSS
± DETECTION
CLAMP
SS/TRK
COMP
CLAMP
STANDBY MODULATOR
HICCUP
CLK
COUNTERS
SUPERVISORY RDS(on) or ILIM
COMPARATORS ± 0.8 V + 8% Shunt Sensing LO
PGOOD +
25 µs FB LO
OCP ± ILIM
delay
±
+ AGND
+ 0.8 V - 8% CURRENT LIMIT
COMPARATOR
5 FB NC 16 VOUT
CC2
LM5146 Q2
6 AGND EP 15
RFB2 SYNC
out 7 SYNCOUT CIN COUT
VCC 14
8 SYNCIN LO 13
SYNC
9 NC
ILIM
PGND 12 GND
PGOOD
oponal 10 11
CVCC
RPG
PG RILIM
CILIM
Figure 8-1. Schematic Diagram for VIN Operating Range of 5.5 V to 100 V
In high-voltage applications, take extra care to ensure the VIN pin does not exceed the absolute maximum
voltage rating of 100 V during line or load transient events. Voltage ringing on the VIN pin that exceeds the
values in the Absolute Maximum Ratings can damage the IC. Use high-quality ceramic input capacitors to
minimize ringing. An RC filter from the input rail to the VIN pin (for example, 4.7 Ω and 0.1 µF) provides
supplementary filtering at the VIN pin.
8.3.2 Output Voltage Setpoint and Accuracy (FB)
The reference voltage at the FB pin is set at 0.8 V with a feedback system accuracy over the full junction
temperature range of ±1%. Junction temperature range for the device is –40°C to +150°C. While dependent
on switching frequency and load current requirements, the LM5146 is generally capable of providing an output
voltage in the range of 0.8 V to a maximum of 60 V or slightly less than VIN, whichever is lower. The DC output
voltage setpoint during normal operation is set by the feedback resistor network, RFB1 and RFB2, connected to
the output.
8.3.3 High-Voltage Bias Supply Regulator (VCC)
The LM5146 contains an internal high-voltage VCC regulator that provides a bias supply for the PWM controller
and its gate drivers for the external MOSFETs. The input pin (VIN) can be connected directly to an input voltage
source up to 100 V. The output of the VCC regulator is set to 7.5 V. However, when the input voltage is below
the VCC setpoint level, the VCC output tracks VIN with a small voltage drop. Connect a ceramic decoupling
capacitor between 1 µF and 5 µF from VCC to AGND for stability.
The VCC regulator output has a current limit of 40 mA (minimum). At power up, the regulator sources current
into the capacitor connected to the VCC pin. When the VCC voltage exceeds its rising UVLO threshold of 4.93
V, the output is enabled (if EN/UVLO is above 1.2 V), and the soft-start sequence begins. The output remains
active until the VCC voltage falls below its falling UVLO threshold of 4.67 V (typical) or if EN/UVLO goes to a
standby or shutdown state.
Internal power dissipation of the VCC regulator can be minimized by connecting the output voltage or an
auxiliary bias supply rail (up to 13 V) to VCC using a diode DVCC as shown in Figure 8-2. A diode in series with
the input prevents reverse current flow from VCC to VIN if the input voltage falls below the external VCC rail.
LM5146
Required if VIN < VCC(EXT)
DVIN DVCC
VIN 20 VIN VCC 14 VCC-EXT
5.5 V to 100 V 8 V to 13 V
CVIN CVCC
0.1 PF 2.2 PF
AGND
6
Figure 8-2. VCC Bias Supply Connection From VOUT or Auxiliary Supply
Note that a finite bias supply regulator dropout voltage exists and is manifested to a larger extent when driving
high gate charge (QG) power MOSFETs at elevated switching frequencies. For example, at VVIN = 6 V, the VCC
voltage is 5.8 V with a DC operating current, IVCC, of 20 mA. Such a low gate drive voltage can be insufficient
to fully enhance the power MOSFETs. At the very least, MOSFET on-state resistance, RDS(ON), can increase at
such low gate drive voltage.
Here are the main considerations when operating at input voltages below 7.5 V:
• Increased MOSFET RDS(on) at lower VGS, leading to Increased conduction losses and reduced OCP setpoint
• Increased switching losses given the slower switching times when operating at lower gate voltages
• Restricted range of suitable power MOSFETs to choose from (MOSFETs with RDS(on) rated at VGS = 4.5 V
become mandatory)
8.3.4 Precision Enable (EN/UVLO)
The EN/UVLO input supports adjustable input undervoltage lockout (UVLO) with hysteresis programmed by
the resistor values for application specific power-up and power-down requirements. EN/UVLO connects to a
comparator-based input referenced to a 1.2-V bandgap voltage. An external logic signal can be used to drive the
EN/UVLO input to toggle the output ON and OFF and for system sequencing or protection. The simplest way
to enable the operation of the LM5146 is to connect EN/UVLO directly to VIN. This allows self start-up of the
LM5146 when VCC is within its valid operating range. However, many applications benefit from using a resistor
divider RUV1 and RUV2 as shown in Figure 8-3 to establish a precision UVLO level.
Use Equation 1 and Equation 2 to calculate the UVLO resistors given the required input turn-on and turn-off
voltages.
VIN(on) VIN(off)
RUV1
IHYS (1)
VEN
RUV2 RUV1 ˜
VIN(on) VEN (2)
LM5146 vcc
VIN
10 A
RUV1
EN/UVLO
1
RUV2
Remote 1.2 V Enable
shutdown comparator
The LM5146 enters a low IQ shutdown mode when EN/UVLO is pulled below approximately 0.4 V. The internal
LDO regulator powers off and the internal bias supply rail collapses, shutting down the bias currents of the
LM5146. The LM5146 operates in standby mode when the EN/UVLO voltage is between the hard shutdown and
precision enable (standby) thresholds.
8.3.5 Power Good Monitor (PGOOD)
The LM5146 provides a PGOOD flag pin to indicate when the output voltage is within a regulation window. Use
the PGOOD signal as shown in Figure 8-4 for start-up sequencing of downstream converters, fault protection,
and output monitoring. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater
than 13 V. The typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to
decrease the voltage from a higher voltage pullup rail.
VIN(on) = 15 V
VIN(off) = 10 V
VOUT(MASTER) = 5 V VOUT(SLAVE) = 3.3 V
LM5146 LM5146
RUV1
499 k PGOOD 10 PGOOD 10
RFB1 RPG RFB3
1 EN/UVLO 20 k 20 k 1 EN/UVLO 20 k
RUV2 FB FB 5
5 0.8 V 0.8 V
43.2 k
RFB2 RFB4
3.83 k 6.34 k
Regulator #1 Regulator #2
Start-up based on Sequential start-up
input voltage UVLO based on PGOOD
When the FB voltage exceeds 94% of the internal reference VREF, the internal PGOOD switch turns off and
PGOOD can be pulled high by the external pullup. If the FB voltage falls below 92% of VREF, the internal
PGOOD switch turns on, and PGOOD is pulled low to indicate that the output voltage is out of regulation.
Similarly, when the FB voltage exceeds 108% of VREF, the internal PGOOD switch turns on, pulling PGOOD low.
If the FB voltage subsequently falls below 105% of VREF, the PGOOD switch is turned off and PGOOD is pulled
high. PGOOD has a built-in deglitch delay of 25 µs.
VSW 10 V/DIV
VSYNCIN
2 V/DIV
1 Ps/DIV
Figure 8-5 shows a clock signal at 400 kHz and the corresponding SW node waveform (VIN = 48 V, VOUT = 5 V,
free-running frequency = 280 kHz). The SW voltage waveform is synchronized with respect to the rising edge of
SYNCIN. The rising edge of the SW voltage is phase delayed relative to SYNCIN by approximately 100 ns.
8.3.7 Configurable Soft Start (SS/TRK)
After the EN/UVLO pin exceeds its rising threshold of 1.2 V, the LM5146 begins charging the output to the
DC level dictated by the feedback resistor network. The LM5146 features an adjustable soft start (set by a
capacitor from the SS/TRK pin to GND) that determines the charging time of the output. A 10-µA current source
charges this soft-start capacitor. Soft start limits inrush current as a result of high output capacitance to avoid
an overcurrent condition. Stress on the input supply rail is also reduced. The soft-start time, tSS, for the output
voltage to ramp to its nominal level is set by Equation 4.
CSS ˜ VREF
t SS
ISS (4)
where
• CSS is the soft-start capacitance
• VREF is the 0.8-V reference
• ISS is the 10-µA current sourced from the SS/TRK pin
More simply, calculate CSS using Equation 5.
The SS/TRK pin is internally clamped to VFB + 115 mV to allow a soft start recovery from an overload event.
The clamp circuit requires a soft-start capacitance greater than 2 nF for stability and has a current limit of
approximately 2 mA.
8.3.7.1 Tracking
The SS/TRK pin also doubles as a tracking pin when master-slave power-supply tracking is required. This
tracking is achieved by simply dividing down the output voltage of the master with a simple resistor network.
Coincident, ratiometric, and offset tracking modes are possible.
If an external voltage source is connected to the SS/TRK pin, the external soft-start capability of the LM5146
is effectively disabled. The regulated output voltage level is reached when the SS/TRK pin reaches the 0.8-V
reference voltage level. It is the responsibility of the system designer to determine if an external soft-start
capacitor is required to keep the device from entering current limit during a start-up event. Likewise, the system
designer must also be aware of how fast the input supply ramps if the tracking feature is enabled.
SS/TRK
160mV/DIV
VOUT 1V/DIV
PGOOD
2V/DIV
10 ms/DIV
Figure 8-6 shows a triangular voltage signal directly driving SS/TRK and the corresponding output voltage
tracking response. Nominal output voltage here is 5 V, with oscilloscope channel scaling chosen such that the
waveforms overlap during tracking. As expected, the PGOOD flag transitions at thresholds of 94% (rising) and
92% (falling) of the nominal output voltage setpoint.
Two practical tracking configurations, ratiometric and coincident, are shown in Figure 8-7. The most common
application is coincident tracking, used in core versus I/O voltage tracking in DSP and FPGA implementations.
Coincident tracking forces the master and slave channels to have the same output voltage ramp rate until the
slave output reaches its regulated setpoint. Conversely, ratiometric tracking sets the output voltage of the slave
to a fraction of the output voltage of the master during start-up.
VOUTMASTER = 3.3 V
LM5146 LM5146
RTRK1 RFB1 RTRK3 RFB3
26.7 k 12.5 k 10 k 10 k
SYNCOUT
from Master
Figure 8-7. Tracking Implementation with Master, Ratiometric Slave, and Coincident Slave Rails
For coincident tracking, connect the SS/TRK input of the slave regulator to a resistor divider from the output
voltage of the master that is the same as the divider used on the FB pin of the slave. In other words, simply
select RTRK3 = RFB3 and RTRK4 = RFB4 as shown in Figure 8-7. As the master voltage rises, the slave voltage
rises identically (aside from the 80-mV offset from SS/TRK to FB when VFB is below 0.8 V). Eventually, the slave
voltage reaches its regulation voltage, at which point the internal reference takes over the regulation while the
SS/TRK input continues to 115 mV above FB, and no longer controls the output voltage.
In all cases, to ensure that the output voltage accuracy is not compromised by the SS/TRK voltage being too
close to the 0.8-V reference voltage, the final value of the SS/TRK voltage of the slave should be at least 100
mV above FB.
8.3.8 Voltage-Mode Control (COMP)
The LM5146 incorporates a voltage-mode control loop implementation with input voltage feedforward to
eliminate the input voltage dependence of the PWM modulator gain. This configuration allows the controller
to maintain stability throughout the entire input voltage operating range and provides optimal response to input
voltage transient disturbances. The constant gain provided by the controller greatly simplifies loop compensation
design because the loop characteristics remain constant as the input voltage changes, unlike a buck converter
without voltage feedforward. An increase in input voltage is matched by a concomitant increase in ramp voltage
amplitude to maintain constant modulator gain. The input voltage feedforward gain, kFF, is 15, equivalent to the
input voltage divided by the ramp amplitude, VIN/VRAMP. See Section 9.1.3 for more detail.
8.3.9 Gate Drivers (LO, HO)
The LM5146 gate driver impedances are low enough to perform effectively in high output current applications
where large die-size or paralleled MOSFETs with correspondingly large gate charge, QG, are used. Measured
at VVCC = 7.5 V, the low-side driver of the LM5146 has a low impedance pulldown path of 0.9 Ω to minimize
the effect of dv/dt induced turn-on, particularly with low gate-threshold voltage MOSFETs. Similarly, the high-side
driver has 1.5-Ω and 0.9-Ω pullup and pulldown impedances, respectively, for faster switching transition times,
lower switching loss, and greater efficiency.
The high-side gate driver works in conjunction with an integrated bootstrap diode and external bootstrap
capacitor, CBST. When the low-side MOSFET conducts, the SW voltage is approximately at 0 V and CBST is
charged from VCC through the integrated boot diode. Connect a 0.1-μF or larger ceramic capacitor close to the
BST and SW pins.
Furthermore, there is a proprietary adaptive dead-time control on both switching edges to prevent shoot-through
and cross-conduction, minimize body diode conduction time, and reduce body diode reverse recovery losses.
8.3.10 Current Sensing and Overcurrent Protection (ILIM)
The LM5146 implements a lossless current sense scheme designed to limit the inductor current during an
overload or short-circuit condition. Figure 8-8 portrays the popular current sense method using the on-state
resistance of the low-side MOSFET. Meanwhile, Figure 8-9 shows an alternative implementation with current
shunt resistor, RS. The LM5146 senses the inductor current during the PWM off-time (when LO is high).
VIN VIN
Q1 Q1
HO HO LF
LF VOUT
VOUT
SW
SW
RILIM Q2
ILIM LO
COUT COUT
ILIM
Q2 RILIM
LO RS
GND GND
Figure 8-8. MOSFET RDS(on) Current Sensing Figure 8-9. Shunt Resistor Current Sensing
The ILIM pin of the LM5146 sources a reference current that flows in an external resistor, designated RILIM, to
program of the current limit threshold. A current limit comparator on the ILIM pin prevents further SW pulses if
the ILIM pin voltage goes below GND. Figure 8-10 shows the implementation.
Resistor RILIM is tied to SW to use the RDS(on) of the low-side MOSFET as a sensing element (termed RDS(on)
mode). Alternatively, RILIM is tied to a shunt resistor connected at the source of the low-side MOSFET (termed
RSENSE mode). The LM5146 detects the appropriate mode at start-up and sets the source current amplitude and
temperature coefficient (TC) accordingly.
The ILIM current with RDS-ON sensing is 200 µA at 27°C junction temperature and incorporates a TC of +4500
ppm/°C to generally track the RDS(on) temperature variation of the low-side MOSFET. Conversely, the ILIM
current is a constant 100 µA in RSENSE mode. This controls the valley of the inductor current during a steady-
state overload at the output. Depending on the chosen mode, select the resistance of RILIM using Equation 6.
- IOUT 'IL 2
° I ˜ RDS(on)Q2 , RDS(on) sensing
° RDSON
RILIM ®
° IOUT 'IL 2
° ˜ RS , shunt sensing
¯ IRS (6)
where
• ΔIL is the peak-to-peak inductor ripple current
• RDS(on)Q2 is the on-state resistance of the low-side MOSFET
ValleyPWM
R Q
COMP
PWML HO
Q1
Error Amp IRAMP
FB LF
PWM Comp S Q
Gate SW VOUT
+ Driver
VREF + R Q
VRAMP PWM
Latch Q2
LO
COUT
RILIM
ILIM
IRDSON(TJ)
+
± 300 mV
CILIM
PWM Aux
COMP + +
ILIM
Clamp VCLAMP PGND GND
comparator
Modulator
Figure 8-10. OCP Setpoint Defined by Current Source IRDSON and Resistor RILIM in RDS-ON Mode
Note that current sensing with a shunt component is typically implemented at lower output current levels
to provide accurate overcurrent protection. Burdened by the unavoidable efficiency penalty, PCB layout, and
additional cost implications, this configuration is not usually implemented in high-current applications (except
where OCP setpoint accuracy and stability over the operating temperature range are critical specifications).
CLAMP
COMP Many
cycles
RAMP
300 mV
ILIM Threshold
Inductor Current
CLK
PWML
ValleyPWM
In addition to valley current limiting, the LM5146 uses a proprietary duty-cycle limiter circuit to reduce the PWM
on-time during an overcurrent condition. As shown in Figure 8-10, an auxiliary PWM comparator along with a
modulated CLAMP voltage limits how quickly the on-time increases in response to a large step in the COMP
voltage that typically occurs with a voltage-mode control loop architecture.
As depicted in Figure 8-11, the CLAMP voltage, VCLAMP, is normally regulated above the COMP voltage to
provide adequate headroom during a response to a load-on transient. If the COMP voltage rises quickly during
an overloaded or shorted output condition, the on-time pulse terminates, thereby limiting the on-time and peak
inductor current. Moreover, the CLAMP voltage is reduced if additional valley current limit events occur, further
reducing the average output current. If the overcurrent condition exists for 128 continuous clock cycles, a hiccup
event is triggered and SS is pulled low for 8192 clock cycles before a soft-start sequence is initiated.
8.4 Device Functional Modes
8.4.1 Shutdown Mode
The EN/UVLO pin provides ON / OFF control for the LM5146. When the EN/UVLO voltage is below 0.37 V
(typical), the device is in shutdown mode. Both the internal bias supply LDO and the switching regulator are off.
The quiescent current in shutdown mode drops to 13.5 μA (typical) at VIN = 48 V. The LM5146 also includes
undervoltage protection of the internal bias LDO. If the internal bias supply voltage is below its UVLO threshold
level, the switching regulator remains off.
8.4.2 Standby Mode
The internal bias supply LDO has a lower enable threshold than the switching regulator. When the EN/UVLO
voltage exceeds 0.42 V (typical) and is below the precision enable threshold (1.2 V typically), the internal LDO is
on and regulating. Switching action and output voltage regulation are disabled in standby mode.
8.4.3 Active Mode
The LM5146 is in active mode when the VCC voltage is above its rising UVLO threshold of 5 V and the
EN/UVLO voltage is above the precision EN threshold of 1.2 V. The simplest way to enable the LM5146 is to
tie EN/UVLO to VIN. This allows self start-up of the LM5146 when the input voltage exceeds the VCC threshold
plus the LDO dropout voltage from VIN to VCC.
'IL
IL(peak) IOUT
2 (8)
Check the inductor data sheet to ensure that the saturation current of the inductor is well above the peak
inductor current of a particular design. Ferrite designs have very low core loss and are preferred at high
switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low
inductor core loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite
core materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation
current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple,
not to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor
generally decreases as its core temperature increases. Of course, accurate overcurrent protection is key to
avoiding inductor saturation.
9.1.2.2 Output Capacitors
Ordinarily, the output capacitor energy store of the regulator combined with the control loop response are
prescribed to maintain the integrity of the output voltage within the dynamic (transient) tolerance specifications.
The usual boundaries restricting the output capacitor in power management applications are driven by finite
available PCB area, component footprint and profile, and cost. The capacitor parasitics—equivalent series
resistance (ESR) and equivalent series inductance (ESL)—take greater precedence in shaping the load transient
response of the regulator as the load step amplitude and slew rate increase.
The output capacitor, COUT, filters the inductor ripple current and provides a reservoir of charge for step-load
transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple
and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively
compact footprint for transient loading events.
Based on the static specification of peak-to-peak output voltage ripple denoted by ΔVOUT, choose an output
capacitance that is larger than that given by Equation 9.
'IL
COUT t
2 2
8 ˜ FSW 'VOUT RESR ˜ 'IL
(9)
Figure 9-1 conceptually illustrates the relevant current waveforms during both load step-up and step-down
transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps
to match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit
of charge in the output capacitor, which must be replenished as rapidly as possible during and after the load
step-up transient. Similarly, during and after a load step-down transient, the slew rate limiting of the inductor
current adds to the surplus of charge in the output capacitor that must be depleted as quickly as possible.
IOUT1
diL VOUT
dt LF
'IOUT inductor current, iL(t)
'QC
IOUT2
load current,
iOUT(t)
diOUT 'IOUT
dt tramp
inductor current, iL(t)
IOUT2
'QC
diL VIN VOUT
'IOUT
dt LF load current, iOUT(t)
IOUT1
tramp
Figure 9-1. Load Transient Response Representation Showing COUT Charge Surplus or Deficit
In a typical regulator application of 48-V input to low output voltage (for example, 5 V), the load-off transient
represents the worst case in terms of output voltage transient deviation. In that conversion ratio application, the
steady-state duty cycle is approximately 10% and the large-signal inductor current slew rate when the duty cycle
collapses to zero is approximately –VOUT/L. Compared to a load-on transient, the inductor current takes much
longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage
to significantly overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible,
the inductor current must ramp below its nominal level following the load step. In this scenario, a large output
capacitance can be advantageously employed to absorb the excess charge and limit the voltage overshoot.
To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as
ΔVOVERSHOOT with step reduction in output current given by ΔIOUT), the output capacitance should be larger than
2
LF ˜ 'IOUT
COUT t 2 2
VOUT 'VOVERSHOOT VOUT (10)
The ESR of a capacitor is provided in the manufacturer’s data sheet either explicitly as a specification or
implicitly in the impedance vs. frequency curve. Depending on type, size and construction, electrolytic capacitors
have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces contribute some
parasitic resistance and inductance as well. Ceramic output capacitors, on the other hand, have low ESR and
ESL contributions at the switching frequency, and the capacitive impedance component dominates. However,
depending on package and voltage rating of the ceramic capacitor, the effective capacitance can drop quite
significantly with applied DC voltage and operating temperature.
Ignoring the ESR term in Equation 9 gives a quick estimation of the minimum ceramic capacitance necessary
to meet the output ripple specification. One to four 47-µF, 10-V, X7R capacitors in 1206 or 1210 footprint is
a common choice. Use Equation 10 to determine if additional capacitance is necessary to meet the load-off
transient overshoot specification.
A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling
capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor
is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range.
While the ceramic provides excellent mid- and high-frequency decoupling characteristics with its low ESR and
ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk capacitance
provides low-frequency energy storage to cope with load transient demands.
9.1.2.3 Input Capacitors
Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switching-
frequency AC currents. TI recommends using X5R or X7R dielectric ceramic capacitors to provide low
impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in
the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET and
the source of the low-side MOSFET. The input capacitor RMS current is given by Equation 11.
§ 2 'IL ·
2
ICIN,rms D ˜ ¨ IOUT ˜ 1 D ¸
¨ 12 ¸
© ¹ (11)
The highest input capacitor RMS current occurs at D = 0.5, at which point the RMS current rating of the
capacitors should be greater than half the output current.
Ideally, the DC component of input current is provided by the input voltage source and the AC component by the
input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (IOUT −
IIN) during the D interval and sinks IIN during the 1−D interval. Thus, the input capacitors conduct a square-wave
current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component
of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak
ripple voltage amplitude is given by Equation 12.
IOUT ˜ D ˜ 1 D
'VIN IOUT ˜ RESR
FSW ˜ CIN (12)
The input capacitance required for a particular load current, based on an input voltage ripple specification of
ΔVIN, is given by Equation 13.
D ˜ 1 D ˜ IOUT
CIN t
FSW ˜ 'VIN RESR ˜ IOUT (13)
Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized
input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with
high-Q ceramics. One bulk capacitor of sufficiently high current rating and two or three 2.2-μF 100-V X7R
ceramic decoupling capacitors are usually sufficient. Select the input bulk capacitor based on its ripple current
rating and operating temperature.
9.1.2.4 Power MOSFETs
The choice of power MOSFETs has significant impact on DC/DC regulator performance. A MOSFET with
low on-state resistance, RDS(on), reduces conduction loss, whereas low parasitic capacitances enable faster
transition times and reduced switching loss. Normally, the lower the RDS(on) of a MOSFET, the higher the gate
charge and output charge (QG and QOSS respectively), and vice versa. As a result, the product RDS(on) × QG
is commonly specified as a MOSFET figure-of-merit. Low thermal resistance ensures that the MOSFET power
dissipation does not result in excessive MOSFET die temperature.
The main parameters affecting power MOSFET selection in a LM5146 application are as follows:
• RDS(on) at VGS = 7.5 V
• Drain-source voltage rating, BVDSS, typically 60 V, 80 V, or 100 V, depending on maximum input voltage
• Gate charge parameters at VGS = 7.5 V
• Output charge, QOSS, at the relevant input voltage
• Body diode reverse recovery charge, QRR
• Gate threshold voltage, VGS(th), derived from the Miller plateau evident in the QG versus VGS plot in the
MOSFET data sheet. With a Miller plateau voltage typically in the range of 2 V to 5 V, the 7.5-V gate drive
amplitude of the LM5146 provides an adequately-enhanced MOSFET when on and a margin against Cdv/dt
shoot-through when off.
The MOSFET-related power losses are summarized by the equations presented in Table 9-1, where suffixes 1
and 2 represent high-side and low-side MOSFET parameters, respectively. While the influence of inductor ripple
current is considered, second-order loss modes, such as those related to parasitic inductances and SW node
ringing, are not included. Consult the LM5146 Quickstart Calculator to assist with power loss calculations.
Table 9-1. Buck Regulator MOSFET Power Losses
POWER LOSS MODE HIGH-SIDE MOSFET LOW-SIDE MOSFET
§ 2
'IL· § 'IL ·
2
MOSFET conduction(2) 2 2
(3) Pcond1 D ˜ ¨ IOUT ¸ ˜ RDS(on)1 Pcond2 Dc ˜ ¨ IOUT ¸ ˜ RDS(on)2
¨ 12 ¸ ¨ 12 ¸
© ¹ © ¹
VIN ˜ FSW ª§ 'IL · § 'IL · º
MOSFET switching Psw1 «¨ IOUT ¸ ˜ tR ¨ IOUT ¸ ˜ tF » Negligible
2 ¬© 2 ¹ © 2 ¹ ¼
MOSFET gate drive(1) PGate1 VCC ˜ FSW ˜ QG1 PGate2 VCC ˜ FSW ˜ QG2
MOSFET output
PCoss FSW ˜ VIN ˜ Qoss2 Eoss1 Eoss2
charge(4)
ª§ 'IL · § 'IL · º
Body diode conduction N/A PcondBD VF ˜ FSW «¨ IOUT ¸ ˜ t dt1 ¨ IOUT ¸ ˜ t dt2 »
¬© 2 ¹ © 2 ¹ ¼
(1) Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally-added series gate resistance and the
relevant gate driver resistance of the LM5146.
(2) MOSFET RDS(on) has a positive temperature coefficient of approximately 4500 ppm/°C. The MOSFET junction temperature, TJ, and its
rise over ambient temperature is dependent upon the device total power dissipation and its thermal impedance. When operating at or
near minimum input voltage, ensure that the MOSFET RDS(on) is rated at VGS = 4.5 V.
(3) D' = 1–D is the duty cycle complement.
(4) MOSFET output capacitances, Coss1 and Coss2, are highly non-linear with voltage. These capacitances are charged losslessly by the
inductor current at high-side MOSFET turn-off. During turn-on, however, a current flows from the input to charge Coss2 of the low-side
MOSFET. Eoss1, the energy of Coss1, is dissipated at turnon, but this is offset by the stored energy Eoss2 on Coss2.
(5) MOSFET body diode reverse recovery charge, QRR, depends on many parameters, particularly forward current, current transition
speed, and temperature.
The high-side (control) MOSFET carries the inductor current during the PWM on-time (or D interval) and typically
incurs most of the switching losses. It is therefore imperative to choose a high-side MOSFET that balances
conduction and switching loss contributions. The total power dissipation in the high-side MOSFET is the sum of
the losses due to conduction, switching (voltage-current overlap), output charge, and typically two-thirds of the
net loss attributed to body diode reverse recovery.
The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D
interval). The low-side MOSFET switching loss is negligible as it is switched at zero voltage – current just
commutates from the channel to the body diode or vice versa during the transition deadtimes. The LM5146, with
its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses
scale directly with switching frequency.
In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching
period. Therefore, to attain high efficiency, it is critical to optimize the low-side MOSFET for low RDS(on). In cases
where the conduction loss is too high or the target RDS(on) is lower than available in a single MOSFET, connect
two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses
due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode
reverse recovery. The LM5146 is well suited to drive TI's portfolio of NexFET™ power MOSFETs.
9.1.3 Control Loop Compensation
The poles and zeros inherent to the power stage and compensator are respectively illustrated by red and blue
dashed rings in the schematic embedded in Table 9-2. The compensation network typically employed with
voltage-mode control is a Type-III circuit with three poles and two zeros. One compensator pole is located at
the origin to realize high DC gain. The normal compensation strategy uses two compensator zeros to counteract
the LC double pole, one compensator pole located to nullify the output capacitor ESR zero, with the remaining
compensator pole located at one-half switching frequency to attenuate high frequency noise. The resistor divider
network to FB determines the desired output voltage. Note that the lower feedback resistor, RFB2, has no
impact on the control loop from an AC standpoint because the FB node is the input to an error amplifier and is
effectively at AC ground. Hence, the control loop is designed irrespective of output voltage level. The proviso
here is the necessary output capacitance derating with bias voltage and temperature.
Table 9-2. Buck Regulator Poles and Zeros
VIN
Power Stage
Q1
&L &o
D
Adaptive VOUT
Gate LF
&ESR
RDAMP IOUT
Driver RESR
Q2
Modulator RL
COUT
PWM Ramp
VRAMP GND
Compensator
Error
Amp VREF CC3 &p2 RC2
COMP +
+ FB
PWM
Comparator
CC1 &z1 RC1
RFB1 &z2
RFB2
CC2 &p1
POWER STAGE POLES POWER STAGE ZEROS COMPENSATOR POLES COMPENSATOR ZEROS
1 1 1 1 1
Zo ZESR Zp1 #
RC1 ˜ (CC1 CC2 ) RC1 ˜ CC2
Zz1
§ 1 RESR RL · RESR ˜ COUT RC1 ˜ CC1
LF ˜ COUT ¨ ¸
© 1 RESR RDAMP ¹
1 LF 1 1
# ZL Zp2 Zz2
LF ˜ COUT RDAMP RC2 ˜ CC3 (RFB1 RC2 ) ˜ CC3
(1) (2)
The small-signal open-loop response of a buck regulator is the product of modulator, power train and
compensator transfer functions. The power stage transfer function can be represented as a complex pole pair
associated with the output LC filter and a zero related to the ESR of the output capacitor. The DC (and low
frequency) gain of the modulator and power stage is VIN/VRAMP. The gain from COMP to the average voltage at
the input of the LC filter is held essentially constant by the PWM line feedforward feature of the LM5146 (15 V/V
or 23.5 dB).
Complete expressions for small-signal frequency analysis are presented in Table 9-3. The transfer functions are
denoted in normalized form. While the loop gain is of primary importance, a regulator is not specified directly
by its loop gain but by its performance related characteristics, namely closed-loop output impedance and audio
susceptibility.
Table 9-3. Buck Regulator Small-Signal Analysis
TRANSFER FUNCTION EXPRESSION
vÖ comp (s) vÖ o (s) Ö
d(s)
Open-loop transfer function Tv (s) ˜ ˜ Gc (s) ˜ Gvd (s) ˜ FM
vÖ o (s) Ö
d(s) vÖ comp (s)
s
1
vÖ o (s) ZESR
Duty-cycle-to-output transfer function
Gvd (s) VIN
Ö
d(s) vÖ in (s)0 s s
2
Öi (s) 0
o
1 2
QoZo Zo
§ Zz1 · § s ·
vÖ comp (s) ¨1 s ¸ ¨1 Z ¸
© ¹© z2 ¹
Compensator transfer function(1) Gc (s) K mid
vÖ o (s) § s ·§ s ·
¨1 ¸¨ 1 ¸
¨ Zp1 ¸¨ Zp2 ¸
© ¹© ¹
Ö
d(s) 1
Modulator transfer function FM
vÖ comp (s) VRAMP
(1) Kmid = RC1/RFB1 is the mid-band gain of the compensator. By expressing one of the compensator zeros in inverted zero format, the
mid-band gain is denoted explicitly.
Figure 9-2 shows the open-loop response gain and phase. The poles and zeros of the system are marked with
x and o symbols, respectively, and a + symbol indicates the crossover frequency. When plotted on a log (dB)
scale, the open-loop gain is effectively the sum of the individual gain components from the modulator, power
stage, and compensator (see Figure 9-3). The open-loop response of the system is measured experimentally by
breaking the loop, injecting a variable-frequency oscillator signal, and recording the ensuing frequency response
using a network analyzer setup.
40 0
Loop Complex
Gain LC Double
Pole
Crossover -45
20 Frequency, fc
Compensator Loop
Loop Compensator Poles
Gain 0 Zeros -90 Phase
(°)
(dB) Loop
Phase
NM
-20 -135
Output
Capacitor
ESR Zero
-40 -180
1 10 100 1000
Frequency (kHz)
Figure 9-2. Typical Buck Regulator Loop Gain and Phase With Voltage-Mode Control
If the pole located at ωp1 cancels the zero located at ωESR and the pole at ωp2 is located well above crossover,
the expression for the loop gain, Tv(s) in Table 9-3, can be manipulated to yield the simplified expression given in
Equation 14.
2
VIN Zo
Tv (s) RC1 ˜ CC3 ˜ ˜
VRAMP s (14)
VIN
Zc 2 S ˜ fc Zo ˜ K mid ˜
VRAMP (15)
fc 1 RC1
K mid ˜
fo kFF RFB1 (16)
40
Loop Gain Modulator Compensator
Gain Gain
20
Gain
(dB)
0
-20
Filter Gain
-40
1 10 fc 100 1000
Frequency (kHz)
The loop crossover frequency is usually selected between one-tenth to one-fifth of switching frequency. Inserting
an appropriate crossover frequency into Equation 16 gives a target for the mid-band gain of the compensator,
Kmid. Given an initial value for RFB1, RFB2 is then selected based on the desired output voltage. Values for RC1,
RC2, CC1, CC2, and CC3 are calculated from the design expressions listed in Table 9-4, with the premise that the
compensator poles and zeros are set as follows: ωz1 = 0.5·ωo, ωz2 = ωo, ωp1 = ωSW/2, and ωp2 = ωESR.
Table 9-4. Compensation Component Selection
RESISTORS CAPACITORS
RFB1 1
RFB2 CC1
VOUT VREF 1 Zz1 ˜ RC1
1
RC1 K mid ˜ RFB1 CC2
Zp1 ˜ RC1
1 1
RC2 CC3
Zp2 ˜ CC3 Zz2 ˜ RFB1
Referring to the bode plot in Figure 9-2, the phase margin, indicated as φM, is the difference between the loop
phase and –180° at crossover. A target of 50° to 70° for this parameter is considered ideal. Additional phase
boost is dialed in by locating the compensator zeros at a frequency lower than the LC double pole. This helps
mitigate the phase dip associated with the LC filter, particularly at light loads when the Q-factor is higher and
the phase dip becomes especially prominent. The ramification of low phase in the frequency domain is an
under-damped transient response in the time domain.
The power supply designer now has all the necessary expressions to optimally position the loop crossover
frequency while maintaining adequate phase margin over the required line, load and temperature operating
ranges. The LM5146 Quickstart Calculator is available to expedite these calculations and to adjust the bode plot
as needed.
9.1.4 EMI Filter Design
Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An
underdamped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability,
the filter output impedance must be less than the absolute value of the converter input impedance.
2
VIN(min)
ZIN
PIN
(17)
LIN
VIN Q1
LF
CD
VOUT
CF CIN
Q2 COUT
RD
GND GND
By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it
by the input impedance (the impedance is defined by the existing input capacitor CIN), a formula is derived to
obtain the required attenuation as shown by Equation 18.
§ IL(PEAK) 1 ·
Attn 20log ¨ 2 ˜ sin S ˜ DMAX ˜ ¸ VMAX
¨ S ˜F ˜ C 1 9¸
© SW IN ¹ (18)
where
• VMAX is the noise specification in dBμV from the applicable EMI standard, for example CISPR 32 Class B
• CIN is the existing input capacitance of the buck regulator
Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output
impedance of the filter must be sufficiently small such that the input filter does not significantly affect the loop
gain of the buck converter. The impedance peaks at the filter resonant frequency. The resonant frequency of the
filter is given by Equation 20.
1
fres
2S ˜ LIN ˜ CF (20)
The purpose of RD is to reduce the peak output impedance of the filter at the resonant frequency. Capacitor CD
blocks the DC component of the input voltage to avoid excessive power dissipation in RD. Capacitor CD must
have lower impedance than RD at the resonant frequency with a capacitance value greater than that of the input
capacitor CIN. This prevents CIN from interfering with the cutoff frequency of the main filter. Added damping is
needed when the output impedance of the filter is high at the resonant frequency (Q of filter formed by LIN and
CIN is too high). An electrolytic capacitor CD can be used for damping with a value given by Equation 21.
CD t 4 ˜ CIN (21)
LIN
RD
CIN (22)
U1
1 20 CBST
RC2 RRT
0.1 F
150 Ω RFB1 40.2 kΩ EN/UVLO VIN Q1
23.2 kΩ 2 RT BST 17
CC3 CSS
RC1 CC1 3 SS/TRK HO 18
820 pF
7.5 kΩ 6.8 nF 47 nF LF
4 COMP SW 19 3.3 H
VOUT = 5 V
5 FB NC 16
CC2 150 pF
LM5146 Q2
6 AGND EP 15
RFB2
4.42 kΩ SYNC Out 7 SYNCOUT CIN COUT
VCC 14
6 4.7 F 5 47 μF
8 SYNCIN LO 13
SYNC In 9 NC PGND 12
PGOOD ILIM
GND
300 kHz 10 11
CVCC
2.2 μF
RPG
PGOOD 20 kΩ RILIM
CILIM 499 Ω
10 pF
Figure 9-5. Application Circuit 1 With LM5146 48-V to 5-V, 12-A Buck Regulator at 300 kHz
Note
This and subsequent design examples are provided herein to showcase the LM5146 controller in
several different applications. Depending on the source impedance of the input supply bus, an
electrolytic capacitor may be required at the input to ensure stability, particularly at low input voltage
and high output current operating conditions. See Section 10 for more detail.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.1.4 Custom Design With Excel Quickstart Tool
Select components based on the regulator specifications using the LM5146 Quickstart Calculator available for
download from the product folder.
100
95
SW 10V/DIV SYNCOUT 1V/DIV
90
Efficiency (%)
85
80
75 VIN = 12V
VIN = 24V
70 VIN = 36V
VIN = 48V
65 VIN = 60V
VIN = 75V
1 Ps/DIV
60
0 2 4 6 8 10 12
Output Current (A) VIN = 48 V IOUT = 6 A
Figure 9-6. Efficiency and Power Loss vs IOUT and Figure 9-7. SYNCOUT and SW Node Voltages
VIN
PGOOD 2V/DIV
IOUT 2A/DIV
IOUT 2A/DIV
PGOOD 2V/DIV
VIN 2V/DIV
Figure 9-8. Start-Up, Resistive Load Figure 9-9. Shutdown Through UVLO
PGOOD 2V/DIV
EN 1V/DIV
IOUT 5A/DIV
1 ms/DIV 40 Ps/DIV
Figure 9-10. ENABLE ON, Resistive Load Figure 9-11. Load Transient Response, 6 A to 12 A
to 6 A
IOUT 5A/DIV
VIN 20V/DIV
IOUT 5A/DIV
40 Ps/DIV 2 ms/DIV
VIN = 48 V IOUT = 6 A
Figure 9-12. Load Transient Response, 0 A to 12 A Figure 9-13. Line Transient Response, 12 V to 85 V
to 0 A
VOUT 50mV/DIV
SW 10V/DIV
VIN 20V/DIV
VOUT 50mV/DIV
IOUT 5A/DIV
20 ms/DIV 1 Ps/DIV
Figure 9-14. Line Transient Response, 85 V to 12 V Figure 9-15. SW Node and Output Ripple Voltages
9.2.2 Design 2 – High Density, 12-V, 8-A Rail From 48-V Telecom Power
Figure 9-16 shows the schematic diagram of a 400-kHz, 12-V output, 8-A synchronous buck regulator intended
for 48-V telecom applications.
RUV2 RUV1
9.31 kΩ 100 kΩ
VIN = 14 V to 85 V
RVIN
CVIN 2.2 Ω
VOUT
0.1 μF
U1
RC2 RRT 1 20 RBST
100 Ω RFB1 24.9 kΩ 2.2 Ω
EN/UVLO VIN
21 kΩ 2 RT BST 17
CC3 CSS Q1
RC1 CC1 3 SS/TRK HO 18
1 nF
8.06 kΩ 4.7 nF 47 nF LF
4 COMP SW 19
CBST 6.8 H
0.1 F VOUT = 12 V
5 FB NC 16
CC2 100 pF
LM5146
6 AGND EP 15
RFB2
Q2
1.5 kΩ 7 SYNCOUT CIN COUT
SYNC Out VCC 14
5 2.2 F 5 22 μF
SYNC In 8 SYNCIN LO 13
9 NC PGND 12
PGOOD ILIM
10 11 GND
D1
CVCC optional
2.2 μF
PGOOD RILIM
CILIM 619 Ω
10 pF
Figure 9-16. Application Circuit 2 With LM5146 48-V to 12-A Synchronous Buck Regulator at 400 kHz
The selected buck converter powertrain components are cited in Table 9-8, including power MOSFETs,
buck inductor, input and output capacitors, and ICs. Using the LM5146 Quickstart Calculator, compensation
components are selected based on a target loop crossover frequency of 40 kHz and phase margin greater than
55°. The output voltage soft-start time is 6 ms based on the selected soft-start capacitance, CSS, of 47 nF.
Table 9-8. List of Materials for Application Circuit 2
REFERENCE
QTY SPECIFICATION MANUFACTURER PART NUMBER
DESIGNATOR
TDK CGA6N3X7R2A225K
2.2 µF, 100 V, X7R, 1210, ceramic
CIN 5 Taiyo Yuden HMK325B7225KM-P
2.2 µF, 100 V, X7S, 1206, ceramic Murata GCM31CC72A225KE02
TDK CGA6P3X7R1E226M
COUT 5 22 µF, 25 V, X7R, 1210, ceramic Murata GCM32EC71E226KE36
Taiyo Yuden TMK325B7226KMHT
6.8 µH, 12 mΩ, 13.3 A, 10.85 × 10.0 × 5.2 mm Cyntec VCHA105D-6R8MS6
LF 1
6.8 µH, 13.3 mΩ, 21.4 A, 10.5 × 10.0 × 6.5 mm TDK SPM10065VT-6R8M-D
Q1 1 100 V, 22 mΩ, MOSFET, SON 5 × 6 Onsemi NVMFS6B25NLT1G
Q2 1 100 V, 10 mΩ, MOSFET, SON 5 × 6 Onsemi NVMFS6B14NLT1G
U1 1 Wide VIN synchronous buck controller Texas Instruments LM5146RGYR
As shown in Figure 9-16, a 2.2-Ω resistor in series with CBST is used to slow the turn-on transition of the high-
side MOSFET, reducing the spike amplitude and ringing of the SW node voltage and minimizing the possibility of
Cdv/dt-induced shoot-through of the low-side MOSFET. If needed, place an RC snubber (for example, 2.2 Ω and
100 pF) close to the drain (SW node) and source (PGND) terminals of the low-side MOSFET to further attenuate
any SW node voltage overshoot and/or ringing. Please refer to the application note Reduce Buck Converter EMI
and Voltage Stress by Minimizing Inductive Parasitics for more detail.
100
95 SW 10V/DIV
90
Efficiency (%)
85
80 VIN = 15V
VIN = 24V
VIN = 36V
75 VIN = 48V
VIN = 60V
VIN = 75V
1 Ps/DIV
70
0 2 4 6 8
Output Current (A) VIN = 48 V IOUT = 8 A
Figure 9-17. Efficiency vs IOUT and VIN Figure 9-18. SW Node Voltages
Figure 9-19. Start-Up, 8-A Resistive Load Figure 9-20. Shutdown By Input UVLO, 8-A
Resistive Load
EN 2V/DIV EN 2V/DIV
Figure 9-21. ENABLE ON, 10-A Resistive Load Figure 9-22. ENABLE OFF, 10-A Resistive Load
100 Ps/DIV
100 Ps/DIV
VIN = 48 V VIN = 48 V
Figure 9-23. Load Transient Response, 1 A to 8 A Figure 9-24. Load Transient Response, 2 A to 8 A
to 1 A to 2 A
VOUT 20 mV/DIV
IOUT 2A/DIV
EN 1V/DIV
PGOOD 5V/DIV
VIN 20V/DIV
20 ms/DIV 1 ms/DIV
SYNCIN
1V/DIV
1 Ps/DIV 1 Ps/DIV
Figure 9-29. SW Node and SYNCIN Voltages Figure 9-30. SW Node and SYNCOUT Voltages
Margin
Margin
Start 150 kHz Stop 30 MHz Start 30 MHz Stop 108 MHz
VIN = 48 V VOUT = 12 V 6-A resistive load VIN = 48 V VOUT = 12 V 6-A resistive load
Figure 9-31. CISPR 25 Class 5 Conducted EMI, 150 Figure 9-32. CISPR 25 Class 5 Conducted EMI, 30
kHz to 30 MHz MHz to 108 MHz
VOUT ˜ IOUT
IIN
VIN ˜ K (23)
where
• η is the efficiency
If the converter is connected to an input supply through long wires or PCB traces with a large impedance,
take special care to achieve stable performance. The parasitic inductance and resistance of the input cables
may have an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR
ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients
at VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to
dip during a load transient. If the regulator is operating close to the minimum input voltage, this dip can cause
false UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from
the input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics.
The moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage
overshoots. A capacitance in the range of 10 µF to 47 µF is usually sufficient to provide input damping and helps
to hold the input voltage steady during large load transients.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability
as well as some of the effects mentioned above. The application report Simple Success with Conducted EMI
for DC-DC Converters (SNVA489) provides helpful suggestions when designing an input filter for any switching
regulator.
11 Layout
11.1 Layout Guidelines
Proper PCB design and layout is important in a high-current, fast-switching circuits (with high current and voltage
slew rates) to assure appropriate device operation and design robustness. As expected, certain issues must
be considered before designing a PCB layout using the LM5146. The high-frequency power loop of the buck
converter power stage is denoted by #1 in the shaded area of Figure 11-1. The topological architecture of a buck
converter means that particularly high di/dt current flows in the components of loop 1, and it becomes mandatory
to reduce the parasitic inductance of this loop by minimizing its effective loop area. Also important is the gate
drive loops of the low-side and high-side MOSFETs, denoted by 2 and 3, respectively, in Figure 11-1.
VIN
LM5146
CIN #1
BST High frequency
VCC 14 17
power loop
CBST
HO Q1
High-side
18
gate driver LF
#2
SW
19 VOUT
VCC
14
CVCC
Q2 COUT
Low-side LO
13
gate driver
#3
PGND
12 GND
Figure 11-1. DC/DC Regulator Ground System With Power Stage and Gate Drive CirCuit Switching Loops
4. Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer,
including pad geometry and solder paste stencil design.
5. The SW pin connects to the switch node of the power conversion stage and acts as the return path for the
high-side gate driver. The parasitic inductance inherent to loop #1 in Figure 11-1 and the output capacitance
(COSS) of both power MOSFETs form a resonant circuit that induces high frequency (> 100 MHz) ringing
on the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than the
input voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit
for the SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW
node to GND damps the ringing and decreases the peak amplitude. Provide provisions for snubber network
components in the PCB layout. If testing reveals that the ringing amplitude at the SW pin is excessive, then
include snubber components as needed.
11.1.2 Gate Drive Layout
The LM5146 high-side and low-side gate drivers incorporate short propagation delays, adaptive dead-time
control and low-impedance output stages capable of delivering large peak currents with very fast rise and
fall times to facilitate rapid turnon and turnoff transitions of the power MOSFETs. Very high di/dt can cause
unacceptable ringing if the trace lengths and impedances are not well controlled.
Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance,
whether it be series gate inductance that resonates with MOSFET gate capacitance or common source
inductance (common to gate and power loops) that provides a negative feedback component opposing the
gate drive command, thereby increasing MOSFET switching times. The following loops are important:
• Loop 2: high-side MOSFET, Q1. During the high-side MOSFET turnon, high current flows from the bootstrap
(boot) capacitor through the gate driver and high-side MOSFET, and back to the negative terminal of the boot
capacitor through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from
the gate of the high-side MOSFET through the gate driver and SW, and back to the source of the high-side
MOSFET through the SW trace. Refer to loop #2 of Figure 11-1.
• Loop 3: low-side MOSFET, Q2. During the low-side MOSFET turn-on, high current flows from the VCC
decoupling capacitor through the gate driver and low-side MOSFET, and back to the negative terminal of the
capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from the gate of
the low-side MOSFET through the gate driver and GND, and back to the source of the low-side MOSFET
through ground. Refer to loop #3 of Figure 11-1.
TI strongly recommends following circuit layout guidelines when designing with high-speed MOSFET gate drive
circuits.
1. Connections from gate driver outputs, HO and LO, to the respective gate of the high-side or low-side
MOSFET must be as short as possible to reduce series parasitic inductance. Use 0.65 mm (25 mils) or wider
traces. Use a via or vias, if necessary, of at least 0.5 mm (20 mils) diameter along these traces. Route HO
and SW gate traces as a differential pair from the LM5146 to the high-side MOSFET, taking advantage of
flux cancellation.
2. Minimize the current loop path from the VCC and BST pins through their respective capacitors as these
provide the high instantaneous current, up to 3.5 A, to charge the MOSFET gate capacitances. Specifically,
locate the bootstrap capacitor, CBST, close to the BST and SW pins of the LM5146 to minimize the area of
loop #2 associated with the high-side driver. Similarly, locate the VCC capacitor, CVCC, close to the VCC and
PGND pins of the LM5146 to minimize the area of loop #3 associated with the low-side driver.
3. Placing a 2-Ω to 10-Ω resistor in series with the boot capacitor, as shown in Figure 9-16, slows down the
high-side MOSFET turn-on transition, serving to reduce the voltage ringing and peak amplitude at the SW
node at the expense of increased MOSFET turnon power loss.
11.1.3 PWM Controller Layout
With the proviso to locate the controller as close as possible to the MOSFETs to minimize gate driver trace runs,
the components related to the analog and feedback signals, current limit setting, and temperature sense are
considered in the following:
1. Separate power and signal traces, and use a ground plane to provide noise shielding.
2. Place all sensitive analog traces and components such as COMP, FB, RT, ILIM, and SS/TRK away from
high-voltage switching nodes such as SW, HO, LO, or BST to avoid mutual coupling. Use an internal layer or
layers as a ground plane or ground planes. Pay particular attention to shielding the feedback (FB) trace from
power traces and components.
3. The upper feedback resistor can be connected directly to the output voltage sense point at the load device or
the bulk capacitor at the converter side.
4. Connect the ILIM setting resistor from the drain of the low-side MOSFET to ILIM and make the connections
as close as possible to the LM5146. The trace from the ILIM pin to the resistor must avoid coupling to a
high-voltage switching net.
5. Minimize the loop area from the VCC and VIN pins through their respective decoupling capacitors to the
GND pin. Locate these capacitors as close as possible to the LM5146.
11.1.4 Thermal Design and Layout
The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO
regulator is greatly affected by:
• Average gate drive current requirements of the power MOSFETs
• Switching frequency
• Operating input voltage (affecting bias regulator LDO voltage drop and hence its power dissipation)
• Thermal characteristics of the package and operating environment
For a PWM controller to be useful over a particular temperature range, the package must allow for the efficient
removal of the heat produced while keeping the junction temperature within rated limits. The LM5146 controller
is available in a small 3.5-mm × 4.5-mm 20-pin VQFN (RGY) PowerPAD™ package to cover a range of
application requirements. The thermal metrics of this package are summarized in Section 7.4. The application
report Semiconductor and IC Package Thermal Metrics provides detailed information regarding the thermal
information table.
The 20-pin VQFN package offers a means of removing heat from the semiconductor die through the exposed
thermal pad at the base of the package. While the exposed pad of the package is not directly connected to any
leads of the package, it is thermally connected to the substrate of the LM5146 device (ground). This allows a
significant improvement in heat sinking, and it becomes imperative that the PCB is designed with thermal lands,
thermal vias, and a ground plane to complete the heat removal subsystem. The exposed pad of the LM5146 is
soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the
thermal resistance to a very low value. Wide traces of the copper tying in the no-connect pins of the LM5146
(pins 9 and 16) and connection to this thermal land helps to dissipate heat.
Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal and solder-side ground
plane(s) are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed on the
PCB layer below the power components. Not only does this provide a plane for the power stage currents to flow
but it also represents a thermally conductive path away from the heat generating devices.
The thermal characteristics of the MOSFETs also are significant. The drain pad of the high-side MOSFET is
normally connected to a VIN plane for heat sinking. The drain pad of the low-side MOSFET is tied to the SW
plane, but the SW plane area is purposely kept relatively small to mitigate EMI concerns.
11.1.5 Ground Plane Design
As mentioned previously, using one or more of the inner PCB layers as a solid ground plane is recommended.
A ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for
the control circuitry. Connect the PGND pin to the system ground plane using an array of vias under the exposed
pad. Also connect the PGND directly to the return terminals of the input and output capacitors. The PGND net
contains noise at the switching frequency and can bounce because of load current variations. The power traces
for PGND, VIN and SW can be restricted to one side of the ground plane. The other side of the ground plane
contains much less noise and is ideal for sensitive analog trace routes.
Input
Capacitors
Output
Capacitor
VIN
High-side
MOSFET
S G PGND
ILIM
LO
VOUT Inductor SW VCC
FB
Low-side
HO
MOSFET
AGND
SW
S G
PGND
Output Capacitor
Legend
Keep SW copper Place PGND vias close to the Locate controller close Copper island
Top Layer Copper source of the low-side FET
area small to the power stage connected to
Layer 2 GND Plane AGND pin
Top Solder
Q2 Q1 Cin1-4
SW VIN
GND GND
L1
0.15mm
L2
L3
0.3mm
L4 vias
Note
See the Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage
Layout application report for more detail.
Figure 11-3. PCB Stack-up Diagram With Low L1-L2 Intra-layer Spacing
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• LM5146-Q1 EVM User's Guide
• LM5145 EVM User's Guide
• LM5143-Q1 Synchronous Buck Controller EVM
• LM5143-Q1 Synchronous Buck Controller High-Density 4-Phase Design
• Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics
• AN-2162 Simple Success with Conducted EMI from DC-DC Converters
• White Papers:
– Valuing Wide VIN, Low-EMI Synchronous Buck Circuits for Cost-Effective, Demanding Applications
– An Overview of Conducted EMI Specifications for Power Supplies
– An Overview of Radiated EMI Specifications for Power Supplies
12.2.1.1 PCB Layout Resources
• Improve High-current DC/DC Regulator Performance for Free with Optimized Power Stage Layout
• AN-1149 Layout Guidelines for Switching Power Supplies
• Constructing Your Power Supply – Layout Considerations
• Technical Articles:
– High-Density PCB Layout of DC-DC Converters
12.2.1.2 Thermal Design Resources
• AN-2020 Thermal Design by Insight, Not Hindsight
• AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
• Semiconductor and IC Package Thermal Metrics
• Thermal Design Made Simple with LM43603 and LM43602
• PowerPAD™ Thermally Enhanced Package
• PowerPAD Made Easy
• Using New Thermal Metrics
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.5 Trademarks
NexFET™, PowerPAD™, and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
are registered trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 1-Jul-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
LM5146RGYR ACTIVE VQFN RGY 20 3000 RoHS & Green NIPDAU | SN Level-2-260C-1 YEAR -40 to 150 LM5146 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 1-Jul-2023
• Automotive : LM5146-Q1
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Sep-2023
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 9-Sep-2023
Width (mm)
H
W
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGY 20 VQFN - 1 mm max height
3.5 x 4.5, 0.5 mm pitch PLASTIC QUAD FGLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225264/A
www.ti.com
PACKAGE OUTLINE
RGY0020B SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3.6 B
A
3.4
4.6
4.4
0.1 MIN
(0.05)
SECTION A-A
SECTION A-A
SCALE 30.000
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.08 C
0.00
1.7 0.1
2X 1.5 (0.2) TYP
10 11 EXPOSED
14X 0.5 THERMAL PAD
9
12
SYMM 21
2X 2.7 0.1
3.5
A A
2
19
0.3
1 20 20X
0.2
PIN 1 ID SYMM
(OPTIONAL) 0.1 C A B
0.5 0.05
20X
0.3
4222860/B 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0020B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.7)
SYMM
1 20
20X (0.6)
2
19
20X (0.25)
(1.1)
(4.3)
SYMM 21
(2.7)
14X (0.5)
(0.6)
9 12
(R0.05) TYP
10 11
(0.75) TYP
(3.3)
SOLDER MASK
METAL OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK METAL UNDER
OPENING SOLDER MASK
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0020B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (0.75)
(R0.05) TYP
1 20
20X (0.6)
2
19
21
20X (0.25)
4X
(1.21)
SYMM
(4.3)
(0.71)
TYP
14X (0.5)
9 12
METAL
TYP
10 11
4X (0.75) (0.475)
TYP
SYMM
(3.3)
EXPOSED PAD 21
80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4222860/B 06/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
RGY0020G SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
3.6 B
A
3.4
4.6
4.4
1.0 C
0.8
SEATING PLANE
0.05
0.00 1.7 0.1 0.08 C
2X 1.5
(0.1) TYP
10 11 EXPOSED
THERMAL PAD
9
12
14X 0.5
2X SYMM 21
3.5 2.7 0.1
2
19
PIN 1 ID 0.3
1 20 20X
(45 X 0.3) 0.2
SYMM
0.1 C A B
0.5 0.05
20X
0.3
4229343/A 01/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0020G VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1.7)
SYMM
1 20
20X (0.6)
2
19
20X (0.25)
(1.1)
(4.3)
SYMM 21
(2.7)
14X (0.5)
(0.6)
9 12
(R0.05) TYP
10 11
(0.75) TYP
(3.3)
SOLDER MASK
METAL OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK METAL UNDER
OPENING SOLDER MASK
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0020G VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (0.75)
(R0.05) TYP
1 20
20X (0.6)
2
19
21
20X (0.25)
4X
(1.21)
SYMM
(4.3)
(0.71)
TYP
14X (0.5)
9 12
METAL
TYP
10 11
4X (0.75) (0.475)
TYP
SYMM
(3.3)
EXPOSED PAD 21
80% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4229343/A 01/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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