LMR 23625
LMR 23625
LMR 23625
1 Features 3 Description
• 4-V to 36-V input range The LMR23625 SIMPLE SWITCHER® is an easy-to-
• 2.5-A continuous output current use 36-V, 2.5-A synchronous step-down regulator.
• Integrated synchronous rectification With a wide input range from 4 V to 36 V, the
• Current mode control device is suitable for various industrial application
• Minimum switch ON time: 60 ns for power conditioning from unregulated sources.
• 2.1-MHz switching frequency with PFM and Peak current-mode control is employed to achieve
forced-PWM-mode options (HSOIC) simple control-loop compensation and cycle-by-cycle
• 2.1-MHz switching frequency with forced-PWM current limiting. A quiescent current of 75 μA makes
mode only (WSON) it suitable for battery-powered systems. An ultra-low
• Frequency synchronization to external clock 2 μA shutdown current can further prolong battery
• Internal compensation for ease of use life. Internal loop compensation means that the user
• 75-µA quiescent current at no load is free from the tedious task of loop compensation
• Soft start into a prebiased load design. This also minimizes the external components.
• High duty-cycle operation supported The device has an option for fixed-frequency FPWM
• Precision enable input mode to achieve small output-voltage ripple at light
• Output short-circuit protection with hiccup mode load. An extended family for HSOIC is available in
• Thermal protection 1-A (LMR23610) and 3-A (LMR23630) load current
• 8-Pin HSOIC with PowerPAD™ package options in pin-to-pin compatible packages which
• 12-Pin WSON wettable flanks package with allows simple, optimum PCB layout. A precision
PowerPAD™ enable input allows simplification of regulator control
• Use the LMZM33603 module for faster time to and system power sequencing. Protection features
market include cycle-by-cycle current limit, hiccup-mode
• Create a custom design using the LMR23625 with short-circuit protection and thermal shutdown due to
the WEBENCH® Power Designer excessive power dissipation.
2 Applications Device Information
PART NUMBER (1) PACKAGE BODY SIZE (NOM)
• Factory and building automation systems: PLC
CPU, HVAC control, elevator control HSOIC (8) 4.89 mm × 3.90 mm
LMR23625
• GSM, GPRS modules for fleet management, smart WSON (12) 3.00 mm × 3.00 mm
grids, and security
(1) For all available packages, see the orderable addendum at
• General purpose wide VIN regulation the end of the data sheet.
space
VIN up to 36 V 100
CIN
VIN
90
EN/SYNC BOOT
CBOOT
L
Efficiency (%)
VOUT
AGND SW 80
RFBT
COUT 70
RFBB
VCC FB
CVCC
PGND 60
VOUT = 5 V
VOUT = 3.3 V
50
Simplified Schematic 0.0001 0.001 0.01 0.1 1 10
IOUT (A) D000
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR23625
SNVSAH3E – FEBRUARY 2018 – REVISED JULY 2020 www.ti.com
Table of Contents
1 Features............................................................................1 8 Application and Implementation.................................. 19
2 Applications..................................................................... 1 8.1 Application Information............................................. 19
3 Description.......................................................................1 8.2 Typical Applications.................................................. 19
4 Revision History.............................................................. 2 9 Power Supply Recommendations................................26
5 Pin Configuration and Functions...................................4 10 Layout...........................................................................26
Pin Functions.................................................................... 4 10.1 Layout Guidelines................................................... 26
6 Specifications.................................................................. 5 10.2 Layout Example...................................................... 27
6.1 Absolute Maximum Ratings........................................ 5 10.3 Compact Layout for EMI Reduction........................ 28
6.2 ESD Ratings............................................................... 5 10.4 Ground Plane and Thermal Considerations............28
6.3 Recommended Operating Conditions.........................5 10.5 Feedback Resistors................................................ 29
6.4 Thermal Information....................................................6 11 Device and Documentation Support..........................30
6.5 Electrical Characteristics.............................................6 11.1 Device Support........................................................30
6.6 Timing Requirements.................................................. 8 11.2 Receiving Notification of Documentation Updates.. 30
6.7 Switching Characteristics............................................8 11.3 Support Resources................................................. 30
6.8 Typical Characteristics................................................ 9 11.4 Trademarks............................................................. 30
7 Detailed Description...................................................... 11 11.5 Electrostatic Discharge Caution.............................. 30
7.1 Overview................................................................... 11 11.6 Glossary.................................................................. 30
7.2 Functional Block Diagram......................................... 11 12 Mechanical, Packaging, and Orderable
7.3 Feature Description...................................................11 Information.................................................................... 30
7.4 Device Functional Modes..........................................18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Note
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
SW 1 8 PGND
Pin Functions
PIN I/O (1)
WSON With DESCRIPTION
HSOIC NAME
PGOOD
Switching output of the regulator. Internally connected to both power MOSFETs.
1 1, 2 SW P
Connect to power inductor.
Boot-strap capacitor connection for high-side driver. Connect a high-quality 100nF to
2 3 BOOT P
470-nF capacitor from BOOT to SW.
Internal bias supply output for bypassing. Connect 2.2-µF, 16-V bypass capacitor from
3 4 VCC P this pin to AGND. Do not connect external loading to this pin. Never short this pin to
ground during operation.
Feedback input to regulator, connect the midpoint of feedback resistor divider to this
4 5 FB A
pin.
Open drain output for power-good flag. Use a 10-kΩ to 100-kΩ pullup resistor to logic
N/A 6 PGOOD A
rail or other DC voltage no higher than 12 V.
Enable input to regulator. High = On, Low = Off. Can be connected to VIN. Do not float.
Adjust the input undervoltage lockout with two resistors. The internal oscillator can be
5 8 EN/SYNC A
synchronized to an external clock by coupling a positive pulse into this pin through a
small coupling capacitor. See Section 7.3.3 for details.
Analog ground pin. Ground reference for internal references and logic. Connect to
6 7 AGND G
system ground.
7 9, 10 VIN P Input supply voltage.
Power ground pin, connected internally to the low side power FET. Connect to system
8 12 PGND G ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as short as
possible.
Low impedance connection to AGND. Connect to PGND on PCB. Major heat
9 13 PAD G
dissipation path of the die. Must be used for heat sinking to ground plane on PCB.
N/A 11 NC N/A Not for use. Leave this pin floating.
6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted)(1)
PARAMETER MIN MAX UNIT
VIN to PGND –0.3 42
EN/SYNC to AGND –5.5 VIN + 0.3
Input voltages FB to AGND –0.3 4.5 V
PGOOD to AGND -0.3 15
AGND to PGND –0.3 0.3
SW to PGND –1 VIN + 0.3
SW to PGND less than 10-ns transients –5 42
Output voltages V
BOOT to SW –0.3 5.5
VCC to AGND –0.3 4.5(2)
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) In shutdown mode, the VCC to AGND maximum value is 5.25 V.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) Recommended Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Section 6.5.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Determine power rating at a specific ambient temperature TA with a maximum junction temperature (TJ) of 125°C (see Section 6.3).
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER GOOD (PGOOD PIN)
Power-good flag overvoltage % of reference voltage
VPG_OV 104% 107% 110%
tripping threshold
Power-good flag undervoltage % of reference voltage
VPG_UV 92% 94% 96.5%
tripping threshold
Power-good flag recovery % of reference voltage
VPG_HY S 1.5%
hysteresis
Minimum VIN for valid PGOOD
VIN_PG_MIN 1.5
output
100 90
90 80
80 70
70
60
Efficiency (%)
Efficiency (%)
60
50
50
40
40
PFM, VIN = 8 V 30 PFM, VIN = 8 V
30 PFM, VIN = 12 V PFM, VIN = 12 V
PFM, VIN = 24 V 20 PFM, VIN = 24 V
20 FPWM, VIN = 8 V FPWM, VIN = 8 V
10 FPWM, VIN = 12 V 10 FPWM, VIN = 12 V
FPWM, VIN = 24 V FPWM, VIN = 24 V
0 0
0.0001 0.001 0.01 0.1 1 10 0.0001 0.001 0.01 0.1 1 10
IOUT (A) IOUT (A) D002
D001
Figure 6-1. Efficiency vs Load Current Figure 6-2. Efficiency vs Load Current
100 100
90 90
80 80
70 70
Efficiency (%)
60 Efficiency (%) 60
50 PFM, VIN = 8 V 50 PFM, VIN = 8 V
40 PFM, VIN = 12 V 40 PFM, VIN = 12 V
PFM, VIN = 24 V PFM, VIN = 24 V
30 PFM, VIN = 36 V 30 PFM, VIN = 36 V
FPWM, VIN = 8 V FPWM, VIN = 8 V
20 FPWM, VIN = 12 V 20 FPWM, VIN = 12 V
10 FPWM, VIN = 24 V 10 FPWM, VIN = 24 V
FPWM, VIN = 36 V FPWM, VIN = 36 V
0 0
0.0001 0.001 0.01 0.1 1 10 50 0.0001 0.001 0.01 0.1 1 10 50
IOUT (A) D003
IOUT (A) D004
fSW = 1000 kHz (Sync) VOUT = 5 V fSW = 1000 kHz (Sync) VOUT = 3.3 V
Figure 6-3. Efficiency vs Load Current Figure 6-4. Efficiency vs Load Current
5.08 5.01
VIN = 8 V VIN = 8 V
VIN = 12 V VIN = 12 V
5.06 VIN = 24 V 5 VIN = 24 V
5.04 4.99
VOUT (V)
VOUT (V)
5.02 4.98
5 4.97
4.98 4.96
4.96 4.95
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
IOUT (A) D005
IOUT (A) D006
5.5 3.6
5
3.3
4.5
VOUT (V)
VOUT (V)
3
4
70 3.64
3.63
65
3.62
60 3.61
-50 0 50 100 150 -50 0 50 100 150
Temperature (°C) Temperature (°C) D009
D008
Figure 6-9. IQ vs Junction Temperature Figure 6-10. VIN UVLO Rising Threshold vs
Junction Temperature
0.425 5.5
LS Limit
HS Limit
5
VIN UVLO Hysteresis (V)
0.42
Current Limit (A)
4.5
4
0.415
3.5
0.41
-50 0 50 100 150 3
Temperature (°C) -50 0 50 100 150
D010
Temperature (°C) D011
VIN = 12 V
Figure 6-11. VIN UVLO Hysteresis vs Junction
Figure 6-12. HS and LS Current Limit vs Junction
Temperature
Temperature
7 Detailed Description
7.1 Overview
The LMR23625 SIMPLE SWITCHER® regulator is an easy-to-use synchronous step-down DC-DC converter
operating from 4-V to 36-V supply voltage. The device delivers up to 2.5-A DC load current with good thermal
performance in a small solution size. An extended family is available in multiple current options from 1 A to 3 A in
pin-to-pin compatible packages.
The LMR23625 employs fixed frequency peak-current-mode control. The device enters PFM mode at light load
to achieve high efficiency. A user-selectable FPWM option is provided to achieve low output-voltage ripple,
tight output-voltage regulation, and constant switching frequency. The device is internally compensated, which
reduces design time and requires few external components. The LMR23625 is capable of synchronization to an
external clock within the range of 200 kHz to 2.2 MHz.
Additional features such as precision enable and internal soft start provide a flexible and easy-to-use solution for
a wide range of applications. Protection features include thermal shutdown, VIN and VCC undervoltage lockout,
cycle-by-cycle current limit, and hiccup-mode short-circuit protection.
The family requires very few external components and has a pinout designed for simple, optimum PCB layout.
7.2 Functional Block Diagram
EN/SYNC VCC
SYNC Signal
SYNC VCC
LDO VIN
Detector Enable
Precision
Internal BOOT
Enable
SS
HS I Sense
EA
REF
Rc
TSD UVLO
Cc
SYNC Signal
Oscillator LS I Sense
FB
AGND PGND
LS NMOS switches with controlled duty cycle. During high-side switch ON time, the SW pin voltage swings
up to approximately VIN, and the inductor current iL increases with linear slope (VIN – VOUT) / L. When the HS
switch is turned off by the control logic, the LS switch is turned on after an anti-shoot-through dead time. Inductor
current discharges through the LS switch with a slope of –VOUT / L. The control parameter of a buck converter is
defined as duty cycle D = tON / TSW, where tON is the high-side switch ON time and TSW is the switching period.
The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal buck
converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the
input voltage: D = VOUT / VIN.
VSW
D = tON/ TSW
SW Voltage
VIN
tON tOFF
t
0
-VD
TSW
iL
Inductor Current
ILPK
IOUT
'iL
t
0
Figure 7-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The LMR23625 employs fixed-frequency peak current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current threshold to control the
ON time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer
external components, makes it easy to design, and provides stable operation with almost any combination of
output capacitors. The regulator operates with fixed switching frequency at normal load condition. At light load
condition, the LMR23625 operates in PFM mode to maintain high efficiency (PFM option) or in FPWM mode for
low output-voltage ripple, tight output voltage regulation, and constant switching frequency (FPWM option).
7.3.2 Adjustable Output Voltage
A precision 1-V reference voltage is used to maintain a tightly regulated output voltage over the entire operating
temperature range. The output voltage is set by a resistor divider from output voltage to the FB pin. TI
recommends using 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the
low-side resistor RFBB for the desired divider current and use Equation 1 to calculate high-side RFBT. RFBT in the
range from 10 kΩ to 100 kΩ is recommended for most applications. A lower RFBT value can be used if static
loading is desired to reduce VOUT offset in PFM operation. Lower RFBT will reduce efficiency at very light load.
Less static current goes through a larger RFBT and might be more desirable when light load efficiency is critical.
However, RFBT larger than 1 MΩ is not recommended because it makes the feedback path more susceptible
to noise. Larger RFBT value requires more carefully designed feedback path on the PCB. The tolerance and
temperature variation of the resistor dividers affect the output voltage regulation.
VOUT
RFBT
FB
RFBB
VOUT VREF
RFBT u RFBB
VREF (1)
7.3.3 Enable/Sync
The voltage on the EN/SYNC pin controls the ON or OFF operation of LMR23625. A voltage less than 1 V
(typical) shuts down the device while a voltage higher than 1.6 V (typical) is required to start the regulator.
The EN/SYNC pin is an input and cannot be left open or floating. The simplest way to enable the operation of
the LMR23625 is to connect the EN to VIN. This allows self-start-up of the LMR23625 when VIN is within the
operation range.
Many applications will benefit from the employment of an enable divider RENT and RENB (Figure 7-3) to establish
a precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility
power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection,
such as a battery discharge level. An external logic signal can also be used to drive EN input for system
sequencing and protection.
VIN
RENT
EN/SYNC
RENB
The EN pin also can be used to synchronize the internal oscillator to an external clock. The internal oscillator
can be synchronized by AC coupling a positive edge into the EN pin. The AC coupled peak-to-peak voltage at
the EN pin must exceed the SYNC amplitude threshold of 2.8 V (typical) to trip the internal synchronization pulse
detector, and the minimum SYNC clock ON and OFF time must be longer than 100ns (typical). A 3.3-V or higher
amplitude pulse signal coupled through a 1-nF capacitor CSYNC is a good starting point. Keeping RENT // RENB
(RENT parallel with RENB) in the 100-kΩ range is a good choice. RENT is required for this synchronization circuit,
but RENB can be left unmounted if system UVLO is not needed. LMR23625 switching action can be synchronized
to an external clock from 200 kHz to 2.2 MHz. Figure 7-5 and Figure 7-6 show the device synchronized to an
external system clock.
VIN
CSYNC RENT
EN/SYNC
RENB
Clock
Source
Figure 7-5. Synchronizing in PWM Mode Figure 7-6. Synchronizing in PFM Mode
Given fixed TON_MIN and TOFF_MIN, the higher the switching frequency the narrower the range of the allowed
duty cycle. In the LMR23625, a frequency foldback scheme is employed to extend the maximum duty cycle
when TOFF_MIN is reached. The switching frequency decreases once longer duty cycle is needed under low VIN
conditions. A wide range of frequency foldback allows the LMR23625 output voltage stay in regulation with a
much lower supply voltage VIN. This leads to a lower effective dropout voltage.
Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution
size and efficiency. The maximum operation supply voltage can be found by:
VOUT
VIN _ MAX
fSW u TON _ MIN
(4)
At lower supply voltage, the switching frequency decreases once TOFF_MIN is tripped. The minimum VIN without
frequency foldback can be approximated by:
VOUT
VIN _ MIN
1 fSW u TOFF _ MIN
(5)
Taking considerations of power losses in the system with heavy load operation, VIN_MAX is higher than the result
calculated in Equation 4. With frequency foldback, VIN_MIN is lowered by decreased fSW.
2500
2000
Frequency (kHz)
1500
1000
IOUT = 0.5 A
IOUT = 1.0 A
500 IOUT = 1.5 A
IOUT = 2.0 A
IOUT = 2.5 A
0
4.9 5.3 5.7 6.1 6.5 6.9 7.3 7.7
VIN (V) D010
RFBT CFF
FB
RFBB
The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the crossover frequency of
the control loop to boost phase margin. The zero frequency can be found by:
1
fZ _ CFF
2S u CFF u RFBT (6)
1
fP _ CFF
2S u CFF u RFBT //RFBB (7)
The zero fZ_CFF adds phase boost at the crossover frequency and improves transient response. The pole fP-CFF
helps maintaining proper gain margin at frequency beyond the crossover. Table 8-1 lists the combination of
COUT, CFF and RFBT for typical applications, designs with similar COUT but RFBT other than recommended value,
adjust CFF so that (CFF × RFBT) is unchanged and adjust RFBB such that (RFBT / RFBB) is unchanged.
Designs with different combinations of output capacitors need different CFF. Different types of capacitors have
different equivalent series resistance (ESR). Ceramic capacitors have the smallest ESR and need the most CFF.
Electrolytic capacitors have much larger ESR than ceramic, and the ESR zero frequency location would be low
enough to boost the phase up around the crossover frequency. Designs that use mostly electrolytic capacitors at
the output may not need any CFF. The location of this ESR zero frequency can be calculated with Equation 8:
1
fZ _ESR
2S u COUT u ESR (8)
The CFF creates a time constant with RFBT that couples in the attenuate output voltage ripple to the FB node.
If the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. Therefore,
calculate CFF based on output capacitors used in the system. At cold temperatures, the value of CFF might
change based on the tolerance of the chosen component. This may reduce its impedance and ease noise
coupling on the FB node. To avoid this, more capacitance can be added to the output or the value of CFF can be
reduced.
7.3.7 Bootstrap Voltage (BOOT)
The LMR23625 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and
SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the
high-side MOSFET is off and the low-side switch conducts. TI recommends a BOOT capacitor with a value of
0.1 μF to 0.47 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or higher
is recommended for stable performance over temperature and voltage.
7.3.8 Overcurrent and Short-Circuit Protection
The LMR23625 is protected from overcurrent conditions by cycle-by-cycle current limit on both the peak and
valley of the inductor current. Hiccup mode is activated if a fault condition persists to prevent over-heating.
High-side MOSFET over-current protection is implemented by the nature of the peak-current-mode control. The
HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is
compared to the output of the error amplifier (EA) minus slope compensation every switching cycle. See Section
7.2 for more details. The peak current of HS switch is limited by a clamped maximum peak-current threshold
IHS_LIMIT which is constant. Thus, the peak current limit of the high-side switch is not affected by the slope
compensation and remains constant over the full duty cycle range.
The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor
current begins to ramp down. The LS switch will not be turned OFF at the end of a switching cycle if its current is
above the LS current limit ILS_LIMIT. The LS switch is kept ON so that inductor current keeps ramping down until
the inductor current ramps below the LS current limit ILS_LIMIT. Then the LS switch is turned OFF, and the HS
switch will be turned on after a dead time. This is somewhat different than the more typical peak current limit and
results in Equation 9 for the maximum load current.
If the current of the LS switch is higher than the LS current limit for 64 consecutive cycles, hiccup-current-
protection mode is activated. In hiccup mode, the regulator is shut down and kept off for 5 ms typically before
the LMR23625 tries to start again. If an overcurrent or short-circuit fault condition still exists, hiccup repeats
until the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions,
prevents over-heating and potential damage to the device.
For FPWM option, the inductor current is allowed to go negative. Should this current exceed IL_NEG, the LS
switch is turned off until the next clock cycle. This is used to protect the LS switch from excessive negative
current.
The external components must fulfill the needs of the application, but also the stability criteria of the device
control loop. Table 8-1 can be used to simplify the output filter component selection.
Table 8-1. L, COUT and CFF Typical Values
fSW (kHz) VOUT (V) L (µH) (1) COUT (µF) (2) CFF (pF) RFBT (kΩ)(3) (4)
2100 3.3 2.2 47 33 51
2100 5 2.2 33 18 88.7
VOUT VREF
RFBT u RFBB
VREF (10)
Choose the value of RFBB to be 22.1 kΩ. With the desired output voltage set to 5 V and the VREF = 1 V, the RFBB
value can then be calculated using Equation 10. The formula yields to a value 88.7 kΩ.
8.2.2.3 Switching Frequency
The default switching frequency of the LMR23625 is 2100 kHz. For other switching frequencies, the device must
be synchronized to an external clock ( see Section 7.3.3 for more details).
8.2.2.4 Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current, and the rated current. The
inductance is based on the desired peak-to-peak ripple current ΔiL. Because the ripple current increases with
the input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use
Equation 12 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the
amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of
KIND must be 20% to 40%. During an instantaneous short or over current operation event, the RMS and peak
inductor current can be high. The inductor current rating must be higher than the current limit of the device.
In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. However,
inductance that is too low can generate an inductor current ripple that is too high so that overcurrent protection
at the full load may be falsely triggered. It also generates more conduction loss and inductor core loss. Larger
inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak-current-
mode control, TI does not recommend having an inductor current ripple that is too small. A larger peak current
ripple improves the comparator signal-to-noise ratio.
For this design example, choose KIND = 0.4, the minimum inductor value is calculated to be 1.9 µH. Choose the
nearest standard 2.2 μH ferrite inductor with a capability of 3.5-A RMS current and 6-A saturation current.
8.2.2.5 Output Capacitor Selection
Choose the output capacitor(s), COUT, with care because it directly affects the steady-state output-voltage ripple,
loop stability, and the voltage over/undershoot during load-current transients.
The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going
through the ESR of the output capacitors:
The other is caused by the inductor current ripple charging and discharging the output capacitors:
The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the
sum of two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew rate. When a fast large load increase happens,
output capacitors provide the required charge before the inductor current can slew up to the appropriate level.
The control loop of the regulator usually needs four or more clock cycles to respond to the output voltage droop.
The output capacitance must be large enough to supply the current difference for four clock cycles to maintain
the output voltage within the specified range. Equation 15 shows the minimum output capacitance needed
for specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb
energy stored in the inductor. which results in an output voltage overshoot. Equation 16 calculates the minimum
capacitance required to keep the voltage overshoot within a specified range.
4 u IOH IOL
COUT !
fSW u VUS (15)
2 2
IOH IOL
COUT ! 2
uL
2
VOUT VOS VOUT (16)
where
• IOL = Low level output current during load transient
• IOH = High level output current during load transient
• VUS = Target output voltage undershoot
• VOS = Target output voltage overshoot
For this design example, the target output ripple is 50 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 50 mV, and
chose KIND = 0.4. Equation 13 yields ESR no larger than 50 mΩ and Equation 14 yields COUT no smaller than
1.2 μF. For the target over/undershoot range of this design, VUS = VOS = 5% × VOUT = 250 mV. The COUT can be
calculated to be no smaller than 17.5 μF and 5.3 μF by Equation 15 and Equation 16, respectively. Consider of
derating, one 33-μF, 16-V ceramic capacitor with 5-mΩ ESR is used.
8.2.2.6 Feed-forward Capacitor
The LMR23625 is internally compensated. Depending on the VOUT and frequency fSW, if the output capacitor
COUT is dominated by low ESR (ceramic type) capacitors, it could result in low phase margin. To improve
the phase boost an external feed-forward capacitor CFF can be added in parallel with RFBT. Choose CFF so
that phase margin is boosted at the crossover frequency without CFF. A simple estimation for the crossover
frequency (fX) without CFF is shown in Equation 17, assuming COUT has very small ESR, and COUT value is after
derating.
8.32
fX
VOUT u COUT (17)
1
CFF
4S u fX u RFBT (18)
For designs with higher ESR, CFF is not needed when COUT has very high ESR, and CFF calculated from
Equation 18 should be reduced with medium ESR. Table 8-1 can be used as a quick starting point.
For the application in this design example, a 18-pF, 50-V, COG capacitor is selected.
8.2.2.7 Input Capacitor Selection
The LMR23625 device requires high-frequency input decoupling capacitor(s) and a bulk input capacitor,
depending on the application. The typical recommended value for the high-frequency decoupling capacitor is
4.7 μF to 10 μF. TI recommends a high-quality ceramic capacitor type X5R or X7R with sufficiency voltage
rating. To compensate the derating of ceramic capacitors, a voltage rating twice the maximum input voltage is
recommended. Additionally, some bulk capacitance can be required, especially if the LMR23625 circuit is not
located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to
the voltage spike due to the lead inductance of the cable or the trace. For this design, two 4.7-μF, 50-V, X7R
ceramic capacitors are used. A 0.1-μF for high-frequency filtering and place it as close as possible to the device
pins.
8.2.2.8 Bootstrap Capacitor Selection
Every LMR23625 design requires a bootstrap capacitor (CBOOT). TI recommends a capacitor of 0.47 μF, ated 16
V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap capacitor
must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.
RENT RENB
VIN _ RISING VENH u
RENB (19)
The EN rising threshold (VENH) for LMR23625 is set to be 1.55 V (typical). Choose the value of RENB to be 287
kΩ to minimize input current from the supply. If the desired V IN UVLO level is at 6.0 V, then the value of RENT can
be calculated using Equation 20:
§ VIN _ RISING ·
RENT ¨¨ 1¸¸ u RENB
© VENH ¹ (20)
Equation 20 yields a value of 820 kΩ. The resulting falling UVLO threshold, equals 4.4 V, can be calculated by
Equation 21, where EN hysteresis (VEN_HYS) is 0.4 V (typical).
RENT RENB
VIN _ FALLING VENH VEN _ HYS u
RENB (21)
Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 2100 kHz, L = 2.2 µH, COUT = 47 µF, TA = 25 °C.
VOUT = 5 V IOUT = 2.5 A fSW = 2100 kHz VOUT = 5 V IOUT = 100 mA fSW = 2100 kHz
VOUT = 5 V IOUT = 0 mA fSW = 2100 kHz VOUT = 5 V IOUT = 0 mA fSW = 2100 kHz
Output Bypass
Output Inductor Capacitor
Input Bypass
SW Capacitor
PGND
BOOT Capacitor
BOOT VIN
VCC AGND
VCC
Capacitor FB EN/
SYNC
SW PGND
Input Bypass
SW NC
Capacitor
BOOT
Capacitor
BOOT VIN
VCC
VCC VIN
Capacitor
FB EN/SYNC
UVLO Adjust
PGOOD AGND Resistor
Thermal
Output VIA
Voltage Set VIA (Connect to GND
Resistor Plane)
TJ = PD × RθJA + TA (22)
where
• TJ = junction temperature in °C
• PD = device power dissipation in watt
• RθJA = junction-to-ambient thermal resistance of the device in °C/W
• TA = ambient temperature in °C
• DCR = inductor DC parasitic resistance in ohm
The recommended operating junction temperature of the LMR23625 is 125°C. RθJA is highly related to PCB size
and layout, as well as environmental factors such as heat sinking and air flow.
11.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 25-Jan-2021
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
LMR23625CDDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 F25C
LMR23625CDDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 F25C
LMR23625CFDDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 F25CF
LMR23625CFDDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 F25CF
LMR23625CFPDRRR ACTIVE WSON DRR 12 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 3625P
LMR23625CFPDRRT ACTIVE WSON DRR 12 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 3625P
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 25-Jan-2021
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive: LMR23625-Q1
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2022
TUBE
Pack Materials-Page 3
PACKAGE OUTLINE
DRR0012D SCALE 4.000
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
3.1 B
A
2.9
(0.05)
SECTION A-A
SECTION A-A
SCALE 30.000
TYPICAL
0.8 C
0.7
SEATING PLANE
0.05
0.00 0.08 C
A A
2X 13
2.5 2.5 0.1
1
12
10X 0.5 0.3
0.38 12X
12X 0.2
PIN 1 ID 0.28
(OPTIONAL) 0.1 C A B
0.05 C
4223146/D 10/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRR0012D WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.7)
12X (0.53) SYMM
1
12
12X (0.25)
13
SYMM
10X (0.5) (2.5)
(1)
(R0.05) TYP
6
7
(0.6)
( 0.2) VIA
TYP (2.87)
4223146/D 10/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRR0012D WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
12X (0.25)
METAL
TYP
(0.675)
SYMM
13
10X (0.5)
(1.15)
(R0.05) TYP
6
7
(0.74)
(2.87)
EXPOSED PAD
80.1% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4223146/D 10/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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