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LMR 23625

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LMR23625

SNVSAH3E – FEBRUARY 2018 – REVISED JULY 2020

LMR23625 SIMPLE SWITCHER® 36-V, 2.5-A Synchronous Step-Down Converter

1 Features 3 Description
• 4-V to 36-V input range The LMR23625 SIMPLE SWITCHER® is an easy-to-
• 2.5-A continuous output current use 36-V, 2.5-A synchronous step-down regulator.
• Integrated synchronous rectification With a wide input range from 4 V to 36 V, the
• Current mode control device is suitable for various industrial application
• Minimum switch ON time: 60 ns for power conditioning from unregulated sources.
• 2.1-MHz switching frequency with PFM and Peak current-mode control is employed to achieve
forced-PWM-mode options (HSOIC) simple control-loop compensation and cycle-by-cycle
• 2.1-MHz switching frequency with forced-PWM current limiting. A quiescent current of 75 μA makes
mode only (WSON) it suitable for battery-powered systems. An ultra-low
• Frequency synchronization to external clock 2 μA shutdown current can further prolong battery
• Internal compensation for ease of use life. Internal loop compensation means that the user
• 75-µA quiescent current at no load is free from the tedious task of loop compensation
• Soft start into a prebiased load design. This also minimizes the external components.
• High duty-cycle operation supported The device has an option for fixed-frequency FPWM
• Precision enable input mode to achieve small output-voltage ripple at light
• Output short-circuit protection with hiccup mode load. An extended family for HSOIC is available in
• Thermal protection 1-A (LMR23610) and 3-A (LMR23630) load current
• 8-Pin HSOIC with PowerPAD™ package options in pin-to-pin compatible packages which
• 12-Pin WSON wettable flanks package with allows simple, optimum PCB layout. A precision
PowerPAD™ enable input allows simplification of regulator control
• Use the LMZM33603 module for faster time to and system power sequencing. Protection features
market include cycle-by-cycle current limit, hiccup-mode
• Create a custom design using the LMR23625 with short-circuit protection and thermal shutdown due to
the WEBENCH® Power Designer excessive power dissipation.
2 Applications Device Information
PART NUMBER (1) PACKAGE BODY SIZE (NOM)
• Factory and building automation systems: PLC
CPU, HVAC control, elevator control HSOIC (8) 4.89 mm × 3.90 mm
LMR23625
• GSM, GPRS modules for fleet management, smart WSON (12) 3.00 mm × 3.00 mm
grids, and security
(1) For all available packages, see the orderable addendum at
• General purpose wide VIN regulation the end of the data sheet.

space
VIN up to 36 V 100

CIN
VIN
90
EN/SYNC BOOT
CBOOT
L
Efficiency (%)

VOUT
AGND SW 80

RFBT
COUT 70
RFBB
VCC FB
CVCC
PGND 60
VOUT = 5 V
VOUT = 3.3 V
50
Simplified Schematic 0.0001 0.001 0.01 0.1 1 10
IOUT (A) D000

Efficiency vs Load VIN = 12 V, PFM Option

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR23625
SNVSAH3E – FEBRUARY 2018 – REVISED JULY 2020 www.ti.com

Table of Contents
1 Features............................................................................1 8 Application and Implementation.................................. 19
2 Applications..................................................................... 1 8.1 Application Information............................................. 19
3 Description.......................................................................1 8.2 Typical Applications.................................................. 19
4 Revision History.............................................................. 2 9 Power Supply Recommendations................................26
5 Pin Configuration and Functions...................................4 10 Layout...........................................................................26
Pin Functions.................................................................... 4 10.1 Layout Guidelines................................................... 26
6 Specifications.................................................................. 5 10.2 Layout Example...................................................... 27
6.1 Absolute Maximum Ratings........................................ 5 10.3 Compact Layout for EMI Reduction........................ 28
6.2 ESD Ratings............................................................... 5 10.4 Ground Plane and Thermal Considerations............28
6.3 Recommended Operating Conditions.........................5 10.5 Feedback Resistors................................................ 29
6.4 Thermal Information....................................................6 11 Device and Documentation Support..........................30
6.5 Electrical Characteristics.............................................6 11.1 Device Support........................................................30
6.6 Timing Requirements.................................................. 8 11.2 Receiving Notification of Documentation Updates.. 30
6.7 Switching Characteristics............................................8 11.3 Support Resources................................................. 30
6.8 Typical Characteristics................................................ 9 11.4 Trademarks............................................................. 30
7 Detailed Description...................................................... 11 11.5 Electrostatic Discharge Caution.............................. 30
7.1 Overview................................................................... 11 11.6 Glossary.................................................................. 30
7.2 Functional Block Diagram......................................... 11 12 Mechanical, Packaging, and Orderable
7.3 Feature Description...................................................11 Information.................................................................... 30
7.4 Device Functional Modes..........................................18

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (February 2018) to Revision E (July 2020) Page


• Added LMZM33603 bullet to Section 1 ..............................................................................................................1
• Updated the numbering format for tables, figures and cross-references throughout the document...................1

Changes from Revision C (June 2017) to Revision D (February 2018) Page


• Changed HSOIC and WSON Input Range to 4V to 36V from 4.5V for HSOIC and 4V for WSON.................... 1
• Changed Programmable Logic Controller Power Supply to Factory and Building Automation System... in
Applications ....................................................................................................................................................... 1
• Deleted Multi-Function Printers and Industrial Power Supplies and reworded Applications ............................. 1
• Changed HVAC Systems from Applications to General Purpose Wide VIN Regulation ................................... 1
• Removing RT row on the Pin Functions ............................................................................................................ 4
• Added "2.2-µF, 16-V" for VCC pin bypass capacitor ..........................................................................................4
• Added PGOOD to AGND row on Absolute Maximum Ratings .......................................................................... 5
• Consolidating all the common EC table characteristic between HSOIC and WSON, for example Operation
Input Voltage, VIN_UVLO, IEN and Mnimum turn-on time ................................................................................. 6
• Changed Typical Value for VIN_UVLO Rising threshold typical from 3.6-V to 3.7-V .........................................6
• Removing VEN = 0 V, VIN = 4.5 V to 36 V, TJ = –40°C to 125°C (HSOIC) Test Condition.................................. 6
• Changed the operating from "4.5-V" ... to "4-V" in Device Functional Modes ..................................................18
• Changed from VOUT = 7 V to 36 V to VIN = 7 V to 36 V on Figure 8-9 .............................................................24

Changes from Revision B (April 2017) to Revision C (June 2017) Page


• Deleted "Automotive Battery Regulation" and reworded Applications ...............................................................1
• Added details of WSON package throughout data sheet .................................................................................. 1
• Added Device Comparison Table .................................................................................................................. 0
• Change EN Abs Max to EN/SYNC Abs Max ..................................................................................................... 5
• Adding VCCABS Max Table Note ......................................................................................................................5
• Updating ESD Ratings to include HSOIC and WSON .......................................................................................5
• Adding PGOOD input voltage.............................................................................................................................5

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• Adding PGOOD pin current ............................................................................................................................... 5


• Corrected denominator of equation 16 from "(VOUT x VOS)" to "(VOUT + VOS)" ............................................... 21
• clarified equations equation 22 and equation 23.............................................................................................. 28

Changes from Revision A (July 2016) to Revision B (April 2017) Page


• Changed high side current limit to 6.2 from 6.0.................................................................................................. 6
• Changed low side current limit to 4.2 from 4.6................................................................................................... 6
• Changed all the four efficiency graphs D001, D002, D003 and D004 in the Typical Characteristics section..... 9

Note
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (December 2015) to Revision A (July 2016) Page


• Changed from Product Preview to Production Data and added all the remaining sections............................... 1

Device Comparison Table


ADJUSTABLE
PACKAGE PART NUMBER FIXED 2.1 MHz FREQUENCY POWER GOOD FPWM
RESISTOR
LMR23625CDDA yes no no no
HSOIC (8)
LMR23625CFDDA yes no no yes
WSON (12) LMR23625CFPDRR yes no yes yes

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5 Pin Configuration and Functions

SW 1 8 PGND

BOOT 2 Thermal Pad 7 VIN


(9)
VCC 3 6 AGND

FB 4 5 EN/SYNC Figure 5-2. DRR Package 12-Pin WSON With


PGOOD and Thermal Pad Top View

Figure 5-1. DDA Package 8-Pin HSOIC Top View

Pin Functions
PIN I/O (1)
WSON With DESCRIPTION
HSOIC NAME
PGOOD
Switching output of the regulator. Internally connected to both power MOSFETs.
1 1, 2 SW P
Connect to power inductor.
Boot-strap capacitor connection for high-side driver. Connect a high-quality 100nF to
2 3 BOOT P
470-nF capacitor from BOOT to SW.
Internal bias supply output for bypassing. Connect 2.2-µF, 16-V bypass capacitor from
3 4 VCC P this pin to AGND. Do not connect external loading to this pin. Never short this pin to
ground during operation.
Feedback input to regulator, connect the midpoint of feedback resistor divider to this
4 5 FB A
pin.
Open drain output for power-good flag. Use a 10-kΩ to 100-kΩ pullup resistor to logic
N/A 6 PGOOD A
rail or other DC voltage no higher than 12 V.
Enable input to regulator. High = On, Low = Off. Can be connected to VIN. Do not float.
Adjust the input undervoltage lockout with two resistors. The internal oscillator can be
5 8 EN/SYNC A
synchronized to an external clock by coupling a positive pulse into this pin through a
small coupling capacitor. See Section 7.3.3 for details.
Analog ground pin. Ground reference for internal references and logic. Connect to
6 7 AGND G
system ground.
7 9, 10 VIN P Input supply voltage.
Power ground pin, connected internally to the low side power FET. Connect to system
8 12 PGND G ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as short as
possible.
Low impedance connection to AGND. Connect to PGND on PCB. Major heat
9 13 PAD G
dissipation path of the die. Must be used for heat sinking to ground plane on PCB.
N/A 11 NC N/A Not for use. Leave this pin floating.

(1) I = Input, O = Output, G = Ground.

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6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted)(1)
PARAMETER MIN MAX UNIT
VIN to PGND –0.3 42
EN/SYNC to AGND –5.5 VIN + 0.3
Input voltages FB to AGND –0.3 4.5 V
PGOOD to AGND -0.3 15
AGND to PGND –0.3 0.3
SW to PGND –1 VIN + 0.3
SW to PGND less than 10-ns transients –5 42
Output voltages V
BOOT to SW –0.3 5.5
VCC to AGND –0.3 4.5(2)
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) In shutdown mode, the VCC to AGND maximum value is 5.25 V.

6.2 ESD Ratings


VALUE UNIT
Human-body model (HBM) for HSOIC (1) ±2000

Electrostatic Human-body model (HBM) for WSON with PGOOD ±2500


V(ESD) V
discharge Charged-device model (CDM) for HSOIC(2) ±1000
Charged-device model (CDM) for WSON PGOOD(2) ±750

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions


Over the recommended operating junction temperature range of –40°C to 125°C (unless otherwise noted) (1)
MIN MAX UNIT
VIN 4 36
EN/SYNC –5 36
Input voltage V
FB –0.3 1.2
PGOOD –0.3 12
Input current PGOOD pin current 0 1 mA
Output voltage VOUT 1 28 V
Output vurrent IOUT 0 2.5 A
Temperature Operating junction temperature, TJ –40 125 °C

(1) Recommended Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Section 6.5.

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6.4 Thermal Information


THERMAL METRIC(1) (2) DDA (8 PINS) DRR (12 PINS) UNIT
RθJA Junction-to-ambient thermal resistance 42.0 41.5 °C/W
ψJT Junction-to-top characterization parameter 5.9 0.3 °C/W
ψJB Junction-to-board characterization parameter 23.4 16.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 45.8 39.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.6 3.4 °C/W
RθJB Junction-to-board thermal resistance 23.4 16.3 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Determine power rating at a specific ambient temperature TA with a maximum junction temperature (TJ) of 125°C (see Section 6.3).

6.5 Electrical Characteristics


Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY (VIN PIN)
VIN Operation input voltage 4 36 V

Undervoltage lockout Rising threshold 3.3 3.7 3.9 V


VIN_UVLO
thresholds Falling threshold 2.9 3.3 3.5 V
ISHDN Shutdown supply current VEN = 0 V, VIN = 12 V, TJ = –40°C to 125°C 2 4 μA
Operating quiescent current VIN =12 V, VFB = 1.1 V, TJ = –40°C to 125°C,
IQ 75 μA
(non- switching) PFM mode
ENABLE (EN/SYNC PIN)
VEN_H Enable rising threshold Voltage 1.4 1.55 1.7 V
VEN_HYS Enable hysteresis voltage 0.4 V
VWAKE Wake-up threshold 0.4 V
VIN = 4 V to 36 V, VEN= 2 V 10 100 nA
IEN Input leakage current at EN pin
VIN = 4 V to 36 V, VEN = 36 V 1 μA
VOLTAGE REFERENCE (FB PIN)
VIN = 4 V to 36 V, TJ = 25°C 0.985 1 1.015
VREF Reference voltage V
VIN = 4 V to 36 V, TJ =–40°C to 125°C 0.98 1 1.02
ILKG_FB Input leakage current at FB pin VFB = 1 V 10 nA

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Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER GOOD (PGOOD PIN)
Power-good flag overvoltage % of reference voltage
VPG_OV 104% 107% 110%
tripping threshold
Power-good flag undervoltage % of reference voltage
VPG_UV 92% 94% 96.5%
tripping threshold
Power-good flag recovery % of reference voltage
VPG_HY S 1.5%
hysteresis
Minimum VIN for valid PGOOD
VIN_PG_MIN 1.5
output

PGOOD low level output 0.4


VPG_LOW
voltage 0.4
INTERNAL LDO (VCC PIN)
VCC Internal LDO output voltage 4.1 V

VCC undervoltage lockout Rising threshold 2.8 3.2 3.6


VCC_UVLO V
thresholds Falling threshold 2.4 2.8 3.2
CURRENT LIMIT
HSOIC package 3.6 4.8 6.2
IHS_LIMIT Peak inductor current limit A
WSON package 4.0 5.5 6.6
ILS_LIMIT HSOIC package 2.8 3.5 4.6
Valley inductor current limit A
WSON package 2.9 3.6 4.2
IL_ZC Zero cross current limit HSOIC and WSON packages –0.04 A
IL_NEG Negative current limit (FPWM
HSOIC and WSON packages –2.7 –2 –1.3 A
Option)
INTEGRATED MOSFETS

High-side MOSFET ON- HSOIC package, VIN = 12 V, IOUT = 1 A 185


RDS_ON_HS mΩ
resistance WSON package, VIN = 12 V, IOUT = 1 A 160

Low-side MOSFET ON- HSOIC package, VIN = 12 V, IOUT = 1 A 105


RDS_ON_LS mΩ
resistance WSON package, VIN = 12 V, IOUT = 1 A 95
THERMAL SHUTDOWN
TSHDN Thermal shutdown threshold 162 170 178 °C
THYS Hysteresis 15 °C

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6.6 Timing Requirements


Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)
MIN NOM MAX UNIT
HICCUP MODE
Number of cycles that LS current
NOC (1) limit is tripped to enter hiccup 64 Cycles
mode
Hiccup retry delay time HSOIC package 5
TOC ms
WSON package 10
SOFT START
HSOIC package, the time of internal
2 ms
reference to increase from 0 V to 1 V
TSS Internal soft-start time
WSON package, the time of internal
6 ms
reference to increase from 0 V to 1 V
POWER GOOD
Power-good flag rising transition
TPGOOD_RISE 150 μs
deglitch delay
Power-good flag falling transition
TPGOOD_FALL 18 μs
deglitch delay

(1) Ensured by design.

6.7 Switching Characteristics


Over the recommended operating junction temperature range of –40°C to +125°C (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
SW (SW PIN)
fSW Default switching frequency 1785 2100 2415 kHz
TON_MIN Minimum turnon time WSON package 60 90 ns
TOFF_MIN (1) Minimum turnoff time 100 ns
SYNC (EN/SYNC PIN)
fSYNC SYNC frequency range 200 2200 kHz
VSYNC Amplitude of SYNC clock AC signal (measured at SYNC pin) 2.8 5.5 V
TSYNC_MIN Minimum sync clock ON and OFF time 100 ns

(1) Specified by design.

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6.8 Typical Characteristics


Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 2100 kHz, L = 2.2 µH, COUT = 47 µF,
TA = 25 °C.

100 90
90 80
80 70
70
60

Efficiency (%)
Efficiency (%)

60
50
50
40
40
PFM, VIN = 8 V 30 PFM, VIN = 8 V
30 PFM, VIN = 12 V PFM, VIN = 12 V
PFM, VIN = 24 V 20 PFM, VIN = 24 V
20 FPWM, VIN = 8 V FPWM, VIN = 8 V
10 FPWM, VIN = 12 V 10 FPWM, VIN = 12 V
FPWM, VIN = 24 V FPWM, VIN = 24 V
0 0
0.0001 0.001 0.01 0.1 1 10 0.0001 0.001 0.01 0.1 1 10
IOUT (A) IOUT (A) D002
D001

fSW = 2100 kHz VOUT = 5 V fSW = 2100 kHz VOUT = 3.3 V

Figure 6-1. Efficiency vs Load Current Figure 6-2. Efficiency vs Load Current
100 100
90 90
80 80
70 70
Efficiency (%)

60 Efficiency (%) 60
50 PFM, VIN = 8 V 50 PFM, VIN = 8 V
40 PFM, VIN = 12 V 40 PFM, VIN = 12 V
PFM, VIN = 24 V PFM, VIN = 24 V
30 PFM, VIN = 36 V 30 PFM, VIN = 36 V
FPWM, VIN = 8 V FPWM, VIN = 8 V
20 FPWM, VIN = 12 V 20 FPWM, VIN = 12 V
10 FPWM, VIN = 24 V 10 FPWM, VIN = 24 V
FPWM, VIN = 36 V FPWM, VIN = 36 V
0 0
0.0001 0.001 0.01 0.1 1 10 50 0.0001 0.001 0.01 0.1 1 10 50
IOUT (A) D003
IOUT (A) D004

fSW = 1000 kHz (Sync) VOUT = 5 V fSW = 1000 kHz (Sync) VOUT = 3.3 V

Figure 6-3. Efficiency vs Load Current Figure 6-4. Efficiency vs Load Current
5.08 5.01
VIN = 8 V VIN = 8 V
VIN = 12 V VIN = 12 V
5.06 VIN = 24 V 5 VIN = 24 V

5.04 4.99
VOUT (V)

VOUT (V)

5.02 4.98

5 4.97

4.98 4.96

4.96 4.95
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
IOUT (A) D005
IOUT (A) D006

PFM Option VOUT = 5 V FPWM Option VOUT = 5 V

Figure 6-5. Load Regulation Figure 6-6. Load Regulation

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5.5 3.6

5
3.3

4.5
VOUT (V)

VOUT (V)
3
4

IOUT = 0.5 A IOUT = 0.5 A


IOUT = 1.0 A 2.7 IOUT = 1.0 A
3.5 IOUT = 1.5 A IOUT = 1.5 A
IOUT = 2.0 A IOUT = 2.0 A
IOUT = 2.5 A IOUT = 2.5 A
3 2.4
4 4.5 5 5.5 6 3.3 3.5 3.7 3.9 4.1 4.3 4.5
VIN (V) D007
VIN (V) D008

VOUT = 5 V VOUT = 3.3 V

Figure 6-7. Dropout Curve Figure 6-8. Dropout Curve


80 3.67

VIN UVLO Rising Threshold (V)


3.66
75
3.65
IQ (µA)

70 3.64

3.63
65
3.62

60 3.61
-50 0 50 100 150 -50 0 50 100 150
Temperature (°C) Temperature (°C) D009
D008

VIN = 12 V VFB = 1.1 V

Figure 6-9. IQ vs Junction Temperature Figure 6-10. VIN UVLO Rising Threshold vs
Junction Temperature
0.425 5.5
LS Limit
HS Limit
5
VIN UVLO Hysteresis (V)

0.42
Current Limit (A)

4.5

4
0.415

3.5

0.41
-50 0 50 100 150 3
Temperature (°C) -50 0 50 100 150
D010
Temperature (°C) D011

VIN = 12 V
Figure 6-11. VIN UVLO Hysteresis vs Junction
Figure 6-12. HS and LS Current Limit vs Junction
Temperature
Temperature

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7 Detailed Description
7.1 Overview
The LMR23625 SIMPLE SWITCHER® regulator is an easy-to-use synchronous step-down DC-DC converter
operating from 4-V to 36-V supply voltage. The device delivers up to 2.5-A DC load current with good thermal
performance in a small solution size. An extended family is available in multiple current options from 1 A to 3 A in
pin-to-pin compatible packages.
The LMR23625 employs fixed frequency peak-current-mode control. The device enters PFM mode at light load
to achieve high efficiency. A user-selectable FPWM option is provided to achieve low output-voltage ripple,
tight output-voltage regulation, and constant switching frequency. The device is internally compensated, which
reduces design time and requires few external components. The LMR23625 is capable of synchronization to an
external clock within the range of 200 kHz to 2.2 MHz.
Additional features such as precision enable and internal soft start provide a flexible and easy-to-use solution for
a wide range of applications. Protection features include thermal shutdown, VIN and VCC undervoltage lockout,
cycle-by-cycle current limit, and hiccup-mode short-circuit protection.
The family requires very few external components and has a pinout designed for simple, optimum PCB layout.
7.2 Functional Block Diagram
EN/SYNC VCC

SYNC Signal
SYNC VCC
LDO VIN
Detector Enable

Precision
Internal BOOT
Enable
SS
HS I Sense

EA
REF

Rc

TSD UVLO
Cc

PFM PWM CONTROL LOGIC SW


Detector
OV/UV
Detector
FB
Slope
Comp
Freq Zero HICCUP
Foldback Cross Detector

SYNC Signal

Oscillator LS I Sense

FB

AGND PGND

7.3 Feature Description


7.3.1 Fixed-Frequency Peak-Current-Mode Control
The following operating description of the LMR23625 refers to Section 7.2 and to the waveforms in Figure 7-1.
The LMR23625 device is a step-down synchronous buck regulator with integrated high-side (HS) and low-side
(LS) switches (synchronous rectifier). The device supplies a regulated output voltage by turning on the HS and

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LS NMOS switches with controlled duty cycle. During high-side switch ON time, the SW pin voltage swings
up to approximately VIN, and the inductor current iL increases with linear slope (VIN – VOUT) / L. When the HS
switch is turned off by the control logic, the LS switch is turned on after an anti-shoot-through dead time. Inductor
current discharges through the LS switch with a slope of –VOUT / L. The control parameter of a buck converter is
defined as duty cycle D = tON / TSW, where tON is the high-side switch ON time and TSW is the switching period.
The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal buck
converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to the
input voltage: D = VOUT / VIN.
VSW
D = tON/ TSW

SW Voltage
VIN

tON tOFF
t
0
-VD
TSW
iL
Inductor Current

ILPK

IOUT
'iL

t
0

Figure 7-1. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)

The LMR23625 employs fixed-frequency peak current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current threshold to control the
ON time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer
external components, makes it easy to design, and provides stable operation with almost any combination of
output capacitors. The regulator operates with fixed switching frequency at normal load condition. At light load
condition, the LMR23625 operates in PFM mode to maintain high efficiency (PFM option) or in FPWM mode for
low output-voltage ripple, tight output voltage regulation, and constant switching frequency (FPWM option).
7.3.2 Adjustable Output Voltage
A precision 1-V reference voltage is used to maintain a tightly regulated output voltage over the entire operating
temperature range. The output voltage is set by a resistor divider from output voltage to the FB pin. TI
recommends using 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the
low-side resistor RFBB for the desired divider current and use Equation 1 to calculate high-side RFBT. RFBT in the
range from 10 kΩ to 100 kΩ is recommended for most applications. A lower RFBT value can be used if static
loading is desired to reduce VOUT offset in PFM operation. Lower RFBT will reduce efficiency at very light load.
Less static current goes through a larger RFBT and might be more desirable when light load efficiency is critical.
However, RFBT larger than 1 MΩ is not recommended because it makes the feedback path more susceptible
to noise. Larger RFBT value requires more carefully designed feedback path on the PCB. The tolerance and
temperature variation of the resistor dividers affect the output voltage regulation.
VOUT

RFBT

FB

RFBB

Figure 7-2. Output Voltage Setting

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VOUT VREF
RFBT u RFBB
VREF (1)

7.3.3 Enable/Sync
The voltage on the EN/SYNC pin controls the ON or OFF operation of LMR23625. A voltage less than 1 V
(typical) shuts down the device while a voltage higher than 1.6 V (typical) is required to start the regulator.
The EN/SYNC pin is an input and cannot be left open or floating. The simplest way to enable the operation of
the LMR23625 is to connect the EN to VIN. This allows self-start-up of the LMR23625 when VIN is within the
operation range.
Many applications will benefit from the employment of an enable divider RENT and RENB (Figure 7-3) to establish
a precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility
power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection,
such as a battery discharge level. An external logic signal can also be used to drive EN input for system
sequencing and protection.

VIN

RENT

EN/SYNC

RENB

Figure 7-3. System UVLO by Enable Divider

The EN pin also can be used to synchronize the internal oscillator to an external clock. The internal oscillator
can be synchronized by AC coupling a positive edge into the EN pin. The AC coupled peak-to-peak voltage at
the EN pin must exceed the SYNC amplitude threshold of 2.8 V (typical) to trip the internal synchronization pulse
detector, and the minimum SYNC clock ON and OFF time must be longer than 100ns (typical). A 3.3-V or higher
amplitude pulse signal coupled through a 1-nF capacitor CSYNC is a good starting point. Keeping RENT // RENB
(RENT parallel with RENB) in the 100-kΩ range is a good choice. RENT is required for this synchronization circuit,
but RENB can be left unmounted if system UVLO is not needed. LMR23625 switching action can be synchronized
to an external clock from 200 kHz to 2.2 MHz. Figure 7-5 and Figure 7-6 show the device synchronized to an
external system clock.

VIN

CSYNC RENT

EN/SYNC

RENB
Clock
Source

Figure 7-4. Synchronize to External Clock

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Figure 7-5. Synchronizing in PWM Mode Figure 7-6. Synchronizing in PFM Mode

7.3.4 VCC, UVLO


The LMR23625 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The
nominal voltage for VCC is 4.1 V. The VCC pin is the output of an LDO and must be properly bypassed. Place a
high-quality ceramic capacitor with a value of 2.2 µF to 10 µF, 16 V or higher rated voltage as close as possible
to VCC and grounded to the exposed PAD and ground pins. The VCC output pin must not be loaded, or shorted
to ground during operation. Shorting VCC to ground during operation may cause damage to the LMR23625.
VCC undervoltage lockout (UVLO) prevents the LMR23625 from operating until the VCC voltage exceeds 3.3 V
(typical). The VCC UVLO threshold has 400 mV (typical) of hysteresis to prevent undesired shutdown due to
temporary VIN drops.
7.3.5 Minimum ON-time, Minimum OFF-time and Frequency Foldback at Drop-out Conditions
Minimum ON-time, TON_MIN, is the smallest duration of time that the HS switch can be on. TON_MIN is typically
60 ns in the LMR23625. Minimum OFF-time, TOFF_MIN, is the smallest duration that the HS switch can be
off. TOFF_MIN is typically 100 ns in the LMR23625. In CCM operation, TON_MIN and TOFF_MIN limit the voltage
conversion range given a selected switching frequency.
The minimum duty cycle allowed is:

DMIN = TON_MIN × fSW (2)

And the maximum duty cycle allowed is:

DMAX = 1 – TOFF_MIN × fSW (3)

Given fixed TON_MIN and TOFF_MIN, the higher the switching frequency the narrower the range of the allowed
duty cycle. In the LMR23625, a frequency foldback scheme is employed to extend the maximum duty cycle
when TOFF_MIN is reached. The switching frequency decreases once longer duty cycle is needed under low VIN
conditions. A wide range of frequency foldback allows the LMR23625 output voltage stay in regulation with a
much lower supply voltage VIN. This leads to a lower effective dropout voltage.
Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution
size and efficiency. The maximum operation supply voltage can be found by:

VOUT
VIN _ MAX
fSW u TON _ MIN
(4)

At lower supply voltage, the switching frequency decreases once TOFF_MIN is tripped. The minimum VIN without
frequency foldback can be approximated by:

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VOUT
VIN _ MIN
1 fSW u TOFF _ MIN
(5)

Taking considerations of power losses in the system with heavy load operation, VIN_MAX is higher than the result
calculated in Equation 4. With frequency foldback, VIN_MIN is lowered by decreased fSW.
2500

2000
Frequency (kHz)
1500

1000

IOUT = 0.5 A
IOUT = 1.0 A
500 IOUT = 1.5 A
IOUT = 2.0 A
IOUT = 2.5 A
0
4.9 5.3 5.7 6.1 6.5 6.9 7.3 7.7
VIN (V) D010

Figure 7-7. Frequency Foldback at Dropout (VOUT = 5 V, fSW = 2100 kHz)

7.3.6 Internal Compensation and CFF


The LMR23625 device is internally compensated as shown in Section 7.2. The internal compensation is
designed such that the loop response is stable over the entire operating frequency and output voltage range.
Depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors.
TI recommends an external feedforward capacitor CFF be placed in parallel with the top resistor divider RFBT for
optimum transient performance.
VOUT

RFBT CFF

FB

RFBB

Figure 7-8. Feed-forward Capacitor for Loop Compensation

The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the crossover frequency of
the control loop to boost phase margin. The zero frequency can be found by:

1
fZ _ CFF
2S u CFF u RFBT (6)

An additional pole is also introduced with CFF at the frequency of:

1
fP _ CFF
2S u CFF u RFBT //RFBB (7)

The zero fZ_CFF adds phase boost at the crossover frequency and improves transient response. The pole fP-CFF
helps maintaining proper gain margin at frequency beyond the crossover. Table 8-1 lists the combination of

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COUT, CFF and RFBT for typical applications, designs with similar COUT but RFBT other than recommended value,
adjust CFF so that (CFF × RFBT) is unchanged and adjust RFBB such that (RFBT / RFBB) is unchanged.
Designs with different combinations of output capacitors need different CFF. Different types of capacitors have
different equivalent series resistance (ESR). Ceramic capacitors have the smallest ESR and need the most CFF.
Electrolytic capacitors have much larger ESR than ceramic, and the ESR zero frequency location would be low
enough to boost the phase up around the crossover frequency. Designs that use mostly electrolytic capacitors at
the output may not need any CFF. The location of this ESR zero frequency can be calculated with Equation 8:

1
fZ _ESR
2S u COUT u ESR (8)

The CFF creates a time constant with RFBT that couples in the attenuate output voltage ripple to the FB node.
If the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. Therefore,
calculate CFF based on output capacitors used in the system. At cold temperatures, the value of CFF might
change based on the tolerance of the chosen component. This may reduce its impedance and ease noise
coupling on the FB node. To avoid this, more capacitance can be added to the output or the value of CFF can be
reduced.
7.3.7 Bootstrap Voltage (BOOT)
The LMR23625 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and
SW pins provides the gate-drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the
high-side MOSFET is off and the low-side switch conducts. TI recommends a BOOT capacitor with a value of
0.1 μF to 0.47 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16 V or higher
is recommended for stable performance over temperature and voltage.
7.3.8 Overcurrent and Short-Circuit Protection
The LMR23625 is protected from overcurrent conditions by cycle-by-cycle current limit on both the peak and
valley of the inductor current. Hiccup mode is activated if a fault condition persists to prevent over-heating.
High-side MOSFET over-current protection is implemented by the nature of the peak-current-mode control. The
HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is
compared to the output of the error amplifier (EA) minus slope compensation every switching cycle. See Section
7.2 for more details. The peak current of HS switch is limited by a clamped maximum peak-current threshold
IHS_LIMIT which is constant. Thus, the peak current limit of the high-side switch is not affected by the slope
compensation and remains constant over the full duty cycle range.
The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor
current begins to ramp down. The LS switch will not be turned OFF at the end of a switching cycle if its current is
above the LS current limit ILS_LIMIT. The LS switch is kept ON so that inductor current keeps ramping down until
the inductor current ramps below the LS current limit ILS_LIMIT. Then the LS switch is turned OFF, and the HS
switch will be turned on after a dead time. This is somewhat different than the more typical peak current limit and
results in Equation 9 for the maximum load current.

VIN VOUT VOUT


IOUT _ MAX ILS _ LIMIT u
2 u fSW u L VIN (9)

If the current of the LS switch is higher than the LS current limit for 64 consecutive cycles, hiccup-current-
protection mode is activated. In hiccup mode, the regulator is shut down and kept off for 5 ms typically before
the LMR23625 tries to start again. If an overcurrent or short-circuit fault condition still exists, hiccup repeats
until the fault condition is removed. Hiccup mode reduces power dissipation under severe overcurrent conditions,
prevents over-heating and potential damage to the device.
For FPWM option, the inductor current is allowed to go negative. Should this current exceed IL_NEG, the LS
switch is turned off until the next clock cycle. This is used to protect the LS switch from excessive negative
current.

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7.3.9 Thermal Shutdown


The LMR23625 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 170°C (typical). The device is turned off when thermal shutdown activates. Once the die temperature
falls below 155°C (typical), the device reinitiates the power-up sequence controlled by the internal soft-start
circuitry.

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7.4 Device Functional Modes


7.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the LMR23625. When VEN is below 1 V (typical), the
device is in shutdown mode. The LMR23625 also employs VIN and VCC UVLO protection. If VIN or V CC voltage
is below their respective UVLO level, the regulator is turned off.
7.4.2 Active Mode
The LMR23625 is in active mode when VEN is above the precision enable threshold, and VIN and VCC are above
their respective UVLO level. The simplest way to enable the LMR23625 is to connect the EN pin to VIN pin. This
allows self start-up when the input voltage is in the operating range 4-V to 36-V. See Section 7.3.4 and Section
7.3.3 for details on setting these operating levels.
In active mode, depending on the load current, the LMR23625 is in one of four modes:
1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the
peak-to-peak inductor current ripple (for both PFM and FPWM options).
2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of
the peak-to-peak inductor current ripple in CCM operation (only for PFM option).
3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load (only for
PFM option).
4. Forced pulse width modulation mode (FPWM) with fixed switching frequency even at light load (only for
FPWM option).
7.4.3 CCM Mode
CCM operation is employed in the LMR23625 when the load current is higher than half of the peak-to-peak
inductor current. In CCM operation, the frequency of operation is fixed, output voltage rippleis at a minimum in
this mode and the maximum output current of 2.5 A can be supplied by the LMR23625.
7.4.4 Light Load Operation (PFM Option)
For the PFM option, when the load current is lower than half of the peak-to-peak inductor current in CCM, the
LMR23625 operates in DCM, also known as diode emulation mode (DEM). In DCM, the LS switch is turned
off when the inductor current drops to IL_ZC (–40 mA typical). Both switching losses and conduction losses are
reduced in DCM, compared to forced PWM operation at light load.
At even lighter current loads, PFM is activated to maintain high efficiency operation. When either the minimum
HS switch ON-time (tON_MIN ) or the minimum peak inductor current IPEAK_MIN (300 mA typical) is reached, the
switching frequency decreases to maintain regulation. In PFM, switching frequency is decreased by the control
loop when load current reduces to maintain output voltage regulation. Switching loss is further reduced in PFM
operation due to less frequent switching actions. The external clock synchronizing is not valid when LMR23625
enters into PFM mode.
7.4.5 Light Load Operation (FPWM Option)
For FPWM option, the LMR23625 device is locked in PWM mode at full load range. This operation is
maintained, even at no-load, by allowing the inductor current to reverse its normal direction. This mode trades off
reduced light load efficiency for low output voltage ripple, tight output voltage regulation, and constant switching
frequency. In this mode, a negative current limit of IL_NEG is imposed to prevent damage to the regulators low
side FET. When in FPWM mode the converter synchronizes to any valid clock signal on the EN/SYNC input.

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8 Application and Implementation


Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

8.1 Application Information


The LMR23625 is a step down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 2.5 A. The following design procedure can be used to
select components for the LMR23625. Alternately, the WEBENCH® software may be used to generate complete
designs. When generating a design, the WEBENCH software utilizes iterative design procedure and accesses
comprehensive databases of components. See www.ti.com for more details.
8.2 Typical Applications
The LMR23625 only requires a few external components to convert from a wide voltage range supply to a fixed
output voltage. Figure 8-1 shows a basic schematic.
VIN 12 V
BOOT CBOOT
VIN
0.47 F L
CIN VOUT
2.2 H
10 F 5 V/ 2.5 A
EN/
SW
SYNC
PAD CFF RFBT
18 pF 88.7 NŸ
COUT
VCC FB 33 F
RFBB
CVCC
22.1 NŸ
2.2 F
PGND AGND

Figure 8-1. Application Circuit

The external components must fulfill the needs of the application, but also the stability criteria of the device
control loop. Table 8-1 can be used to simplify the output filter component selection.
Table 8-1. L, COUT and CFF Typical Values
fSW (kHz) VOUT (V) L (µH) (1) COUT (µF) (2) CFF (pF) RFBT (kΩ)(3) (4)
2100 3.3 2.2 47 33 51
2100 5 2.2 33 18 88.7

(1) Inductance value is calculated based on VIN = 20 V.


(2) All the COUT values are after derating. Add more when using ceramic capacitors.
(3) RFBT = 0 Ω for VOUT = 1 V. RFBB = 22.1 kΩ for all other VOUT setting.
(4) For designs with RFBT other than recommended value, adjust CFF so that (CFF × RFBT) is unchanged and adjust RFBB so that (RFBT /
RFBB) is unchanged.

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8.2.1 Design Requirements


Detailed design procedure is described based on a design example. For this design example, use the
parameters listed in Table 8-2 as the input parameters.
Table 8-2. Design Example Parameters
DESIGN PARAMETER EXAMPLE VALUE
Input voltage, VIN 12 V typical, range from 8 V to 28 V
Output voltage, VOUT 5V
Maximum output current IO_MAX 2.5 A
Transient response 0.2 A to 2.5 A 5%
Output voltage ripple 50 mV
Input voltage ripple 400 mV
Switching frequency fSW 2100 kHz

8.2.2 Detailed Design Procedure


8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR23625 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Setpoint
The output voltage of LMR23625 is externally adjustable using a resistor divider network. The divider network is
comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Equation 10 is used to determine
the output voltage:

VOUT VREF
RFBT u RFBB
VREF (10)

Choose the value of RFBB to be 22.1 kΩ. With the desired output voltage set to 5 V and the VREF = 1 V, the RFBB
value can then be calculated using Equation 10. The formula yields to a value 88.7 kΩ.
8.2.2.3 Switching Frequency
The default switching frequency of the LMR23625 is 2100 kHz. For other switching frequencies, the device must
be synchronized to an external clock ( see Section 7.3.3 for more details).
8.2.2.4 Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current, and the rated current. The
inductance is based on the desired peak-to-peak ripple current ΔiL. Because the ripple current increases with
the input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use
Equation 12 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the
amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of

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KIND must be 20% to 40%. During an instantaneous short or over current operation event, the RMS and peak
inductor current can be high. The inductor current rating must be higher than the current limit of the device.

VOUT u VIN _ MAX VOUT


'iL
VIN _ MAX u L u fSW (11)

VIN _ MAX VOUT VOUT


LMIN u
IOUT u KIND VIN _ MAX u fSW (12)

In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. However,
inductance that is too low can generate an inductor current ripple that is too high so that overcurrent protection
at the full load may be falsely triggered. It also generates more conduction loss and inductor core loss. Larger
inductor current ripple also implies larger output voltage ripple with same output capacitors. With peak-current-
mode control, TI does not recommend having an inductor current ripple that is too small. A larger peak current
ripple improves the comparator signal-to-noise ratio.
For this design example, choose KIND = 0.4, the minimum inductor value is calculated to be 1.9 µH. Choose the
nearest standard 2.2 μH ferrite inductor with a capability of 3.5-A RMS current and 6-A saturation current.
8.2.2.5 Output Capacitor Selection
Choose the output capacitor(s), COUT, with care because it directly affects the steady-state output-voltage ripple,
loop stability, and the voltage over/undershoot during load-current transients.
The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going
through the ESR of the output capacitors:

'VOUT_ESR 'iL u ESR KIND u IOUT u ESR (13)

The other is caused by the inductor current ripple charging and discharging the output capacitors:

'iL KIND u IOUT


'VOUT _ C
8 u fSW u COUT 8 u fSW u COUT (14)

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the
sum of two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew rate. When a fast large load increase happens,
output capacitors provide the required charge before the inductor current can slew up to the appropriate level.
The control loop of the regulator usually needs four or more clock cycles to respond to the output voltage droop.
The output capacitance must be large enough to supply the current difference for four clock cycles to maintain
the output voltage within the specified range. Equation 15 shows the minimum output capacitance needed
for specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb
energy stored in the inductor. which results in an output voltage overshoot. Equation 16 calculates the minimum
capacitance required to keep the voltage overshoot within a specified range.

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4 u IOH IOL
COUT !
fSW u VUS (15)

2 2
IOH IOL
COUT ! 2
uL
2
VOUT VOS VOUT (16)

where
• IOL = Low level output current during load transient
• IOH = High level output current during load transient
• VUS = Target output voltage undershoot
• VOS = Target output voltage overshoot
For this design example, the target output ripple is 50 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 50 mV, and
chose KIND = 0.4. Equation 13 yields ESR no larger than 50 mΩ and Equation 14 yields COUT no smaller than
1.2 μF. For the target over/undershoot range of this design, VUS = VOS = 5% × VOUT = 250 mV. The COUT can be
calculated to be no smaller than 17.5 μF and 5.3 μF by Equation 15 and Equation 16, respectively. Consider of
derating, one 33-μF, 16-V ceramic capacitor with 5-mΩ ESR is used.
8.2.2.6 Feed-forward Capacitor
The LMR23625 is internally compensated. Depending on the VOUT and frequency fSW, if the output capacitor
COUT is dominated by low ESR (ceramic type) capacitors, it could result in low phase margin. To improve
the phase boost an external feed-forward capacitor CFF can be added in parallel with RFBT. Choose CFF so
that phase margin is boosted at the crossover frequency without CFF. A simple estimation for the crossover
frequency (fX) without CFF is shown in Equation 17, assuming COUT has very small ESR, and COUT value is after
derating.

8.32
fX
VOUT u COUT (17)

Equation 18 for CFF was tested:

1
CFF
4S u fX u RFBT (18)

For designs with higher ESR, CFF is not needed when COUT has very high ESR, and CFF calculated from
Equation 18 should be reduced with medium ESR. Table 8-1 can be used as a quick starting point.
For the application in this design example, a 18-pF, 50-V, COG capacitor is selected.
8.2.2.7 Input Capacitor Selection
The LMR23625 device requires high-frequency input decoupling capacitor(s) and a bulk input capacitor,
depending on the application. The typical recommended value for the high-frequency decoupling capacitor is
4.7 μF to 10 μF. TI recommends a high-quality ceramic capacitor type X5R or X7R with sufficiency voltage
rating. To compensate the derating of ceramic capacitors, a voltage rating twice the maximum input voltage is
recommended. Additionally, some bulk capacitance can be required, especially if the LMR23625 circuit is not
located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to
the voltage spike due to the lead inductance of the cable or the trace. For this design, two 4.7-μF, 50-V, X7R
ceramic capacitors are used. A 0.1-μF for high-frequency filtering and place it as close as possible to the device
pins.
8.2.2.8 Bootstrap Capacitor Selection
Every LMR23625 design requires a bootstrap capacitor (CBOOT). TI recommends a capacitor of 0.47 μF, ated 16
V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap capacitor
must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.

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8.2.2.9 VCC Capacitor Selection


The VCC pin is the output of an internal LDO for LMR23625. To insure stability of the device, place a minimum of
2.2-μF, 16-V, X7R capacitor from this pin to ground.
8.2.2.10 Undervoltage Lockout Set-Point
The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and
RENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down
or brown outs when the input voltage is falling. The following equation can be used to determine the VIN UVLO
level.

RENT RENB
VIN _ RISING VENH u
RENB (19)

The EN rising threshold (VENH) for LMR23625 is set to be 1.55 V (typical). Choose the value of RENB to be 287
kΩ to minimize input current from the supply. If the desired V IN UVLO level is at 6.0 V, then the value of RENT can
be calculated using Equation 20:

§ VIN _ RISING ·
RENT ¨¨ 1¸¸ u RENB
© VENH ¹ (20)

Equation 20 yields a value of 820 kΩ. The resulting falling UVLO threshold, equals 4.4 V, can be calculated by
Equation 21, where EN hysteresis (VEN_HYS) is 0.4 V (typical).

RENT RENB
VIN _ FALLING VENH VEN _ HYS u
RENB (21)

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8.2.3 Application Curves

Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 2100 kHz, L = 2.2 µH, COUT = 47 µF, TA = 25 °C.

VOUT = 5 V IOUT = 2.5 A fSW = 2100 kHz VOUT = 5 V IOUT = 100 mA fSW = 2100 kHz

Figure 8-2. CCM Mode Figure 8-3. DCM Mode

VOUT = 5 V IOUT = 0 mA fSW = 2100 kHz VOUT = 5 V IOUT = 0 mA fSW = 2100 kHz

Figure 8-4. PFM Mode Figure 8-5. FPWM Mode

VIN = 12 V VOUT = 5 V IOUT = 2 A VIN = 12 V VOUT = 5 V IOUT = 2 A

Figure 8-6. Start-Up by VIN Figure 8-7. Start-Up by EN

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VIN = 12 V IOUT = 0.2 A to 2.5 A, 100 mA / μs VOUT = 5 V VIN = 7 V to 36 V, 2 V / μs


VOUT = 5 V IOUT = 2.5 A

Figure 8-8. Load Transient Figure 8-9. Line Transient

VOUT = 5 V IOUT = 1 A to short VOUT = 5 V IOUT = short to 1 A

Figure 8-10. Short Protection Figure 8-11. Short Recovery

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9 Power Supply Recommendations


The LMR23625 device is designed to operate from an input voltage-supply range between 4.5 V and 36 V for
the HSOIC package and 4 V to 36 V for the WSON package. This input supply must be able to withstand the
maximum input current and maintain a stable voltage. The resistance of the input supply rail must be low enough
that an input current transient does not cause a high enough drop at the device supply voltage that can cause
a false UVLO fault triggering and system reset. If the input supply is located more than a few inches from the
LMR23625, additional bulk capacitance may be required in addition to the ceramic input capacitors. The amount
of bulk capacitance is not critical, but a 47-μF or 100-μF electrolytic capacitor is a typical choice.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. The input bypass capacitor CIN must be placed as close as possible to the VIN and PGND pins. Grounding
for both the input and output capacitors should consist of localized top side planes that connect to the PGND
pin and PAD.
2. Place bypass capacitors for VCC close to the VCC pin and ground the bypass capacitor to device ground.
3. Minimize trace length to the FB pin net. Both feedback resistors, RFBT and RFBB must be located close to the
FB pin. Place CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, make sure VOUT
sense is made at the load. Route VOUT sense path away from noisy nodes and preferably through a layer on
the other side of a shielded layer.
4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path.
5. Have a single point ground connection to the plane. The ground connections for the feedback and enable
components should be routed to the ground plane. This prevents any switched or load currents from flowing
in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or
erratic output voltage ripple behavior.
6. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
7. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the
ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be
connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking
to keep the junction temperature below 125°C.

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10.2 Layout Example

Output Bypass
Output Inductor Capacitor

Input Bypass
SW Capacitor
PGND

BOOT Capacitor

BOOT VIN

VCC AGND

VCC
Capacitor FB EN/
SYNC

UVLO Adjust Resistor

Output Voltage Set


Resistor Thermal VIA

VIA (Connect to GND Plane)

Figure 10-1. HSOIC Layout Example

Output Output Bypass


Inductor Capacitor

SW PGND

Input Bypass
SW NC
Capacitor
BOOT
Capacitor
BOOT VIN

VCC
VCC VIN
Capacitor

FB EN/SYNC

UVLO Adjust
PGOOD AGND Resistor

Thermal
Output VIA
Voltage Set VIA (Connect to GND
Resistor Plane)

Figure 10-2. WSON Layout Example

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10.3 Compact Layout for EMI Reduction


Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more EMI is generated. High-frequency ceramic bypass
capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing
ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the key to EMI reduction.
The SW pin connecting to the inductor must be as short as possible and just wide enough to carry the load
current without excessive heating. Use short, thick traces or copper pours (shapes) high current conduction path
to minimize parasitic resistance. Place the output capacitors close to the VOUT end of the inductor and closely
grounded to PGND pin and exposed PAD.
Place the bypass capacitors on VCC as close as possible to the pin and closely grounded to PGND and the
exposed PAD.
10.4 Ground Plane and Thermal Considerations
TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding
for sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect
the AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pin is
connected to the source of the internal LS switch. They must be connected directly to the grounds of the input
and output capacitors. The PGND net contains noise at switching frequency and may bounce due to load
variations. PGND trace, as well as VIN and SW traces, must be constrained to one side of the ground plane. The
other side of the ground plane contains much less noise and should be used for sensitive routes.
TI also recommends providing adequate device heat sinking by utilizing the PAD of the device as the primary
thermal path. Use a minimum 4 by 2 array of 12 mil thermal vias to connect the PAD to the system ground plane
heat sink. The vias must be evenly distributed under the PAD. Use as much copper as possible, for system
ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper
thickness for the four layers, starting from the top of, 2 oz / 1 oz / 1 oz / 2 oz. Four-layer boards with enough
copper thickness provides low current conduction impedance, proper shielding, and lower thermal resistance.
The thermal characteristics of the LMR23625 are specified using the parameter RθJA, which characterize the
junction temperature of silicon to the ambient temperature in a specific system. Although the value of RθJA is
dependent on many variables, it still can be used to approximate the operating junction temperature of the
device. To obtain an estimate of the device junction temperature, one may use the following relationship:

TJ = PD × RθJA + TA (22)

PD = VIN × IIN × (1 – Efficiency) – 1.1 × IOUT 2 × DCR in watt (23)

where
• TJ = junction temperature in °C
• PD = device power dissipation in watt
• RθJA = junction-to-ambient thermal resistance of the device in °C/W
• TA = ambient temperature in °C
• DCR = inductor DC parasitic resistance in ohm
The recommended operating junction temperature of the LMR23625 is 125°C. RθJA is highly related to PCB size
and layout, as well as environmental factors such as heat sinking and air flow.

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10.5 Feedback Resistors


To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and
CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high
impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces
the trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace
from VOUT to the resistor divider can be long if short path is not available.
If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for
voltage drops along the traces and provide the best output accuracy. Route the voltage sense trace from the
load to the feedback resistor divider away from the SW node path and the inductor to avoid contaminating the
feedback signal with switch noise, while also minimizing the trace length. This is most important when high-value
resistors are used to set the output voltage. TI recommends routing the voltage sense trace and place the
resistor divider on a different layer than the inductor and SW node path, such that there is a ground plane
in between the feedback trace and inductor/SW node polygon. This provides further shielding for the voltage
feedback path from EMI noises.

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11 Device and Documentation Support


11.1 Device Support

11.1.1 Development Support

11.1.1.1 Custom Design With WEBENCH® Tools


Click here to create a custom design using the LMR23625 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
PowerPAD™ is a trademark of TI.
TI E2E™ is a trademark of Texas Instruments.
SIMPLE SWITCHER® and WEBENCH® are registered trademarks of Texas Instruments.
are registered trademarks of TI.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information


The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: LMR23625


PACKAGE OPTION ADDENDUM

www.ti.com 25-Jan-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LMR23625CDDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 F25C

LMR23625CDDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 F25C

LMR23625CFDDA ACTIVE SO PowerPAD DDA 8 75 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 F25CF

LMR23625CFDDAR ACTIVE SO PowerPAD DDA 8 2500 RoHS & Green NIPDAUAG Level-2-260C-1 YEAR -40 to 125 F25CF

LMR23625CFPDRRR ACTIVE WSON DRR 12 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 3625P

LMR23625CFPDRRT ACTIVE WSON DRR 12 250 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 3625P

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 25-Jan-2021

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LMR23625 :

• Automotive: LMR23625-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMR23625CDDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
Power
PAD
LMR23625CFDDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
Power
PAD
LMR23625CFPDRRR WSON DRR 12 3000 330.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2
LMR23625CFPDRRT WSON DRR 12 250 180.0 12.4 3.3 3.3 1.0 8.0 12.0 Q2

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMR23625CDDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0
LMR23625CFDDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0
LMR23625CFPDRRR WSON DRR 12 3000 367.0 367.0 38.0
LMR23625CFPDRRT WSON DRR 12 250 213.0 191.0 35.0

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal


Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
LMR23625CDDA DDA HSOIC 8 75 517 7.87 635 4.25
LMR23625CFDDA DDA HSOIC 8 75 517 7.87 635 4.25

Pack Materials-Page 3
PACKAGE OUTLINE
DRR0012D SCALE 4.000
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

3.1 B
A
2.9

PIN 1 INDEX AREA


3.1
2.9 0.1 MIN

(0.05)

SECTION A-A
SECTION A-A
SCALE 30.000

TYPICAL

0.8 C
0.7
SEATING PLANE
0.05
0.00 0.08 C

EXPOSED 1.7 0.1 (0.2) TYP


THERMAL PAD
6 7

A A
2X 13
2.5 2.5 0.1

1
12
10X 0.5 0.3
0.38 12X
12X 0.2
PIN 1 ID 0.28
(OPTIONAL) 0.1 C A B
0.05 C

4223146/D 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
EXAMPLE BOARD LAYOUT
DRR0012D WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(1.7)
12X (0.53) SYMM
1
12

12X (0.25)

13
SYMM
10X (0.5) (2.5)

(1)

(R0.05) TYP
6
7
(0.6)
( 0.2) VIA
TYP (2.87)

LAND PATTERN EXAMPLE


EXPOSED METAL SHOWN
SCALE:20X

0.07 MAX 0.07 MIN


ALL AROUND ALL AROUND

EXPOSED METAL EXPOSED METAL

SOLDER MASK METAL EDGE METAL UNDER SOLDER MASK


OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4223146/D 10/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
EXAMPLE STENCIL DESIGN
DRR0012D WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

SYMM

12X (0.53) (0.47)


1
12

12X (0.25)

METAL
TYP
(0.675)
SYMM
13
10X (0.5)

(1.15)

(R0.05) TYP

6
7
(0.74)

(2.87)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
80.1% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X

4223146/D 10/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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