Module 3

Syllabus:
Scaling of MOS Circuits: Scaling Models and Scaling Factors, Scaling Factors for Device
Parameters.
Subsystem Design Processes: Some General Considerations, an illustration of design
processes- 4-bit Arithmetic Processor, Design of a 4-bit Shifter.
Illustration of the Design Process-Computational Elements: Regularity, Design of an ALU
Subsystems. (Text-2)

SCALING MODELS AND SCALING FACTORS:

The most commonly used models are the constant electric field. scaling model and the constant
voltage scaling model. it is useful to refer to Figure 5.1 which indicates the device dimensions
and substrate doping level which are associated with the scaling of a transistor.
SCALING FACTORS FOR DEVICE PARAMETERS:
A simple derivations and calculations reveal the effects of scaling.
Subsystem Design Processes:

Some Problems:
AN ILLUSTRATION OF DESIGN PROCESSES

The General·Arrangement of a 4-bft Arithmetic Processor:

The 4-bit microprocessor has been chosen as a design example because it is particularly
suitable for illustrating the design and interconnection of common architectural blocks. Figure
7.1 sets out the basic architecture of most, if not all, microprocessors.

The data path has been separaJed out in Figure 7.2 and it will be seen that the structure
comprises a unit which processes data applied at one port and presents its output at a second
port. Alternatively, the two data ports may be combined as a single bidirectional port if storage
facilities exist in the data path. Control over the functions to be performed is effected by control
signals as indicated.

The data path into a block diagram showing the main subunits. In doing this it is useful to
anticipate a possible floor plan to show the planned relative disposition of the subunits on the
chip and thus on the mask layouts. A block diagram is presented in Figure 7.3.

The choices in this case range from one-bus, two-bus or three-bus architecture. Some of the
possibilities are shown in Figure 7.4. In pursuing this particular design exercise, it was decided
to implement the structure with a two-bus architecture. In our planning we can now extend on
our interconnections strategy by planning for power rails and notionally making some basic
allocation of layers on which the various signal paths will be predominantly run. These
additional features are illustrated in Figure 7.5, together with a tentative floor plan of the
proposed design which includes some form of interface (I/0) to the parent system data bus (see
Figure 7.1).
The proposed processor will be seen to comprise a register array in which 4-bit numbers can
be stored, either from an input/output port or from the output of the ALU via a shifter. Numbers
from the register array can be fed in pairs to the ALU to be added (or subtracted, etc.) and the
result can be shifted or not, before being returned to the register array or possibly out through
the I/0 port. Obviously, data connections between the 1/0 port, ALU, and shifter must be in the
form of 4-bit buses. Simultaneously, we must recognize that each of the blocks must be suitably
connected to control lines so that its function may be defined for any of a range of possible
operations.
The required arrangement has been turned into a very tentative floor plan, as in Figure 7.5,
which indicates a possible relative disposition of the blocks and also indicates an acceptable
and sensible interconnection strategy indicated by the lines showing the preferred direction of
data flow and control signal distribution. At this stage of learning, floor plans will be very
tentative since we will not as yet be able to accurately assess the area requirements, say for a;4-
bit register or a 4-bit adder.
The Design of a 4-bit Shifter
Any general purpose n-bit shifter should be able to shift incoming data by up to n - 1 places in
a right-shift or left-shift direction. If we now further specify that all shifts should be on an 'end-
around' basis, so that any bit shifted out at one end of a data word will be shifted in at the other
end of the word, then the problem of right shift or left shift is greatly eased.
In fact, a moment's consideration will reveal, for a 4-bit word, that a 1-bit shift right is
equivalent to a 3-bit shift left and a 2-bit shift right is equivalent to a 2-bit shift left, etc. Thus
we can achieve a capability to shift left or right by zero, one, two, or three places by designing
a circuit which will shift right only (say) by zero, one, two, or three places. The nature of the
shifter having been decided on, its implementation must then be considered. Obviously, the
first circuit which comes to mind is that of the shift register in Figures 6.38, 6.39 and 6.40.
Data could be loaded from the output of the ALU and shifting effected; then the outputs of
each stage of the shift register would provide the required parallel output to be returned to the
register array (or elsewhere in the general case).
However, there is danger in accepting the obvious without question. Many designers, used to
the constraints of TTL, MSI, and SSI logic, would be conditioned to think in terms of such
standard arrangements. The shifter must have:

✓ input from a four-line parallel data bus;

✓ four output lines for the shifted data;
✓ means of transferring input data to output lines with any shift from zero to three bits
inclusive.

Consider a direct MOS switch implementation of a 4 x 4 crossbar switch, as in Figure 7.6.

The arrangement is quite general and may be readily expanded to accommodate n-bit
inputs/outputs. In fact, this arrangement is an overkill in that any input line can be connected
to any or all output lines-if all switches are closed, then all inputs are connected to all outputs
in one glorious short circuit. Furthermore, 16 control signals (sw00-sw15), one for each transistor
switch, must be provided to drive the crossbar switch, and such complexity is highly
undesirable. An adaptation of this arrangement recognizes the fact that we can couple the
switch gates together in groups of four (in this case) and also form four separate groups
corresponding to shifts of zero, one, two and three bits. The arrangement is readily adapted so
that the in-lines also run horizontally (to conform to the required strategy). The resulting
arrangement is known as a barrel shifter and a 4 x 4-bit barrel shifter circuit diagram is given
ih Figure 7. 7. The interbus switches have their gate inputs connected in a staircase fashion in
groups of four and there are now four shift control inputs which must be mutually exclusive in
the active state. CMOS transmission gates may be used in place of the simple pass transistor
switches if appropriate.

The structure of the barrel shifter is clearly one of high regularity and generality and it may be
readily represented in stick diagram form. One possible implementation, using simple n-type
switches, is given in Figure 7.8.
The mask layout for standard cell number 2 (arbitrary choice) of Figure 7.8 may then be set
out as in Figure 7.9. Once the standard cell dimensions have been determined, then any n x n
barrel shifter may be configured and its outline, or bounding box, arrived at by summing up
the dimensions of the replicated standard cell. The use of simple n-type switches in a CMOS
environment might be questioned. Although there will be a degrading of logic 1 levels through
n-type switches, this generally does not matter if the shifter is followed by restoring circuitry
such as inverters or gate logic. Furthermore, as there will only ever be one n-type switch in
series between an input and the corresponding output line, the arrangement is fast.
The minimum size bounding box outline for the 4 x 4-way barrel shifter is given in Figure 7.10.
The figure also indicates all inlet and outlet points around the periphery together with the layer
on which each is located. This allows ready placing of the shifter within the floor plan (Figure
7.5) and its interconnection with the other subsystems forming the datapath.

It also emphasizes the fact that, as in this case, many subsystems need external links to complete
their architecture. In this case, the links shown on the right of the bounding box must be made
and must be allowed for in interconnections and overall dimensions. This form of
representation also allows the subsystem geometric characterization to be that of the bounding
box alone for composing higher levels of the system hierarchy.
Illustration of the Design Process-Computational Elements

REGULARITY:
Regularity should be as high as possible to minimize the design effort required for any system.
The level of any particular design as far as this aspect is concerned may be measured by
quantifying regularity as follows:

DESIGN OF AN ALU SUBSYSTEM

Having designed the shifter, we may now tum our attention to another subsystem of the 4-bit
data path (as in Figure 8.1). A convenient and appropriate choice is the ALU.

The heart of the ALU is a 4-bit adder circuit and it is this which we will actually design,
indicating later how it may be readily adapted to subtract and perform logical operations.
Obviously, a 4-bit adder must take the sum of two 4-bit numbers, and it will be seen we have
assumed that all 4-bit quantities are presented in parallel form and that the shifter circuit has
been designed to accept and shift a 4-bit parallel sum from the ALU.
Let us now specify that the sum is to be stored in parallel at the output of the adder from where
it may be fed through the shifter and back to the register array. Thus, a single 4-bit data bus is
needed from the adder to the shifter and another 4-bit bus is required from the shifted output
back to the register array (since the shifter is merely a switch array with no storage capability).
As far as the input to the adder is concerned, the two 4-bit parallel numbers to be added are to
be presented in parallel on two 4-bit buses. We can also decide on some of the basic aspects of
system timing at this stage and will assume clock phase cp 1 as being the phase during which
signals are fed along buses to the adder input and during which their sum is stored at the adder
output. Thus clock signals are required by the ALU as shown.
The shifter is unclocked but must be connected to four shift control lines. It is also necessary
to provide a 'carry out' signal from the adder and, in the general case, to provide for a possible
'carry in' signal, as indicated in Figure 8.1.

Design of a 4-bit Adder:

In order to derive the requirements for an n-bit adder, let us first consider the addition of two
binary numbers A + B as follows:
Adder element requirements:

A standard adder element:

A 1-bit adder element may now be represented as in Figure 8.2. Note that any number of such
elements may be cascaded to form any size of adder and that the element is quite general.
Note: This standard adder element may itself be composed from a number of replicated subcells.
Regularity and generality must be aimed at in all levels of the architecture.
Using multiplexers is an implementation of the logic circuitry for the adder element that is easy
to follow, resulting directly from the way in which the requirements are stated in words. This
approach is illustrated in Figures 8.3 and 8.4 and it may be seen that the words used to describe
the adder logic are directly implemented by the various paths through the multiplexers.

The basic logic requirements of this adder element, or bit-slice, are thus readily met in nMOS
or CMOS technology.
In order to form an n-bit adder, n adder elements must be cascaded with carry out of one
element connecting to carry in of the next more significant element. Thus, the carry chain as a
whole will consist of many pass transistors in series. This will give a very slow response and
the carry line must therefore be, suitably buffered between adder elements.
Also, we have assumed that both complements, and , of the incoming bits are available.
This may not be the case. Furthermore, signals Ak and Bk are to be derived from buses
interconnecting the register with the ALU and may thus be taken off the bus through pass
transistors. If this is the case, then these signals could not be used directly to drive the pass
transistors of the multiplexers. Finally, need to store the sum at the output of the adder.
Standard cells required to be designed for the adder element:
The stick diagram of Figure 8.5 shows that the adder consists of three parts:
For CMOS-based designs, as set out in Figure 8.5, we normally need a complementary CMOS
inverter. A possible mask layout is shown in Figure 8.9.
Adder element bounding box:

Determining a bounding box outline for a suitable CMOS inverter circuit (see Figure 8.9) and
it will be seen that each inverter occupies a rectangle measuring 18A. 'wide' and 35A. 'high'.