STLD200N4F6AG

Automotive-grade N-channel 40 V, 1.27 mΩ typ., 120 A

STripFET™ F6 Power MOSFET in a PowerFLAT™ 5x6 DSC
Datasheet - production data

Features
Order code VDS RDS(on) max. ID
STLD200N4F6AG 40 V 1.50 mΩ 120 A

 AEC-Q101 qualified
 Very low on-resistance
 Very low gate charge
 High avalanche ruggedness
 Low gate drive power loss
 Wettable flank package

Applications
Figure 1: Internal schematic diagram  Switching applications

D(5, 6, 7, 8)
Description
This device is an N-channel Power MOSFET
developed using the STripFET™ F6 technology
with a new trench gate structure. The resulting
Power MOSFET exhibits very low RDS(on) in all
G(4) packages.

S(1, 2, 3)

Table 1: Device summary

Order code Marking Package Packaging
STLD200N4F6AG 200 PowerFLAT™ 5x6 dual side cooling Tape and reel

July 2017 DocID028892 Rev 5 1/13

This is information on a product in full production. www.st.com
Contents STLD200N4F6AG

Contents
1 Electrical ratings ............................................................................. 3
2 Electrical characteristics ................................................................ 4
2.1 Electrical characteristics (curves) ...................................................... 6
3 Test circuits ..................................................................................... 8
4 Package information ....................................................................... 9
4.1 PowerFLAT™ 5x6 dual side cooling package information ................ 9
4.2 PowerFLAT™ 5x6 dual side cooling packing information ............... 11
5 Revision history ............................................................................ 12

2/13 DocID028892 Rev 5

STLD200N4F6AG Electrical ratings

1 Electrical ratings
Table 2: Absolute maximum ratings
Symbol Parameter Value Unit
VDS Drain-source voltage 40 V
VGS Gate-source voltage ±20 V
ID(1)(2) Drain current (continuous) at TC = 25 °C 120 A
ID(1)(2) Drain current (continuous) at TC = 100 °C 120 A
IDM(2)(3) Drain current (pulsed) 480 A
(2)
PTOT Total dissipation at TC = 25 °C 158 W
TJ Operating junction temperature range
-55 to 175 °C
Tstg Storage temperature range

Notes:
(1)Limited by package
(2)The value is rated according to Rthj-case bottom side.
(3)Pulse width limited by safe operating area

Table 3: Thermal data

Symbol Parameter Value Unit
Rthj-c top side Thermal resistance junction-case top side 2.90
Rthj-c bottom side Thermal resistance junction-case bottom side 0.95 °C/W
(1)
Rthj-pcb Thermal resistance junction-pcb 31.3

Notes:
(1)When mounted on 1 inch² 2 Oz. Cu board, t ≤ 10 s

Table 4: Avalanche characteristics

Symbol Parameter Value Unit
Avalanche current, repetitive or not repetitive (pulse width limited by
IAV 90 A
maximum junction temperature)
EAS Single pulse avalanche energy (Tj = 25 °C, IC = IAV, VDD = 16 V) 400 mJ

DocID028892 Rev 5 3/13

Electrical characteristics STLD200N4F6AG

2 Electrical characteristics
(TC= 25 °C unless otherwise specified)
Table 5: On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
Drain-source breakdown
V(BR)DSS VGS = 0 V, ID = 1 mA 40 V
voltage
VGS = 0 V, VDS = 16 V 1 µA
Zero gate voltage drain
IDSS VGS = 0 V, VDS = 16 V,
current 10 µA
Tj = 125 °C (1)
IGSS Gate-body leakage current VDS = 0 V, VGS = ±20 V ±100 nA
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2.5 3.5 V
Static drain-source VGS = 10 V, ID = 75 A 1.27 1.50
RDS(on) mΩ
on-resistance VGS = 6.5 V, ID = 75 A 1.48 2.00

Notes:
(1)Defined by design, not subject to production test.

Table 6: Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Ciss Input capacitance - 10700 - pF
Coss Output capacitance VDS= 10 V, f = 1 MHz, - 1530 - pF
VGS = 0 V
Reverse transfer
Crss - 1100 - pF
capacitance
Qg Total gate charge VDD = 32 V, ID = 90 A, VGS = 0 - 172 - nC
to 10 V (see Figure 14: "Test
Qgs Gate-source charge - 56 - nC
circuit for gate charge
Qgd Gate-drain charge behavior") - 48 - nC

Table 7: Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time VDD = 30 V, ID = 75 A - 150 - ns
tr Rise time RG = 30 Ω, VGS = 10 V (see - 440 - ns
Figure 13: "Test circuit for
td(off) Turn-off-delay time resistive load switching times" - 600 - ns
and Figure 18: "Switching time
tf Fall time waveform") - 410 - ns

4/13 DocID028892 Rev 5

STLD200N4F6AG Electrical characteristics
Table 8: Source drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
ISD(1) Source-drain current - 120 A
Source-drain current
ISDM(1)(2) - 480 A
(pulsed)
VSD (3) Forward on voltage VGS = 0 V, ISD = 90 A - 1.2 V
trr Reverse recovery time - 40 ns
ISD = 90 A, di/dt = 100 A/µs,
Reverse recovery VDD = 20 V (see Figure 15: "Test
Qrr - 53 nC
charge circuit for inductive load
switching and diode recovery
Reverse recovery
IRRM times") - 2.5 A
current

Notes:
(1)Limited by package.
(2)Pulse width is limited by safe operating area.
(3)Pulse test: pulse duration = 300 µs, duty cycle 1.5%

DocID028892 Rev 5 5/13

Electrical characteristics STLD200N4F6AG
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area Figure 3: Thermal impedance

Figure 4: Output characteristics Figure 5: Transfer characteristics

Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance

6/13 DocID028892 Rev 5

STLD200N4F6AG Electrical characteristics
Figure 9: Normalized gate threshold voltage vs
Figure 8: Capacitance variations
temperature

Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature

Figure 12: Source-drain diode forward characteristics

DocID028892 Rev 5 7/13

Test circuits STLD200N4F6AG

3 Test circuits
Figure 13: Test circuit for resistive load Figure 14: Test circuit for gate charge
switching times behavior

Figure 15: Test circuit for inductive load Figure 16: Unclamped inductive load test
switching and diode recovery times circuit

Figure 18: Switching time waveform

Figure 17: Unclamped inductive waveform

8/13 DocID028892 Rev 5

STLD200N4F6AG Package information

4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

4.1 PowerFLAT™ 5x6 dual side cooling package information

Figure 19: PowerFLAT™ 5x6 dual side cooling package outline

DocID028892 Rev 5 9/13

Package information STLD200N4F6AG
Table 9: PowerFLAT™ 5x6 dual side cooling mechanical data
mm
Dim.
Min. Typ. Max.
A 0.66 0.71 0.76
A1 0.60 0.75
b 0.33 0.43 0.53
c 0.15 0.203 0.30
D 5.00 BSC
D1 4.06 4.21 4.36
D2 2.40 BSC
D3 2.80 3.30 3.80
E 6.00 BSC
E1 3.525 3.675 3.825
E2 1.05 1.20 1.35
E3 3.80 BSC
E4 4.20 4.70 5.20
e 1.27 BSC
I 0.15
L 0.15 0.25 0.35
L1 0.925 1.05 1.175
L2 0.45 0.575 0.70
ϑ 12° BSC
ϑ1 7° BSC
j 0.20 BSC

Figure 20: PowerFLAT™ 5x6 dual side cooling recommended footprint (dimensions are in
mm)

10/13 DocID028892 Rev 5

STLD200N4F6AG Package information
4.2 PowerFLAT™ 5x6 dual side cooling packing information
Figure 21: PowerFLAT™ 5x6 dual side cooling tape (dimensions are in mm)

8548087_REV1

Figure 22: PowerFLAT™ 5x6 dual side cooling reel (dimensions are in mm)

DocID028892 Rev 5 11/13

Revision history STLD200N4F6AG

5 Revision history
Table 10: Document revision history
Date Revision Changes
19-Jan-2016 1 First release
Document status promoted from preliminary to production data.
07-Feb-2017 2 Updated Table 3: "Thermal data" and Table 5: "On/off states".
Minor text changes
Updated features on cover page.
Updated Table 5: "On/off states" and Figure 9: "Normalized gate
23-Feb-2017 3
threshold voltage vs temperature"
Minor text changes
04-Apr-2017 4 Updated test conditions in Table 7: "Switching times".
Added Section 4.2: "PowerFLAT™ 5x6 dual side cooling packing
12-Jul-2017 5
information".

12/13 DocID028892 Rev 5

STLD200N4F6AG

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DocID028892 Rev 5 13/13

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