DEVELOPMENT OF FIELD ORIENTED VECTOR CONTROLLER FOR AN

INDUCTION MOTOR USING MATLAB EMBEDDED CODER

by

BHANU BABAIAHGARI

Bachelor of Science, Jawaharlal Nehru Technological University, 2013

A thesis submitted to the

Faculty of the Graduate School of the

University of Colorado in partial fulfillment

of the requirements for the degree of

Master of Science

Electrical Engineering

2015
 ProQuest Number: 1605080

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This thesis for the Master of Science degree by

Bhanu Babaiahgari

has been approved for the

Department of Electrical Engineering

by

Jaedo Park, Chair

Tim Lei

Yiming Deng

November 16, 2015

ii
Babaiahgari, Bhanu (M.S., Electrical Engineering)
Development of Field Oriented vector controller for an induction motor using Matlab
embedded coder

Thesis directed by Assistant Professor Jaedo Park

ABSTRACT

In this thesis project, a field oriented vector control system for an induction motor

is implemented on an experimental evaluation board. By looking at the performance

point of view, the TMS320F28335 DSP is selected as the digital controller of the vector

control system. All the required peripheral and interfacing circuits are developed for

the three-phase inverter control, signal measurement and for system protection as well.

This project is tested by means of level-by-level approach. Firstly, it is tested using a

simpler controller i.e. V/F control. Secondly, a current PI controller is implemented

and next it is tested by speed PI controller. At the stage of the controller design,

the vector control system is simulated in Matlab/Simulink using Simulink blocks.

The simulation results meet the design specifications well. When the control system

is verified by simulations, the DSP evaluation board is programmed using the file

generated by embedded coder (Simulink Tool) and tested. The test results show that

the current regulator and speed regulator are able to control the stator current and

the motor speed accurately. Finally, a performance comparison is evaluated between

the conventional approach and the one used in this project. The results show that

the approach used in this project has higher efficiency and flexibility in terms of

development time.

The form and content of this abstract are approved. I recommend its publication.

iii
Approved: Jaedo Park

iv
 ACKNOWLEDGMENT

I would like to express my deepest thanks to my advisor, Dr. Jae Do Park, for
his valuable guidance and suggestions he has given me in this project. Without him,
this would have been impossible. Also, I thank the committee members, Dr. Tim Lei
and Dr. Yiming Deng for spending their vaulable time for reviewing this report and
attending my defense.
I would like to express gratitude to my mother Samanthakamani(Chitti) and my
father Nagaraju for their encouragement and support throughout the project.
I would also like to thank Muahnnad Alaraj for explaining some of the topics
related to this project.

v
 DEDICATION

The thesis is dedicated to my family and entourage who have encouraged me to go

further during my life.

vi
 TABLE OF CONTENTS

Chapter

1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.3 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Induction Machine Vector Control System Description . . . . . . . . . . . . 3

2.1 AC Induction Machine . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Three-phase Inverter and Pulse Width Modulation (PWM) . . . . . 6

2.3 Vector Control System . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3.1 Clarke and Park Transformations . . . . . . . . . . . . . . . . 9

2.3.2 Inverse Clarke and Park Transformations . . . . . . . . . . . 11

3. Vector Control Design for Machine Control . . . . . . . . . . . . . . . . . . 13

3.1 Measurement and Estimation of Parameters of Induction Machine . 13

3.1.1 Rated value of Rotor Flux Linkage,λedr . . . . . . . . . . . . . 13

3.1.2 Stator Transient Inductance,σLs . . . . . . . . . . . . . . . . 14

3.1.3 Mutual Inductance, Lm . . . . . . . . . . . . . . . . . . . . . 15

3.2 Equivalent model of Induction Machine (T-Model) . . . . . . . . . . 15

3.3 Current Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3.1 Current Reference . . . . . . . . . . . . . . . . . . . . . . . . 18

3.3.2 Feed Forward . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.3.3 Voltage Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.3.4 Anti-windup . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.4 Flux Estimator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.5 Speed Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.6 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.7 Discretization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
vii
4. DSP Programming and CCS V5.5 . . . . . . . . . . . . . . . . . . . . . . . 26

4.1 Overview of DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.1.1 ADC Module . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1.2 PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1.2.1 Time-base submodule . . . . . . . . . . . . . . . . . . . 34

4.1.2.2 Counter-compare submodule . . . . . . . . . . . . . . . 38

4.1.2.3 Action Qualifier submodule . . . . . . . . . . . . . . . 39

4.1.2.4 Deadband submodule . . . . . . . . . . . . . . . . . . . 40

4.1.2.5 Event Trigger submodule . . . . . . . . . . . . . . . . . 41

4.1.2.6 Duty cycle calculation . . . . . . . . . . . . . . . . . . 42

4.1.3 Encoder Module . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.1.4 Offset Measurement . . . . . . . . . . . . . . . . . . . . . . . 46

4.2 Hardware Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.3 System Initialization and Configuration of CCS V5.5 . . . . . . . . . 48

4.3.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.3.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.3.3 Configuration of CCS V5.5 . . . . . . . . . . . . . . . . . . . 52

4.3.3.1 Makefile Setup . . . . . . . . . . . . . . . . . . . . . . 53

4.3.3.2 Configuration Parameters . . . . . . . . . . . . . . . . 54

4.4 Incremental Build Technology . . . . . . . . . . . . . . . . . . . . . 56

4.5 Troubleshooting DSP . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5. Testing and Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.1 Open loop test with V/F control . . . . . . . . . . . . . . . . . . . . 57

5.2 Closed loop test with Current Regulator . . . . . . . . . . . . . . . . 57

5.2.1 Analysis on Results . . . . . . . . . . . . . . . . . . . . . . . 59

5.3 Closed Loop test with Speed Regulator . . . . . . . . . . . . . . . . 59

5.3.1 Experimental Results . . . . . . . . . . . . . . . . . . . . . . 59

viii
 5.3.2 Analysis on Results . . . . . . . . . . . . . . . . . . . . . . . 60

6. Simulink or C: A comparitive study . . . . . . . . . . . . . . . . . . . . . . 61

6.1 Introduction to C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.1.1 How does C work? . . . . . . . . . . . . . . . . . . . . . . . . 62

6.1.2 Drawbacks of C . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.1.3 Replacement for C . . . . . . . . . . . . . . . . . . . . . . . . 63

6.2 Introduction to Simulink . . . . . . . . . . . . . . . . . . . . . . . . 63

6.2.1 Flexibility with Simulink . . . . . . . . . . . . . . . . . . . . . 63

6.3 Advantages of Simulink over C . . . . . . . . . . . . . . . . . . . . . 64

7. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7.1 Results from Present work . . . . . . . . . . . . . . . . . . . . . . . 66

7.2 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Appendix

A. Simulations and Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 69

A.1 Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

A.2 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

ix
 LIST OF TABLES

Table

4.1 ADC input channels and corresponding addresses . . . . . . . . . . . . . 31

4.2 Encoder Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.3 Configuration of ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.4 eQEP configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.5 ePWM configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.1 Open loop test with V/F control . . . . . . . . . . . . . . . . . . . . . . . 57

x
 LIST OF FIGURES

Figure

2.1 Overview of Induction Machine vector control system. . . . . . . . . . . 3

2.2 Structure of an Induction Machine . . . . . . . . . . . . . . . . . . . . . 3

2.3 Operating principle of Induction Machine . . . . . . . . . . . . . . . . . 6

2.4 Three Phase PWM Inverter Schematic (OrCAD) . . . . . . . . . . . . . 7

2.5 Pulse Width Modulation (PWM) generation principle . . . . . . . . . . . 8

2.6 Clarke and Park Transformations . . . . . . . . . . . . . . . . . . . . . . 10

3.1 Equivalent T circuit of the induction motor dynamic model . . . . . . . 15

3.2 Overview of Current Regulator . . . . . . . . . . . . . . . . . . . . . . . 17

3.3 Structure of Flux estimator . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.4 Speed control Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.5 Integral of the complex number in Simulink . . . . . . . . . . . . . . . . 22

3.6 Saturation of the complex number in simulink . . . . . . . . . . . . . . . 23

3.7 Forward Euler approximation . . . . . . . . . . . . . . . . . . . . . . . . 24

3.8 Integral form of Forward Euler approximation . . . . . . . . . . . . . . . 24

4.1 Programming Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2 Flow chart of the program . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.3 Block diagram of ADC module [1] . . . . . . . . . . . . . . . . . . . . . 30

4.4 ADC module configuration setup in this project [1] . . . . . . . . . . . . 32

4.5 Block Diagram of F28335 [2] . . . . . . . . . . . . . . . . . . . . . . . . . 34

4.6 Internal modules of ePWM and their connections [3] . . . . . . . . . . . 37

4.7 Time base counter synchronization scheme for F28335 . . . . . . . . . . 38

4.8 Counter-compare event, up-down counter mode . . . . . . . . . . . . . . 39

4.9 Block diagram of ePWM dead band submodule . . . . . . . . . . . . . . 41

4.10 Waveform of PWM with dead band inserted . . . . . . . . . . . . . . . . 42

4.11 Block diagram of eQEP module [4] . . . . . . . . . . . . . . . . . . . . . 45

xi
4.12 An example waveform of the eQEP (anti-clockwise rotation) . . . . . . . 47

4.13 Harware Setup in the lab . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.14 Simulink code configuration for ADC . . . . . . . . . . . . . . . . . . . . 49

4.15 Simulink configuration for eQEP . . . . . . . . . . . . . . . . . . . . . . 50

4.16 Simulink configuration for ePWM . . . . . . . . . . . . . . . . . . . . . . 51

4.17 Simulink configuration for ePWM . . . . . . . . . . . . . . . . . . . . . . 52

4.18 Make file configuration in Matlab . . . . . . . . . . . . . . . . . . . . . . 53

4.19 Environment variables defined in the project . . . . . . . . . . . . . . . . 55

5.1 Step response of the d and q currents.Fig(a) is the step response of the d

current with a reference of 80mA, and fig(b) is the step response of the q

current with a reference of 80mA. . . . . . . . . . . . . . . . . . . . . . . 58

5.2 Response in q current due to a step in i current. Fig. (a) shows q current

with respect to step in d current and Fig. (b) shows q current with respect

to quadrature reference i.e. zero . . . . . . . . . . . . . . . . . . . . . . . 58

5.3 Speed step response at 300rpm and very small bandwidth . . . . . . . . 59

6.1 Programming Languages used in Embedded Designs [5] . . . . . . . . . . 61

6.2 Illustration of two different approaches that can be used in the project . 64

A.1 Simulink model for V/F . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

A.2 Simulink model for V/F subsystem . . . . . . . . . . . . . . . . . . . . . 69

A.3 Simulink model for Current control . . . . . . . . . . . . . . . . . . . . . 70

A.4 Simulink model for Speed control . . . . . . . . . . . . . . . . . . . . . . 71

A.5 (a) shows Stator voltages in abc reference frame and (b) shows Stator

voltages in stationary reference frame . . . . . . . . . . . . . . . . . . . 72

A.6 Stator voltages in rotating reference frame . . . . . . . . . . . . . . . . . 72

A.7 (a) shows Stator currents in abc reference frame and (b) shows Stator

currents in stationary reference frame . . . . . . . . . . . . . . . . . . . 73

A.8 Stator currents in rotating reference frame . . . . . . . . . . . . . . . . . 73

xii
A.9 Theta varying from −Π to +Π . . . . . . . . . . . . . . . . . . . . . . . 74

A.10 Offset in current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

xiii
1. Introduction

1.1 Background

AC (Alternating Current) motors have a simple structure and has higher efficiency

than the DC motors when operated at a high speed [6]. In the past, due to convenience

of torque and speed control, the DC machine had been used widely for adjustable

speed drive (ASD). However, recently, with the development of power electronics

technology, the AC machine drive system such as the induction machine and the

synchronous machine driven by a variable voltage variable frequency (VVVF) inverter

are being used. AC machines do not have the commutator and brush of DC machine,

which need regular maintenance are the weak points of a DC machine. AC motors

also provide more durable service with a lower cost compared to DC motors. Besides,

AC motors can easily be supplied directly from the grid and therefore they are widely

used in the industry. And this trend shift from DC machine to AC machine has

been continued because of the development of not only the previously mentioned

power electronics but also the control theory of AC machine such as field orientation

control.

For a variable-speed application, if the power source is DC, a variable-speed driver

is needed, which is usually done with three phase inverter. With feedback orientation,

AC motors can be modelled similar to separately excited DC motor through a series

of coordinate transformations. For the transformed AC motor model, DC motor

control methods can be applied to control parameters like speed, torque, currents to

obtain good transient performance [7]. This method of controlling the transformed

AC motor is called vector control.

Usually, an embedded microcontroller takes care of the overall operation of AC

motor controller. Among various microcontrollers, Digital Signal Processor (DSP)

can perform complex computations, such as coordinate transformations and control

algorithms.

1
1.2 Objectives

The main objective of this project is to design and implement sensored vector

control system in Matlab/Simulink on the TMS320F28335 board for an induction

machine. Also, designing an experimental setup for the students to access the entire

project is part of the task. The approach used in this project is much easier to

understand and implement the system. In the past, the programming was usually

done in C language, which requires an expert knowledge in C. But the approach used

in this project is entirely done in Matlab/Simulink, the software that many people

use in these days to reduce the time to implement the system. The final outcome of

this project should be sensored vector control system of an induction machine on an

evaluation board.

1.3 Scope

The contents of this project covers many academic and practical areas, such as

programming, debugging, analog and digital circuit design and construction, induc-

tion machine modelling and vector control theory.

2
2. Induction Machine Vector Control System Description

In this chapter, a brief description of induction machine control system is given.

The basic overview of induction machine vector control system used in this project

is shown in Fig. 2.1. The vector control system includes a few hardware devices

namely induction machine and inverter, and technical theory such as vector control

strategy and Pulse Width Modulation (PWM). Details about the different parts will

be discussed in the latter chapters.

Figure 2.1: Overview of Induction Machine vector control system.

Figure 2.2: Structure of an Induction Machine

3
2.1 AC Induction Machine
An induction or asynchronous machine is an AC electric motor in which the

electric current in the rotor needed to produce torque is obtained by electromagnetic

induction from the magnetic field of the stator winding. An induction motor therefore

does not require mechanical commutation. An induction motor’s rotor can be either

wound type or squirrel-cage type [8]. The induction machine is composed of a stator

and a rotor as shown in Fig. 2.2(a) and Fig. 2.2(b). The stator is fixed while the

rotor rotates inside with a small air gap between them. The rotor contains conductor

bars and end rings as shown in Fig. 2.2(b). The rotor cage is a closed conductor

as the conductor bars are all short-circuited by the end rings. The rotor is mounted

on the shaft with two bearings [8]. Normally one of the two shaft ends is used for

driving the load while the other one for mounting the shaft position or the speed

measurement devices. The stator is made up of several pole pairs. Each pole pair

has three windings placed symmetrically in space as shown in Fig. 2.2(a). Based on

the arrangement of the three windings, the flux linkages (ΨA ,ΨB and ΨC ) generated

by the windings have 120 displacement in space. The magnitudes of flux linkages

(ΨA ,ΨB and ΨC ) could be expressed as

Z
φ(t) = (us (t) − Ris (t))dt, (2.1)

where us (t) is the applied voltage to each winding, R is the resistance of each winding

and is (t) is the current through each winding. If a three phase voltage is applied on

the stator windings, i.e.

π
ua (t) = Upk sin(2πf t + ) (2.2)
2
7π
ub (t) = Upk sin(2πf t + ) (2.3)
6
11π
uc (t) = Upk sin(2πf t + ) (2.4)
6
where Upk and f are the peak value and the frequency of the applied voltage respec-

tively, this will result in a sinusoidal flux linkage in each phase that lags the phase
4
voltage by 90 if the winding resistance is neglected, that is

ΨA (t) = Ψpk sin(2πf t) (2.5)

2π
ΨB (t) = Ψpk sin(2πf t + ) (2.6)
3
4π
ΨC (t) = Ψpk sin(2πf t + ) (2.7)
3
The waveforms of the three currents are shown in Fig. 2.3(a). In each period, the

current from each winding reaches its maximum value once. As shown the Fig.

2.3(b), the resultant flux can be obtained by adding the three flux linkages and has

a magnitude of 1.5Ψpk . From analysis of different moments, it could be noticed that

the magnitude of resultant flux vector doesn’t change and it rotates with a constant

magnitude. The rotation of the rotor can be seen in Fig. 2.3(c). The magnitude of

this rotating flux vectro is 1.5 times of the peak value of each winding’s flux linkage.

The rotating speed Ns (in rpm) of the resultant flux is called synchronous speed,

calculated as
f
Ns = 120 × (2.8)
P
Where f is three phase voltage frequency and P is number of poles.

The rotating resultant stator flux linkage cuts the rotor bars, which will induce a

voltage in the rotor bars. Since the rotor bars are short-circuited, this induced voltage

will drive a current in the rotor bars. By Lenzs law, An induced current is always in

such a direction as to oppose the motion or change producing it, the induced current

will generate a torque trying to make the rotor follow the rotating flux generated

by the stator windings. However, if the rotor speed is exactly equal to synchronous

speed, there will not be an induced current and hence no torque. Other external

factors like friction torque and load torque will make the rotor slow down. So the

induction machine rotor runs at a slightly slower speed than the synchronous speed

in order to get enough induced current and driving torque. There always exists a gap

5
between machine speed and synchronous speed, which is referred to as slip. This is

why induction machine has another name as asynchronous machine.

Figure 2.3: Operating principle of Induction Machine

2.2 Three-phase Inverter and Pulse Width Modulation (PWM)

The three-phase inverter supplies the induction machine with three-phase alter-

nating voltage. From the orcad schematic of three-phase inverter shown in Fig. 2.4,

it can be seen that the three-phase inverter is fed by a DC voltage as the energy

input and has three parts, each containing two IGBTs and two diodes. Consider the

DC-link voltage fed into the three-phase inverter as Vdc . For phase A, if U1 is turned

on, the phase voltage relative to ground will be equal to +Vdc /2; while if switch U2

is turned on, it is equal to Vdc /2.

Though it seems like the three-phase inverter only can generate two possible

voltage values for phase voltage, +Vdc /2 or Vdc /2, Pulse Width Modulation(PWM)
6
makes it possible to for the three-phase inverter to convert the DC-link voltage to

three-phase alternating voltage by controlling the on-times and off-times of the IG-

BTs. By adjusting the proportion of on-time in one PWM switching period for the

same bridge, any value between +Vdc /2 and Vdc /2 can be obtained as the phase volt-

age. The ratio of on time and the total on and off time is described as duty cycle and

can be formulated as:

Ton
D= (2.9)
Ton + Tof f
The basic principle of PWM generation is to compare waveforms of a triangular

Figure 2.4: Three Phase PWM Inverter Schematic (OrCAD)

wave (carrier wave) and a sine wave (reference wave) shown in Fig. 2.5. When the

magnitude of the sine wave is larger than the triangular wave, the PWM signal will

output a high voltage level to switch on the corresponding IGBT. On the contrary,

when the magnitude of the sine wave is smaller than the triangular wave, the PWM
7
signal will produce a low voltage level to turn off the IGBT. This process is illustrated

in Fig. 2.6. Hence the corresponding time moments of the intersections of the two

waves serve as the turning points to switch on or off the IGBT in the inverter.

To show the operation of a three-phase inverter, a simulation in Fig. 2.4 by Or-

CAD software is performed. The reference voltages for the three phases are assumed

to be constant and DC-link voltage is 220V. The loads of the inverter are assumed to

be resistive and connected in a Y-configuration.

Figure 2.5: Pulse Width Modulation (PWM) generation principle

2.3 Vector Control System

Vector control, also called field-oriented control (FOC), is a variable-frequency

drive (VFD) control method where the stator currents of a three-phase AC electric

motor are identified as two orthogonal components that can be visualized with a vec-

tor. One component defines the magnetic flux of the motor, the other the torque. The
8
main advantage of vector control system is it gets rid of machine speed dependency

on power grid frequency and make it possible to reach desired machine speed within

safety and power limits, although it gives rise to a considerable complex computation

for the processor where the control algorithms are implemented.

Normally, in a vector control system, the phase currents of the machine and

machine speed are taken as control system inputs, and phase voltages to the machine

are taken as outputs. Two important transformations involved in the vector control

system allows it to transform AC machine like a separately magnetized DC machine,

namely Clarke Transformation and Park Transformation. The three phase sinusoidal

quantities can be easily transformed into DC quantities in steady state using both

the transformations.

2.3.1 Clarke and Park Transformations

If the three-phase stator coils are arranged symmetrically in space with a 120◦

displacement as shown in Fig. 2.6(a), and the sum of the phase currents amplitude is

zero (ia (t)+ib (t)+ic (t) = 0), neglecting the zero sequence currents, the instantaneous

three-phase currents can be expressed by an equivalent space current vector i~a , with

two-phase quadrature quantities as

2
i~s (t) = (ia (t) + ib (t)ej2Π/3 + ic (t)ej4Π/3 ) (2.10)
3
√
2 1 1 3
= (ia (t) − ib (t) − ic (t) + j (ib (t) − ic (t))) (2.11)
3 2 2 2
= iα + iβ (2.12)

where constant 2/3 is placed in order to make the two-phase quantities to have the

same amplitude as the three-phase quantities. As can be seen from the Fig. 2.6(a),

the α-axis of the αβ coordinate system is aligned with the direction of the A-phase

space vector. As the αβ coordinate system is stationary with respect to the coils and

the coils are fixed to the stator, the αβ coordinate system is stationary as well.

9
 (a) (b)

Figure 2.6: Clarke and Park Transformations

In vector control theory, the three-phase to two-phase coordinate transformation

is named as Clarke Transformation. The reverse process that turns three-phase back

to two-phase is called Inverse Clarke Transformation, which is explained in the latter

sections. Clarke Transformation can be expressed in the matrix notation as:

 
    i
a
2 −1 −1  
iα
  3 3 3    
 =   ib  (2.13)
−1  
1 √

iβ 0 3 3
√
ic

respectively. This transformation can be applied any other three-phase quantities,

such as flux, voltages and so on, in order to get two-phase quantities.

If you notice the α and the β components of these rotating vectors, you could

see that they are still AC sinusoidal quantities. Therefore a new coordinate system

is defined, called the dq coordinate system, which has the same origin as the αβ

coordinate system but it rotates with the speed we specify. Usually we rotate dq

coordinate system with the same speed as flux rotates to make the imaginary part

of the coordinate system to be zero. This transformation of a space vector can be

achieved by multiplying the vector by e−jθ , where θ is the angle between the two

coordinate system. As seen in the Fig. 2.6(b), the αβ coordinate system has been

10
transformed to dz coordinate system. The transformation can be explained as:

i~dq = i~αβ × e−jθ (2.14)

This Transformation from the αβ coordinate system to dq coordinate system is called

Park Transformation while its reverse process is called Inverse Park Transformation,

which is explained in the next section. If the vector notation is expressed in terms of

scalar notation, the above equations can be written as:

i~s = iα + jiβ (2.15)

i~dq = id + jiq (2.16)

and e−jθ can be expanded using Eulers formula as:

e−jθ = cos θ − j sin θ (2.17)

Therefore equation 2.14 can be expressed in matrix form as:

    
id  cos θ − sin θ iα 
 =   (2.18)
iq sin θ cos θ iβ

2.3.2 Inverse Clarke and Park Transformations

As said earlier, the Inverse Clarke Transformation and Inverse Park Transfor-

mation are the reverse process of the transformations discussed above. This inverse

transformations are required in the vector control theory [9] to transform the modified

two-phase rotating quantities to three-phase stationary quantities, which are inputs

to the three phase inverter.

The same theory discussed above applies to the inverse transformation theory

as well, however, we approach this in a reverse direction. Hence we take inverse of

equation 2.13 and this can be explained as:

 
−1  
ia 

2 −1 −1
   3 3 3  iα 
i  =  (2.19)
 b −1
  
  0 √13 √ 3
iβ
ic
11
    
ia   1 0 
 
   √  iα 
 i  =  −1 3   (2.20)
 b  2 2   
   √  iβ
−1 − 3
ic 2 2

The Inverse Park Transformation can be derived from equation 2.14 as:

i~αβ = i~dq × ejθ (2.21)

and ejθ can be expressed using Eulers formula as:

ejθ = cos θ + j sin θ (2.22)

From the above equations, the Inverse Park Transformation can be expressed in

Matrix form as:     

iα   cos θ sin θ  id 
 =   (2.23)
iβ − sin θ cos θ iq

12
3. Vector Control Design for Machine Control
This chapter discusses about designing the controller blocks namely flux estima-

tions, current regulators and speed regulators, that have to be undergone succeeding

the transformations discussed in chapter 2. The parameters of the machine should

be identified for setting the gains of the regulators, limiting values of the limiters of

the controller, reference and feed-forwarding values to the regulator, and so on. In

general, the parameters of the machine are determined using locked rotor test or by

the no-load test. But, in actual operating conditions, these values might vary widely.

The following sections discuss briefly about the vector control system.

3.1 Measurement and Estimation of Parameters of Induction Machine

In this section, some of the methods to identify the parameters of electric machines

[10] based on the extra tests or name plate data of the machinery are introduced.

Though the method based on an extra test provides reasonably accurate parameters,

the methods may need some tools to apply the test signals or special setup for the

test. Hence, it is difficult to be used generally in the industry site.

3.1.1 Rated value of Rotor Flux Linkage,λedr

The stator voltage equation for rotor flux-oriented vector-controlled induction

machine can be written form the calculation part, as

L2m e dieds Lm
Vdse = (Rs + Rr 2
)ids + σLs − ωe σLs ieqs − Rr 2 λedr (3.1)
Lr dt Lr
L2m e dieqs Lm e
Vqse = (Rs + Rr )iqs + σLs + ωe σLs ieds + ωr λ (3.2)
Lr2 dt Lr dr
Based on some approximations done at near rated operating speed with no load, the

equation 3.2 can be written as

Vqse = ωr λedr = ωe λedr (3.3)

In this mode of operation, we have Vqse  Vdse . Therefore the peak of the phase

voltage can be approximated as Vqse . Hence the rated flux can be calculated from the
13
rated voltage and rated frequency of the induction machine. This is done by simply

dividing the peak of the rated phase voltage by the rated angular frequency,λe of the

machine.

3.1.2 Stator Transient Inductance,σLs

The stator transient inductance of the induction machine can be defined and

approximated as
L2m
σLs = Ls − (3.4)
Lr
It is to be noted that, the transient inductance varies with the magnitude and the

frequency of the current flowing through the inductance. If the stator transient induc-

tance is not accurately measured, the torque of the machine might lead to oscillatory

response. The transient inductance can be estimated by applying a short voltage

pulse to the induction machine through a PWM inverter as shown in Fig. 3.1. The

Fig. 3.2 shows the flow of current in the circuit. In this test, the phase voltage

equation can be derived as

dias dias
Vas = (Rs + Rr )ias + (Lls + Llr ) = (Rs + Rr )ias + σLs (3.5)
dt dt

If the width of the voltage pulse is small enough compared to the stator time constant
σLs
defined as T = Rs +Rr
, most of the voltage will be applied to the stator transient

inductance and can be approximated as

dias
Vas = σLs (3.6)
dt

Hence the transient inductance, σLs , can be estimated as

t2 − t1
σLs = Vad (3.7)
ias (t2 ) − ias (t1 )

14
3.1.3 Mutual Inductance, Lm
The mutual inductance of a machine can be identified easily if no-load operation

is possible for the system. In this case, by simply measuring the phase current and

the phase voltage, the sum of the stator leakage reactance and the mutual reactance

can be obtained by dividing voltage by the current. Then the mutual inductance

can be approximated by dividing the sum by the operating frequency, ωe , under

the assumption that the stator leakage inductance is much smaller than the mutual

inductance. Note that the operating frequency should be near the rated value to

reduce the error due to the resistance voltage drop of the stator winding. The mutual

inductance of the machine varies according to the magnitude of the rotor flux linkage

decided by the magnitude of the d-axis current of the synchronous reference frame.

3.2 Equivalent model of Induction Machine (T-Model)

The equivalent model of the induction machine can be described by using space

vectors. Although there are many dynamic models of the machine, we use T model

defined in the stationary αβ system in this manual. The equivalent circuit in the

form of T-circuit [11] is shown in Fig. 3.1 From the circuit shown above, the stator

Figure 3.1: Equivalent T circuit of the induction motor dynamic model

15
and rotor dynamic equations can be derived as,

dψ~s
V~s = Rs i~s + (3.8)
dt

dψ~r
V~r = 0 = Rr i~r + − jωr ψ~r (3.9)
dt
where the stator and rotor flux linkage equations can be written as,

ψ~s = Lls i~s + Lm i~r (3.10)

ψ~r = Llr i~r + Lm i~s (3.11)

The torque equation can be derived finally as,

3 Lm
Te = ×P × × Imag(ψ~s∗ ∗ i~s ) (3.12)
2 Lr

The quantities used in the induction motor are listed below.

V~s = Vsα + jVsβ : Stator voltage Rs : Stator resistance

V~r = Vrα + jVrβ : Rotor voltage Rr : Rotor resistance

i~s = isα + jisβ : Stator current Ls : Stator inductance

i~r = irα + jirβ : Rotor current Lr : Rotor inductance

i~m = is + jir : Magnetizing current Lm : Mutual inductance

ψ~s = ψsα + jψsβ : Stator flux linkage Lls : Stator leakage inductance

ψ~r = ψrα + jψrβ : Rotor flux linkage Llr : Rotor leakage inductance

ωr : Electrical rotor angular speed P : Pole pairs

Te : Torque

3.3 Current Regulator

The main parts of the current regulator are PI regulator [12], feed forward and

anti-windup. The Fig. 3.2 shows the complete structure of a current regulator. The

input signals for the current regulator are:

• ~is,ref , calculated from the reference value of the torque and the rotor flux.

16
 Figure 3.2: Overview of Current Regulator

• i~s , the stator current in dq- coordinates, which is obtained from the transfor-

mations of the measured phase currents.

• The electrical rotor angular speed, ωr which is obtained by multiplying the

number of pole pairs with the mechanical rotor angular speed.

• The angular speed and the magnitude of the rotor flux, which are calculated by

the flux estimator.

The output signal from the current regulator is:

• Stator voltage saturated by the voltage limiter. This limited voltage is then

transformed using Inverse Clarke and Park and then taken to the inverter and

then is applied to the induction machine as three-phase voltages.

17
3.3.1 Current Reference
The current reference term can be derived from the rotor side equation in the

equivalent circuit as,

0 = Rr ierd + pψrd
e e
− (ω − ωr )ψrq (3.13)

e
where p is the differential term. Since the term ψrq = 0, the equation above can be

written as
e
pψrd = Rr ierd (3.14)
e
ψrd − Lm iesd
ierd = (3.15)
Lm
Using both the above two equations and considering a single-order delay system i.e.

p = 0, the final expression would be,

e
ψrd
iesd = (3.16)
Lm

3.3.2 Feed Forward

From the dynamic equation of the stator currents in the T-model, we have

L2m e dieqs Lm e
Vqse = (Rs + Rr 2 )iqs + σLs + ωe σLs ieds + ωr λ (3.17)
Lr dt Lr dr

It could be found that the last term and last but one term need to be removed in

order to get a linear relation between voltage and the current. The first term in the

relation is usually known as the resistive voltage drop and the second term in the

relation is known as the inductive voltage drop. The existence of the third term in

the relation introduces the cross-coupling between d and q components. Also the

fourth term comprises of back-emf turns. Since the coupling and back- emf turns are

not expected during the current regulator design, a feed forward signal is applied to

eliminate the two terms and it is shown in the Fig.3.2

18
3.3.3 Voltage Limiter
As we know based on the principle of the three-phase inverter and PWM, the

amplitude of the equivalent sinusoidal voltage applied to the machine should be lim-

ited to the half of the DC-link voltage. This limitation of the voltage can be done by

using voltage limiter. This can be seen in the Fig. 3.2 It should also be noted that

the amplitude of the modulation voltage is expected to be smaller than the half of the

DC-link voltage because he inverter will output a constant voltage if the magnitude

of the modulation voltage is larger than half DC-link voltage. In this project, as

the DC-link voltage is 48V, the peak value of the phase voltage is set to be within

+20V or -20V. Even after you transform the DC vectors to three-phase sinusoidal

quantities, the peak value of the three-phase quantity remain the same and will never

change. This is why we set the voltage limiter in a current controller.

3.3.4 Anti-windup
There are some instances where, the output voltage of the current regulator may

not reach the value which is needed due to the existence of the voltage limiter. Then

the current error between the reference current and the feedback might let the inte-

grator of the PI regulator integrate to a very large value. Even if the error is finally

reduced, it would still take long time for the integrator to come to normal value,

which gives a delay [13] in the signal. This phenomenon is called integrator windup

problem. In order to overcome this situation, the difference between the voltage val-

ues before and after the voltage limiters fed back to the integrator through some gain

which makes the integrator reset [14] every time and eliminates the integrator windup

problem.

3.4 Flux Estimator

There are two types of flux estimators, voltage model estimator current model

estimator. The structure of an example flux estimator can be seen in Fig. 3.3. The

19
 Figure 3.3: Structure of Flux estimator

current model estimator, is more suitable for low speed application despite of sensitiv-

ity to parameter variations [15] rather than the voltage model estimator. As a result,

the flux estimator used in this project is the current model estimator implemented

in Indirect Field Orientation, which indicates that the quantities used for the flux

estimation are currents taken from the d − q system. With the stator d and q currents

and the electrical rotor angular speed as inputs, the flux determination equations for

the estimator can be derived as,

dψR RR
= RR id − ψR (3.18)
dt LM

0 = RR iq − (ω1 − ωr )ψR (3.19)

where ω1 − ωr is the difference speed between the synchronous speed and the electri-

cal rotor speed, the slip frequency. The Fig.3.3 illustrates the structure of the flux

estimator.

20
3.5 Speed Regulator

Figure 3.4: Speed control Regulator

The dynamic equation of the mechanical part of the induction motor can be

expressed as
dωr B Te − TL
= − ωr + (3.20)
dt J J
where

ωr : The mechanical angular speed

Te : Torque of the motor

TL : Load torque

B : Friction coefficient

J : Motor Inertia

The speed regulator design is very similar to the current regulator design. Like in

current regulator design, the speed regulator also has the anti-windup setup. But

this regulator does not have any feed forward terms but has the current limiter alike

voltage limiter in current control regulator. The current limiter has the peak value
21
of the rated current of the machine since the machine operating current should not

exceed the rated machine current. To avoid large overshoots in the speed response,

anti-windup is added. The structure of the speed regulator is shown in Fig. 3.4

The speed regulator has the output of torque reference which can be converted to

q-current, which acts on the motor immediately and directly. Since the inner current

loop has a very high bandwidth, the speed loop should have smaller bandwidth.

3.6 Simulation
The designated vector control system is implemented or simulated in Mat-

lab/Simulink. The block diagram of the vector control design is same as the figure

shown before and the structures of sub-blocks of the current regulator, flux estimator

and speed regulator are almost the same as shown in the previous figures. But some-

times in Simulink, the integrator block as well as the limiter block does not accept

the complex values. Therefore, the complex number is split into real and imaginary

part, which are then dealt separately. This process is illustrated in the Fig. 3.5 For

Figure 3.5: Integral of the complex number in Simulink

the limiter, the complex number is expressed in polar form, and then the magnitude

of the limiter is saturated as shown in Fig. 3.6 In the entire stages of simulation,

the whole vector control system is built with Simulink blocks. The advantages of

building the model with Simulink blocks is that it is very easy to observe a variable
22
 Figure 3.6: Saturation of the complex number in simulink

by adding a scope wherever it is needed. Moreover, it is more flexible to modify the

system structure.

3.7 Discretization
All the design above is based on continuous time. But the DSP does not allow

to execute the continuous time varying signals. Therefore, the signals of each block

have to be discretized for the proper execution of DSP. For example, if the control

loop period is 0.1msec, the sampling period h for the discretized system is selected as

0.1msec. At a certain time instant t = kh, in one cycle of the control loop sampling

takes place firstly, then the sampled values at t = kh are passed down in to the

function block chain. Then each block takes its input signals and stored state variables

into calculation, derives its output to feed into the next block and then get its state

variable updated for the next iteration at time instant t = (k + 1)h.

In this project, Forward Euler approximation is used to transform the continuous

system into discrete system. With x(t) defined as a continuous variable, x(kh) as its

value at the current time instant and x[(k + 1)h] for the next time instant, as shown

in Fig. 3.7 the derivatives can be approximated with a forward difference as [13]

dx(t) x[(k + 1)h] − x(kh)

= (3.21)
dt h

23
 Figure 3.7: Forward Euler approximation

Figure 3.8: Integral form of Forward Euler approximation

The integral form of Forward Euler approximation is shown in Fig. 3.8, where the

area below the curve x(t) can be approximated to the integral of variable x, denoted

as X. Over the interval between kh and (k + 1)h, the area below the curve of x(t) is

approximated to the area of the rectangle with x(kh) and h as dimension of it. The

24
integral of x(t) can be calculated as, by using the Forward Euler approximation,

X[(k + 1)h] = X[kh] + hx[kh] (3.22)

All the equations which are continuous time varying signals are presented in integral

form using Forward Euler approximation. For the blocks containing dynamic parts

like integrals, the above equation should be used into the original equations to replace

the integrals to make it a completely discrete system.

25
4. DSP Programming and CCS V5.5

The integrated interface for any user developing code in C language in this project

is the Code Composer Studio v5.5. Code Composer Studio (CCS) [16] is the Inte-

grated Development Environment (IDE) for TIs microcontrollers. TI also has an

integrated solution called the ControlSU IT E [17] which consists of all the header

files, source files, libraries, linker command files for executing a program. Also the

Code Composer Studio has many extensive examples and example codes that might

help any new user for a quick start of developing code.

The design of induction motor vector control is shown in Fig. 4.1. There are some

modifications and assumptions, however, in the actual design, during the implemen-

tation. Some of the modifications are firstly, only two phase currents are measured

instead of all the three phases. It is sufficient to take the measurements of two phases

for the Clarke Transformation, if the three phase currents are balanced with the con-

dition of ia (t) + ib (t) + ic (t) = 0 [18]. If three phases are balanced, one phase can be

calculated from the other two phases. At the start if the testing, first, V/F control

is implemented in order to test the motor functionality and the Simulink [19] blocks.

The flow chart of the various steps that the DSP undergoes after implementing the

code is shown in Fig. 4.2. The program, as shown in figure, starts with variables dec-

larations, initializations and configuration of the used hardware in the DSP, start-up

of the inverter and offset measurement. The latter process is in the implementation

in the hardware but the starting process depends on the software. After the DSP

is configures, the PWM sequence is started and the program enters in to loop. In

this project, the control strategy is designed such that, the control loop is synchro-

nized with the PWM carrier wave. Every start of PWM period will trigger an ADC

sequence. The ADC sequence consists of eight channels, which are used to measure

phase currents, fault currents and fault voltages and DC link voltages. At the end

of ADC sequence, the program jumps into measuring the current and speed values,

26
 Figure 4.1: Programming Design

where the offset compensation is added. Following the measurement calculations, the

vector control algorithm is executed. Finally, the PWM duty cycles are updated with

the new calculated values and the program then waits for the next trigger from the

PWM. In the following sections, brief introduction to the F28335 DSP is given and

also description about the hardware modules are given. In this section, introduction

to the DSP F28335 is briefly studied, followed by the modules description and also the

features of DSP. The PWM module plays an important role in this project because

of its functioning to output the three-phase signals to the inverter, decide the control

loop period and to synchronize the ADC. This is the reason why more details are

given in PWM module in this document.

4.1 Overview of DSP

Coming to the peripherals of the DSP, the F28335 DSP consists of a 32-bit CPU

and a single-precision 32-bit floating-point unit (FPU), which enables the floating-

point computation to be performed in the hardware. Also the CPU of the F28335

has a 8-stage pipeline structure, which makes the CPU be able to execute eight

27
 Figure 4.2: Flow chart of the program

instructions simultaneously on one system clock period. The 150MHz system clock is

provided by an on-chip oscillator and a phase-locked loop (PLL) circuit. The oscillator

generates 50MHz clock signal, which is tripled to 150 MHz by the PLL circuit. The

F28335 has independent logical memory spaces and separated memory buses for the

program and the data as seen in Fig. 4.3. The memory bus consists of a program read

bus, a data read bus and data write bus. The physical memory of the F28335 consists

of 34Kx16 single-access random access memory (SARAM), a 256K x16 Flash, an 8K

x 16 read-only memory (ROM), a 1K x 16 one-time programmable memory (OTP)

28
and the registers. The ROM has been pre-programmed by the DSP manufacturer.

The program existing in the ROM has a standard programming procedure for DSP

booting as well as some optimized codes for the mathematical functions. The registers

control the behavior of the DSP and each peripheral module. For the F28335, reading

from or writing to registers applies the bit-field address structures. F28335 also has

the feature of direct memory access (DMA). With the DMA bus, the data can be

passed from one part of the DSP to the other part without the interaction of the

CPU, which increases the data transmission speed. Since it is designed mainly for

applications like ours, the F28335 has plenty of peripheral circuits. For instance,

in our project, the motor vector control uses 16-channel, 12-bit ADC module, the

PWM module and the encoder module. Also there are different communications that

could be achieved with the F28335, which are controller area network (CAN) module,

the serial communication interface (SCI) module, the serial peripheral interface (SPI),

the multichannel buffered serial port (McBSP) module and the inter-integrated circuit

(I2C) module. F28335, also, supports 96 interrupts. These interrupts are governed by

the peripheral interrupt expansion (PIE) block, which helps in enabling or disabling

the interrupts, decide the interrupt priorities and inform the CPU of the occurrence of

a new interrupt. The F28335 has the joint test action group (JTAG) interface, which

helps us in real-time debugging. With the help of this JTAG, anyone can look and

modify the contents of the memory and the registers without stopping the processor.

This section explains about different modules.

4.1.1 ADC Module

The block diagram for ADC module [20] configured in F28335 is shown in Fig. 4.9.

It consists of 16 analog input channels, which are connected to an analog multiplexer

(MUX). The channel to be sampled can be selected by sending its corresponding 4-

bit address to the MUX. The relations between the channels and the 4-bit addresses

are listed in Table. 4.1. From the Fig. 4.9, we can observe that the analog MUX
29
 Figure 4.3: Block diagram of ADC module [1]

consists of two 8-to-1 multiplexers, MUX1 and MUX2. The outputs from the two

multiplexers are connected to two sample and hold (S/H) circuits, S/H-A and S/H-B,

respectively. The two S/H circuits allow the possibility of sampling two analog signal

simultaneously. After the S/H circuit has done the sampling, the analog-to-digital

converter begins to transfer the analog signal held on the S/H circuit into a 12-bit

binary number. The entire functioning of the ADC is governed by the ADC control

registers. There are sequencer blocks in the ADC, Sequencer1 and Sequencer2. These

two sequencers are then merged into a cascaded sequencer, where maximum sixteen

channels can be selected. These two sequencers are placed in an appropriate order and

each sequencer maximum of eight channels can be selected. In order to start an ADC

sequence, a start-of-conversion (SOC) signal is needed. For sequencer1 and sequencer2

or cascaded sequencer, the SOC signal could be given by the PWM module or the

bit S/W, which can be set or reset in the software. Sequencer1 and the cascaded

sequencer could also be triggered by an external signal through a general-purpose

30
 Table 4.1: ADC input channels and corresponding addresses

Input Address Input Address

Channel S3 S2 S1 S0 Channel S3 S2 S1 S0

ADC INA0 0000b ADC INB0 1000b

ADC INA1 0001b ADC INB1 1001b

ADC INA2 0010b ADC INB2 1010b

ADC INA3 0011b ADC INB3 1011b

ADC INA4 0100b ADC INB4 1100b

ADC INA5 0101b ADC INB5 1101b

ADC INA6 0110b ADC INB6 1110b

ADC INA7 0111b ADC INB7 1111b

input/output (GPIO) pin. The ADC clock frequency decides the time to take for one

conversion. The ADC clock is obtained by prescaling the system clock. This is done

in default if you set the DSP as F28335. The total prescaling factor is equal to the

product of the prescaling factors of the high-speed prescalar, the ADC clock prescalar

and the extra prescalar. The conversion results will be will be written into the result

registers, through a result selection MUX. For each sequence, the result selection

MUX will send the first conversion result to Result Reg0, the second one to Result

Reg1 and so on, until this sequence is finished. Whenever the complex conversions

occur like analog-to-digital conversions are needed in two different moments during

one control, the dual-sequence mode can be applied. In this project, all the analog

signals are sampled at the same moment and the number of analog signals is less

than eight. Due to this, one sequence of conversion per control loop is enough. But

cascaded mode of operation is still applied, which can leave flexibility to the channels

and DSP pins assignment. Sometimes it is required that all the analog signals are

31
 Figure 4.4: ADC module configuration setup in this project [1]

sampled at exactly when the PWM carrier wave reaches its peak. But since there

are only two S/H circuits, in the practical implementation, the two phase currents

phase A and phase B are sampled firstly and then the other parameters are sampled.

The sampling mode of the ADC module should be simultaneous. The ADC clock

frequency is better to be high, from the point of conversion speed. But too high ADC

clock frequency might cause some non-linearity to the conversion results [21]. So

12.5MHz, the highest ADC clock frequency is recommended and is being set in this

project. Another issue that might be noticed is the width of the sampling window,

which is defined as the number of clocks that the S/H circuit spends on sampling the

signal. For the signals that change very slowly, a wider sampling window might work

perfect bringing the advantage of removing the noise by averaging the input signal.

But in this project, since the currents change very fast, wide sampling does not

32
work, instead smallest sampling window of one ADC clock is applied. Then the ADC

module should work in start/stop mode, which means that the conversion is started

by the SOC signal and stops when the sequence is finished, waiting for the next SOC

signal. The SOC signal is triggered by the PWM module. Finally, an interrupt service

routine has to be generated by the ADC, once the sequence is finished. The vector

control algorithm will be executed in the Interrupt Service Routines (ISR). The block

diagram based on the ADC module configurations described above in the theory is

shown in Fig. 4.10. In simultaneous sampling mode, a pair of conversions counts for

one. Also the ADC counts from 0 instead of 1, so the value of the M AXCON V should

be calculated as
N o.of Conversions
M AXCON V = [ ]−1 (4.1)
2
This section explains about PWM module.

4.1.2 PWM module

There are six independent enhanced PWM (ePWM) modules in the DSP. The

enhanced PWM means that it can generate complex PWM waveform with the least

CPU resources occupied [22]. Each of the ePWM module has two output channels:

ePWMxA and ePWMxB belonging to the ePWMx module. Each ePWM module

contains seven submodules, which can realize different functions in the generation

of PWM waveforms. They are time-base (TB) submodule, counter-compare (CC)

submodule, action-qualifier (AQ) submodule, dead-band (DB) submodule, PWM-

chopper (PC) submodule, trip zone (TZ) submodule and event-trigger (ET) submod-

ule. The Fig. 4.4 shows the complete structure of a single ePWM module with each

submodule between the subsections. In this project, not all but some of them are

used for various accomplishments. The following sections will briefly describe the

ePWM modules individually to get a clear idea of how the ePWM functions.

33
 Figure 4.5: Block Diagram of F28335 [2]

4.1.2.1 Time-base submodule

The function of time-base module is to take charge of the event timing for its

own ePWM module. The structure and block diagram of the time-base submodule

containing registers is shown in Fig. 4.4. The main function of the time-base sub-

module is to find the PWM time-base block relative to the system clock. The PWM

time-base clock is to regulate the timing of all the events in the PWM module. The

system clock period is defined as TSY SCLKOU T and the time-base clock is defined as

TT BCLK . The time-base clock period can be scaled to many times of the system clock

34
period as:

TT BCLK = TSY SCLKOU T × CLKDIV × HSP CLKDIV (4.2)

where CLKDIV and HSP CLKDIV are bits in the time-base control register

(TBCTL) that helps to set the time-base clock pre-scale.

The time-base submodule is also used to specify the period of the time-base

counter (TBCTR) depending in which mode it is operating. There are three modes

of operation for the time-base submodule, which can be selected in time-base control

register (TBCTL), namely up-count mode, down-count mode and up-down mode. In

the first mode and the second mode, TBCTR always keep incrementing or decre-

menting all the time giving a saw tooth carrier wave. But the third one i.e. up-down

mode, the TBCTR increments in the first half of the PWM period and then decre-

ments the second half part of the PWM period giving a triangular carrier wave. The

main difference of the up-down mode is that in one period the counter changes in a

symmetrical fashion, where the corresponding movement to the PWM carrier peak

time is easily found. The peak time of the PWM carrier wave has to be known for

signal sampling and that is the reason why up-down mode count mode is used in this

project. To obtain the desired PWM frequency, the value in time-base period regis-

ter (TBPRD) is supposed to be determined. For up-down-count mode, the relation

between time-base period and PWM frequency can be written as:

TP W M = 2 × T BP RD × TT BCLK (4.3)

1
fP W M = (4.4)
TP W M
where TP W M stands for PWM period and TT BCLK for time-base clock period. From

the above relations, the value in the time-base period register can be determined as

follows
1 fSY SCLKOU T
T BP RD = × (4.5)
2 fP W M × CLKDIV × HSP CLKDIV

35
Therefore the only parameters that have be known to compute TBPRD are DSP

system clock frequency and the desired PWM frequency. The parameters that have

been used in this project for the configuration of DSP are PWM frequency of 10

kHz and the system clock frequency of the DSP F28335 is 150MHz. The values for

CLKDIV and HSPLCLKDIV, used in this project are 1 and 1 for convenience. From

the above equation, the value set in the time-base period register can be calculated

directly as shown below.

1 150M
T BP RD = × = 7500 (4.6)
2 10k × 1 × 1
Besides, synchronization between different ePWM modules can also be realized in

the time-base submodules. The three-phase PWM is used to produce a three-phase

alternating voltage, hence the synchronization between the three-phase PWM signals

is very important. Each ePWM module has two signal for synchronization between

different ePWM modules. One is synchronization input EPWMxSYNCI and second

is synchronization output EPWMxSYNCO. The Fig. 4.5 shows time-base counter

synchronization scheme for F28335. It can be seen that the PWM modules are con-

nected in series with the synchronization output EPWMxSYNCO of the previous

one fed onto the synchronization input EPWMxSYNCI of the next one. Only the

input synchronization for the first ePWM module is taken from an external pin.

For each ePWMmodule, once apulse from the synchronization input is detected, the

value in the time-base phase register (TBPHS) will be loaded into time-base counter

(TBCTR), where time-base phase register (TBPHS) will be loaded into time-base

register (TBPHS) is used to store the time-base counter (TBCTR) phase value of the

ePWM module with respect to the time-base of its synchronization input signal. As

we know that the inverter output are three phase voltages which are leading or lagging

each other by 120, this is not going to show up in the project i.e. the three PWM sig-

nals have the same phase at any moment. The ePWM module ePWM1, ePWM2 and

ePWM3 are selected for the three-phase PWM generation. Hence the time-base phase
36
 Figure 4.6: Internal modules of ePWM and their connections [3]

register (TBPHS) for the ePWM modules are assigned the value of 0. It means that

there is no phase shift between the output signal ePWM1A, ePWM2A and ePWM3A.

To synchronize between different ePWM modules, the synchronization output select

bit (SYNCOSEL) in the time base control register (TBCTL) is supposed to be con-

figured. ePWM1 is defined as the master phase to generate a synchronization output

EPWM1SYNCO pulse each time its time-base counter (TBCTR) equals zero, while

ePWM2 is defined as a slave phase whose synchronization input EPWM2SYNCI

signal is enabled. Meanwhile, ePWM2s synchronization output EPWM2SYNCO sig-

37
 Figure 4.7: Time base counter synchronization scheme for F28335

nal is set equal to its synchronization input EPWM2SYNCi signal to drive it into

ePWM3 unit. Except ePWM1, the other modules ePWM2 and ePWM3 have to load

the time-base counter (TBCTR) with the time-base phase register (TBPHS) when a

synchronization input EPWMxSYNCI pulse appears.

4.1.2.2 Counter-compare submodule

More practically approaching the things, the PWM waveform generation is mainly

achieved by the comparison between a counter (TBCTR) value (carrier wave) and a

set-point (reference wave) which is stored in counter-compare register. Fig. 4.6 shows

the way to generate a PWM waveform. In the PWM waveform generation process, the

counter-compare submodule (CC) takes the part of event generation, while the action

qualifier takes action on other things. In counter-compare submodule, there are two

counter-compare registers: counter-compare A register (CMPA) and the counter-

compare B register (CMPB) to store the values which are used to compare values

against time-base counter (TBCTR) submodule continuously. The time-base counter

(TBCTR) is treated as the input while the generated event TBCTR = CMPA or

TBCTR = CMPB is the expected output. The Fig. 4.6 show the way it is done

38
in this project. Whenever the carrier wave hits the counter-compare (CMPA) value

on the rise, the ePWMxA is set to off and whenever the carrier ePWMxA hits the

counter-compare (CMPA) value on the down-count, ePWMxA is set to on. This

process is explained in action qualifier submodule.

Figure 4.8: Counter-compare event, up-down counter mode

4.1.2.3 Action Qualifier submodule

The action qualifier submodule takes action whenever the generated events from

the previous submodules are available. The previous submodules that have to gener-

ate events are time-base submodule and counter-compare submodule and hence these

two submodule events are the inputs to the action qualifier submodule. The first one

generates event TBCTR = 0 and TBCTR = TBPRD while the second one produces

TBCTR = CMPA and TBCTR = CMPB. Having time-base counter (TBCTR) state

incrementing or decrementing, the four events are expanded into eight event combi-

nations. When a specified event takes place out of the eight events, there are four

possible actions to be triggered whether to set it high, to low, to toggle and to do

nothing, which can determine the shape of the PWM waveform. The action qualifier
39
output control register (AQCTLA) is used to define the actions that should be taken

if specified events occur. The conditions that are selected in this project to be con-

figured such that when TBCTR = CMPA and TBCTR is decrementing, ePWMxA

is set to high; while TBCTR is incrementing, ePWMxA is cleared low. The arrows

in the figure shows the direction of time-base counter.

4.1.2.4 Deadband submodule

By now we have the ePWMxA signal generated by the action qualifier submodule.

We also require a complimentary signal which is required to feed both the upper and

lower IGBTs in the same leg of the inverter. The dead band submodule can be used

to take the ePWMxA as the signal source and then to produce the two mutually

complimentary PWM outputs as ePWMxA and ePWMxB. The structure of dead-

band submodule is shown in Fig. 4.7. The function of dead band submodule depends

on the six switches present in it. Different combinations of the switches generate

different modes for signal pairs. Since there are six switches, many combinations can

be produced. But in this project, we dont use many of them. The reason behind

inserting the dead band into the ideal PWM waveform is to avoid the two IGBTs

on the same bridge leg of the inverter turned on simultaneously. Therefore operating

mode Active High Complementary (AHC) is selected as the desired one for a pair of

power switches in one phase of a 3-phase motor control system, which can be achieved

by setting the states of the switches in Fig. 4.7, which can be configured in dead band

control register (DBCTL). In Fig. 4.7, a rising edges delay block and a falling edges

delay block are used to insert a rising edge delay or a falling edge delay into the

original PWM output. With the switch S4 and S5 set to 0, ePWMxA is chosen as the

input source for both output A and B. By setting switch S2 to 0 and S1 to 1, a rising

edge delay is inserted into the original ePWMxA signal; by setting switch S3 and S0

to 1, ePWMxA signal is reversed with a falling edge delay added, which is output as

ePWMxB signal. The generated PWM signal in Active High Complimentary mode is
40
 Figure 4.9: Block diagram of ePWM dead band submodule

shown in Fig. 4.8. It can be observed that there is an extremely short period of each

PWM period, when both outputs of the ePWMx module are cleared, which avoids

the mutually complimentary PWM signals are set high at the same time.

4.1.2.5 Event Trigger submodule

The occurrence of events of ADC and PWM should be such that the PWM

output should trigger the ADC start of conversion. But sometimes in a sampling

period, the ADC start of conversion is executed first, then the sampled data is used

to calculate the PWM output. This shouldnt happen which might return in wrong

results. Therefore ADC and PWM signals should be synchronized to function in the

same pace. The event trigger submodule in ePWM is to issue interrupt request or

ADC conversion after receiving event inputs. In order to avoid aliasing from current

ripple, the carrier wave peaks are always chosen as the sampling time instants. Both

TBCTR = 0 and TBCTR = TBPRD can meet this requirement and sampling. In

this project, TBCTR = 0 is defined as the event that triggers ADC start of conversion

A by EPWMxSOCA pulse. It is not required to sample at both at TBCTR = 0 and

41
 Figure 4.10: Waveform of PWM with dead band inserted

TBCTR = TBPRD.

4.1.2.6 Duty cycle calculation

The most important part of the PWM generation is the duty cycle. The value

entered in the counter-compare register corresponds to the duty cycle of the PWM

period. So the counter-compare event register (CMPA) needs to be updated once in

each PWM period to generate the PWM wave with varying duty cycle. The relation

between the values set in CMPA register and PWM duty cycle can be written as:

CM P A = T BP RD × (1 − D) (4.7)

All the submodule roles are introduced in previous sections. The specific output value

of the inverter should be equal to the digital signal given by the DSP, at any point

of time. For instance, let us take an extreme situation case, phase A. The output

voltage for phase A is controlled by switch S1 and S4 and the PWM signals imposed

on S1 and S4 are mutually complimentary. The Vdc is defined as the DC link voltage
42
for the inverter. During a sampling period of the PWM, the switch S1 is turned on

and switch S4 is turned off for the same period. It also can be said in this way that,

the duty cycle of the PWM wave fed to switch S1 is 100 percent, the output voltage

of phase A should be +Vd c/2; on the other side, if the switch stays off and switch S4

is turned on for the whole cycle, the duty cycle for switch S1 is 0 percent, the output

voltage of phase A turns to be V dc/2. And if both the switches are on for one half

of the cycle period, the average voltage of phase A is supposed to be 0. From the

principle of PWM, as the carrier wave of the modulation is triangular wave, from the

basic geometrical knowledge it can be found that the relation between the output

phase voltage from the inverter and the corresponding PWM duty cycle is linear. In

general, if the PWM duty cycle stands at any one point in the range from 0 to 1, the

output voltage for phase A, can be written as:

+Vdc −Vdc
Va = ( ) × Da + ( ) × (1 − Da ) (4.8)
2 2

where Da is denoted as the duty cycle for the upper IGBT of the bridge leg connected

to phase A. From the above relation, the duty cycle can be written as

Va + V2dc
Da = (4.9)
Vdc

The complimentary PWM waveform ePWMxB for the lower IGBT on the bridge leg

can be generated by reversing ePWMxA in the dead band submodule. Hence only one

counter-compare register (CMPA) is required for the generation of one pair of PWM

outputs on the same bridge leg. From the above relations, the value set in CMPA

can be easily calculated. This process applies to other two phases. As a result, the

duty cycles for three phases can be derived as

Va
CM P Aa = T BP RDa (0.5 − ) (4.10)
Vdc
Vb
CM P Ab = T BP RDb (0.5 − ) (4.11)
Vdc
43
 Vc
CM P Ac = T BP RDc (0.5 − ) (4.12)
Vdc
The subscript implies the phase that the register values belong to.

4.1.3 Encoder Module

The enhanced quadrature encoder pulse (eQEP) module [23] of the F28335 is

used to process the digital signal form the encoder built on top of the motor. There

are four different modes in which the quadrature module is able to run. They are

quadrature mode, direct count mode, up count and down count mode. In quadrature

mode, the eQEP module receives two square wave signals from the encoder. These

two square wave signals (A and B) have 90 phase shift with respect to each other,

which can be used to determine the rotation direction. If square wave A is leading

with respect to square wave B, then the rotation is said to be in clockwise direction

and on the other side, if the square B is leading with respect to square wave A,

then the rotation is said to be in anti-clockwise direction. In direction-count mode,

one square wave signal and one direction signal are sent to the eQEP module. The

counter in the module will increase or decrease depending on the direction. For both

modes, an index pulse signal is used to determine the absolute position of the encoder.

The operating mode of the eQEP module is selected by the type of encoder. As the

incremental encoder is used in this project outputs the quadrature signals, the eQEP

module is set to be working in quadrature-count mode. The general block diagram

of eQEP module is shown in Fig. 4.11 which shows the functionality of the encoder.

Two quadrature waves are sent to the QA pin and QB pin of the decoder block

as shown in the Fig. 4.11. Every falling or rising edge of QA and QB will generate

a clock signal (QCLK), which is passed to the position counter (QPOSCNT) from

the decoder. The QPOSCNT will increase or decrease by 1 unit on each pulse of

QCLK, depending on the direction signal (QDIR). If the rotation is clockwise, the

QPOSCNT will increase by 1 unit for every pulse. If the rotation is anti-clockwise,

the QPOSCNT will decrease by 1 unit for every pulse. The following Table 4.2 show
44
 Figure 4.11: Block diagram of eQEP module [4]

the details of the values of QDIR and QPOSCNT. Fig. 4.12 shows the example

waveform of the eQEP, which has the quadrature QA and QB pins, index pulses.

Every time the position counter (QPOSCNT) is reset by the index signal. When it

meets the index signal for the first time, the eQEP module will remember the present

edge and the rotating direction in the first index marker register.

For instance, if the first counter reset happens on the falling edge of QB during

the clockwise direction, then all the later results must be aligned with the falling edge

of QB for the clockwise direction and with the rising edge of QB for the anti-clockwise

direction. The position counter can be reset by the overflow or underflow of itself.

For underflow the limiting value is zero. For the overflow, the upper limiting value

is QPOSMAX, which is the value stored in the QPOSMAX register. This value is

set in the eQEP module in the project. If you do not set the underflow or overflow,

the counter is automatically reset to 0 during the clockwise rotation and reset to

QPOSMAX during the anti-clockwise rotation. If the period of the vector control

loop is set to t, then the rotating speed of the encoder can be calculated as

1s
Speed = × 60rpm (4.13)
t
45
 Table 4.2: Encoder Truth table

Previous Present QDIR QPOSCNT

Edge Edge

QB↑ 1 increment

QA↑ QB↓ 0 decrement

QA↓ TOGGLE increment or decrement

QB↓ 1 increment

QA↓ QB↑ 0 decrement

QA↑ TOGGLE increment or decrement

QA↑ 1 increment

QB↑ QA↓ 0 decrement

QB↓ TOGGLE increment or decrement

QA↓ 1 increment

QB↓ QA↑ 0 decrement

QB↑ TOGGLE increment or decrement

This condition applies if the encoder rotates one revolution during one control loop

period.

4.1.4 Offset Measurement

Generally, both the current and speed measurements contain a small offset, which

is due to the presence of sensors or the ADC conditioning circuit. These offset of either

the currents or the speed should be measured when the machine is in standstill mode

with all the other modules or devices switched on. The measured offset current from

the three phases should be subtracted from the ADC results in the code to compensate

for the current offset. In order to get the samples of current offset, the DSP is allowed

to settle for some time, allow DSP to run in steady state and then the offset can be

sent to the oscilloscope or can be measured by taking many sample per second and

taking average of them. The speed offset can be done using the same way as the

current offset.

4.2 Hardware Setup

An experimental setup is designed in the Energy and Power lab in order to im-

plement the simulink code on to the DSP. Fig 4.13 shows the setup that has been
46
 Figure 4.12: An example waveform of the eQEP (anti-clockwise rotation)

used for the project. The idea of the setup is to have all the equipment namely power

supplies, inverter, DSP board, transformers and the motor on the same platform.

The setup has access to limited input ports and output ports which are used in this

project. There are two switching power supplies in the setup out of which, one acts

Figure 4.13: Harware Setup in the lab

as the input source for inverter (48V DC) and the other acts as input source for DSK

board (24V DC). Since the input voltage for the inverter is 48V DC , the maximum

47
voltage that can be obtained from the inverter is 24V (Vdc/2). The output of the

inverter is then boosted up to 240V using three boost tansformers. The transformer

connections are delta-delta connected. The PWM signals generated digitally and the

analog values in the DSK are sent to the inverter using bus cables as shown in the fig.

4.13. The DSP is emulated using USB JTAG emulator through which, the program

in the computer is sent to the DSP. The DAC pins at the bottom of the figure are

used to receive output signals such as voltages, currents and speed. A serial Commu-

nications interface is setup and connected to computer which enables the serial (one

bit at a time) exchange of data between the DSP and the computer.

4.3 System Initialization and Configuration of CCS V5.5

4.3.1 Initialization

After switching the power supply on, the DSP has to be initialized. The already

installed controlSU IT E supports any user with initialization functions corresponding

to each function unit. The initialization functions only provide the most basic sup-

ports for running the system, for example to initialize the system clock or to enable

some modules.

4.3.2 Configuration
The modules present in the design can run in different modes depending on the

application. But for this project, to run our application, the module units are con-

figured to suitable operating mode as shown in below sections. Each module is taken

individually and both the C code and the Simulink code are presented to illustrate

the difference in configuration setting. The tables 4.3, 4.4 and 4.5 shows the configu-

rations set in this project in each module.

48
 Table 4.3: Configuration of ADC

ADC Clock 12.5MHz

Sampling mode Simultaneous

Operating Mode Start/Stop

No. of Conversions 8

Sampling mode 1 ADC Clock

Sequence mode Cascaded

Trigger Source PWM

Interrupt Post Sequence

(a) (b)

Figure 4.14: Simulink code configuration for ADC

Table 4.4: eQEP configuration

Maximum position counter value 4294967295

Positive Rotation Clockwise Rotation

Positive counter mode Quadrature-count

Gating option On Index pulse

Position counter reset mode On maximum value

49
 (a) (b)

Figure 4.15: Simulink configuration for eQEP

Table 4.5: ePWM configuration

PWM frequency 10kHz

Operating mode Shadow mode

Synchronization mode series

Phase shift 0

CTR mode Up-down

Load mode CTR=0

ADC trigger CTR=0

50
Figure 4.16: Simulink configuration for ePWM

51
 Figure 4.17: Simulink configuration for ePWM

4.3.3 Configuration of CCS V5.5

As discussed earlier, Code Composer Studio is an Integrated Development En-

vironment (IDE) that supports Texas Instruments Microcontrollers and Embedded

Processors. It consists of all the tools that are used to develop and then debug embed-

ded applications. Code Composer Studio also contains optimizing C/C++ compiler,

source code editor, project build environment, debugger, profiler and many other fea-

tures. The IDE provides a single user interface taking you through each step of the

application development flow. Getting familiar with all the tools and features of the

software makes it easier. Code Composer Studio combines advantages of the Eclipse
52
software framework with advanced embedded debug capabilities from TI resulting in

a highly rich development environment for embedded developers.

The figures below and the theory corresponding to the figures helps a new user to

configure CCS v5.5 at any point of time. The early process of configuring CCS v5.5

is to generate a makefile, which is used to automate building and then deploying the

software on target hardware.

4.3.3.1 Makefile Setup

If the control design is done in Simulink, navigate to the command prompt win-

dow, where you can see a command enter signal as >>. If you see that symbol, enter

the command xmakefilesetup in the Matlab command window. The command pops

up the dialog box which is shown in Fig. 4.13

Figure 4.18: Make file configuration in Matlab

If the dialog box does not show up in the same way as the above figure, then the
53
things that should be taken care are the clone configurations. The instructions for

achieving this configuration are: Firstly, clear the check box for display operational

configurations only and click on the N ew configurations, which should pop a display

box showing the names of the configurations. Select the appropriate configurations

for the application and then it creates a configuration that can be applied for the

project.

4.3.3.2 Configuration Parameters

In this section, a brief discussion about setting the configuration parameters in

order to generate an output file, which is appropriate and suitable for the DSP that is

being used in this project. Coming to the solver pane of the configuration parameters,

the values should be selected for the start and stop times of the code and also the solver

type should be selected. The parameters that have been used for this project are the

fixed step solver and discrete solver. Some of the parameters are set by default and are

not necessary to be modified. However, it depends on the application used. Coming

to the hardware section, the hardware that is being implemented in this project is

the Texas Instruments Product and the device is a C2000 family type. Under the

Code generation pane, it should be noticed that the system target file is selected as

idelink − grt.tlc. By doing it that way, the system links the IDE environment to the

target hardware. Also a new pane called coder target pane is available, where all the

parameters about the actual hardware are updated. Later on under the coder target

pane, the build format is set to makefile, since the output format we selected earlier

for the embedded tool was makefile.

The action is set to Build and Execute, which enables the system to build an exe-

cutable file. This process almost sets the configuration of CCS v5.5 on to the system

and you are ready to go. Before you start building the code on CCS v5.5, just make

sure to have everything correct, in case you had something not fixed. The first time

you use embedded coder with Code Composer Studio, you should check that the CCS
54
is installed and configured properly and also has at least one board configured. To

do that, enter the command ccsboardinf o in the Matlab command prompt window.

Matlab, then returns all the boards that are configured and recognized by the CCA

as shown as below.

Also, if necessary check all the third party tools and environment variables that

are set in the configuration using the command checkEnvsetup(ccs, f 28335, check).

The Fig.4.14 shows the environment variables set in this project.

Figure 4.19: Environment variables defined in the project

The next section explains about the incremental build technology.

55
4.4 Incremental Build Technology
Even though the programming is done by evaluating each block at a time, like

modular programming, sometimes it is difficult to debug if all the modules are lumped

together at a time. Therefore, the program structure is built level by level. Every

time before building a new level, the old level should be working correctly.

4.5 Troubleshooting DSP

Sometimes, there might be errors in the code that leads to damage in the DSK

board, which might be issue in many cases. In this section, brief discussion about some

of the damages that could be done to the DSP and the troubleshooting techniques to

repair the DSP are explained.

For the first case, let us take an example of having excess current flowing in

the circuits of DSK, which might result in the damage od some of the parts in the

DSK. If you experience bad smell from the DSK board or an unpleasant smell from

the board, immediately turn the system off, as there is some problem in the code.

Coming to troubleshooting the DSP, firstly, check the power circuit underneath the

DSK board and you can see the circuit leading from the 24V power supply to the

15V power supply of the PWM signal generation. It can be clearly noticed that the

power supply of the PWM is damaged and has to be replaced. The damaged PWM

power supply is then de soldered and then it should be replaced with a new power

supply. This would hopefully make the DSK work properly.

For the second case, let us take an example of overwriting the DSP default vari-

ables and clearing everything from the memory, which might result in the damage to

the main chip in the DSK. The symptoms to this problem are that you may not be

able to receive correct waveforms from ADC and PWM. This problem can only be

eliminated by replacing the chip on the DSK with a new one and that should work

properly.

56
5. Testing and Evaluation

In this chapter, the testing results are shown. As mentioned before, the control

system is programmed in three levels, namely the open loop system, system with cur-

rent regulator and the system with speed regulator, and its performance is evaluated

for all three levels as well.

5.1 Open loop test with V/F control

The open loop test is carried out by setting different frequency to the V/F con-

troller and observing the corresponding motor speed. The testing data are listed in

Table 5.1 and compared with the actual motor speed.

Table 5.1: Open loop test with V/F control

Frequency set(Hz) 10 15 20 25 30 35 40

Synchronous speed(rpm) 300 450 600 750 900 1050 1200

Machine speed(rpm) 295 440 586 730 862 1000 1110

Slip 1.67% 2.22% 2.33% 2.67% 4.22% 4.76% 7.5%

It can be seen from the table 5.1 that, the induction motor runs slightly slower

than the synchronous speed. With increase in the frequency, the slip is also increasing.

This might be due to the reason that the friction torque becomes larger with increasing

motor speed. Therefore larger slip is needed to generate enough torque.

5.2 Closed loop test with Current Regulator

One of the advantage of the setup we use in this project is that the user is able to

access the DAC memory, while the processor is still running. In order to capture the

dynamic response of d and q currents, two memory locations are allocated and can be

directly accesses using the oscilloscope. Once the step change in current reference is

applied, in each control loop, the value of d and q current is stored in the memory until

the memory if full. In the code, if these variables are converted directly to integer, the
57
resolution will be greatly reduced. To guarantee enough resolution, before converting

a variable, the variable is multiplied by 4095 or 2047, depending on how large its

maximum value is.

(a) (b)

Figure 5.1: Step response of the d and q currents.Fig(a) is the step response of the

d current with a reference of 80mA, and fig(b) is the step response of the q current

with a reference of 80mA.

(a) (b)

Figure 5.2: Response in q current due to a step in i current. Fig. (a) shows q

current with respect to step in d current and Fig. (b) shows q current with respect

to quadrature reference i.e. zero

This analysis part is done in this section.

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5.2.1 Analysis on Results
From Fig. 5.1(a) and Fig. 5.1(b), it can be seen that the rise time of both id

and iq are same and matches the design specifications. Though there is noise on

both the curves, it can be noticed that the currents arrive at their reference values

without steady-state error. The only problem is that we have a overshoot in the

iq waveform. Since the desired closed-loop system is a first-order system and anti-

windup has been added, there should not be any large overshoot. But other than

that, all other parameters have a satisfying result.

5.3 Closed Loop test with Speed Regulator

As the speed loop has much slower response than the current loop, more data

needs to be stored to study the step response of the speed loop.

5.3.1 Experimental Results

In the first design plan, the bandwidth for the speed control loop αω is chosen as

20rad/sec. In order to eliminate the non-linearity and two much fluctuation, a much

smaller bandwidth αω for the speed control loop and a smaller reference speed are

applied in the experiment to avoid q current hitting its limit.

Figure 5.3: Speed step response at 300rpm and very small bandwidth

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5.3.2 Analysis on Results

Given the speed control loop bandwidth αω , the rise time of the speed response

is noticed to be satisfactory. Also, it is approaching steady state as it gets a larger

acceleration which causes an unnoticeable overshoot. But the difference between the

simulation results and the experimental results might be due to inaccurate speed

sensing, incorrect motor parameters like B and J, the motor coefficients. The other

factor might be due to inaccurate flux estimation. The variation in the machine

parameters will greatly affect the flux estimation. The error between the estimated

and the actual flux will lead to a wrong calculation of the q current reference, which

will cause a series of reactions and unexpected results.

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6. Simulink or C: A comparitive study

This chapter discusses the main research contribution to this project. In the past

few years, C language has been a primary language for the interface between the real

time models. But, in this project, unlike various other projects which uses C as their

interfacing language, the conventional C language has been replaced by Simulink,

an environment for simulation and model-based design for dynamic and embedded

systems.

6.1 Introduction to C
Embedded Processors can be programmed using various languages. However, the

most common language used to program embedded processors is C language. The

following figure Fig. 6.1 shows that C is used by more than a four-to-one margin over

its nearest competitor, Assembly language.

Figure 6.1: Programming Languages used in Embedded Designs [5]

The reason that C language is used widely in programming embedded machines

is that it is a medium level language, in contrast to other high languages like JAVA or

low languages like Assembly. C, with its medium level of complexity is understandable
61
to humans, executes at a reasonably fast speed, and usually allows programmers to

exercise enough control over the inner working of the embedded processor. This

balance between intelligibility and fundamental control make C language the prime

choice for embedded processor programming. Sometimes, when additional control or

an extremely fast execution speed is needed for a specific instruction, a few lines of

Assembly language may be combined with the main C program.

6.1.1 How does C work?

When a program is written in any language more complex than Assembly (which

can be immediately processed by a computer), several steps are required to convert

that program into an executable file. C in the form that a programmer writes is called

source code, and must go through the build process to generate functional code. This

source code must first be compiled, once compiled the resulting object code is linked

using a linker program. A linker attempts to find any libraries of code that the object

might need to perform its function (e.g. other object code compiled from other source

code); links these bits of code together; and creates an .exe executable file that can

be run.

6.1.2 Drawbacks of C
As discussed above, it is understood that the C language is the widely used

programming language globally because of its executing speed and efficiency. In con-

trast to the advantages produced by the old standby computing language that many

would call obsolete: ANSI C, there are some drawbacks that could be encountered in

developing a model for a particular design. C and other higher languages have be-

come popular for modelling DSP algorithms because of the more concise expression of

behavior. However, these languages lack an effective automated path to implementa-

tion. To become implementable, the tradeoff for description languages like C should

become less concise. Sometimes the C becomes so complicated at instances like aug-

menting C with fixed-point quantization capabilities and loop parallelization. Also,

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C language is considered as difficult to learn in very short period of time. Sometimes,

because of the conciseness in C, the code can be difficult to follow. I does not suite to

applications which require formatting and data file manipulation. For learning how

to write programs in C, we must first know what alphabets, numbers and symbols are

used, then how constants, variables and keywords are formed, and finally how these

are combined to form an instruction.

6.1.3 Replacement for C

Having mentioned all the drawbacks that will be encountered when developing a

project using C as the main language, this section will explain the alternative language

that should be replaced in place of traditional language C. The main reason that a

different approach is used in this project is to reduce the overall time that takes for the

entire vector control algorithm to be implemented and deployed on target hardware

efficiently.

6.2 Introduction to Simulink

After many discussions and debates on using C language in designing vector

control, in this project, a new approach of using Simulink as the interface between

the software and the hardware. Also, this approach enabled us to create a completely

new technology of using Simulink to execute a makef ile to run the hardware, as well

as to generate optimized C code automatically, using Simulinks extension tool called

embeddedcoder. This approach proved beneficial for this project as you can generate

both the Simulink and C code at the same time and in a reduced amount of time.

6.2.1 Flexibility with Simulink

In order to complete this project successfully, we have taken two approaches

into consideration, that can implemented similarly on the target hardware and then,

both the approaches are compared for the time length of the project. The Fig. 6.2

shows the flow chart diagram representing the various steps involved in both the

approaches. As seen from the figure, both the approaches produce the same result.
63
However, approach1 does not offer flexibility in transiting to a different approach,

which in our case is appraoch2. But, appraoch2 offers a much flexibility in doing the

same thing.

Figure 6.2: Illustration of two different approaches that can be used in the project

This section covers the advantages of simulink over C

6.3 Advantages of Simulink over C

Simulink provides an interactive graphical environment and a customizable set

of block libraries that let you design, simulate, implement, and test a variety of

64
time-varying systems, including communications, controls, signal processing, video

processing and image processing. Simulink offers the quickest way of developing your

model in contrast to text-based programming language like C. Also, Simulink has

integrated solvers. But, for C, you have write to write the code to create a solver.

Simulink provides an efficient design and simulation framework for creating high-level

algorithm models and limited capabilities that directly assist in implementation. More

specifically, it allows for defining sample rates and fixed-point data types, a discrete-

time modelling engine, and a rich set of mathematical operations and analysis tools.

Furthermore, it includes methods for automatically propagating the fixed-point types

and sample rates through the algorithm data path. This process saves significant

time in capturing algorithm behavior.

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7. Conclusions

7.1 Results from Present work

The main purpose and objective of this project are generally achieved. The

evaluation board seems to be working well for this project. Considering the interface

board part, the digital signal interfaces, such as PWM and incremental encoder, work

satisfactorily. But, if you observe the current signals from ADC, there is some noise

added to the measured signals. For the vector control design, the control system

on the DSP manages to control the d,q currents and speed accurately. One of the

problems that can be observed from the experimental results is the overshoot in q

current during the current control loop test. It was assumed that the problem might

be due to incorrectness in the parameters.

In the final section of this project, a comparison is done between the old con-

ventional approach and new approach used in this project in designing the vector

control algorithm. It can be concluded that, the approach which uses Simulink as the

interfacing language seems to have higher efficiency and flexibility in terms of time

when compared to the approach which uses C as the interfacing language for those

who are inexperienced in both approaches.

7.2 Future work

There is a room to improve the performance of the present system. Considering

ADC noise, the ADC conditioning circuit needs to be improved. New control strate-

gies could also be considered for control design in order to make system less sensitive

to parameter variation and reduce harmonic distortion. Finally, from many research

papers, it is understood that there is a possibility of controlling several motors simul-

taneously to make full use of F28335 DSP’s capacity.

66
 REFERENCES

[1] Texas Instuments. http://www.ti.com/lit/ug/spru812a/spru812a. pages 9–13.

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35.

[3] Texas Instuments. www.ti.com/lit/pdf/sprufz6. pages 14–18.

[4] Texas Instuments. http://www.ti.com/lit/ug/sprug05a/sprug05a. pages 9–15.

[5] D. Lewis. Fundamentals of embedded software design. Prentice Hall, 2002.

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Rep.

[7] K. Aissa and K. D. Eddine. Vector control using series iron loss model of in-
duction, motors and power loss minimization. World Academy of Science, En-
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[8] An887 ac induction motor fundamentals. Microchip, Tech. Rep., 2003.

[9] M. Deicke and Rik W. De Doncker S. Muller. Adjustable speed generators

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converters linked to the rotor. IEEE, 2000.

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[16] Texas Instruments. Code Composer Studio Integrated Development Environ-
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Appendix A. Simulations and Waveforms

A.1 Simulations

Figure A.1: Simulink model for V/F

Figure A.2: Simulink model for V/F subsystem

69
Figure A.3: Simulink model for Current control

70
Figure A.4: Simulink model for Speed control

71
A.2 Waveforms

(a) (b)

Figure A.5: (a) shows Stator voltages in abc reference frame and (b) shows Stator

voltages in stationary reference frame

Figure A.6: Stator voltages in rotating reference frame

72
 (a) (b)

Figure A.7: (a) shows Stator currents in abc reference frame and (b) shows Stator

currents in stationary reference frame

Figure A.8: Stator currents in rotating reference frame

73
Figure A.9: Theta varying from −Π to +Π

Figure A.10: Offset in current

74