POWER ELECTRONICS

LABORATORY MANUAL

DEPARTMENT OF ELECTRICAL
ENGINEERING

COLLEGE OF ENGINEERING TRIVANDRUM

April 2021

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Contents

0.1 Course Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

0.2 Course Outcomes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
0.3 General Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
0.4 List of Hardware Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . 9
0.5 List of Simulation Experiments . . . . . . . . . . . . . . . . . . . . . . . . . 10

1 Static Characteristics of SCR 11

1.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.1 Reverse Blocking Mode: . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.2 Forward Blocking Mode . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2.3 Forward Conduction Mode . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4.1 Reverse blocking characteristics . . . . . . . . . . . . . . . . . . . . . 13
1.4.2 Determination of Igt . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.4.3 Forward blocking characteristics . . . . . . . . . . . . . . . . . . . . . 14
1.4.4 Forward conduction characteristics . . . . . . . . . . . . . . . . . . . 14
1.4.5 Find Latching and Holding Current . . . . . . . . . . . . . . . . . . . 14
1.5 Outcome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.6 Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2 Phase Control Circuits using R and RC Triggering Circuits 17

2.1 R-Triggering Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.1 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.3 RC Triggering Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3.3 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4 Outcome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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 2.5 Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Ramp Based Line-Synchronised Triggering Circuit 22

3.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5 Outcome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6 Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4 Line-Synchronised Digital Triggering Circuit 26

4.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.3 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5 Outcome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.6 Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5 AC Voltage Controller Using TRIAC 30

5.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.5 Outcome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.6 Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6 Single Phase Fully Controlled Converter Feeding DC motor Load 34

6.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

7 Design and Simulation of Buck Converter 37

7.1 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8 Gate driver circuit for MOSFET 39

8.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.4 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.5 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.6 Outcome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.7 Questions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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 Preface

Power Electronics is one of the key areas of Electrical Engineering. The significance of
Power Electronics is continuously on the rise due to the increased use of drive systems, static
switches, SMPS, active filters, renewable energy integration to the grid and so on. The
undergraduate students of Electrical Engineering need to get a thorough understanding of
the theoretical and practical fundamentals of Power Electronics.
This manual is an updated version with some corrections and additions. This is prepared
to help the students do the experiments related to the course ”Power Electronics and Drives
Lab”, with ease, and to pose interesting questions which, the enterprising students may seek
answers on their own, enriching the laboratory experience.
I take this opportunity to express thanks to Dr. Sreejaya P., Professor & Head of the
Department of Electrical Engineering, for her continued interest and encouragement for this
work. We are also thankful to all faculty members of the Electrical Engineering Department
for their cooperation in the preparation of this manual. I gratefully acknowledge the efforts
of Mr. Akhil Nandan and Mr. Arun K. Vijayan, M.Tech scholars of the department in
typesetting this version.

Dr. Dinesh Gopinath

Department of Electrical Engineering
College of Engineering Trivandrum
Thiruvananthapuram, Kerala

April 2021
 DEPARTMENT VISION AND MISSION

VISION

Be a centre of excellence and higher learning in electrical engineering and

allied areas.

MISSION

• To impart quality education in electrical engineering and bring-up

professionally competent engineers.
• To mould ethically sound and socially responsible electrical engineers
with leadership qualities.
• To inculcate research attitude among students and encourage them to
pursue higher studies.

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 Program Educational Objectives (PEOs)

Graduates will:

• Excel as technically competent Electrical Engineers.

• Excel in higher studies and build on fundamental knowledge to develop technical

skills within and across disciplines.

• Have the ability to function effectively as members or leaders in technical teams.

• Adapt to changes in global technological scenario and societal needs through lifelong
learning.

Program Outcomes (POs)

PO1 Engineering knowledge: Apply the knowledge of mathematics, science, engineering

fundamentals, and an engineering specialization to the solution of complex
engineering problems.

PO2 Problem analysis: Identify, formulate, review research literature, and analyze
complex engineering problems reaching substantiated conclusions using first principles
of mathematics, natural sciences, and engineering sciences.

PO3 Design/development of solutions: Design solutions for complex engineering

problems and design system components or processes that meet the specified needs
with appropriate consideration for public health and safety, and the cultural, societal,
and environmental considerations.

PO4 Conduct investigations of complex problems: Use research-based knowledge

and research methods including design of experiments, analysis and interpretation of
data, and synthesis of the information to provide valid conclusions.

PO5 Modern tool usage: Create, select, and apply appropriate techniques, resources,
and modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.

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 PO6 The engineer and society: Apply reasoning informed by the contextual knowledge
to assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.

PO7 Environment and sustainability: Understand the impact of the professional

engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.

PO8 Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.

PO9 Individual and team work: Function effectively as an individual, and as a member
or leader in diverse teams, and in multidisciplinary settings.

PO10 Communication: Communicate effectively on complex engineering activities with

the engineering community and with society at large, such as, being able to
comprehend and write effective reports and design documentation, make effective
presentations, and give and receive clear instructions.

PO11 Project management and finance: Demonstrate knowledge and understanding of

the engineering and management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multidisciplinary
environments.

PO12 Life-long learning: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological
change.

Program Specific Objectives (PSOs)

(What the graduates of a specific undergraduate engineering program should be able to do

at the time of graduation)

PSO1: Apply engineering knowledge to analyse, model, design and operate modern systems
for generation, transmission, distribution and control of electrical power.

PSO2: Design, develop and test modern hardware and software systems for signal processing,
measurement, instrumentation and control applications.

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0.1 Course Objectives
The objectives of this course are:

1. To introduce practical power conversion circuits.

2. To introduce basic design practices in power electronic circuits.

3. To familiarise the students with modelling and simulation techniques for power
electronic circuits.

0.2 Course Outcomes

After successful completion of this laboratory course, the students will be able to:

1. Develop test procedures to characterize power semiconductor devices and evaluate

their operating parameters.

2. Design, set-up and test basic gate drive circuits for thyristors with
line-synchronisation.

3. Set-up and test basic power converters with varying load conditions.

4. Develop simulations for power conversion circuits with varying operating conditions.

5. Develop simulations for basic motor drive schemes.

0.3 General Instructions

• Safety measures and dress codes as applicable to Electrical Laboratories are to be
strictly followed in Power Electronics Lab.

• Students must keep separate rough record and fair record for the lab class.

• Circuit diagram, tabular column etc. should be drawn in the rough record before each
lab class.

• While drawing circuit diagrams, use standard symbols as far as possible.

• Draw the circuit diagrams in the fair record with pen only (not pencils).

• Prepare the tabular columns in the following format.

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0.4 List of Hardware Experiments
1. Static characteristics of SCR
Aim: Determine latching current, holding current and static characteristics of SCR.

2. R and RC firing circuits

Aim: Design and set up R and RC firing circuits and observe waveforms across load
resistance and SCR.

3. UJT trigger circuit with single-phase controlled rectifier

Aim: Design & set up UJT Triggering Circuit and observe waveforms across load
resistance, SCR, capacitance and pulse transformer output.

4. Static characteristics of MOSFET

Aim: Plot the characteristics of a Power MOSFET.

5. AC Voltage Controller using Triac

Aim: Set a 1-phase AC Voltage Controller & observe waveforms across load
resistance, triac and capacitor for different firing angles.

6. Single Phase fully-controlled SCR Bridge circuit

Aim: Set up a 1-phase full converter with RL load & with and without freewheeling
diode.

7. Single-phase half bridge/full bridge inverter using power MOSFET/IGBT

Aim: Design and set up a single-phase half-bridge/full-bridge inverter and observe the
waveforms across load and firing pulses.

8. Single-phase sine PWM inverter with LC filter

Aim: Design and set up a single-phase sine PWM inverter with LC filter using
microcontroller.

9. Chopper controlled DC motor

Aim: Control the speed of a DC motor using a step-down chopper.

10. Speed control of 3-phase induction motor

Aim: Control the speed of 3-phase induction motor using V/f control.

11. IGBT based Three-phase PWM Inverter

Aim: Set up a 3-phase PWM Inverter with RL load and observe the waveforms.

12. Closed Loop Control of Single-phase fully-controlled Rectifier

Aim: Design and set up a closed loop control circuit for a 1-phase fully-controlled
rectifier such that it keeps the load voltage constant irrespective of the load variations
(use R load).

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0.5 List of Simulation Experiments
1. Simulation of 1-phase fully-controlled and half-controlled rectifier fed separately
excited DC motor.
Aim: Simulate 1-phase fully-controlled and half-controlled rectifier fed SEDC motor
and observe the speed, torque, armature current, armature voltage, source current
waveforms and find the THD in source current and input power factor.

2. Simulation of closed loop speed control of DC motor with different control schemes
(PID, Hysteresis current control, Fuzzy, ANFIS etc).

3. Simulation of open loop or closed loop speed control of 3-phase induction motor using
V/f control and using sine PWM.

4. Design and simulation of buck, boost and buck-boost converters.

5. Simulation of Dual Converter – 4 quadrant operation – separately excited DC motor.

6. Simulation of Regenerative Braking – Bidirectional Power Transfer.

7. Simulation of Switched Mode Rectifiers – keeping load voltage constant irrespective of

line and load variations – closed loop circuit simulation.

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Experiment 1

Static Characteristics of SCR

1.1 Objectives
1. To experimentally determine the forward-blocking, forward-conducting, and
reverse-blocking characteristics of an SCR.

2. To experimentally determine the latching and holding currents of an SCR.

3. To experimentally determine the minimum gate voltage and current required to

turn-on an SCR.

1.2 Theory
A Silicon Controlled Rectifier (SCR) is the oldest and the most widely used member of the
thyristor family. The SCR is a four-layer PNPN device with three junctions. It has three
terminals: Anode, Cathode and Gate. The SCR is used essentially as a controlled switch.
High reliability, high current and voltage ratings are some of the major features which make
the SCR suitable for power control in many high-power applications, especially the ones
that require phase-control of line-frequency AC power.
The static V-I characteristics of an SCR are shown in Fig. 1.1. The SCR has three basic
modes of operation: reverse blocking mode, forward blocking mode (off state) and forward
conduction mode(on-state).

1.2.1 Reverse Blocking Mode:

When the cathode is positive with respect to the anode, junctions J1 and J3 (See Fig. 1.2)
are reverse biased and J2 is forward biased. Only a small reverse leakage current of the
order of a few milliamperes flows and the device is in the reverse blocking mode. When the
voltage is increased to the reverse breakdown voltage, the depletion layers at the junctions
J1 and J3 break down and the current through the device increases to a high value. The

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 iA , A

ig3 > ig2 > ig1

ig3 > igt,min

iL ig3 ig2 ig1 ig = 0

ih
VBO vAK

Figure 1.1: v-i Characteristics of SCR

Figure 1.2: PNPN structure of SCR

high current at high voltage causes more losses in the device, and the junction temperature
may exceed the permissible value resulting in the damage of the device.

1.2.2 Forward Blocking Mode

When the anode is made positive with respect to the cathode, junctions J1 and J3 are
forward biased and junction J2 is reverse biased. The reverse biased junction J2 limits the
anode current to a few milliamperes (forward leakage current). The SCR is then said to be
in the forward blocking mode. Application of a small positive gate current causes increase
of forward leakage current, which in turn causes triggering of conduction at a voltage less
than the forward break-over voltage.

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1.2.3 Forward Conduction Mode
When the SCR is in the forward blocking mode, if the anode to cathode voltage is increased
to the forward break over voltage, junction J2 breaks down so that the SCR becomes
equivalent to a conducting diode. The voltage across the device falls to a small value and
the anode current is limited by the load impedance. When the forward voltage is less than
the forward break-over voltage, the SCR can be triggered into conduction by applying a
pulse of positive gate current. At higher gate trigger currents, the turn-on happens at lower
anode-to-cathode voltage and at lower gate current, the turn-on happens at higher anode to
cathode voltage. If the gate current is sufficiently large, the device can be turned on with a
small anode to cathode voltage. The minimum gate current at which a forward-biased SCR
turns on is an SCR specification, denoted usually as Igt,min .

1.3 Design
The design of this circuit is done by selecting 2P4M (SCR). Some essential parameters of
these devices are provided below (for more details, please refer the Data sheet)
Gate Threshold Voltage,VGT = 0.8V
Gate Threshold Current,IGT = 200
Max. Anode Current,IAmax = 2A
VGG − VGT
RG >= (1.1)
IG T
VSS
RLmin = (1.2)
IAmax

1.4 Procedure
1.4.1 Reverse blocking characteristics
Make the connections as in Fig. 1.3. The 100 V source must be a dc power supply with
current limit. The current limit for the power supply shall be kept under about 1 A, to
ensure that current is kept within limits in case of a breakdown of the SCR while doing the
experiment. Keeping the potential divider in the minimum position, switch on the supply.
Increase the cathode to anode voltage gradually and note the ammeter and voltmeter
readings. The SCR selected should be having a reverse breakdown voltage greater than
100 V.

1.4.2 Determination of Igt

To find the minimum gate current required to turn on the SCR, connections are made as in
Fig. 1.3. The anode circuit resistance is kept in the maximum position and the supply is

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 0 − 100µA

A
Gate open
G
Rh1
100 V V T1
1000Ω
0 − 100V

Figure 1.3: Circuit to find out reverse blocking characteristics

switched on. The gate voltage is gradually increased till the SCR is turned on. The gate
current when the SCR just turns on (indicated by a sudden increase in anode current) is
the value of Igtmin .

1.4.3 Forward blocking characteristics

Keeping the gate circuit open, the anode to cathode voltage is increased in steps each time
noting the ammeter reading. Now the switch S1 is closed and the gate voltage is adjusted
to get 0.5 Igt and the procedure is repeated.

1.4.4 Forward conduction characteristics

After making the connections as in Fig 1.4, the gate voltage is adjusted to get sufficient
gate current to turn on the SCR. Supply is switched on keeping the anode circuit resistance
maximum . After making sure that the SCR is conducting, now the anode current and the
anode to cathode voltage are recorded. The anode current is increased in steps and the
anode to cathode voltage is noted in each case.

1.4.5 Find Latching and Holding Current

After making the connections as in Fig 1.5, keep proper anode to cathode voltage to trigger
SCR by gate current. Then trigger SCR by applying gate current. Gradually decrease
Anode to Cathode voltage in steps and at each step switch-off the gate supply and observe
that, whether device remains in the ON state or not. Repeat the procedure (by trial and
error method) till the SCR jumps to blocking state, and then note down the minimum
value of anode current which keeps device in the on state as Latching current.

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Figure 1.4: Circuit to determine forward conduction characteristics

Figure 1.5: Circuit to determine latching and holding current

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 To fing the holding current, Keep proper anode to cathode voltage to trigger SCR by
gate current. Then trigger SCR by applying gate current. Switch-Off the gate source. Now
gradually decrease anode to cathode voltage and note down the minimum value of anode
current below which, the device suddenly falls from ON-state to OFF- state as Holding
current.

1.5 Outcome
After doing this experiment, the student should be able to design experiments to obtain the
static characteristics of SCR and other power devices.

1.6 Questions
1. Explain the working of SCR using two transistor analogy.

2. Can you apply a forward voltage across the thyristor soon after the reverse recovery
current drops to zero? Justify your answer.

3. List the important specifications/ratings of an SCR.

4. What are the conditions for successful turn-on of an SCR?

5. What are the conditions for successful turn-off of an SCR?

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Experiment 2

Phase Control Circuits using R and

RC Triggering Circuits

2.1 R-Triggering Circuit

2.1.1 Objective
To set up a resistance trigger circuit for a phase-controlled rectifier.

2.1.2 Theory
The resistance trigger circuit is the simplest means of triggering a thyristor from the main
supply. The circuit provides phase control essentially from 0 to 90 electrical degrees of the
anode voltage.
Fig 2.1 shows the basic arrangement of triggering a thyristor using a resistance triggering
circuit. The thyristor will trigger when the minimum gate current is applied and gate
voltage is available. In the circuit shown the condition is reached when the instantaneous
anode voltage is related as
e= RIGT +VGT +VD
Where, IGT -Minimum gate current in amperes to trigger the thyristor at the prevailing
junction temperature and the instantaneous voltage.
VGT -The minimum gate voltage to trigger the thyristor corresponding to IGT and
VD - Voltage drop of the diode D1 .
The diode D1 is provided to prevent reverse voltage from being applied to the gate during
the reverse part of the anode voltage. The diode should have a peak inverse voltage rating
greater than the peak value of the anode voltage.
As the potentiometer P1 is varied the thyristor will trigger in accordance with the equation
shown above. The circuit provides continuously variable control for the thyristor from full
ON (firing angle 0◦ ) to half ON (firing angle 90◦ ).

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 Figure 2.1: R trigger circuit

2.2 Design
The design of this circuit is done by selecting 2P4M (SCR) . Some essential parameters of
these devices are provided below (for more details, please refer the Data sheet)
Gate Threshold Voltage,VGT = 0.8V
Gate Threshold Current, IGT = 200microA
Max. Anode Current, IAmax = 2A
Max. Gate Current, IGmax = 200mA
Max. Gate Voltage, VGmax = 6V

Vmax
R1 >= (2.1)
IG max
For firing angle α
Vm Sinα − 0.7
Rmax = (2.2)
200microA
VGM R1
R2 <= (2.3)
Vm − VGM

2.2.1 Procedure
Note down the minimum gate current and the minimum gate voltage of the thyristor from
the datasheet. Calculate the value of R from the equation knowing the maximum value of

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 Figure 2.2: RC triggering circuit

the anode voltage. Set up the circuit and take down the waveform across the thyristor T1
and load (Rh1).

2.3 RC Triggering Circuit

2.3.1 Objective
To set up RC triggering circuit of single-phase half wave-controlled circuit.

2.3.2 Theory
The resistance triggering circuit provides phase-controlled delay of 0 to 90 electrical degrees
only. RC triggering circuit provides control for 0 to 180 degrees of the anode voltage.
Fig. 2.2 shows RC triggering circuit. On the positive half cycle of the thyristor anode
voltage, the capacitor will charge to the triggering point of the thyristor. The time required
to reach the trigger point is determined by the time constant RC and the rising anode
voltage.

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Figure 2.3: Waveform of R triggering circuit

Figure 2.4: Waveform of RC triggering circuit

20
On the negative half cycle, the top plate of the capacitor will charge to peak value of the
negative voltage cycle through D2. Thus, resetting it for the next charging cycle.
The value of RC is chosen empirically as,

RC ≈ 1.3T /2
where T = 1/f .
When VC = VGT + VD1 the thyristor will trigger, provided gate current IGT is available.
Since the anode voltage across capacitor is essentially constant at the instant of triggering,
the current IGT must be instantaneously supplied through resistor R.
Hence, R < (e - VD1 - VGT ) / IGtmin

2.3.3 Procedure
Design values for R and C for the given thyristor and anode voltage. Set up the circuit and
test it. Observe the voltage across thyristor, load and capacitor for different firing angles.
Plot the waveforms for a particular firing angle.

2.4 Outcome
Students should be able to design and set up the R and RC triggering circuits and analyse
the output waveforms.

2.5 Questions
1. What is the order of magnitude of the on-state voltage of thyristor?

2. “A conducting thyristor can be turned off by applying a negative pulse at the gate”.
Is this statement true? If not, how a conducting thyristor can be turned off?

3. What are the advantages and disadvantages of simple R, RC triggering circuits?

4. What are the disadvantages of RC triggering circuit? How this is overcame in RC

circuit using Diac?

5. How the power circuit can be modified to achieve full-wave controlled rectification
with a single SCR and still using R or RC triggering circuit?
Experiment 3

Ramp Based Line-Synchronised

Triggering Circuit

3.1 Objective
To design and set up a ramp-control trigger circuit for a thyristor in a single-phase half
wave-controlled rectifier.

3.2 Theory
For phase-controlled rectification the trigger pulse must be synchronized with the main
supply. In the ramp control circuit as shown in Fig. 8.1, a ramp generator circuit produces
a saw-tooth waveform synchronised with the main supply. This ramp is compared with a dc
level using an op-amp comparator.
The output of the comparator is the trigger pulse which may be applied directly or through
an amplifier and pulse-transformer to the thyristor gate. The trigger delay can be varied by
varying the dc level applied to the comparator. The dc level variation is obtained by
adjusting the potentiometer P1.

3.3 Design
Assume the value of capacitor as 1 µF. The capacitor is charged at a constant current.
Then the capacitor voltage will rise according the expression:
i×t
V = (3.1)
C
Assume the height of the ramp (maximum voltage) as 5 V at 10 ms, then:
C ×V 1 × 10−6 × 5
i= = = 0.5 mA
t 10 × 10−3

22
 Figure 3.1: Ramp controlled trigger circuit

Figure 3.2: Ramp controlled trigger circuit – waveforms

23
Assume emitter resistance voltage as about 3V, then
3
RE = = 6 kΩ
0.5 × 10−3
Take RE as 5.6 kΩ. With RE = 5.6 kΩ, VRE = 5.6 × 103 × 0.5 × 10−3 = 2.8 V .
Assume I2 = 0.1 mA. The base current will be negligible when compared to I2 .
Vcc 12
R1 + R2 = = = 120 kΩ
I2 0.1 × 10−3

VB = VCC − VRE − VBE = 12 − 2.8 − 0.7 = 8.5 V

Also, we have:
VCC × R2
VB =
R1 + R2
Then,
VB × (R2 + R2 ) 8.5 × 120
R2 = = = 85 kΩ
Vcc 12
R1 = 120 − 85 = 35 kΩ
Take R1 = 33 kΩ and R2 = 82 kΩ, being the nearest standard values.

3.4 Procedure
Setup the circuit and observe the waveforms at different point by varying the firing angle.
Plot the waveforms for two typical firing angles. Observe the range of firing angle.

3.5 Outcome
Student should be able to:

• Design and set up the ramp-control line-synchronised triggering circuit and observe
the waveforms.

• Modify the design to change the range of firing angle to different limts.

• Modify the design to suit fully-controlled converters, by incorporating additional logic.

24
3.6 Questions
1. How do you modify the circuit for application in a fully controlled rectifier?

2. Explain the design of constant current source and reset circuit of part of the ramp
control circuit.

3. Suggest an alternative way of implementing the circuit with an opamp comparator as

an ZCD instead of the transistor based ZCD. Consult the datasheet of a typical
comparator IC LM339 that can reduce the number of components in the circuit.
Design the circuit with LM 339.

25
Experiment 4

Line-Synchronised Digital Triggering

Circuit

4.1 Objectives
1. To design, set-up and test a line-synchronised triggering circuit for half-wave
controlled rectifier using digital ICs.

2. To modify the design to suit for fully-controlled converters.

4.2 Theory
In phase-controlled converters, the trigger pulse must be synchronised to the mains supply
waveform. The transistor Q1 in Fig. 4.1 produces a rectangular pulse at its collector,
synchronised with the zero-crossings of the mains waveform. The positive going edge of this
pulse is used to trigger the mono-shot U1, which generates a variable-width pulse at its
output. The negative edge1 of this pulse is used to trigger mono-shot U2, whose output is
the desired trigger pulse. It may be noted that the mono-shot 1 shall be designed with a
minimum pulse width of 10 ms, and a maximum pulse width corresponding to 20 ms so as
to get a firing-angle range of 0o to 180o . The trigger delay can be varied by varying the
pulse width of mono-shot U1, which is achieved by the variable resistor RV1.

1
See how the edge triggering is altered by connecting A1, A2 and B pins of the mono-shot 74121 to
appropriate levels. For more details, consult the datasheet of 74121.

26
27
Figure 4.1: Circuit diagram of line-synchronised digital triggering circuit
 Line voltage

ωt
α

5V Test point 3:
Trigger to Mono 1
5V
Test point 4:
Trigger to Mono 2
5V Test point 5:
Output of Mono 2,
(Gate pulse)

Figure 4.2: Waveforms

4.3 Design
Assume that the firing delay vary from 0 to 9 ms. For mono-shot U1, T = 0.7Rx Cx . Take
C1 = 1µF . Then, the minimum time for mono1 is 10 ms, corresponding to minimum firing
delay, and the maximum pulse width for the mono 1 is 10+9 = 19 ms corresponding to the
maximum firing angle. See Fig. 4.2. Hence the minimum value of Rx is:

10 × 10−3
Rmin = = 14.285 kΩ
0.7 × 1 × 10−6
The maximum value of Rx is given by:

19 × 10−3
Rmax = = 27.142 kΩ
0.7 × 1 × 10−6
Choosing standard values, we may take a resistance R3 of 15 kΩ and a series variable
resistor RV1 of 12 kΩ.
Mono U2 is designed with a desired minimum constant pulse width. This is in accordance
with the requirement of the minimum gate pulse width. Let Tmono2 = 0.5 ms. Choose Cx
(C2)for mono U2 as 0.1 µF . Then Rx for mono U2 is:

0.5 × 10−3
Rx = = 7.142 kΩ
0.7 × 0.1 × 10−6
Take R4 as 8.2 kΩ.

28
4.4 Procedure
Set up the circuit on a bread-board. Observe the waveforms at different test points (TP1 -
TP5), under varying firing angles. Plot the waveforms.

4.5 Outcome
After doing this experiment, the student will be able to design, set-up and test line-synchronised
digital triggering circuit for a half-wave controlled rectifier, and modify it to suit fully-
controlled converters.

4.6 Questions
• Which of the mono-shot ICs are designed with negative edge triggering?

• What modification would you suggest to the circuit, to include a high-frequency pulse
train instead of a single pulse as the gate pulse?

• What modification would you suggest to increase the drive-capacity of this circuit?

• How would you modify this circuit to include gate-drive isolation?

• Modify this circuit with proper logic gates and gate isolation circuits to suit a fully
controlled converter.

• Redesign the circuit with an Opamp comparator (LM 311) as the ZCD and IC 555 as
the monostable multivibrator.

• What are the limitations of this circuit?

29
Experiment 5

AC Voltage Controller Using TRIAC

5.1 Objective
To study and setup, a Triac circuit for ac phase control.

5.2 Theory
A Triac is a bi-directional device. The term cathode and anode are not applicable and con-
nections are simply designed by numbers (MT1 and MT2 ). The volt ampere characteristics
lies in the first and third quadrants. The device is normally triggered by a positive signal at
the gate when MT2 is positive and by a negative signal, when MT2 is negative with respect to
MT1 (other modes of triggering are also possible). Fig. 5.1 shows the static v-i characteristics.
RC phase control circuit can be used for triggering a Triac. This circuit, however, is not
stable and usually requires a large value of capacitor. A much better circuit is one that uses
a Diac as trigger device.
Diac’s are available with breakdown voltage in the range of 10-40 volts. Fig. 5.2 shows a
phase control circuit using Triac. As the voltage across the capacitor reaches the breakdown
value of Diac in either direction, a sudden discharge pulse from the capacitor triggers the
Triac. The trigger current is not dependent on the resistance value as in the case of RC
triggering. Therefore, a large value of resistance and smaller capacitance can be used. As
the breakdown point of Diac is very stable, the trigger point also is very stable.

5.3 Design
The design of this circuit is done by selecting BT136 (TRIAC) and DB3 (DIAC). Some
essential parameters of these devices are provided below (for more details, please refer the
Data sheet)
BT136
Gate Threshold Voltage,VGT = 0.25V

30
Figure 5.1: VI characteristics of TRIAC

Figure 5.2: Triac firing circuit using Diac

31
 Figure 5.3: Triac circuit waveforms

Gate Threshold Current, IGT = 35mA

Max. Gate Current, IGM = 2A
DB3
Threshold Voltage, VT = 32V

R = R 2 + P1

VS − VGT − VT
R <= (5.1)
IG T
√
Peak value of Input Voltage Waveform , VS = 110 2
1.3T
RC >= (5.2)
2
VS
R2 = (5.3)
IGM

5.4 Procedure
Setup the circuit as shown in Fig. 5.2. Adjust the fire angle using the potentiometer and
trace the waveforms of load voltage, voltage across Triac etc. Care has to be taken while
using two-channel oscilloscopes, as the channels are not isolated electrically. Hence, when two
waveforms are to be simultaneously seen on the scope, the probe grounds shall be connected
only to one point. The design of the RC network can be done with the same empirical relation

32
used for RC triggering circuit. It is to be noted that the capacitor charges to both polarities
of voltage, hence it should not be an electrolytic capacitor.

5.5 Outcome
Student should be able to understand the working of TRIAC and its output waveforms.

5.6 Questions
1. Compare the performance of a triac with that of two SCR connected in anti-parallel.

2. Is it possible to connect a FWD at the output of a triac controller?

33
Experiment 6

Single Phase Fully Controlled

Converter Feeding DC motor Load

6.1 Objective
To set up and study a single phase fully controlled bridge rectifier feeding a dc motor load
and observe the performance.

6.2 Theory
The circuit diagram of a single phase fully controlled bridge converter feeding a dc motor
load is shown in Fig. ??. The single phase fully controlled bridge converter is obtained by
replacing all the diode of the corresponding uncontrolled converter by thyristors. Thyristors
T1 and T2 are fired together while T3 and T4 are fired 180o after T1 and T2 . From the circuit
diagram it is clear that for any load current to flow at least one thyristor from the top group
(T1 , T3 ) and one thyristor from the bottom group (T2 , T4 ) must conduct. It can also be
argued that neither T1 − T3 nor T2 − T4 can conduct simultaneously. For example, whenever
T3 and T4 are in the forward blocking state and a gate pulse is applied to them, they turn
ON and at the same time a negative voltage is applied across T1 and T2 commutating them
immediately. Similar argument holds for T1 and T2 . For the same reason T1 − T4 or T2 − T3
cannot conduct simultaneously. Therefore, the only possible conduction modes when the
current I0 can flow are T1 − T2 and T3 − T4 . Of course, it is possible that at a given moment
none of the thyristors conduct. This situation will typically occur when the load current
becomes zero in between the firings of T1 − T2 and T3 − T4 . Once the load current becomes
zero all thyristors remain off. In this mode the load current remains zero. Consequently, the
converter is said to be operating in the discontinuous conduction mode (DCM).

Figure 6.3 shows the voltage across different devices and the dc output voltage during

34
Figure 6.1: Single Phase Fully Controlled SCR R Load

Figure 6.2: Single Phase Fully Controlled SCR RL Load

35
 Figure 6.3: Waveforms of voltage and current across/through load, thyristor and source.

each of these conduction modes. It is to be noted that whenever T1 −T2 conducts, the voltage
across T3 and T4 becomes negative. Therefore,T3 and T4 can be fired only when vi is negative
i.e., over the negative half cycle of the input supply voltage. Similarly, T1 and T2 can be
fired only over the positive half cycle of the input supply. The voltage across the devices
when none of the thyristors conduct depends on the off-state impedance of each device. The
values listed in Figure assume identical devices.
Under normal operating condition of the converter the load current may or may not
remain zero over some interval of the input voltage cycle. If i0 is always greater than zero
then the converter is said to be operating in the continuous conduction mode. In this mode
of operation of the converter T1 − T2 and T3 − T4 conducts for alternate half cycle of the input
supply. However, in the discontinuous conduction mode none of the thyristors conduct over
some portion of the input cycle. The load current remains zero during that period.

36
Experiment 7

Design and Simulation of Buck

Converter

7.1 Objectives
To design and simulate a buck converter circuit.

7.2 Theory
A buck converter performs power conversion from a higher voltage dc source to a lower
voltage dc load. Figure 7.1 shows the circuit diagram.
The switch S (MOSFET in this example), is turned ON and OFF with a switching
frequency fs . When the switch is turned ON, the supply voltage Vg is connected to the LC
filter. When the switch is OFF, the diode conducts and hence the LC filter has zero voltage
applied across it. When the inductor current is continuous, the waveforms are as shown in
Fig. 7.1 (b). By assuming negligible ripple in the output voltage and continuous conduction
mode, the principle of volt-sec balance on the inductor yields the voltage gain of the
converter as:
Vo
M= =D (7.1)
Vg

From the waveforms, we can obtain the expressions for the value of L and C as follows:

(1 − D)
L = Vo (7.2)
fs ∆IL
(1 − D)Vo
C= (7.3)
8Lfs2

37
 S

S L iL DTs Ts
io
+ vL - + vL
ic (Vg − Vo )

Vg D C R Vo

0 DTs Ts
-
Vo
iL ∆IL

0
DTs Ts
(a) (b)
Figure 7.1: Buck Converter

38
Experiment 8

Gate driver circuit for MOSFET

8.1 Objective
8.2 Theory
Every power semiconductor-controlled device requires a gate signal to enter into the
conduction state. The nature of the gate drive needs depends on the voltage and current
ratings, as well as the type of device. The power MOSFET gate is electrically insulated
from the rest of the system. There should be no current flows in the ideal situation.
When a DC voltage is delivered to the gate, a leakage current flows(of the order of 10−10 A).
As a result, a small current is sufficient to
charge. and discharge the capacitance of the device.
TTL or CMOS digital logic circuits can readily be used to drive the gate of a power
MOSFET directly. Because CMOS has limited source and sink current capaci-
ties (2 and 4 mA @ VDD 12 V, respectively), the Miller effect (charging and discharg-
ing current requirements) is likely to create a slight de-
lay in rise and fall times. The CMOS IC, on the other hand, can drive the gate di-
rectly with the needed amount of driving voltage. When Vcc is less than 5 V, the out-
put voltage available for a TTL device with a totem pole output is around 3.5 V. This volt-
age (3.5 V) might not be enough to get the MOSFET into conduc-
tion mode. TTL, on the other hand, offers better source and sink capabilities than CMOS.

39
 Figure 8.1: Ramp controlled trigger circuit

Figure 8.2: Ramp controlled trigger circuit – waveforms

40
 8.3 Theory
8.4 Design
8.5 Procedure
8.6 Outcome
8.7 Questions
1.

2.

3.

41