DIGITAL ELECTRONICS LAB MANUAL

FOR IV SEMESTER B.E (ECE / EI)

DEPARTMENT OF ELECTRONICS & COMMUNICATION

NATIONAL INSTITUTE OF TECHNOLOGICAL, ROURKELA

1

CONTENTS

Experiment No

Page. No

1. VERIFICATIONOFGATES03 2. HALFADDER/FULLADDER/SUBTRACTOR08 3. Multiplexer and demultiplexer

4. COMPARATORS 5. FLIPFLOP 6. COUNTERS 7. SHIFTREGISTERS

EXPERIMENT 1

VERIFICATION OF GATES

Inverter Gate (NOT Gate)

7404LS

2-input AND gate

7408LS

2-input OR gate

7432LS

2-input NAND gate

4

7400LS

2-input NOR gate

7402LS

2-input EX-OR gate

7486LS

3-input NAND gate

7410LS

2-input NAND gate

CD4011

2-input NOR gate

CD4001

4-input NAND gate

7420LS

Experiment 2

Half/full adder & Half/full subtractor

7

Aim: - To realize half/full adder and half/full subtractor. i. ii. Using X-OR and basic gates Using only NAND gates.

Apparatus Required: IC 7486, IC 7432, IC 7408, IC 7400, etc.

Procedure: 1. Verify the gates. 2. Make the connections as per the circuit diagram. 3. Switch on V CC and apply various combinations of input according to the truth table 4. Note down the output readings for half/full adder and half/full subtractor sum/difference and the carry/borrow bit for different combination of input.

Half Adder using basic gates:8

Full Adder using basic gates:-

Half Adder using NAND gates only:-

Full adder using NAND gates only:9

1)

Using X-OR and basic gates (a) Half subtractor

(b) Full subtractor

2)

Using only NAND gates

10

(a)Half subtractor

(b)

Full subtractor

11

12

Experiment :-3

Multiplexer And Demultiplexer

Aim: - To verify the truth table of multiplexer using 74153 & to verify a demultiplexer using 74139. To study the arithmetic circuits half-adder half Subtractor, full adder and full Subtractor using multiplexer. Apparatus Required: IC 74153, IC 74139, IC 7404, etc. Procedure: - (IC 74153) 1. The Pin [16] is connected to + Vcc. 2. Pin [8] is connected to ground. 3. The inputs are applied either to A input or B input 4. If MUX A has to be initialized, Ea is made low and if MUX B has to be initialized, E is made low. 5. Based on the selection lines one of the inputs will be selected at the output and thus the truth table is verified. 6. In case of half adder using MUX, sum and carry is obtained by applying a constant inputs at I0a, I1a,I2a,I3a and I0b,I1b,I2b and I3b and the corresponding values of select lines are changed as per table and the output is taken at Z0a as sum and Z0b as carry. 7. In this case, the channels A and B are kept at constant inputs according to the table and the inputs A and B are varied. Making Ea and Eb zero and the output is taken at Za, and Zb. 8. In full adder using MUX, the input is applied at Cn-1, An and Bn According to the table corresponding outputs are taken at Cn and Dn.

13

Half Adder using 74153:-

Full Adder using 74153:-

Half Substractor :-

Full Substractor:-

14

Pin Details:

15

Procedure: - (IC 74139) 1. The inputs are applied to either a input or b input 2. The demux is activated by making Ea low and Eb low. 3. The truth table is verified

16

Experiment no:-4

COMPARATORS
Aim: - To verify the truth table of one bit and two bit comparators using logic gates. Apparatus Required: IC 7486, IC 7404, IC 7408, etc Procedure: 1. Verify the gates. 2. Make the connections as per the circuit diagram. 3. Switch on Vcc. 4. Applying I/p and Check for the outputs. 5. The voltmeter readings of outputs are taken and tabulated in tabular column. 6. The o/p is verified.

One bit comparator

17

Two bit comparator

4-bit comparator

18

8-bit comparator

Tabular column for 8-bit comparator

19

Experiment no:-5

FLIP-FLOP
Aim: - Truth table verification of Flip-Flops: 1) JK Master Slave 2) D- Type 3) T- Type Apparatus Required: IC 7410, IC 7400, etc. Procedure: 1. Connections are made as per circuit diagram. 2. The truth table is verified for various combinations of inputs Circuit Diagram: -

Master Slave JK Flip-Flop

20

D Flip-Flop

T Flip-Flop

21

Truth Table:-

Master Slave JK Flip-Flop

D Flip-Flop

T Flip-Flop

22

Experiment no: - 6

COUNTERS
Aim:- Realization of 3-bit counters as a sequential circuit and Mod-N counter design (7476, 7490, 74192, 74193). Apparatus Required:IC 7408, IC 7476, IC 7490, IC 74192, IC 74193, IC 7400, IC 7416, IC 7432 etc. Procedure: 1. Connections are made as per circuit diagram. 2. Clock pulses are applied one by one at the clock I/P and the O/P is observed at QA, QB & QC for IC 7476. 3. Truth table is verified. Procedure (IC 74192, IC 74193):1. Connections are made as per the circuit diagram except the connection from output of NAND gate to the load input 2. The data (0011) = 3 is made available at the data i/ps A, B, C & D respectively. 3. The load pin made low so that the data 0011 appears at QD, QC, QB & QA respectively. 4. Now connect the output of the NAND gate to the load input 5. Clock pulses are applied to count up pin and the truth table is verified 6. Now apply (1100) = 12 for 12 to 5 counter and remaining is same as for 3 to 8 counter. 7. The pin diagram of IC 74192 is same as that of 74193. 74192 can be configured to count between 0 and 9 in either direction. The starting value can be any number between 0 and 9

23

Circuit Diagram: - 3-Bit Asynchronous Down Counter

Mod 5 Asynchronous Counter:-

24

Mod 3 Asynchronous Counter:-

25

3-bit Synchronous Counter:-

IC 7490 (Decade Counter):-

26

IC 7490 (MOD-8 Counter):-

Circuit Diagram (IC 74193) To Count from 3 to 8:-

Circuit Diagram (IC 74193) To Count from 8 to 3:-

27

Function Table for 7490:-

4 I/P OR Gate can be realized as follows:-

28

Experiment:-7 SHIFT REGISTERS

Aim: - Realization of 3-bit counters as a sequential circuit and Mod-N counter design (7476, 7490, 74192, 74193). Apparatus Required: IC 7495, etc. Procedure: Serial In Parallel Out:1. Connections are made as per circuit diagram. 2. Apply the data at serial i/p 3. Apply one clock pulse at clock 1 (Right Shift) observe this data at QA. 4. Apply the next data at serial i/p. 5. Apply one clock pulse at clock 2, observe that the data on QA will shift to QB and the new data applied will appear at QA. 6. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the shift register. Pin diagram: Truth Table:-

29

Serial In Serial Out:1. Connections are made as per circuit diagram. 2. Load the shift register with 4 bits of data one by one serially. 3. At the end of 4th clock pulse the first data d0 appears at QD. 4. Apply another clock pulse; the second data d1 appears at QD. 5. Apply another clock pulse; the third data appears at QD. 6. Application of next clock pulse will enable the 4th data d3 to appear at QD. Thus the data applied serially at the input comes out serially at QD

Pin Diagram:

Truth Table:-

Parallel In Parallel Out:1. Connections are made as per circuit diagram. 2. Apply the 4 bit data at A, B, C and D. 3. Apply one clock pulse at Clock 2 (Note: Mode control M=1). 4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD respectively.

30

Truth Table:-

Parallel In Serial Out:1. Connections are made as per circuit diagram. 2. Apply the desired 4 bit data at A, B, C and D. 3. Keeping the mode control M=1 apply one clock pulse. The data applied at A, B, C and D will appear at QA, QB, QC and QD respectively. 4. Now mode control M=0. Apply clock pulses one by one and observe the data coming out serially at QD.

31

Truth Table:-

32

Left Shift:1. Connections are made as per circuit diagram 2. Apply the first data at D and apply one clock pulse. This data appears at QD. 3. Now the second data is made available at D and one clock pulse applied. The data appears at QD to QC and the new data appears at QD. 4. Step 3 is repeated until all the 4 bits are entered one by one At the end 4th clock pulse the 4 bits are available at QA, QB, QC and QD.

Pin diagram: -

Truth Table:-

Conclusion :

33