VLSI SYSTEM DESIGN

logic synthesis using VHDL

 Lecture#5
Realization of basic gates using CMOS
NOT Gate using CMOS
❖ The NOT or INVERT function is often considered the simplest Boolean operation. It has an input
A and at the output we get the inverted output.

Fig.1 Logic symbol Fig.2 NOT Gate using CMOS

CMOS Inverter
❖ CMOS inverter Consists of two complementary MOSFETS PMOS and NMOS .
❖ The source terminal of the PMOS is connected to the VDD.
❖ The source terminal of the NMOS is connected to the GND.
❖ The drain terminal of both the MOSFETs are connected together, that is output (Out).
NAND Gate using CMOS
❖ Use a complementary NMOS/PMOS pair for each input.
❖ Connect the output node to the power supply VDD through PMOS.
❖ Connect the output node to ground through NMOS.

Fig.1 Logic symbol Fig.2 NAND Gate using

CMOS
NOR Gate using CMOS
❖ Implementation of NOR gate utilizes same topology. It requires two sets of complementary pairs,
each driven by separate input.

Fig.1 Logic symbol Fig.2 NOR Gate using CMOS

Complex Combinational Logic
❖ Implement the function
• F(A,B,C,D)=
Demorgan’s Theorem
❖ NAND-OR rule
-- bubble=inversion

❖ NOR-AND rule
Complex Combinational Logic
❖ Implement the function below by constructing the NMOS network and
complementing operations for the PMOS:

❖ For NMOS
1. Invert Output
2. Eliminate NANDs and NORs
3. Reduce Function
4. Complement operations for PMOS
 Lecture#6
Physical structure of CMOS integrated
circuits
Integrated Circuit Layers
❖ The primary task of the VLSI designer is to
translate circuit schematics into silicon form; this
process is called physical design.
❖ CMOS integrated circuits are electronic switching
networks that are created on small area of a silicon
wafer using a complex set of physical and chemical
processes.
❖ Integrated circuits are a stack of patterned layers:
--Metals, good conduction, used for
interconnects
--Insulators (silicon dioxide), block conduction
--Semiconductors(silicon), conducts under
certain conditions Fig. Two separate material layers

❖ Stacked layers form 3-dimensional structures

Three-dimensional Structure
❖ Combining the top and side views of an IC allows us to visualize the three-dimensional structure:
--The side view illustrates the order of the stacking.
--Insulating layers separate the two metal layers so that they are electrically distinct.
--The patterning of each layer is shown by a top view perspective

(a) Side view (b) Top view

Fig. Layers after the stacking process is completed
Three-dimensional Structure
❖ The stacking order is established in the manufacturing process, and can not be altered by
the VLSI designer.

(a) Side view (b) Top view

Fig. Layers after the stacking process is completed
Interconnect Resistance and Capacitance
❖ Logic gates communicate with each other by signal flow
paths from one point to another
--Using patterned metal lines (interconnects)
--Current flow is governed by the physical
characteristics of the material and the dimensions of the
line
Fig.1. Symbol for a linear resistor
--Ohm’s law, V=IR
❖ Line resistance Rline: a parasitic (unwanted) electrical
element that cannot be avoided:

Fig.2. Geometry of a conducting line

Sheet Resistance Model
❖ Sheet resistance Rs, rewriting
(a) Top-view geometry

(b) Sheet resistance contributions

Fig. Top-view geometry of a patterned line

❖ We can determine how many ‘squares’ of the layer

are present from the top view of layout, Example R
= 8*Rs
 Lecture#7
Resistive and capacitive effects
 Capacitor
❖ Interconnect lines also exhibit the property of capacitance.
--In electronics, the element that stores charge is called
capacitor

--Since electric current is defined by the time derivative I

= (dQ/dt), differentiating gives the I-V equation Fig.1. Circuit symbol for a capacitor

❖ Capacitance exists between any two conducting bodies that

are electrically separated .
--For the interconnect line, the conductor is isolated from
the substrate by an insulating layer of silicon dioxide glass
-- So, the capacitance depends on the geometry of the
line

Fig.2. Geometry for calculating the line

Where is the permittivity of the insulating oxide F / capacitance
cm
Effects of R and C on performance Parameters
❖ Wires are important as they determine:
--Speed
--Power
--Noise
❖ So conventionally alternative layers run orthogonally.
 Delay: RC Time Constant
❖ The interconnect line exhibits both parasitic resistance Rline [Ω]
and capacitance Cline [F]. (a) Physical structure
❖ Forming the product of these two quantities gives

❖ In high speed digital circuits, signals on an interconnect line are

delayed by time constant, which places a limiting factor on the
speed of the network.
--VLSI processing are directed toward minimizing both
Rline and Cline.
--Circuit designers are then faced with creating the fastest
switching network within the limits of delay.

(b) Circuit model

Fig. Time delay due to the interconnect
time constant
 MOSFETs
❖ MOSFET is a small area set of two basic patterned
layers that together act like a controlled switch
--The voltage applied to the gate determines the
electrical current flow between the source and drain
terminals (a) nFET symbol (b) nFET layers
❖ Assuming that the drain and source are formed on
the same layer, then this behavior can be used to Fig.1. nFET circuit symbol and layer equivalents
deduce that
--The gate signal G is responsible for the absence
or presence of the conducting region between the
drain and source region

(a) Open switch (b) Closed switch

Fig.2. Simplified operational view of an nFET

MOSFET Device Dimension
❖ Physical dimensions of a MOSFET
• L = channel length
• W = channel width
• W/L = aspect ratio
❖ Side and Top views

Fig.1. Layers used to create a MOSFET

(a) Side view (b) Top view

Fig.2. Views of a MOSFET
 nFET and pFET
❖ The polarity of a FET (n or p) is determined
by the polarity of the drain and source regions.
❖ nFET: the drain and source regions are
labeled as “n+” to indicate that they are
heavily doped as in Figure (a).
❖ pFET: the source and drain regions are p+
sections that are embedded in an n-type “well”
layer as in Figure (b).
❖ Metal contacts have been added to connect the (a) nFET cross section (b) pFET cross section
drain and source regions to other parts of the
circuit.
Fig. nFET and pFET layers
❖ pn junction are formed between n+ regions
and the p type substrate to prevent current
flow between adjacent layers.
 Lecture#8
Fabrication of MOSFETs
Silicon wafer
• Silicon is a base material for MOS fabrication.
• Typical diameter of 4-12 inches.

Fig.1. Silicon wafer (Source:Google image) Fig.2. Die on a Silicon wafer (Source:Google image)
Fabrication Technologies
❖ CMOS fabrication can be accomplished using either of the three technologies:
--N-well/P-well technologies
--Twin well technology
--Silicon On Insulator (SOI)
Fabrication overview
❖ Oxidation
--Formation of silicon dioxide layer on the surface of Si wafer
--Dry oxidation: lower rate and higher quality
--Wet oxidation: higher rate and lower quality
❖ Deposition
--Formation a thin film on the surface of Si wafer
--Thin film materials: semiconductor, insulator and metal
❖ Implantation/diffusion
--Process steps to specify the doping species and concentration
--Ion implantation: dopants are vaporized, accelecrated and directed at a Si substrate
--Diffusion: dopants diffuse from a high-concentration source into Si substrate
Fabrication overview
❖ Etch
--Removal of specific material layers on the Si substrate
--Classified as dry and wet etch
❖ Photolithography
--Uniformly covers of the substrate with photoresist
-- Selectively exposes with a mask
--Develops the photoresist to define the desirable patterns
--Suitable for pattern definition with small feature sizes
❖ Isolation
--Isolation is required from one active area to another
--Typical isolation is provided by a thick oxide layer (field oxide)
--Parasitic channel should be prevented under the field oxide
--Local oxidation of silicon (LOCOS) technique
Fabrication process flow:
Basic steps
❖ The simplified process sequence for the fabrication of CMOS
integrated circuits on a p-type silicon substrate is as follows:
• N-well regions are created for PMOS transistors, by impurity
implantation into the substrate.
• This is followed by the growth of a thick oxide in the regions
surround the NMOS and PMOS active regions.
• The thin gate oxide is subsequently grown on the surface
through thermal oxidation.
• After this n+ and p+ regions (source, drain and channel-stop
implants) are created.
• The metallization step (creation of metal interconnects) forms
the final step in this process.
Simplified Process Sequence For Fabrication Of CMOS ICs
Process steps required for patterning of Sio2
Process steps required for patterning of Sio2
 Lecture#9
Fabrication of MOSFETs
Process flow for the fabrication of an n-FET
Process flow for the fabrication of an n-FET
Process flow for the fabrication of an n-FET
n-well Process
❖ CMOS fabrication process:
• In simplest terms, this refers to the sequence
of steps that we use to take a bare “wafer” of
silicon to the finished form of an electronic
integrated circuit.
• The n-well process starts with a p-type
substrate (wafer) that is used as a base layer.
• nFETs can be fabricated directly in the
p-type substrate.
• N-well regions are needed to accommodate
p-type substrate.
 n-well Process
❖ Visible Features
--p-substrate
--n-well
--n+ S/D regions
--p+ S/D regions
--gate oxide
--poly silicon gate
 CMOS Layers
❖ Cover lower layers with oxide insulator, Ox1
❖ Contacts through oxide, Ox1
-- metal1 contacts to poly and active
❖ Layers: (Metal, Insulator Ox2, Via contacts, Metal
2, Repeat insulator/via/metal)
❖ Full Device Illustration Fig.1 Metal interconnect layers

-- active
-- poly gate
--contacts (active & gate)
-- metal1
-- Via
--metal

Fig.2. Interconnect layout example

 Lecture#10
Designing FET Arrays
 Series MOSFET Layout
❖ Series connected transistors

a. Schematic b. Surface pattern c. Side View

❖ Multiple Series transistors

a. Schematic b. Surface pattern

Parallel MOSFET Layout
❖ Parallel transistors
--one shared S/D junction with contact
--short other S/D using interconnect layer (metal1)

a. Schematic b. Surface pattern

❖ Alternate layout strategy
-- horizontal gates

a. Schematic b. Surface pattern

Designing FET Arrays
❖ Design notes
--Both the power supply (VDD) and ground
(GND) are routed using the Metal layer
-- n+ and p+ regions are denoted using the
same fill pattern. The difference is that pFETs are a . Circuit b. Layer Patterning
embedded within an n-well boundary. Fig.1. Layout for a CMOS NOT gate
--Contacts are needed from Metal to n+ or p+
since they are at different levels in the structure.

a. Circuit b. Layer Patterning

Fig.2. Alternate layout for a CMOS NOT gate

Multi Functional Cells
❖ Sharing power supply rail connections
-- independent gate inputs and outputs
--shared power supply nodes Fig.1. Logic diagram of of Non-inverting buffer

Fig.2. Layout of Non-inverting buffer

Layout of NAND / NOR Gates

Fig.1(a). Circuit of NAND Gate Fig.2(a). Circuit of NOR Gate

Fig.1(b). Layout of NAND Gate Fig.2(b). Layout of NOR Gate

Interconnects in CMOS inverter

a. Layout diagram b. Stick diagram

 Lecture#11
MOS Structure
MOSFETs
❖ Metal oxide field effect transistor is an active three terminal device.
❖ There are two types of MOSFETs:
--Depletion-Type MOSFET
--Enhancement-Type MOSFET
Enhancement-Type MOSFET
❖ The metal-oxide-semiconductor field-effect transistor (MOSFET) is composed of a MOS structure
(MOS diode / MOS capacitor) and two pn-junctions placed immediately adjacent to the MOS
structure.
❖ A MOSFET is a charge controlled device. Charges have to be accumulated on the gate to control
the device properties. As a consequence of voltage applied to the gate a channel is formed at the
interface between dielectric an substrate.

Fig. Schematic cross section of an enhanced-type NMOS transistor. (Source: Google image)
Working of the MOSFET
 Lecture#12
I-V Characteristics of MOSFETS
 The MOS Structure
❖ The energy band diagram of a MOS structure using a p-type
semiconductor is shown in the figure under thermal
equilibrium (V=0). Before discussing the energy diagram the
following functions and energies are introduced: Energy band
diagram of an ideal MOS structure for V=0 (flat band
condition).
❖ The work function qΦ is defined as the energy required to
remove an electron from the Fermi level EF to a position
outside the material
❖ The electron affinity qχ is the energy required to remove an
electron from the bottom of the conduction band to the
vacuum level. (vacuum level).
❖ Energy band diagram of an ideal MOS structure for V=0(flat
band condition).

Fig.Energy band diagram of an ideal MOS structure for V=0