XTR110

SBOS141C – JANUARY 1984 – REVISED SEPTEMBER 2009

PRECISION VOLTAGE-TO-CURRENT
CONVERTER/TRANSMITTER

FEATURES APPLICATIONS
● 4mA TO 20mA TRANSMITTER ● INDUSTRIAL PROCESS CONTROL
● SELECTABLE INPUT/OUTPUT RANGES: ● PRESSURE/TEMPERATURE TRANSMITTERS
0V to +5V, 0V to +10V Inputs ● CURRENT-MODE BRIDGE EXCITATION
0mA to 20mA, 5mA to 25mA Outputs
● GROUNDED TRANSDUCER CIRCUITS
Other Ranges
● CURRENT SOURCE REFERENCE FOR DATA
● 0.005% MAX NONLINEARITY, 14 BIT
ACQUISITION
● PRECISION +10V REFERENCE OUTPUT
● PROGRAMMABLE CURRENT SOURCE FOR
● SINGLE-SUPPLY OPERATION TEST EQUIPMENT
● WIDE SUPPLY RANGE: 13.5V to 40V ● POWER PLANT/ENERGY SYSTEM
MONITORING

DESCRIPTION
The XTR110 is a precision voltage-to-current converter
designed for analog signal transmission. It accepts inputs
VREF Force 15 16 +VCC
of 0 to 5V or 0 to 10V and can be connected for outputs of R9
Source
4mA to 20mA, 0mA to 20mA, 5mA to 25mA, and many other VREF Sense 12 +10V
R8 1
Resistor
Reference
commonly used ranges. VREF Adjust 11 13 Source
Sense
A precision on-chip metal film resistor network provides input Gate
VIN1 (10V) 4 A2 14
Drive
scaling and current offsetting. An internal 10V voltage refer-
ence can be used to drive external circuitry. VREF In 3 R1 7 Offset
R3 (zero)
The XTR110 is available in 16-pin plastic DIP, ceramic DIP R5 6 Adjust

and SOL-16 surface-mount packages. Commercial and in- R4 A1

dustrial temperature range models are available. R2
Span
8
Adjust
R7
VIN2 (5V) 5 10 4mA
Span
R6
Common 2 9 16mA
Span

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 1984-2009, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

www.ti.com
ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC
Power Supply, +VCC ............................................................................ 40V
Input Voltage, VIN1, VIN2, VREF IN ....................................................... +VCC DISCHARGE SENSITIVITY
See text regarding safe negative input voltage range.
Storage Temperature Range: A, B ................................ –55°C to +125°C This integrated circuit can be damaged by ESD. Texas Instruments
K, U .................................. –40°C to +85°C recommends that all integrated circuits be handled with appropriate
Output Short-Circuit Duration, Gate Drive precautions. Failure to observe proper handling and installation proce-
and VREF Force ................................ Continuous to common and +VCC dures can cause damage.
Output Current Using Internal 50Ω Resistor ................................... 40mA
ESD damage can range from subtle performance degradation to
NOTE: (1) Stresses above these ratings may cause permanent damage. complete device failure. Precision integrated circuits may be more
Exposure to absolute maximum conditions for extended periods may degrade susceptible to damage because very small parametric changes could
device reliability. cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION(1)
PACKAGE TEMPERATURE
PRODUCT PACKAGE-LEAD DESIGNATOR RANGE
XTR110AG DIP-16 Ceramic JD –40°C to +85°C
XTR110BG DIP-16 Ceramic JD –40°C to +85°C
XTR110KP DIP-16 Plastic N 0°C to +70°C
XTR110KU SOL-16 Surface-Mount DW 0°C to +70°C

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com.

PIN CONFIGURATION
TOP VIEW

Source Resistor 1 16 +VCC

Common 2 15 VREF Force

VREF In 3 14 Gate Drive

VIN1 (10V) 4 13 Source Sense

VIN2 (5V) 5 12 VREF Sense

Zero Adjust 6 11 VREF Adjust

Zero Adjust 7 10 4mA Span

Span Adjust 8 9 16mA Span

2
XTR110
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ELECTRICAL CHARACTERISTICS
At TA = +25°C and VCC = +24V and RL = 250Ω**, unless otherwise specified.

XTR110AG, KP, KU XTR110BG

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

TRANSMITTER
Transfer Function IO = 10 [(VREFIn/16) + (VIN1/4) + (VIN2/2)] /RSPAN
Input Range: VIN1(5) Specified Performance 0 +10 * * V
VIN2 Specified Performance 0 +5 * * V
Current, IO Specified Performance(1) 4 20 * * mA
Derated Performance(1) 0 40 * * mA
Nonlinearity 16mA/20mA Span(2) 0.01 0.025 0.002 0.005 % of Span
Offset Current, IOS IO = 4mA(1)
Initial (1) 0.2 0.4 0.02 0.1 % of Span
vs Temperature (1) 0.0003 0.005 * 0.003 % of Span/°C
vs Supply, VCC (1) 0.0005 0.005 * * % of Span/V
Span Error IO = 20mA
Initial (1) 0.3 0.6 0.05 0.2 % of Span
vs Temperature (1) 0.0025 0.005 0.0009 0.003 % of Span/°C
vs Supply, VCC (1) 0.003 0.005 * * % of Span/V
Output Resistance From Drain of FET (QEXT)(3) 10 x 109 * Ω
Input Resistance VIN1 27 * kΩ
VIN2 22 * kΩ
VREF In 19 * kΩ
Dynamic Response
Settling Time To 0.1% of Span 15 * µs
To 0.01% of Span 20 * µs
Slew Rate 1.3 * mA/µs
VOLTAGE REFERENCE
Output Voltage +9.95 +10 +10.05 +9.98 * +10.02 V
vs Temperature 35 50 15 30 ppm/°C
vs Supply, VCC Line Regulation 0.0002 0.005 * * %/V
vs Output Current Load Regulation 0.0005 0.01 * * %/mA
vs Time 100 * ppm/1k hrs
Trim Range –0.100 +0.25 * * V
Output Current Specified Performance 10 * mA
POWER SUPPLY
Input Voltage, VCC +13.5 +40 * * V
Quiescent Current Excluding IO 3 4.5 * * mA
TEMPERATURE RANGE
Specification: AG, BG –40 +85 * * °C
KP, KU 0 +70 °C
Operating: AG, BG –55 +125 * * °C
KP, KU –25 +85 °C

* Specifications same as AG/KP grades. ** Specifications apply to the range of RL shown in Typical Performance Curves.
NOTES: (1) Including internal reference. (2) Span is the change in output current resulting from a full-scale change in input voltage. (3) Within compliance range limited
by (+VCC – 2V) +VDS required for linear operation of the FET. (4) For VREF adjustment circuit see Figure 3. (5) For extended IREF drive circuit see Figure 4. (5) Unit may
be damaged. See Input Voltage Range section.

XTR110 3
SBOS141C www.ti.com
 TYPICAL PERFORMANCE CURVES
TA = +25°C, VCC = 24VDC, RL = 250Ω, unless otherwise noted.

VREF LINE REGULATION vs FREQUENCY IO POWER SUPPLY REGULATION vs FREQUENCY

10 10

∆ IO /∆ VCC (% of span/V)
1 1
∆ VREF/∆ VCC (%/V)

0.1 0.1

0.01 0.01

0.001 0.001
1 10 100 1k 10k 100k 1 10 100 1k 10k 100k
Ripple Frequency (Hz) Ripple Frequency (Hz)

JUNCTION TEMPERATURE RISE

vs VREF OUTPUT CURRENT TOTAL OUTPUT ERROR vs TEMPERATURE
100 2
Max. Temp. Rise
for +85°C Ambient
Junction Temperature Rise

80
Max. TJ = +175°C 1 AG
Above Ambient (°C)

Error (% of span)

θJA = 70°C/W VCC = +40V

60
0 BG
40
VCC = +24V
–1 AG
20 VCC = +15V

0 –2
0 2 4 6 8 10 –40 –20 0 20 40 60 80
VREF Output Current (mA) Temperature (°C)
(IOUT has minimal effect on TJ)

ICC vs TEMPERATURE MAXIMUM RL vs VCC

5 2500

IO = 20mA
4 2000
ICC (mA) (excluding IO)

IO MAX = 20mA
3 1500
RL (Ω)

IO = 4mA

2 1000
IO MAX = 40mA

1 500

0 0
–40 –20 0 20 40 60 80 15 20 25 30 35 40
Temperature (°C) +VCC (V)

4
XTR110
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TYPICAL PERFORMANCE CURVES (Continued)
At TA = +25°C, VCC = 24VDC, RL = 250Ω, unless otherwise noted.

SETTLING TIME WITH NEG VIN STEP PULSE RESPONSE

VIN VIN

0V 0V

0V
IO Error IO
(0.01% of into
Span/Box) 500Ω
0V

SETTLING TIME WITH POS VIN STEP

VIN

0V

0V

IO Error
(0.01% of
Span/Box)

XTR110 5
SBOS141C www.ti.com
APPLICATIONS INFORMATION have a voltage rating equal or greater than the maximum
power supply voltage. Various recommended types are shown
Figure 1 shows the basic connections required for 0V to 10V in Table I.
input and 4ma to 20mA output. Other input voltage and
output current ranges require changes in connections of pins MANUFACTURER PART NO. BVDSS(1) BVGS(1) PACKAGE
3, 4, 5, 9 and 10 as shown in the table of Figure 1. Ferranti ZVP1304A 40V 20V TO-92
The complete transfer function of the XTR110 is: ZVP1304B 40V 20V TO-39
ZVP1306A 60V 20V TO-92
ZVP1306B 60V 20V TO-39
(VREF IN) (VIN1) (VIN2)
10 + + International
16 4 2 Rectifier IRF9513 60V 20V TO-220
IO = (1)
RSPAN Motorola MTP8P08 80V 20V TO-220
RCA RFL1P08 80V 20V TO-39
RFT2P08 80V 20V TO-220
RSPAN is the total impedance seen at the emitter of the
internal NPN transistor. This impedance varies depending Siliconix VP0300B 30V 40V TO-39
(preferred) VP0300L 30V 40V TO-92
on how pins 8, 9 and 10 are configured. Typical operating VP0300M 30V 40V TO-237
region configurations are shown in Figure 1. An external VP0808B 80V 40V TO-39
RSPAN can be connected for different output current ranges VP0808L 80V 40V TO-92
VP0808M 80V 40V TO-237
as described later.
Supertex VP1304N2 40V 20V TO-220
VP1304N3 40V 20V TO-92
EXTERNAL TRANSISTOR VP1306N2 60V 20V TO-220
VP1306N3 60V 20V TO-92
An external pass transistor, QEXT, is required as shown in NOTE: (1) BVDSS—Drain-source breakdown voltage. BVGS—Gate-source
Figure 1. This transistor conducts the output signal current. breakdown voltage.
A P-channel MOSFET transistor is recommended. It must
TABLE I. Available P-Channel MOSFETs.

+VCC +
1µF +VCC
Force 15 16 13.5 to 40V

R9 50Ω
Sense 12 +10V R8 1 IO
Reference 500Ω Short
VREF 11 13
Connection
Adj.
(see text)
4 14 QEXT
VIN IO/10 P-Channel
0 to 10V 3 7 MOSFET
15kΩ
R3 Zero (see text)
R1 R5 Adjust
20kΩ 6
16.25kΩ
IO
R4 4 to 20mA
10kΩ RL
R2 5kΩ (250Ω typ)
8
Span Adjust
R7 6250Ω
5 IO/10 10
4mA Span

2 9 16mA Span

R6 1562.5Ω

INPUT OUTPUT
RANGE (V) RANGE (mA) PIN 3 PIN 4 PIN 5 PIN 9 PIN 10
0-10 0-20 Com Input Com Com Com
2-10 4-20 Com Input Com Com Com
0-10 4-20 +10V Ref Input Com Com Open
0-10 5-25 +10V Ref Input Com Com Com
0-5 0-20 Com Com Input Com Com
1-5 4-20 Com Com Input Com Com
0-5 4-20 +10V Ref Com Input Com Open
0-5 5-25 +10V Ref Com Input Com Com

FIGURE 1. Basic Circuit Connection.

6
XTR110
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If the supply voltage, +VCC, exceeds the gate-to-source
+VCC
breakdown voltage of QEXT, and the output connection
(drain of QEXT) is broken, QEXT could fail. If the gate-to-
16
source breakdown voltage is lower than +VCC, QEXT can be 1 47nF
protected with a 12V zener diode connected from gate to
13 TIP30B
source. XTR110
etc.
14
Two PNP discrete transistors (Darlington-connected) can be
0.047µF
used for QEXT—see Figure 2. Note that an additional capaci- 2
tor is required for stability. Integrated Darlington transistors 2N2907 IOUT
etc.
are not recommended because their internal base-emitter
resistors cause excessive error. RL

Common
TRANSISTOR DISSIPATION
Maximum power dissipation of QEXT depends on the power FIGURE 2. QEXT Using PNP Transistors.
supply voltage and full-scale output current. Assuming that
the load resistance is low, the power dissipated by QEXT is:
PMAX = (+VCC) IFS (2) +VCC
The transistor type and heat sinking must be chosen accord- VREF Force 15
ing to the maximum power dissipation to prevent overheat- VREF Sense
16
12
ing. See Table II for general recommendations. VREF Adjust
VREF 11
XTR110
R (1)
PACKAGE TYPE ALLOWABLE POWER DISSIPATION RS
20kΩ
TO-92 Lowest: Use minimum supply and at +25°C. Adjust Range
TO-237 Acceptable: Trade-off supply and temperature. 2 Common
±5% Optimum
TO-39 Good: Adequate for majority of designs.
TO-220 Excellent: For prolonged maximum stress.
TO-3 Use if hermetic package is required.
NOTE: (1) RS gives higher resolution with reduced
TABLE II. External Transistor Package Type and range, set RS = 0Ω for larger range.
Dissipation.
FIGURE 3. Optional Adjustment of Reference Voltage.
INPUT VOLTAGE RANGE
The internal op amp A1 can be damaged if its non-inverting
input (an internal node) is pulled more than 0.5V below
common (0V). This could occur if input pins 3, 4 or 5 were
driven with an op amp whose output could swing negative QREF Force 15
16
under abnormal conditions. The voltage at the input of A1 is: Sense 12 +VCC

+10VREF
(VREF IN) (VIN1) (VIN2) XTR110
VA1 = + + (3)
16 4 2 2

This voltage should not be allowed to go more negative than

–0.5V. If necessary, a clamp diode can be connected from
For 100mA with VCC up to
the negative-going input to common to clamp the input 40V use 2N3055 for QREF.
voltage.
FIGURE 4. Increasing Reference Current Drive.
COMMON (Ground)
Careful attention should be directed toward proper con- 3 should be connected to this point. The circuit in Figure 3
nection of the common (grounds). All commons should shows adjustment of the voltage reference.
be joined at one point as close to pin 2 of the XTR110 as The current drive capability of the XTR110’s internal refer-
possible. The exception is the IOUT return. It can be ence is 10mA. This can be extended if desired by adding an
returned to any point where it will not modulate the external NPN transistor shown in Figure 4.
common at pin 2.

OFFSET (ZERO) ADJUSTMENT

VOLTAGE REFERENCE
The offset current can be adjusted by using the potentiom-
The reference voltage is accurately regulated at pin 12 eter, R1, shown in Figure 5. Set the input voltage to zero and
(VREF SENSE). To preserve accuracy, any load including pin then adjust R1 to give 4mA at the output. For spans starting

XTR110 7
SBOS141C www.ti.com
 20 R1 = 100kΩ
1µF Tantalum
15 R2 = 100kΩ
16 Third Wire R3 = 49.9kΩ

Output Current, IO (mA)

R4 = 31.6Ω
12 1 +
24V 15
S – Span Adjust ±0.45%
13
3 16mA Span
XTR110 as shown

10
4 14 G

5 2
0V 8 9 D Zero Adjust ±1.8% of Span
to 6 7 5
4mA to
+10V R4
20mA Out 1V
4mA Offset
RL to
R1
250Ω +5V
R3
Out −2.5 0 2 4 6 8 10
Input Voltage, VIN1 (V)
R2
Offset
Adjust Span Adjust FIGURE 6. Zero and Span of 0V to +10V Input, 4mA to
20mA Output Configuration (see Figure 5).

FIGURE 5. Offset and Span Adjustment Circuit for 0V to

20
+10V Input, 4mA to 20mA Output.
See values in Figure 6.
Output Current, IO (mA) In addition, connect
at 0mA, the following special procedure is recommended: pins 9 and 10 together.
15
set the input to a small nonzero value and then adjust R1 to
the proper output current. When the input is zero the output
will be zero. Figures 6 and 7 show graphically how offset is 20mA Span Span Adjust
10
adjusted.

SPAN ADJUSTMENT 5
The span is adjusted at the full-scale output current using the Zero Adjust
potentiometer, R2, shown in Figure 5. This adjustment is 0mA Offset
interactive with the offset adjustment, and a few iterations
0 2 4 6 8 10
may be necessary. For the circuit shown, set the input
Input Voltage, VIN1 (V)
voltage to +10V full scale and adjust R2 to give 20mA full-
scale output. Figures 6 and 7 show graphically how span is
adjusted. FIGURE 7. Zero and Span of 0V to +10VIN, 0mA to 20mA
Output Configuration (see Figure 5).
The values of R2, R3, and R4 for adjusting the span are
determined as follows: choose R4 in series to slightly de-
crease the span; then choose R2 and R3 to increase the span
to be adjustable about the center value.
EXTENDED SPAN
For spans beyond 40mA, the internal 50Ω resistor (R9) may
LOW TEMPERATURE COEFFICIENT OPERATION
be replaced by an external resistor connected between pins
Although the precision resistors in the XTR110 track within 13 and 16.
1ppm/°C, the output current depends upon the absolute
temperature coefficient (TC) of any one of the resistors, R6, Its value can be calculated as follows:
R7, R8, and R9. Since the absolute TC of the output current REXT = R9 (SpanOLD/SpanNEW)
can have 20ppm/°C, maximum, the TC of the output current Since the internal thin-film resistors have a 20% absolute
can have 20ppm/°C drift. For low TC operation, zero TC value tolerance, measure R9 before determining the final
resistors can be substituted for either the span resistors (R6 value of REXT. Self-heating of REXT can cause nonlinearity.
or R7) or for the source resistor (R9) but not both. Therefore, choose one with a low TC and adequate power
rating. See Figure 10 for application.

8
XTR110
www.ti.com SBOS141C
TYPICAL APPLICATIONS
The XTR110 is ideal for a variety of applications requiring and low price of the XTR110 allow versatility with a
high noise immunity current-mode signal transmission. The minimum of external components and design engineering
precision +10V reference can be used to excite bridges and expense.
transducers. Selectable ranges make it very useful as a Figures 8 through 10 show typical applications of the
precision programmable current source. The compact design XTR110.

+15V
15 16

12 1 R1
+10V
2Ω
Reference
11 13
VIN

4 14
A4 T1

3 7

R9 6
15kΩ

R10
1kΩ 8
Offset
R7
Adjust
5 10 4.75kΩ
A3

R3 2 9 R8 200Ω
20kΩ Fine Trim Span
R5 Adjust
2MΩ RH 50kΩ
R6
Coarse Trim
402Ω

T3 A2 IO

A1 T2

R4
2kΩ
R2
4.99Ω

–15V

200 IO (mA) R1, R2: Low TC resistors to dissipate 0.32W continuous power.
For other current ranges, scale both resistors proportionately.
R8, R10, R11: 10-turn trimpots for greatest sensitivity.
R6, R7: Low TC resistors.
VIN (V) A1 - A4: 1/4 LM324 (powered by ±15V).
0
T1: International Rectifier IR9513(1).
5 10
T2: International Rectifier IR513(1).
T3: International Rectifier IRFF9113(1).

–200 NOTE: (1) Or other adequate power rating MOS transistor.

FIGURE 8. ±200mA Current Pump.

XTR110 9
SBOS141C www.ti.com
 Isolation Barrier
+15V

Isolated Power
Supply (722)

1µF

–15V +15V –15V +15V 15

16
12 1

3 13
XTR110
S
15 7 4 14 G
ISO122 4mA to 20mA Out
0 to –10V 8 5 2 D
16 9

RL
VL

FIGURE 9. Isolated 4mA to 20mA Channel.

+24V

15
REXT
16
0.1Ω
12 13

4
XTR110
0A to
0V to +10V S
3 14 G 10A Out

5 2 D
9

See extended span section.

FIGURE 10. 0A to 10A Output Voltage-to-Current Converter.

10
XTR110
www.ti.com SBOS141C
 Revision History

DATE REVISION PAGE SECTION DESCRIPTION

Front Page Changed front page to standard format.
9/09 C 6
Applications Information Changed text in third paragraph.

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

XTR110 11
SBOS141C www.ti.com
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

XTR110AG NRND CDIP SB JD 16 1 Green (RoHS AU N / A for Pkg Type -40 to 85 XTR110AG
& no Sb/Br)
XTR110BG NRND CDIP SB JD 16 1 Green (RoHS AU N / A for Pkg Type -40 to 85 XTR110BG
& no Sb/Br)
XTR110KP ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 XTR110KP
& no Sb/Br)
XTR110KPG4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -40 to 85 XTR110KP
& no Sb/Br)
XTR110KU ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 XTR110KU
& no Sb/Br)
XTR110KU/1K ACTIVE SOIC DW 16 1000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 XTR110KU
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
XTR110KU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
XTR110KU/1K SOIC DW 16 1000 367.0 367.0 38.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
DW 16 SOIC - 2.65 mm max height
7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224780/A

www.ti.com
 PACKAGE OUTLINE
DW0016A SCALE 1.500
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
14X 1.27
16
1

10.5 2X
10.1 8.89
NOTE 3

8
9
0.51
16X
0.31
7.6
B 0.25 C A B 2.65 MAX
7.4
NOTE 4

0.33
TYP
0.10

SEE DETAIL A
0.25
GAGE PLANE

0.3
0 -8 0.1
1.27
0.40 DETAIL A
(1.4) TYPICAL

4220721/A 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

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 EXAMPLE BOARD LAYOUT
DW0016A SOIC - 2.65 mm max height
SOIC

16X (2) SEE

SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

R0.05 TYP

(9.3)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220721/A 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DW0016A SOIC - 2.65 mm max height
SOIC

16X (2) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

R0.05 TYP
(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220721/A 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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