IRFR6215PbF

IRFU6215PbF

 P-Channel HEXFET® Power MOSFET

 175°C Operating Temperature
 Surface Mount (IRFR6215) VDSS -150V
 Straight Lead (IRFU6215)
RDS(on) 0.295
 Advanced Process Technology
 Fast Switching ID -13A
 Fully Avalanche Rated
 Lead-Free D
D
Description
Fifth Generation HEXFETs from International Rectifier utilize advanced
processing techniques to achieve the lowest possible on-resistance per S S
D
silicon area. This benefit, combined with the fast switching speed G G
and ruggedized device design that HEXFET Power MOSFETs are D- Pak I- Pak
well known for, provides the designer with an extremely efficient device IRFR6215PbF IRFU6215PbF
for use in a wide variety of applications.
The D-PAK is designed for surface mounting using vapor phase,
G D S
infrared, or wave soldering techniques. The straight lead version
(IRFU series) is for through-hole mounting applications. Power Gate Drain Source
dissipation levels up to 1.5 watts are possible in typical surface
mount applications.

Standard Pack
Base part number Package Type Orderable Part Number
Form Quantity
IRFU6215PbF I-Pak Tube 75 IRFU6215PbF
Tube 75 IRFR6215PbF
IRFR6215PbF D-Pak
Tape and Reel Left 3000 IRFR6215TRLPbF

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ -10V -13
ID @ TC = 100°C Continuous Drain Current, VGS @ -10V -9.0 A
IDM Pulsed Drain Current  -44
PD @TC = 25°C Maximum Power Dissipation 110 W
Linear Derating Factor 0.71 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy  310 mJ
IAR Avalanche Current  -6.6 A
EAR Repetitive Avalanche Energy  11 mJ
dv/dt Peak Diode Recovery dv/dt 5.0 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range °C
Soldering Temperature, for 10 seconds (1.6mm from case) 300

Thermal Resistance
Symbol Parameter Typ. Max. Units
RJC Junction-to-Case ––– 1.4
RJA Junction-to-Ambient ( PCB Mount)  ––– 50 °C/W
RJA Junction-to-Ambient ––– 110

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Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage -150 ––– ––– V VGS = 0V, ID = -250µA
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient ––– -0.20 ––– V/°C Reference to 25°C, ID = -1mA
––– ––– 0.295 VGS = -10V, ID = -6.6A 
RDS(on) Static Drain-to-Source On-Resistance 
––– ––– 0.58 VGS = -10V, ID = -6.6A TJ =150°C
VGS(th) Gate Threshold Voltage -2.0 ––– -4.0 V VDS = VGS, ID = -250µA
gfs Forward Trans conductance 3.6 ––– ––– S VDS = -50V, ID = -6.6A
––– ––– -25 VDS = -150V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– -250 VDS = -120V,VGS = 0V,TJ =150°C
Gate-to-Source Forward Leakage ––– ––– -100 VGS = -20V
IGSS nA
Gate-to-Source Reverse Leakage ––– 100 VGS = 20V
Qg Total Gate Charge ––– ––– 66 ID = -6.6A
Qgs Gate-to-Source Charge ––– ––– 8.1 nC VDS = -120V
Qgd Gate-to-Drain Charge ––– ––– 35 VGS = -10V, See Fig. 6 and 13 
td(on) Turn-On Delay Time ––– 14 ––– VDD = -75V
tr Rise Time ––– 36 ––– ID = -6.6A
ns
td(off) Turn-Off Delay Time ––– 53 ––– RG = 6.8
tf Fall Time ––– 37 ––– RD = 12See Fig. 10 
Between lead
LD Internal Drain Inductance ––– 4.5 –––
,6mm (0.25in.)
nH
from package
LS Internal Source Inductance ––– 7.5 –––
and center of die contact
Ciss Input Capacitance ––– 860 ––– VGS = 0V
Coss Output Capacitance ––– 220 ––– pF VDS = -25V
Crss Reverse Transfer Capacitance ––– 130 ––– ƒ = 1.0MHz,See Fig. 5 

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions
Continuous Source Current MOSFET symbol
IS ––– ––– -13
(Body Diode) showing the
A
Pulsed Source Current integral reverse
ISM ––– ––– -44
(Body Diode) p-n junction diode.
VSD Diode Forward Voltage ––– ––– -1.6 V TJ = 25°C,IS = -6.6A,VGS = 0V 
trr Reverse Recovery Time ––– 160 240 ns TJ = 25°C ,IF = -6.6A
Qrr Reverse Recovery Charge ––– 1.2 1.7 C di/dt = 100A/µs 
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by max. junction temperature. (See Fig.11)
 starting TJ = 25°C, L = 14mH, RG = 25, IAS = -6.6A.(See Fig.12)
 ISD -6.6A, di/dt  -620A/µs, VDD  V(BR)DSS, TJ  175°C
 Pulse width 300µs; duty cycle  2%.
 This is applied for I-PAK, LS of D-PAK is measured between lead and center of die contact.
Uses IRF6215 data and test conditions.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to
application note #AN-994.

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100 100
VGS VGS
TOP - 15V TOP - 15V
- 10V - 10V
- 8.0V - 8.0V
- 7.0V - 7.0V

-ID , Drain-to-Source Current (A)

-ID , Drain-to-Source Current (A)

- 6.0V - 6.0V
- 5.5V - 5.5V
- 5.0V - 5.0V
BOTTOM - 4.5V BOTTOM - 4.5V

10 10

-4.5V

-4.5V 20µs PULSE WIDTH 20µs PULSE WIDTH

Tc = 25°C TC = 175°C
1 A 1 A
1 10 100 1 10 100
-VDS , Drain-to-Source Voltage (V) -VDS , Drain-to-Source Voltage (V)

Fig. 1 Typical Output Characteristics Fig. 2 Typical Output Characteristics

100 2.5
I D = -11A
R DS(on) , Drain-to-Source On Resistance
-ID , Drain-to-Source Current (A)

2.0

TJ = 25°C
1.5
(Normalized)

TJ = 175°C
10

1.0

0.5

VDS = -50V
20µs PULSE WIDTH VGS = -10V
1 0.0 A
A
4 5 6 7 8 9 10 -60 -40 -20 0 20 40 60 80 100 120 140 160 180

-VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature (°C)

Fig. 3 Typical Transfer Characteristics Fig. 4 Normalized On-Resistance

vs. Temperature

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2000 20
V GS = 0V, f = 1MHz I D = -6.6A
C iss = Cgs + C gd , Cds SHORTED VDS = -120V
C rss = C gd VDS = -75V

-V GS , Gate-to-Source Voltage (V)

1600 C oss = Cds + C gd 16 VDS = -30V
C, Capacitance (pF)

Ciss
1200 12

Coss
800 8

Crss

400 4

FOR TEST CIRCUIT

SEE FIGURE 13
0 A 0 A
1 10 100 0 20 40 60 80
-VDS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Fig 6. Typical Gate Charge vs.

Drain-to-Source Voltage Gate-to-Source Voltage

100 100
OPERATION IN THIS AREA LIMITED
BY R DS(on)
-ISD , Reverse Drain Current (A)

10µs
-I D , Drain Current (A)

TJ = 175°C
10

TJ = 25°C
10 100µs

1ms

TC = 25°C
TJ = 175°C
VGS = 0V Single Pulse 10ms
0.1 A 1 A
0.2 0.6 1.0 1.4 1.8 1 10 100 1000
-VSD , Source-to-Drain Voltage (V) -VDS , Drain-to-Source Voltage (V)

Fig. 7 Typical Source-to-Drain Diode

Fig 8. Maximum Safe Operating Area
Forward Voltage

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14

12
-ID , Drain Current (A)

10

8
Fig 10a. Switching Time Test Circuit
6

0
25 50 75 100 125 150 175
TC , Case Temperature ( °C)

Fig 9. Maximum Drain Current vs. Case Temperature Fig 10b. Switching Time Waveforms

10
Thermal Response (ZthJC )

1 D = 0.50

0.20

0.10
PDM
0.05
0.1
0.02 t
1
0.01 t2
SINGLE PULSE Notes:
(THERMAL RESPONSE) 1. Duty factor D = t /t
1 2
2. Peak TJ = PDM x Z thJC + T C
0.01 A
0.00001 0.0001 0.001 0.01 0.1 1

t 1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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800
ID

EAS , Single Pulse Avalanche Energy (mJ)

TOP -2.7A
-4.7A
BOTTOM -6.6A
600

400

200
Fig 12a. Unclamped Inductive Test Circuit

0 A
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

vs. Drain Current

Fig 12b. Unclamped Inductive Waveforms

Fig 13a. Gate Charge Waveform Fig 13b. Gate Charge Test Circuit

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Fig 14. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs

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D-Pak (TO-252AA) Package Outline (Dimensions are shown in millimeters (inches))

D-Pak (TO-252AA) Part Marking Information

EXAMPLE: THIS IS AN IRFR120

PART NUMBER
WITH ASSEMBLY INTERNATIONAL
LOT CODE 1234 RECTIFIER IRFR120 DATE CODE
ASSEMBLED ON WW 16, 2001 LOGO 116A YEAR 1 = 2001
IN THE ASSEMBLY LINE "A" 12 34 WEEK 16
LINE A
Note: "P" in assembly line position ASSEMBLY
indicates "Lead-Free" LOT CODE
"P" in assembly line position indicates
"Lead-Free" qualification to the consumer-level

PART NUMBER
INTERNATIONAL
OR RECTIFIER IRFR120
DATE CODE
P = DESIGNATES LEAD-FREE
LOGO PRODUCT (OPTIONAL)
12 34
P = DESIGNATES LEAD-FREE
ASSEMBLY PRODUCT QUALIFIED TO THE
CONSUMER LEVEL (OPTIONAL)
LOT CODE
YEAR 1 = 2001
WEEK 16
A = ASSEMBLY SITE CODE

Note: For the most current drawing please refer to Infineon’s web site www.infineon.com

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I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

EXAMPLE: THIS IS AN IRFU120 PART NUMBER

INTERNATIONAL
WITH ASSEMBLY
RECTIFIER IRFU120 DATE CODE
LOT CODE 5678
LOGO 119A YEAR 1 = 2001
ASSEMBLED ON WW 19, 2001
56 78 WEEK 19
IN THE ASSEMBLY LINE "A"
LINE A
ASSEMBLY
LOT CODE
Note: "P" in assembly line position
indicates Lead-Free"

OR
PART NUMBER
INTERNATIONAL
RECTIFIER IRFU120 DATE CODE
LOGO P = DESIGNATES LEAD-FREE
56 78 PRODUCT (OPTIONAL)
YEAR 1 = 2001
ASSEMBLY
LOT CODE WEEK 19
A = ASSEMBLY SITE CODE

Note: For the most current drawing please refer to Infineon’s web site www.infineon.com

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D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches)

TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) 8.1 ( .318 )

FEED DIRECTION FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

Note: For the most current drawing please refer to Infineon’s web site www.infineon.com

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Qualification Information†
Industrial
Qualification Level
(per JEDEC JESD47F) ††
D-Pak MSL1
Moisture Sensitivity Level
I-Pak (per JEDEC J-STD-020D) ††
RoHS Compliant Yes

† Qualification standards can be found at Infineon’s web site www.infineon.com

†† Applicable version of JEDEC standard at the time of product release.

Revision History

Date Comments
 Updated datasheet with corporate template.
5/31/2016
 Added disclaimer on last page.

Trademarks of Infineon Technologies AG

µHVIC™, µIPM™, µPFC™, AU‐ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™,
DAVE™, DI‐POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™,
HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my‐d™, NovalithIC™, OPTIGA™,
Op MOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO‐SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™,
SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™

Trademarks updated November 2015

Other Trademarks
All referenced product or service names and trademarks are the property of their respec ve owners.

Edi on 2016‐04‐19 IMPORTANT NOTICE For further informa on on the product, technology,
The informa on given in this document shall in no delivery terms and condi ons and prices please
Published by event be regarded as a guarantee of condi ons or contact your nearest Infineon Technologies office
Infineon Technologies AG characteris cs (“Beschaffenheitsgaran e”) . (www.infineon.com).
81726 Munich, Germany
With respect to any examples, hints or any typical
values stated herein and/or any informa on Please note that this product is not qualified
© 2016 Infineon Technologies AG. regarding the applica on of the product, Infineon according to the AEC Q100 or AEC Q101 documents
All Rights Reserved. Technologies hereby disclaims any and all of the Automo ve Electronics Council.
warran es and liabili es of any kind, including
Do you have a ques on about this without limita on warran es of non‐infringement WARNINGS
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Document reference applicable legal requirements, norms and Except as otherwise explicitly approved by Infineon
standards concerning customer’s products and any Technologies in a wri en document signed by
ifx1 authorized representa ves of Infineon Technologies,
use of the product of Infineon Technologies in Infineon Technologies’ products may not be used in
customer’s applica ons. any applica ons where a failure of the product or
any consequences of the use thereof can reasonably
The data contained in this document is exclusively be expected to result in personal injury.
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended applica on and the completeness of the
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respect to such applica on.

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