Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd Logo
Upload

Welcome to Scribd!

  • 1 views

    exp_3

    Uploaded by

    usutkarsh0705

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    exp_3

    Uploaded by

    usutkarsh0705
    1 views2 pages

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    1 views2 pages

    exp_3

    Uploaded by

    usutkarsh0705

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    You are on page 1of 2

    EXPERIMENT – 3

    Objective: - Write Verilog Code for Implementation of Shift Register.

    Resources Required:

    Hardware requirements: Computer System.

    Software requirements: XILINX VIVADO Software.

    Theory

    A group of flip flops which is used to store multiple bits of data and the data is moved from one flip
    flop to another is known as shift register. The bits stored in registers shifted when the clock pulse is
    applied within and inside or outside the registers. A Shift Register can shift the bits either to the left or
    to the right. A Shift Register, which shifts the bit to the left, is known as "Shift left register", and it
    shifts the bit to the right, known as "Right left register".

    Verilog Code: -
     RTL Design
    `timescale 1ns / 1ps
    module shift_reg(
    input clk,
    input clr,
    input shift,
    input ld,
    input[7:0] Din,
    input SI,
    output reg [7:0]Dout
    );
    always@(posedge clk)
    begin
    if(clr) Dout<=0;
    else if(ld) Dout<=Din;
    else if(shift) Dout<={Dout[6:0],SI};
    end
    endmodule

     Testbench
    module test_shift;

    reg clk,clr,ld,shift,SI;reg[7:0] Din;


    wire [7:0] Dout;
    shift_reg D(clk,clr,shift,ld,Din, SI,Dout);
    initial
    begin
    clk=1'b0;
    repeat(100)
    #10 clk=~clk;
    end

    initial
    begin
    Din=8'b00000001;
    1
    clr =1'b0;
    ld=1'b1;

    #20 ld =1'b0;
    SI=1'b1;
    shift=1'b1;
    #20 ld =1'b0;
    SI=1'b1;
    shift=1'b1;
    #20 $finish;
    end
    endmodule

    OUTPUT: -
    Figure 1. and Figure 2. shows the Simulation Waveform and RTL Design of the above Verilog
    code respectively

    Figure1: - Simulated waveform

    Figure2: - RTL Schematic

    Results:

    Verilog Code for Shift Register is simulated, and RTL schematic was also generated.

    You might also like