M54/74HCT563

M54/74HCT573
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT
HCT563 INVERTING - HCT573 NON INVERTING

. HIGH SPEED

. tPD = 18 ns (TYP.) AT VCC = 5 V

LOW POWER DISSIPATION

. ICC = 4 µA (MAX.) AT TA = 25 °C
COMPATIBLE WITH TTL OUTPUTS

. VIH = 2V (MIN.) VIL = 0.8V (MAX.)

OUTPUT DRIVE CAPABILITY
B1R
(Plastic Package)
F1R
(Ceramic Package)

. 15 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE

. IOL = IOH= 6 mA (MIN.)

BALANCED PROPAGATION DELAYS

. tPLH = tPHL
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS563/573
M1R
(Micro Package)
ORDER CODES :
C1R
(Chip Carrier)

M54HCTXXXF1R M74HCTXXXM1R
DESCRIPTION M74HCTXXXB1R M74HCTXXXC1R

The M54/74HCT563 and M54HCT573 are high the eight outputs will be in a normal logic state (high
speed CMOS OCTAL LATCH WITH 3-STATE or low logic level) and while high level the outpts will
OUTPUTS fabricated with silicon gate C2MOS be in a high impedance state.
technology. The application designer has a choise of
These ICs achive the high speed operation similar combination of inverting and non inverting outputs.
to equivalent LSTTL while maintaining the CMOS This integrated circuit has input and output
low power dissipation. characteristics that are fully compatible with 54/74
These 8 bit D-Type latches are controlled by a latch LSTTL logic families. M54/74HCT devices are
enable input (LE) and a output enable input (OE). designed to directly interface HSC2MOS systems
While the LE input is held at a high level, the Q with TTL and NMOS components. They are also
outputs will follow the data input precisely or plug in replacements for LSTTL devices giving a
inversely. When the LE is taken low, the Q outputs reduction of power consumption.
will be latched precisely or inversely at the logic level All inputs are equipped with protection circuits
of D input data. While the OE input is at low level, against discharge and transient excess voltage.

PIN CONNECTION (top view)

HCT563 HCT573 HCT563 HCT573

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M54/M74HCT563/573

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION (HCT563) PIN DESCRIPTION (HCT573)

PIN No SYMBOL NAME AND FUNCTION PIN No SYMBOL NAME AND FUNCTION
1 OE 3 State output Enable 1 OE 3 State output Enable
Input (Active LOW) Input (Active LOW)
2, 3, 4, 5, D0 to D7 Data Inputs 2, 3, 4, 5, D0 to D7 Data Inputs
6, 7, 8, 9 6, 7, 8, 9
12, 13, 14, Q0 to Q7 3 State Latch Outputs 12, 13, 14, Q0 to Q7 3 State Latch Outputs
15, 16, 17, 15, 16, 17,
18, 19 18, 19
11 LE Latch Enable Input 11 LE Latch Enable Input
10 GND Ground (0V) 10 GND Ground (0V)
20 V CC Positive Supply Voltage 20 VCC Positive Supply Voltage

IEC LOGIC SYMBOLS

HCT563 HCT573

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 M54/M74HCT563/573

TRUTH TABLE
INPUTS OUTPUTS
OE LE D Q (HCT573) Q (HCT563)
H X X Z Z
L L X NO CHANGE * NO CHANGE *
L H L L H
L H H H L
X: DON’T CARE
Z: HIGH IMPEDANCE
*: Q/Q OUTPUTS ARE LATCHED AT THE TIME WHEN THE LE INPUT IS TAKEN LOW LOGIC LEVEL.

LOGIC DIAGRAMS

HCT563

HCT573

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M54/M74HCT563/573

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7 V
VI DC Input Voltage -0.5 to VCC + 0.5 V
VO DC Output Voltage -0.5 to VCC + 0.5 V
IIK DC Input Diode Current ± 20 mA
IOK DC Output Diode Current ± 20 mA
IO DC Output Source Sink Current Per Output Pin ± 35 mA
ICC or IGND DC VCC or Ground Current ± 70 mA
PD Power Dissipation 500 (*) mW
o
Tstg Storage Temperature -65 to +150 C
o
TL Lead Temperature (10 sec) 300 C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied.
(*) 500 mW: ≅ 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit
VCC Supply Voltage 4.5 to 5.5 V
VI Input Voltage 0 to VCC V
VO Output Voltage 0 to VCC V
o
Top Operating Temperature: M54HC Series -55 to +125 C
o
M74HC Series -40 to +85 C
tr, tf Input Rise and Fall Time (VCC = 4.5 to 5.5V) 0 to 500 ns

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 M54/M74HCT563/573

DC SPECIFICATIONS
Test Conditions Value
Symbol Parameter TA = 25 oC -40 to 85 oC -55 to 125 oC Unit
VCC
54HC and 74HC 74HC 54HC
(V)
Min. Typ. Max. Min. Max. Min. Max.
VIH High Level Input 4.5 2.0 2.0 2.0 V
Voltage to
5.5
V IL Low Level Input 4.5 0.8 0.8 0.8 V
Voltage to
5.5
V OH High Level VI = IO=-20 µA 4.4 4.5 4.4 4.4
Output Voltage VIH
4.5 V
or IO=-6.0 mA 4.18 4.31 4.13 4.10
V IL
VOL Low Level Output VI = IO= 20 µA 0.0 0.1 0.1 0.1
Voltage VIH
4.5 V
or IO= 6.0 mA 0.17 0.26 0.33 0.4
V IL
II Input Leakage VI = VCC or GND ±0.1 ±1 ±1 µA
5.5
Current
IOZ 3 State Output 5.5 VI = VIH or VIL ±0.5 ±5.0 ±10 µA
Off State Current VO = VCC or GND
ICC Quiescent Supply 5.5 VI = VCC or GND 4 40 80 µA
Current
∆ICC Additional worst 5.5 Per Input pin 2.0 2.9 3.0 mA
case supply VI = 0.5V or
current V I = 2.4V
Other Inputs at
V CC or GND

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M54/M74HCT563/573

AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = t f = 6 ns)

Test Conditions Value
o
Symbol Parameter TA = 25 C -40 to 85 oC -55 to 125 oC Unit
VCC CL
54HC and 74HC 74HC 54HC
(V) (pF)
Min. Typ. Max. Min. Max. Min. Max.
tTLH Output Transition 4.5 50 7 12 15 18 ns
tTHL Time
tPLH Propagation 4.5 50 21 33 41 50 ns
tPHL Delay Time 4.5 150 25 39 49 59 ns
(LE - Q, Q)
tPLH Propagation 4.5 50 19 30 38 45 ns
tPHL Delay Time 4.5 150 23 36 45 54 ns
(D - Q, Q)
tPZL 3 State Output 4.5 50 RL = 1 KΩ 19 30 38 45 ns
tPZH Enable Time 4.5 150 RL = 1 KΩ 23 36 45 54 ns
tPZL 3 State Output 4.5 50 RL = 1 KΩ 18 25 31 38 ns
tPZH Disable Time
tW(L) Minimum Pulse 4.5 50 7 15 19 22 ns
tW(H) Width (LE)
ts Minimum Set-up 4.5 50 4 10 13 15 ns
Time
th Minimum Hold 4.5 50 5 5 5 ns
Time
CIN Input Capacitance 5 10 10 10 pF
COUT Output 10
pF
Capacitance
CPD (*) Power Dissipation 51
pF
Capacitance
(*) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load.
(Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD •VCC •fIN + ICC/8 (per Flip-Flop)

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SWITCHING CHARACTERISTICS TEST WAVEFORM

tPLH, tPHL (D - Q) tPLH, tPHL (LE - Q), ts, th, tw

tPLZ, tPZL tPHZ, tPZH

The 1KΩ load resistors should be connected between The 1KΩ load resistors and the 50pF load capacitors
outputs and VCC line and the 50pF load capacitors should be connected between each output and GND
should be connected between outputsand GND line. line.
All inputs except OE input should be connected to VCC All inputs except OE input should be connected to VCC
line or GND line such that outputs will be in low logic or GND line such that output will be in high logic level
level while OE input is held low. while OE input is held low.

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M54/M74HCT563/573

TEST CIRCUIT ICC (Opr.)

INPUT WAVEFORM IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICS TEST.

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 M54/M74HCT563/573

Plastic DIP20 (0.25) MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.254 0.010

B 1.39 1.65 0.055 0.065

b 0.45 0.018

b1 0.25 0.010

D 25.4 1.000

E 8.5 0.335

e 2.54 0.100

e3 22.86 0.900

F 7.1 0.280

I 3.93 0.155

L 3.3 0.130

Z 1.34 0.053

P001J

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Ceramic DIP20 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 25 0.984

B 7.8 0.307

D 3.3 0.130

E 0.5 1.78 0.020 0.070

e3 22.86 0.900

F 2.29 2.79 0.090 0.110

G 0.4 0.55 0.016 0.022

I 1.27 1.52 0.050 0.060

L 0.22 0.31 0.009 0.012

M 0.51 1.27 0.020 0.050

N1 4° (min.), 15° (max.)

P 7.9 8.13 0.311 0.320

Q 5.71 0.225

P057H

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SO20 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.65 0.104
a1 0.10 0.20 0.004 0.007
a2 2.45 0.096
b 0.35 0.49 0.013 0.019
b1 0.23 0.32 0.009 0.012
C 0.50 0.020
c1 45° (typ.)
D 12.60 13.00 0.496 0.512
E 10.00 10.65 0.393 0.419
e 1.27 0.050
e3 11.43 0.450
F 7.40 7.60 0.291 0.299
L 0.50 1.27 0.19 0.050
M 0.75 0.029
S 8° (max.)

P013L

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M54/M74HCT563/573

PLCC20 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.

A 9.78 10.03 0.385 0.395

B 8.89 9.04 0.350 0.356

D 4.2 4.57 0.165 0.180

d1 2.54 0.100

d2 0.56 0.022

E 7.37 8.38 0.290 0.330

e 1.27 0.050

e3 5.08 0.200

F 0.38 0.015

G 0.101 0.004

M 1.27 0.050

M1 1.14 0.045

P027A

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 M54/M74HCT563/573

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.

 1994 SGS-THOMSON Microelectronics - All Rights Reserved

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