lmk5c22212as1

LMK5C22212AS1
SNAS922 – NOVEMBER 2024
LMK5C22212AS1 2-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With

JESD204B/C and BAW for Wireless Communications With IEEE-1588 PTP Stack
1 Features 3 Description
• Ultra-low jitter BAW VCO based Wireless The LMK5C22212AS1 is a high-performance network
Infrastructure and Ethernet clocks synchronizer and jitter cleaner designed to meet the
– 40fs typical/ 57fs maximum RMS jitter at stringent requirements of wireless communications
491.52MHz and infrastructure applications.
– 50fs typical/ 62fs maximum RMS jitter at The device is bundled with software support
245.76MHz for IEEE-1588 PTP synchronization to a primary
• 2 high-performance Digital Phase Locked Loops reference clock source. For more information, contact
(DPLLs) with 2 Analog Phase Locked Loops TI.
ADVANCE INFORMATION
(APLLs)
The network synchronizer integrates 2 DPLLs to
– Programmable DPLL loop filter bandwidth from provide hitless switching and jitter attenuation with
1mHz to 4kHz programmable loop bandwidth and no external loop
– < 1ppt DCO frequency adjustment step size filters, maximizing flexibility and ease of use. Each
• 2 differential or single-ended DPLL inputs DPLL phase locks a paired APLL to a reference input.
– 1Hz (1PPS) to 800MHz input frequency
– Digital Holdover and Hitless Switching APLL1 features ultra high performance PLL with TI's
• 12 differential outputs with programmable HSDS, proprietary Bulk Acoustic Wave (BAW) technology
AC-LVPECL, LVDS and HSCL formats (known as the BAW APLL) and can generate output
– Up to 16 total frequency outputs when clocks with 40fs typical / 60fs maximum 12kHz to
configured with 6 LVCMOS frequency outputs 20MHz RMS jitter at 491.52MHz, independent of the
on OUT0_P/N, OUT1_P/N, GPIO1 and GPIO2 jitter and frequency of the XO and DPLL reference
and 10 differential outputs on OUT2_P/N to inputs. APLL2/DPLL2 provides an option for a second
OUT11_P/N frequency and/or synchronization domain.
– 1Hz (1PPS) to 1250MHz output frequency with Reference validation circuitry monitors the DPLL
programmable swing and common mode reference clocks and performs a hitless switch
– PCIe Gen 1 to 6 compliant between inputs upon detecting a switchover event.
• I2C or 3-wire/4-wire SPI Zero-Delay Mode (ZDM) and phase cancellation can
be enabled to control the phase relationship from
2 Applications input to outputs.
• 4G and 5G Wireless Networks
The device is fully programmable through I2C or SPI.
– Active Antenna System (AAS), mMIMO The integrated EEPROM can be used to customize
– Macro Remote Radio Unit (RRU) system start-up clocks. The device also features
– CPRI/eCPRI Baseband, Centralized, factory default ROM profiles as fallback options.
Distributed Units (BBU, CU, DU)
– Small cell base station Package Information
• SyncE (G.8262), SONET/SDH (Stratum 3/3E, PART NUMBER PACKAGE (1) PACKAGE SIZE(2)
G.813, GR-1244, GR-253), IEEE-1588 PTP LMK5C22212AS1 RGC (VQFN, 64) 9.00mm × 9.00mm
secondary clock
(1) For all available packages, see the orderable addendum at
• Jitter cleaning, wander attenuation, and reference the end of the data sheet.
clock generation for 112G/224G PAM4 SerDes (2) The package size (length × width) is a nominal value and
• Optical Transport Networks (OTN G.709) includes pins, where applicable.
• Broadband fixed line access
• Industrial
– Test and measurement
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
LMK5C22212AS1
SNAS922 – NOVEMBER 2024 www.ti.com
Low Jitter Radio DEVCLK

122.88MHz/ 245.76MHz/ 491.52MHz 2
4
Radio SYSREF Clocks

RF AFE
3 1.92MHz/ 7.68MHz 2
TCXO
Network Sync Clock

156.25MHz/ 125MHz/ 25MHz
GPS/ 10MHz/ 1PPS (opt)

LMK5C22212 SoC/
Network Synchronizer PHY Recovered Clock ASIC
25MHz/ 156.25MHz
REF Clock
Register I2C or SPI Control Interface

and
DCO
ADVANCE INFORMATION
control PCIe REFCLK (opt)

2
100MHz PCIe
CPU REF_CLK FPGA/CPU
LMK5C22212AS1 Typical System Block Diagram
2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: LMK5C22212AS1

LMK5C22212AS1
www.ti.com SNAS922 – NOVEMBER 2024
Table of Contents
1 Features............................................................................1 7.3 Feature Description...................................................35
2 Applications..................................................................... 1 7.4 Device Functional Modes..........................................64
3 Description.......................................................................1 8 Application and Implementation.................................. 80
4 Pin Configuration and Functions...................................4 8.1 Application Information............................................. 80
5 Specifications.................................................................. 7 8.2 Typical Application.................................................... 83
5.1 Absolute Maximum Ratings........................................ 7 8.3 Best Design Practices...............................................88
5.2 ESD Ratings............................................................... 7 8.4 Power Supply Recommendations.............................88
5.3 Recommended Operating Conditions.........................7 8.5 Layout....................................................................... 89
5.4 Thermal Information....................................................8 9 Device and Documentation Support............................91
5.5 Electrical Characteristics.............................................8 9.1 Documentation Support............................................ 91
5.6 Timing Diagrams....................................................... 17 9.2 Receiving Notification of Documentation Updates....91
5.7 Typical Characteristics.............................................. 21 9.3 Support Resources................................................... 91
6 Parameter Measurement Information.......................... 24 9.4 Trademarks............................................................... 92
ADVANCE INFORMATION
6.1 Differential Voltage Measurement Terminology........ 24 9.5 Glossary....................................................................92
6.2 Output Clock Test Configurations............................. 25 9.6 Electrostatic Discharge Caution................................92
7 Detailed Description......................................................27 10 Revision History.......................................................... 92
7.1 Overview................................................................... 27 11 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram......................................... 28 Information.................................................................... 92
Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

LMK5C22212AS1
4 Pin Configuration and Functions
VDDO_8_TO_11
OUT10_N
OUT10_P
OUT11_N
OUT11_P
OUT9_N
OUT8_N
OUT9_P
OUT8_P
GPIO1
GPIO0
LF1
NC
NC
NC
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VDDO_0_1 1 48 CAP_APLL1
OUT0_P 2 47 VDD_APLL1
OUT0_N 3 46 NC
ADVANCE INFORMATION
OUT1_N 4 45 NC
OUT1_P 5 44 VDD_DIG
NC 6 43 NC
NC 7 42 NC
VDD_XO 8 41 VDD_DIG
DAP
XO 9 40 CAP_DIG
GPIO2 10 39 IN1_P
VDDO_2_3 11 38 IN1_N
OUT2_P 12 37 VDD_IN1
OUT2_N 13 36 PD#
OUT3_N 14 35 IN0_N
OUT3_P 15 34 IN0_P
SDIO 16 33 VDD_IN0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CAP3_APLL2
CAP2_APLL2
CAP1_APLL2
SCS_ADD
VDD_APLL2
SCK
LF2
OUT5_P
OUT5_N
OUT4_N
OUT4_P
OUT6_P
OUT6_N
OUT7_N
OUT7_P
VDDO_4_TO_7
Not to scale
Figure 4-1. LMK5C22212AS1 RGC Package 64-Pin VQFN Top View
Table 4-1. LMK5C22212AS1 Pin Functions

PIN
TYPE(1) DESCRIPTION
NAME NO.
POWER
Power supply for OUT0 and OUT1. Connect to supply; do not leave floating or
VDDO_0_1 1 P
connect to GND.
Power supply for XO. Connect to supply; do not leave floating or connect to
VDD_XO 8 P
GND.
Power supply for OUT2 and OUT3. Connect to supply; do not leave floating or
VDDO_2_3 11 P
connect to GND.
VDD_APLL2 23 P Power supply for APLL2

LMK5C22212AS1
Table 4-1. LMK5C22212AS1 Pin Functions (continued)

PIN
TYPE(1) DESCRIPTION
NAME NO.
VDDO_4_To_7 28 P Power supply for OUT4 to OUT7
VDD_IN0 33 P Power supply for IN0 DPLL reference
VDD_IN1 37 P Power supply for IN1 DPLL reference
VDD_DIG 41 P Power supply for digital
VDD_DIG 44 p Power supply for digital. Typically connected to pin 41.
Power supply for APLL1. Connect to supply; do not leave floating or connect to
VDD_APLL1 47 P
GND.
VDDO_8_TO_11 55 P Power supply for OUT8 to OUT11.
DAP N/A G Ground
External loop filter cap for APLL2 (100nF), refer to APLL Loop Filters (LF1, LF2)
ADVANCE INFORMATION
LF2 19 A
for more details.
CAP3_APLL2 20 A Internal bias bypass capacitor for APLL2 VCO (10µF)
CAP2_APLL2 21 A Internal bias bypass capacitor for APLL2 VCO (10µF)
CAP1_APLL2 22 A LDO bypass capacitor for APLL2 VCO (10µF)
CAP_DIG 40 A LDO bypass capacitor for Digital Core Logic (100nF)
CAP_APLL1 48 A Internal bias bypass capacitor for APLL1 (10µF)
External loop filter cap for APLL1 (470nF), refer to APLL Loop Filters (LF1, LF2)
LF1 49 A
for more details.
XO/TCXO/OCXO input pin, refer to Oscillator Input (XO) for configuring the
XO 9 I
internal XO input termination.
IN0_P 34 I Reference input to DPLLx or buffered to OUT0 or OUT1. Refer to Reference
IN0_N 35 I Inputs for configuring the internal reference input termination.
IN1_P 39 I Reference input to DPLLx or buffered to OUT0 or OUT1. Refer to Reference

IN1_N 38 I Inputs for configuring the internal reference input termination.
OUT0_P 2 O Clock Output 0. Sources from DPLL reference inputs, XO, or all VCO post-
dividers. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL,
OUT0_N 3 O LVDS, HSDS, HCSL, 1.8V LVCMOS, or 2.65V LVCMOS. Refer to Clock Outputs
for details on configuring and terminating the outputs.
OUT1_N 4 O Clock Output 1. Sources from DPLL reference inputs, XO, or all VCO post-
dividers. Supports SYSREF/1-PPS output. Programmable formats: AC-LVPECL,
OUT1_P 5 O LVDS, HSDS, HCSL, 1.8V LVCMOS, or 2.65V LVCMOS. Refer to Clock Outputs
for details on configuring and terminating the outputs.
OUT2_P 12 O Clock Output 2. Sources from APLL1 and APLL2. Programmable formats:
AC-LVPECL, LVDS, HSDS or HCSL. Refer to Clock Outputs for details on
OUT2_N 13 O configuring and terminating the outputs.
OUT3_N 14 O Clock Output 3. Sources from APLL1 and APLL2. Programmable formats:
AC-LVPECL, LVDS, HSDS or HCSL. Refer to Clock Outputs for details on
OUT3_P 15 O configuring and terminating the outputs.
OUT4_P 26 O Clock Output 4. Sources from APLL1 or APLL2. Supports SYSREF/1-PPS
output. Programmable formats: AC-LVPECL, LVDS, HSDS or HCSL. Refer to
OUT4_N 27 O Clock Outputs for details on configuring and terminating the outputs.
OUT7_N 31 O Clock Output 7. Sources from APLL1 or APLL2. Supports SYSREF/1-PPS
OUT7_P 32 O Clock Outputs for details on configuring and terminating the outputs.

LMK5C22212AS1
Table 4-1. LMK5C22212AS1 Pin Functions (continued)

PIN
TYPE(1) DESCRIPTION
NAME NO.
ADVANCE INFORMATION
POR: See ROM Page Selection

GPIO2(2) 10 I/O, S
Normal Operation: GPIO input or output
SDIO(3) 16 I/O SPI or I2C Data (SDA)
SCK(3) 17 I SPI or I2C Clock (SCL)
POR: I2C address select (see GPIO1 and SCS_ADD Functionalities and I2C
SCS_ADD(2) 18 I, S Serial Interface)
Normal Operation: SPI Chip Select (2-state)
PD# 36 I Device power down (active low), internal 200kΩ pullup to VCC
POR: See ROM Page Selection
GPIO0(2) 50 I/O, S
POR: See GPIO1 and SCS_ADD Functionalities
GPIO1(2) 64 I/O, S
NC 6 -
NC 7
NC 60
No connect. Leave floating, do not connect to GND.
NC 61 -
NC 62
NC 63 -
NC 42 -
NC 43 -
No connect. Leave floating or connect to GND.
NC 45 -
NC 46 -
(1) P = Power, G = Ground, I = Input, O = Output, I/O = Input or Output, A = Analog, S = Configuration.
(2) When 3-level mode is enabled during power supply ramp or when PD# is LOW: internal voltage divider of 555kΩ to VCC and 201kΩ to
GND. When 2 level input mode is enabled: internal 408kΩ pulldown to GND.
(3) 670kΩ pullup to internal 2.6V LDO.

LMK5C22212AS1
5 Specifications
5.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD(2) Core supply voltages –0.3 3.6 V
VDDO(3) Output supply voltages –0.3 3.6 V
VIN Input voltage range for clock and logic inputs –0.3 VDD+0.3 V
VOUT_LOGIC Output voltage range for logic outputs –0.3 VDD+0.3 V
VOUT Output voltage range for clock outputs –0.3 VDDO+0.3 V
Tj Junction temperature 150 °C
Tstg Storage temperature range –65 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
ADVANCE INFORMATION
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) VDD refers to all core supply pins or voltages. All VDD core supplies should be powered-on before the PD# is pulled high to trigger the
internal power-on reset (POR).
(3) VDDO refers to all output supply pins or voltages. VDDO_x refers to the output supply for a specific output channel, where x denotes
the channel index.
5.2 ESD Ratings

VALUE UNIT
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000
V(ESD) V
discharge Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002, all pins(2) ±750
(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD(1) Core supply voltages 3.135 3.3 3.465 V
VDDO_x(2) Output supply voltages(3) 3.135 3.3 3.465 V
VDDOD Output voltage range for open drain outputs 1.71 3.465 V
TA Operating ambient temperature range -40 85 °C
TJ Junction temperature 135 °C
TCONT-LOCK Continuous lock over temperature - no VCO recalibration needed 125 °C
tVDD Power supply ramp time(4) 0.01 100 ms
(1) VDD refers to all core supply pins or voltages. All VDD core supplies must be powered-on before internal power-on reset (POR).
(2) VDDO refers to all output supply pins or voltages. VDDO_x refers to the output supply for a specific output channel, where x denotes
the channel index.
(3) CMOS output voltage levels are determined by internal programming of the CMOS output LDO to support either 1.8V or 2.65V.
(4) Time for VDD to ramp monotonically above 2.7V for proper internal power-on reset. For slower or non-monotonic VDD ramp, hold PD#
low until after VDD voltages are valid.

LMK5C22212AS1
5.4 Thermal Information

LMK5C22212AS1
THERMAL METRIC(1) (2) (3) RGC (VQFN) UNIT
64 PINS
RθJA Junction-to-ambient thermal resistance 21.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 11.1 °C/W
RθJB Junction-to-board thermal resistance 6.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.8 °C/W
ψJT Junction-to-top characterization parameter 0.3 °C/W
ψJB Junction-to-board characterization parameter 6.3 °C/W
(1) For more information about traditional and new thermal metrics, see the application note, Semiconductor and IC Package Thermal
Metrics.
ADVANCE INFORMATION
(2) The thermal information is based on a 10-layer 200mm x 250mm board with 49 thermal vias (7mm x 7mm pattern, 0.3mm holes).
(3) ΨJB can allow the system designer to measure the board temperature (TPCB) with a fine-gauge thermocouple and back-calculate the
device junction temperature, TJ = TPCB + (ΨJB x Power). Measurement of ΨJB is defined by JESD51-6.
5.5 Electrical Characteristics

Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Consumption Characteristics
245.76MHz from OUT0 to OUT11
LVDS outputs, BAW APLL post-divider
750 mA
= 5, div2 enabled, channel dividers
bypassed, DPLL2 and APLL2 disabled.
Total current consumption with 245.76MHz from OUT0 to OUT11,
IDD_TOT
specified configuration HSDS outputs, channel dividers
890 mA
enabled , BAW APLL post divider
bypassed, DPLL2 and APLL2 disabled.
OUT0 to OUT11 HSDS outputs, BAW
1000 mA
APLL and APLL2 enabled.
IDD-XO XO input current consumption XO 3.5 mA
Current consumption per XO
IDD-XO2X XO doubler(1) 0.3 mA
doubler
IDD-DPLL Current consumption per DPLL DPLL(2) 55 mA
IDD-APLL2 APLL2 current consumption APLL2 160 mA
IDD-APLL1 APLL1 current consumption APLL1 120 mA
Analog circuitry from VDDXO supply
IDD-ANA Analog bias current consumption 42 mA
pin. Always on when device is enabled.
Digital control circuitry from VDD_DIG
Digital control current
IDD-DIG supply pin., Always on when device is 34 mA
consumption
enabled.
Current consumption per channel
IDDO-CHDIV 12-bit channel divider 20 mA
divider block
Current consumption per 1PPS/
IDDO-1PPSDIV 20-bit 1PPS/SYSREF divider 12 mA
SYSREF divider block
Current consumption per 1PPS/
IDDO-DELAY Analog delay function enabled 10 mA
SYSREF analog delay block
HSDS buffer (VCM level = s1, Iout =
19 mA
4mA, 100Ω termination)
HSDS current consumption per HSDS buffer (VCM level = s1, Iout =
IDDO-HSDS 22 mA
output driver 7mA, 100Ω termination)
HSDS buffer (VCM level = s1, Iout =
25 mA
10mA, 100Ω termination)

LMK5C22212AS1

HCSL current consumption per
IDDO-HCSL HCSL output (50Ω termination per side) 30.5 mA
output driver
IDD_PD Power-down current consumption Device powered-down, PD# = LOW 90 110 mA
Reference Input Characteristics (INx)
Single-ended input 0.5E–6 200
fIN INx frequency range MHz
Differential input 5 800
VIH Single-ended input high voltage 1.2 VDD + 0.3 V
DC-coupled input mode (3)
VIL Single-ended input low voltage 0.5 V
VIN-SE-PP Single-ended input voltage swing AC-coupled input mode (4) 0.4 2 Vpp
VIN-DIFF-PP Differential input voltage swing AC- or DC- coupled input (5) 0.4 2 Vpp
VICM Input Common Mode DC- coupled differential input (6) 0.1 2 V
ADVANCE INFORMATION
Single-ended input 0.2 0.5 V/ns
dV/dt Input slew rate
Differential input 0.2 0.5 V/ns
IDC Input Clock Duty Cycle Non 1PPS signal 40 60 %
tPULSE-1PPS 1PPS pulse width for input 1PPS or pulsed signal 100 ns
Single pin INx_P or INx_N, 50Ω and
IIN-DC DC input leakage current 100Ω internal terminations disabled, –350 350 µA
AC coupled mode enabled or disabled
CIN Input capacitance Single-ended, each pin 2 pF
XO/TCXO Input Characteristics (XO)
fCLK XO input frequency range (7) 10 156.25 MHz
VIH LVCMOS Input high voltage 1.4 VDD + 0.3 V
DC-coupled input mode (8)
VIL LVCMOS Input low voltage 0.8 V
VIN-SE Single-ended input voltage swing AC-coupled input mode (9) 0.4 VDD + 0.3 Vpp
dV/dt Input slew rate 0.2 0.5 V/ns
IDC Input duty cycle 40 60 %
Single pin XO_P, 50Ω and 100Ω
IIN-DC DC Input leakage current –350 350 µA
internal terminations disabled
CIN Input capacitance on each pin 1 pF
CEXT External AC coupling cap 10 nF
APLL/VCO Characteristics
BAW APLL Fractional feedback divider 110 MHz
fPFD PFD frequency range
APLL2 Fractional feedback divider 125 MHz
fVCO2 VCO2 Frequency range 5595 5950 MHz
fVCO1 VCO1 Frequency range 2457.35 2457.6 2457.85 MHz
Time between soft or hard reset and
tAPLL2-LOCK APLL2 lock time 350 460 ms
stable APLL2 output.
Time between soft or hard reset and
tBAW APLL-LOCK BAW APLL lock time 12.5 13 ms
stable BAW APLL output.

LMK5C22212AS1

HSDS Output Characteristics (OUTx)
fOUT Output frequency range 1E–6 1250 MHz
2×VOD-
VOUT-DIFF Differential output swing mVpp
HSDS
fout < 100MHz, Iout = 4mA 350 400 440 mV

100MHz ≤ fout ≤ 325MHz, Iout = 4mA 335 400 445 mV
ADVANCE INFORMATION

VOD-HSDS HSDS output voltage swing
325MHz < fout ≤ 800MHz, Iout = 4mA 300 350 400 mV
VOH Output voltage high VOL + VOD mVpp
VCM level = s1 50 150 250 mV
VOL Output voltage low
VCM level = s2+3 300 470 720 mV
VOL +
VCM level = s1 or s2+3 V
VOD/2
VCM Output common mode voltage
VCM level = s2, Iout = 4mA 0.6 0.7 0.8 V
VCM level = s3, Iout = 4mA 1.125 1.25 1.375 V
Same APLL, same post divider and
50 ps
channel divider values, same bank
tSKEW Output skew (13)
80 ps
channel divider values, between banks
fOUT < 100MHz, 20% to 80%,
200 250 350 ps
OUT_x_CAP_EN = 0, CL = 2pF
100MHz ≤ fOUT ≤ 325MHz, 20% to
80%, Iout ≥ 8mA, OUT_x_CAP_EN = 0, 165 225 260 ps
CL = 2pF
tR/tF Rise/Fall time 100MHz ≤ fOUT ≤ 325MHz, 20% to
175 230 300 ps
80%, OUT_x_CAP_EN = 0, CL = 2pF
325MHz < fOUT ≤ 800MHz, 20% to
150 215 285 ps
800MHz < fOUT ≤ 1250MHz, 20% to
120 205 250 ps
ODC Output duty cycle 48 52 %
HCSL Output Characteristics (OUTx)
fOUT Output frequency range HSCL output mode 25 100 650 MHz
VOL Output voltage low –150 0 150 mV
VOH Output voltage high 600 750 900 mV
VMIN Output voltage minimum Including undershoot –300 0 150 mV

LMK5C22212AS1

VMAX Output voltage maximum Including overshoot 600 750 1150 mV
±150mV around center point,
dV/dt Differential output slew rate 2 4 V/ns
OUT_x_CAP_EN = 1, CL= 2pF
±150mV around center
dV/dt Differential output slew rate 3 5 V/ns
point,OUT_x_CAP_EN = 0, CL= 2pF
50 ps
channel divider values, same bank
tSKEW Output skew (13)
80 ps
channel divider values, between banks
VCROSS Absolute voltage crossing point fOUT = 100MHz 300 500 mV
ΔVCROSS Voltage crossing point variation fOUT = 100MHz 75 mV
ADVANCE INFORMATION
1.8V LVCMOS Output Characteristics (OUT0, OUT1)
VOH Output high voltage IOH = -2mA 1.5 V
VOL Output low voltage IOL = 2mA 0.2 V
tR/tF Output rise/fall time 20% to 80% 150 ps
OUT0_P, OUT0_N, OUT1_P, OUT1_N
with same polarity, same APLL post
60 ps
divider and output divider values. Same
tSK Output-to-output skew polarity and output type (LVCMOS)
output divider values. Skew between 0.7 1 1.3 ns
LVCMOS and differential outputs
ROUT Output impedance 54 64 75 Ω
2.65V LVCMOS Output Characteristics (OUT0, OUT1)
VOH Output high voltage IOH = -2mA 2.3 V
tR/tF Output rise/fall time 20% to 80% 150 ps
OUT_P, OUT0_N, OUT1_P, OUT1_N
with same polarity, same APLL post
60 ps
divider and output divider values. Same
tSK Output-to-output skew polarity and output type (LVCMOS)
output divider values. Skew between 0.7 1.0 1.3 ns
LVCMOS and differential outputs
Output phase noise floor
PNFLOOR 25MHz –155 dBc/Hz
(fOFFSET > 10MHz)
3.3V LVCMOS GPIO Clock Output Characteristics (GPIO0, GPIO1, GPIO2)
fOUT Maximum output frequency GPIO1, GPIO2 25 MHz
VOH Output high voltage IOH= 2mA 2.4 V
VOL Output low voltage IOL= 2mA 0.4 V
IIH Input high current VIN = VDD 100 µA
IIL Output low current VIN = 0V -100 µA
tR/tF Output rise/fall time 20% to 80%, 1kΩ to GND 0.5 1.3 2.6 ns

LMK5C22212AS1

GPIO1, GPIO2 output skew compared
to OUT0_P, OUT0_N, OUT1_P,
tSK Output-to-output skew OUT1_N CMOS outputs. GPIOx_SEL 7.5 11 ns
= 115
fout = 100kHz
PLL Output Clock Noise Characteristics
XO = 48MHz, fout = 1228.8MHz, post
divider P1APLL1 = 2, HSDS output VOD 45 fs
≥ 800mV(10)
divider P1APLL1 = 4, HSDS output VOD 35 50 fs
ADVANCE INFORMATION
≥ 800mV(10)
divider P1APLL1 = 5, HSDS output 40 57 fs
VOD ≥ 800mV(10)
divider P1APLL1 = 10, HSDS output 45 64 fs
(10)
12kHz to 20MHz integrated RMS VOD ≥ 800mV
RJAPLL1
jitter for APLL1 outputs XO = 48MHz, fout =
245.76MHz, bypass post divider
50 62 fs
P1APLL1 = 1, HSDS output VOD ≥
800mV (11)
XO = 48MHz, fout =
122.88MHz, bypass post divider
55 86 fs
P1APLL1 = 1, HSDS output VOD ≥
800mV (11)
XO = 48MHz, fout = 245.76MHz, HSDS
50 80 fs
output, all VOD levels(10)
XO = 48MHz, fout = 122.88MHz, HSDS
60 90 fs
output, all VOD levels(10)
XO = 48MHz, fout = 153.6MHz (VCO2
= 5836.8MHz), 155.52MHz (VCO2 =
5598.72MHz), 174.703084MHz (VCO2
= 5765.2MHz) or 184.32MHz (VCO2 =
5898.24MHz) from APLL2.
110 150 fs
HSDS output , VOD ≥ 800mV from
OUT4, OUT5, OUT6 and OUT7 or
OUT2 and OUT3. 156.25MHz from
BAW APLL output in all other output
banks.
XO = 48MHz, fout = 161.1328125MHz
or 322.265625MHz (VCO2 =
12kHz to 20MHz integrated RMS 5800.78125MHz), or 212.5MHz (VCO2
RJAPLL2
jitter for APLL2 outputs = 5950MHz) from APLL2.
110 150 fs
HSDS output , VOD ≥ 800mV
from OUT4, OUT5, OUT6 and OUT7.
156.25MHz from BAW APLL output in
all other output banks.
XO = 48MHz, fout = 156.25MHz
or 125MHz (VCO2 = 5625MHz), or
100MHz (VCO2 = 5600MHz) from
APLL2. HSDS output , VOD ≥ 800mV
110 150 fs
from OUT4, OUT5, OUT6 and OUT7
or OUT2 and OUT3. 156.25MHz from
BAW APLL output in all other output
banks.

LMK5C22212AS1

Power supply noise rejection Vcc = 3.3V, VN = 50mVpp, HSDS,
PSNRVDDO_0_1 -105 dBc
VDD_0_1 LVDS or AC-LVPECL outputs. (12)
VDD_2_3 LVDS or AC-LVPECL outputs. (12)
VDDO_4_7 LVDS or AC-LVPECL outputs. (12)
VDDO_8_11 LVDS or AC-LVPECL outputs. (12)
PSNRVDD_XO -100 dBc
VDD_XO LVDS or AC-LVPECL outputs. (12)
PSNRVDD_APLL2 -105 dBc
VDD_APLL2 LVDS or AC-LVPECL outputs. (12)
ADVANCE INFORMATION
PSNRVDD_APLL1 -105 dBc
VDD_APLL1 LVDS or AC-LVPECL outputs. (12)
PSNRVDD_DIG -120 dBc
VDD_DIG LVDS or AC-LVPECL outputs. (12)
PCIe Jitter Characteristics
PCIe Gen 1 (2.5 GT/s) Common APLL2 or APLL1 output, 3x noise
JPCIE-Gen1-CC 0.8 5 ps p-p
Clock jitter folding
PCIe Gen 2 (5.0 GT/s) Common APLL2 or APLL1 output, 3x noise
JPCIE-Gen2-CC 85 250 fs RMS
PCIe Gen 3 (8 GT/s) Common APLL2 or APLL1 output, 3x noise
JPCIe-Gen3-CC 25 100 fs RMS
DPLL Characteristics
fTDC TDC rate range for DPLLx 1E–6 26 MHz
dφ/dt Phase slew during switchover Programmable range 695 ns/s
DPLL-BW DPLL loop bandwidth Programmable loop bandwidth(17) 1E–3 4000 Hz
JPK DPLL closed-loop jitter peaking 0.1 dB
Compliant with G.8262 Options 1
JTOL Jitter tolerance and 2. Jitter modulation = 10Hz, 6455 UI p-p
25.78152Gbps line rate
DCO Characteristics
DPLL DCO frequency tuning
fDCO-DPLL DPLLx -200 200 ppm
range
BAW APLL in holdover or APLL only
-200 200 ppm
operation.
fDCO-APLL DCO frequency tuning range
APLL2in holdover or APLL only
-1000 1000 ppm
operation.
Zero-Delay Mode (ZDM) Characteristics
Output frequency range with ZDM DPLL1: OUT0 or OUT10 1E–6 1250 MHz
fOUT-ZDM
enabled DPLL2: OUT0 or OUT4 1E–6 700 MHz
Input-to-output propagation delay OUT0, fIN ≤ fTDC_MAX, fOUT ≤ fTDC_MAX,
tDLY-ZDM 150 ps
with ZDM enabled DPLLx_PH_OFFSET = 172500
Input-to-output propagation delay OUT0, fIN ≤ fTDC_MAX, fOUT ≤ fTDC_MAX,
tDLY-VAR-ZDM 65 ±ps
variation with ZDM enabled DPLLx_PH_OFFSET = 0
1PPS Reference Characteristics

LMK5C22212AS1

XO = 48MHz, initial error =
DPLL frequency lock time with ±25ppb, -180° ≤ Θ ≤ 180°. DPLL
tDPLL_FL 5 6 s
1PPS reference LBW = 10mHz, frequency lock Δfout ≤
±4.6ppm
XO = 48MHz, initial error =
DPLL phase lock time with 1PPS ±25ppb, -180° ≤ Θ ≤ 180°. DPLL LBW
tDPLL_PL 34 38 s
reference = 10mHz, DPLL LBW = 10mHz, phase
lock ≤ ±100ns
Hitless Switching Characteristics
INx = 1Hz, INy = 1Hz, frequency
locked. INx and INy relative phase
4 ± ps
offset -180° ≤ Θ ≤ 180°. DPLL LBW =
10mHz.
ADVANCE INFORMATION
INx = 8kHz, INy = 8kHz, frequency

tHIT Phase transient during switchover 19 ± ps
1Hz
Nx = 25MHz, INy = 25MHz, frequency
1.8 ± ps
1Hz
INx = 1Hz, INy = 1Hz, frequency
0.85 ± ppb
10mHz
INx = 8kHz, INy = 8kHz, frequency
Frequency transient during locked. INx and INy relative phase
fHIT 0.45 ± ppb
switchover offset -180° ≤ Θ ≤ 180°. DPLL LBW =
1Hz
INx = 25MHz, INy = 25MHz, frequency
0.63 ± ppb
1Hz
Programmable Output Delay Characteristics
BAW APLL = 2457.6MHz, VCO
post-divider = 2, 0.5x range scale,
13.13 ps
1Hz ≤ OUTx ≤ 122.88MHz,
ANA_DELAY_LINEARITY_CODE = 2
post-divider= 1, 2x range scale,
26.25 ps
1Hz ≤ OUTx ≤ 122.88MHz,
tANA-DLY Analog delay step size (13)
APLL2 = 5625.0MHz, VCO post-
divider = 3, 1x range scale,
17.2 ps
1Hz ≤ OUTx ≤ 156.25MHz,
APLL2= 5625.0MHz, VCO post-
divider = 4; 1x range scale,
22.9 ps
1Hz ≤ OUTx ≤ 156.25MHz,

LMK5C22212AS1

post-divider = 2, 0.5x range scale,
-6.56 6.56 ps
1Hz ≤ OUTx ≤ 122.88MHz,
post-divider= 1, 2x range scale,
-13.13 13.13 ps
1Hz ≤ OUTx ≤ 122.88MHz,
tANA-DLY-ERR Analog delay step size error
divider = 3, 1x range scale,
-8.6 8.6 ps
1Hz ≤ OUTx ≤ 156.25MHz,
divider = 4; 1x range scale,
ADVANCE INFORMATION
-11.45 11.45 ps
1Hz ≤ OUTx ≤ 156.25MHz,
31 × tANA-
tANA-DLY-RANGE Analog delay range ps
DLY
Analog delay absolute accuracy for any

setting N = 0 to 31 across analog delay
range. Worst case error of actual value
tANA-DLY-ACC Analog delay accuracy -25 25 ps
relative to expected value N × tANA-DLY-
STEP for ANA_DELAY_LINEARITY_CO
DE = 3, 4, 5
ANA_DELAY_LINEARITY_CODE = 2 333 450 ps
tANA-DLY-LIN Analog delay linearity (15)
VCO post-divider frequency output =
196.6 ps
2457.6MHz , half step setting
tDIG-DLY Digital delay step size
VCO post-divider frequency output =
786.4 ps
2457.6MHz, full step setting
3-Level Logic Input Characteristics (GPIO0, GPIO1, GPIO2, SCS_ADD)
VIH Input high voltage 1.4 V
VIM Input mid voltage 0.6 0.95 V
Input floating with internal bias and PD#
VIM Input mid voltage self-bias 0.7 0.9 V
pulled low
Internal pulldown resistor for mid
RIM-PD 145 163 180 kΩ
level self-bias (16)
Internal pullup for mid level self-
RIM-PU 470 526 580 kΩ
bias (16)
VIL Input low voltage 0.4 V
IIH Input high current VIH = VDD –40 40 µA
IIL Input low current VIL = GND –40 40 µA
CIN Input capacitance 2 pF
2-Level Logic Input Characteristics (PD#, SCK, SDIO, SCS_ADD; GPIO0, GPIO1 and GPIO2 after power up)
IIH Input high current VIH = VDD, except PD# –40 40 µA
IIL Input low current VIL = GND, except PD# –40 40 µA
VIH = VDD, PD# with internal 200kΩ
IIH Input high current –57 24 µA
pull-up

LMK5C22212AS1

VIL = GND, PD# with internal 200kΩ
IIL Input low current –57 24 µA
pull-up
Input pulse width for GPIO
SYNC, SYSREF request, TEC
tWIDTH Monotonic edges 200 ns
trigger, DPLL input selection,
FDEV trigger and FDEV_dir
Logic Output Characteristics (GPIO0, GPIO1, GPIO2, SDIO)
VOH Output high voltage IOH = 1mA 2.4 V
20% to 80%, LVCMOS mode, 1kΩ to
tR/tF Output rise/fall time 500 ps
GND
ADVANCE INFORMATION
Open Drain Output (GPIO0, GPIO1, GPIO2, SDA)

IOL = 3mA 0.3 V
VOL Output Low Level
IOL = 6mA 0.6 V
IOH Output Leakage Current -15 15 µA
SPI Timing Requirements (SDIO, SCK, SCS_ADD)
SPI clock rate 20 MHz
fSCK SPI clock rate; during SRAM read
5 10 MHz
and write operations
SCS to SCK setup time (start
t1 10 ns
communication cycle)
t2 SDI to SCK setup time 10 ns
t3 SDI to SCK hold time 10 ns
t4 SCK high time 25 ns
t5 SCK low time 25 ns
t6 SCK to SDO valid read-back data 20 ns
t7 SCS pulse width 20 ns
SCK to SCS setup time (end
t8 10 ns
communication cycle)
I2C Timing Requirements (SDA, SCL)
IIH Input leakage –15 15 µA
Standard 100
fSCL I2C clock rate kHz
Fast mode 400
tSU(START) START condition setup time SCL high before SDA low 0.6 µs
tH(START) START condition hold time SCL low after SDA low 0.6 µs
tW(SCLH) SCL pulse width high 0.6 µs
tW(SCLL) SCL pulse width low 1.3 µs
tSU(SDA) SDA setup time 100 ns
tH(SDA) SDA hold time SDA valid after SCL low 0 0.9 µs
tR(IN) SDA/SCL input rise time 300 ns
tF(IN) SDA/SCL input fall time 300 ns
tF(OUT) SDA output fall time CBUS ≤ 400pF 300 ns

LMK5C22212AS1

tSU(STOP) STOP condition setup time 0.6 µs
Bus free time between STOP and
tBUS 1.3 µs
START
tVD-DAT Data valid time 0.9 µs
tVD-ACK Data valid acknowledge time 0.9 µs
EEPROM Characteristics
nEE-CYC EEPROM programming cycles 100 cycle
EEPROM SRAM read/write time
tSRAM-R/W 0 ms
delay between bytes
(1) This is the current consumption of one XO doubler. All XO doublers consume the same current.
(2) This is the current consumption of one DPLL. Each DPLL consumes the same current.
ADVANCE INFORMATION
(3) REFx_ITYPE = 8 or 12.
(4) REFx_ITYPE = 1, 3 or 5, non-driven input directly tied to GND, capacitor to GND or 50Ω to GND.
(5) REFx_ITYPE = 1, 3 or 5.
(6) Combination of common mode voltage and DC coupled different input voltage must not exceed Absolute Maximum Ratings.
(7) When XO input frequency is greater than the APLL phase detector maximum supported comparison frequency, the APLL R divider
must be set to minimum of divide by 2.
(8) Register XO_ITYPE = 8 or 12.
(9) Register XO_ITYPE = 1, 3 or 5
(10) OUT0 to sourced from post divider.
(11) post divider bypassed by setting = 1. OUT0 to sourced from channel dividers.
(12) PSNR is the single-sideband spur level measured in dBc when sinusoidal noise with amplitude VN and frequency between 100kHz and
10MHz is injected onto VDD and VDDO pins with 1.0µF decoupling capacitance.
(13) Output dividers are synchronized. SYNC status achieved from power up or SYNC_SW.
(14) Typical analog delay step size based on APLL post-divider output period divided by 31, times the analog delay range scale value 0.5, 1
or 2.
(15) Analog delay linearity typically selected based on the period of the analog delay range, tANA-DLY-RANGE.
(16) Variation of internal pullup resistor tracks variation of pulldown resistor to maintain a consistent mid voltage self-bias ratio.
(17) DPLL loop bandwidth must be less than 1/100 of TDC frequency and less than 1/10 of APLL loop bandwidth.
5.6 Timing Diagrams

t1 t4 t5
SCK
t2
²
SDI Write/Read W/R A14 A13...D1/A1 D0/A0 '21¶7 &$5(
t6
SDO Read '21¶7 &$5( D7 D1 D0
t7
SCS
t8
Figure 5-1. SPI Write Timing Diagram

LMK5C22212AS1
t1 t4 t5
SCK '21¶7 &$5(

t2 t3
SDI '21¶7 &$5( R A14 A13...A1 A0 '21¶7 &$5(
t6
SDO '21¶7 &$5( D7 D6...D1 D0
t7
SCS
t8
Figure 5-2. SPI 4-Wire Read Timing Diagram
t1 t4 t5
ADVANCE INFORMATION
SCK '21¶7 &$5(

t2 t3
t6
_
SDIO '21¶7 &$5( W A14 A13...A1 A0 D7 D6...D1 D0 '21¶7 &$5(
t7
SCS
t8
Figure 5-3. SPI 3-Wire Read Timing Diagram

ACK STOP
STOP START
tW(SCLL) tW(SCLH) tr(SM) tf(SM)

~
~
VIH(SM)
SCL
VIL(SM)
~
~
th(START) tSU(SDATA)
tr(SM)
tSU(START) th(SDATA) tSU(STOP)
tf(SM)
tBUS
~
~
~
~
VIH(SM)
SDA
VIL(SM)
~
~
Figure 5-4. I2C Timing Diagram

LMK5C22212AS1
OUTx_N VOH
VOD = VOH - VOL
OUTx_P VOL
80%
0V VOUT-DIFF = 2 × VOD
20%
tR tF
Figure 5-5. Differential Output Voltage and Rise/Fall Time
ADVANCE INFORMATION
80%
OUT_REFx/2 VOUT,SE
20%
tR tF
Figure 5-6. Single-Ended Output Voltage and Rise/Fall Time

LMK5C22212AS1
INx_P
Single Ended
INx_P
Differential
INx_N
tPHO,DIFF
OUTx_P
Differential, PLL
OUTx_N
tSK,DIFF,INT
ADVANCE INFORMATION
OUTx_P
Differential, PLL
OUTx_N
tSK,SE-DIFF,INT
OUTx_P/N Single Ended, PLL
tPHO, SE
tSK,SE,INT
OUTx_P/N
Single Ended, PLL
Figure 5-7. Differential and Single-Ended Output Skew and Phase Offset

LMK5C22212AS1
5.7 Typical Characteristics
ADVANCE INFORMATION
Jitter = 44fs RMS (12kHz to 20MHz) Jitter = 51fs RMS (12kHz to 20MHz)
f APLL1 = 2457.6MHz f APLL1 = 2457.6MHz
Figure 5-8. 491.52MHz HSDS Output From APLL1 Figure 5-9. 245.76MHz HSDS Output From APLL1
BAW BAW
f APLL1 = 2457.6MHz fAPLL2 = 5800.78125MHz
Figure 5-10. 122.88MHz HSDS Output From APLL1 Figure 5-11. 322.265625MHz HSDS Output From
BAW APLL2
Figure 5-12. 312.5MHz HSDS Output From APLL2 Jitter = 103fs RMS (12kHz to 20MHz)
fAPLL2 = 5950MHz
Figure 5-13. 212.5MHz HSDS Output From APLL2

LMK5C22212AS1
fAPLL2 = 5800.78125MHz fAPLL2 = 5598.72MHz
ADVANCE INFORMATION
Figure 5-14. 161.1328125MHz HSDS Output From Figure 5-15. 155.52MHz HSDS Output From APLL2
APLL2
Jitter = 100fs RMS (12kHz to 20MHz)

fAPLL2 = 5836.8MHz
Figure 5-16. 153.6MHz HSDS Output From APLL2
50 50
Min Min
40 Max 40 Max
30 Avg 30 Avg
20 20
Delay variation (ps)
10 10
0 0
-10 -10
-20 -20
-30 -30
-40 -40
-50 -50
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
Analog delay setting (steps/code) Analog delay setting (steps/code)
Figure 5-17. SYSREF/1PPS Delay Linearity vs. Figure 5-18. SYSREF/1PPS Delay Linearity vs.
Analog Delay Code 2 Analog Delay Code 3

LMK5C22212AS1
50 50
Min Min
40 Max 40 Max
30 Avg 30 Avg
20 20

10 10
0 0
-10 -10
-20 -20
-30 -30
-40 -40
-50 -50
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35
Analog delay setting (steps/code) Analog delay setting (steps/code)
Figure 5-19. SYSREF/1PPS Delay Linearity vs. Figure 5-20. SYSREF/1PPS Delay Linearity vs.
Analog Delay Code 4 Analog Delay Code 5
ADVANCE INFORMATION

LMK5C22212AS1
6 Parameter Measurement Information

6.1 Differential Voltage Measurement Terminology
The differential voltage of a differential signal can be described by two different definitions, causing confusion
when reading data sheets or communicating with other engineers. This section addresses the measurement
and description of a differential signal so that the reader is able to understand and distinguish between the two
different definitions when used.
The first definition used to describe a differential signal is the absolute value of the voltage potential between the
inverting and noninverting signal. The symbol for this first measurement is typically VID or VOD depending on if
an input or output voltage is being described.
The second definition used to describe a differential signal is to measure the potential of the noninverting
signal with respect to the inverting signal. The symbol for this second measurement is VSS and is a calculated
parameter. Nowhere in the IC does this signal exist with respect to ground, the signal only exists in reference to
ADVANCE INFORMATION
the differential pair. VSS can be measured directly by oscilloscopes with floating references, otherwise this value
can be calculated as twice the value of VOD as described in the first description.
Figure 6-1 shows the two different definitions side-by-side for inputs and Figure 6-2 shows the two different
definitions side-by-side for outputs. The VID and VOD definitions show VA and VB DC levels that the noninverting
and inverting signals toggle between with respect to ground. VSS input and output definitions show that if the
inverting signal is considered the voltage potential reference, the noninverting signal voltage potential is now
increasing and decreasing above and below the noninverting reference. Thus the peak-to-peak voltage of the
differential signal can be measured.
VID and VOD are often defined as volts (V) and VSS is often defined as volts peak-to-peak (VPP).
VID Definition VID Definition for Input
Non-Inverng Clock
VA
VID VID-DIFF
VB
Inver ng Clock
VID = | VA - VB | VID-DIFF = 2·VID
GND
Figure 6-1. Two Different Definitions for Differential Input Signals
VOD Definition VOD Definition for Output

Non-Inverng Clock
VA
VOD VOD-DIFF
VB
Inver ng Clock
VOD = | VA - VB | VOD-DIFF = 2·VOD
GND
Figure 6-2. Two Different Definitions for Differential Output Signals

LMK5C22212AS1
6.2 Output Clock Test Configurations

This section describes the characterization test setup for different output formats.
High-impedance probe
LMK Device
Oscilloscope
LVCMOS driver
2pF
Figure 6-3. LVCMOS Output Time Domain Test Configuration
ADVANCE INFORMATION
LMK Device Phase Noise
LVCMOS driver Analyzer
Figure 6-4. LVCMOS Output Phase Domain Test Configuration
100
LMK Device Oscilloscope
HSDS driver (Hi-Z termination)
Figure 6-5. HSDS Output Time Domain Test Configuration
100
Balun
HSDS driver Analyzer
Figure 6-6. HSDS Output Phase Domain Test Configuration
LMK Device Oscilloscope

HCSL driver (Hi-Z termination)
50 50
Figure 6-7. HCSL Output Time Domain Test Configuration

LMK5C22212AS1

Balun
HCSL driver Analyzer
50 50
Figure 6-8. HCSL Output Phase Domain Test Configuration
Sine wave
ADVANCE INFORMATION
Modulator
Power Supply
Phase Noise/
Signal Generator DUT Device Output Balun Spectrum
Reference Analyzer
Input
Single-side band spur level measured in dBc with a known noise amplitude and frequency injected onto the device power supply.
Figure 6-9. Power Supply Noise Rejection (PSNR) Test Configuration

LMK5C22212AS1
7 Detailed Description
7.1 Overview
The LMK5C22212AS1 has two reference inputs, two digital PLLs (DPLL), two analog PLLs (APLLs) with
integrated VCOs, and twelve output clocks. APLL1 uses an ultra-high performance BAW VCO (VCBO) with
a very high quality factor, and thus minimizes dependency on the phase noise or frequency of the external
oscillator (XO) input clock. TI's VCBO technology reduces the overall solution cost to meet the free-run and
holdover frequency stability requirements. An XO, TCXO, or OCXO must be selected based on system holdover
stability requirements. APLL1 can be controlled by the corresponding DPLL1, allowing the APLL1 domain to
be locked to the DPLL1 reference input for synchronous clock generation. The DPLL2/APLL2 similarly can
be locked to the same referenced input as DPLL1 or locked to a separate reference input to create another
synchronization domain. Each APLL can select a reference from either XO port or another APLL divided clock.
The DPLL can select a synchronization input reference from reference inputs INx or align to another APLL
domain by selecting feedback from a cascade dividers.
ADVANCE INFORMATION
The DPLL reference input mux supports automatic input selection based on priority and reference signal
monitoring criteria. Manual input selection is also possible through software or pin control. The device provides
Hitless Switching between reference sources with proprietary phase cancellation and phase slew control for
superior phase transient performance. The Reference Input Monitoring block monitors the clock inputs and
performs a hitless switchover or holdover when a loss of reference (LOR) is detected. A LOR condition is
detected upon any violation of the threshold limits set for the input monitors, which include frequency, missing
and early pulse, runt pulse, and 1PPS (pulse-per-second) detectors. The threshold limits for each input detector
can be set and enabled per reference clock input. The Tuning Word History monitor feature determines the initial
output frequency accuracy upon entry into holdover based on the historical average frequency when locked,
thereby minimizing the frequency and phase disturbance during a LOR condition.
The LMK5C22212AS1 has twelve outputs with programmable output driver types, allowing up to twelve
differential clocks or a combination of differential and single-ended clocks). Up to four single-ended 1.8V or
2.65V LVCMOS output clocks (each from _P and _N outputs from OUT0 and OUT1) can be configured with
ten differential output clocks. Each output clock derives from one of two APLL/VCO domains through the output
muxes. Output 0 (OUT0) and Output 1 (OUT1) are the most flexible and can select the source from the XO,
reference input, or any APLL domain. A CMOS 1PPS output can be supported on Outputs 0 (OUT0) and
Output 1 (OUT1). The output dividers have a SYNC feature to allow multiple outputs to be phase-aligned.
Zero-Delay Mode (ZDM) can also achieve a deterministic phase alignment between a clock from DPLL1 or
DPLL2 presented to OUT0 and the selected reference input. An alternate ZDM feedback path is available on
OUT10 for DPLL1 and OUT4 for DPLL2.
To support IEEE 1588 PTP secondary clock or other clock steering applications, the DPLL supports DCO mode
with less than 1ppt (part per trillion) frequency resolution for precise frequency and phase adjustment through
software or pin control.
The device is fully programmable through I2C or SPI and supports start-up frequency configuration with factory
preprogrammed internal ROM pages. A programmable EEPROM Overlay, which allows POR configuration
of registers related to APLL and output configuration, provides flexible power up output clocks. The DPLL
configuration is not set by EEPROM values, but initialized based on the ROM Page Selection, and fully
programmable using the serial control interface. Internal LDO regulators provide excellent PSNR to reduce
the cost and complexity of the power delivery network. The clock input and PLL monitoring status are visible
through the GPIO status pins and interrupt registers readback for full diagnostic capability.

LMK5C22212AS1
7.2 Functional Block Diagram

C1 C2
XO LF1 LF2
Outputs
Inputs
HSDS, LVDS HCSL or 1.8-V/2.65-V LVCMOS

CH Div
DPLL1/APLL1 12-b & Delay
APLL1 post
LF1 divider OUT0
x1 M div
R div x2 5-b
IN0 16-b /1 to /8 SYSREF Div
20-b & Delay
R div
IN1 16-b VCBO: 2457.6 MHz
Hitless switching
OUT1
with priority
/2 CH Div
N Div
12-b & Delay
40-b fractional
x1
x2
TDC
ADVANCE INFORMATION
CH Div
R div OUT2
12-b
16-b FB Div
40-b fractional
ZDM OUT0
ZDM OUT10
CH Div
/4 APLL1
OUT3
12-b
Cascade Div
/2
DPLL2/APLL2
APLL2 post
SYSREF Div
R div LF2 divider 20-b & Delay
OUT5
16-b x1 M div
x2 5-b
/2 to /13
R div
16-b CH Div OUT4
12-b & Delay
VCO2: 5595 to 5950 MHz
x1 N Div
Hitless switching
40-b fractional
with priority
x2 CH Div
12-b & Delay OUT6
TDC
R div
16-b SYSREF Div OUT7
20-b & Delay
FB Div
40-b fractional
ZDM OUT0
HSDS, LVDS or HCSL

ZDM OUT4
CH Div
OUT8
12-b & Delay
/10 APLL2
Cascade Div
/4
SYSREF Div
20-b & Delay
OUT9
CH Div
OUT10
12-b & Delay
Control SYSREF Div

20-b & Delay
OUT11
Registers ROM
CMOS 3.3V or Open Drain

SDIO
GPIO1/
SCK SR_OUT1
SYSEF/
Device Control 6
GPIO2/
SCS_ADD 1PPS MUX
and Status SR_OUT2
PDN#
Power Conditioning
GPIO0
VDD_IN (x2) VDD_APLL (x3) VDDO (x5) VDD_DIG (x2) CAP_APLL (x4) CAP_DIG
3.3 V 3.3 V 3.3 V 3.3 V
Figure 7-1. LMK5C22212AS1 Top-Level Block Diagram
7.2.1 PLL Architecture Overview

Figure 7-2 shows the PLL architecture implemented in the LMK5C22212AS1 . The primary channel consists of
a digital PLL (DPLL1) and analog PLL (APLL1) with integrated BAW VBCO (VCO1). APLL2 with integrated LC
VCO (VCO2) can generate secondary frequency domain. The numerator in the APLL2 feedback N divider can
be controlled by DPLL2 if a second synchronization domain is needed.
The DPLL is comprised of a time-to-digital converter (TDC), digital loop filter (DLF), and programmable 40-bit
fractional feedback (FB) divider with sigma-delta-modulator (SDM). The APLLs are comprised of a reference (R)
divider, phase-frequency detector (PFD), loop filter (LF), fractional feedback (N) divider with SDM, and VCO.

LMK5C22212AS1
The DPLL has a reference selection mux that allows the DPLL to be either locked to another VCO domain
(DPLL Cascaded) of the APLL or locked to the reference input (Non-Cascaded) providing unique flexibility in
frequency and phase control across multiple clock domains.
Each APLL has a reference selection mux that allows the APLL to be either locked to another VCO domain
(APLL Cascaded) of the APLL or locked to the XO input (Non-Cascaded).
Do not cascade one VCO output to both the DPLL reference and APLL reference of the same DPLL/APLL pair.
Each APLL has a fixed 40 bit denominator controllable by the DPLL. When operating an APLL without the DPLL,
a programmable 24 bit denominator is also available allowing an APLL to cascade between frequency domains
with 0ppm frequency error.
Any unused DPLL or APLL must be disabled (powered-down) to save power. Each VCO of the APLL drives the
clock distribution blocks using the respective VCO post-dividers. If the post-divider setting is 1 for VCO1, the
post-divider is bypassed and VCO1 feeds the output clock distribution blocks directly.
ADVANCE INFORMATION
From XO or/APLL2
cascaded to APLL1
From INx or APLL2

DPLL1 APLL1
fTDC fPD1 VCBO
cascaded to DPLL1 ÷R fVCO1
TDC DLF 5-bit LF
PFD
÷FB ÷N
40-bit Frac-N SDM 40-bit Frac-N SDM
38-bit
DPLL DCO DCO
option FDEV DPLL feedback clock
ZDM from OUT0 or OUT10
From XO or/APLL1
cascaded to APLL2
From INx or APLL1

DPLL2 APLL2
fTDC fPD2 LC-VCO
cascaded to DPLL2 ÷R fVCO2
TDC DLF 5-bit LF
PFD
÷FB ÷N
38-bit
DPLL DCO DCO
Figure 7-2. PLL Architecture
The following sections describe the basic principles of DPLL and APLL operation. See DPLL Operating States
for more details on the PLL modes of operation including holdover.
7.2.2 DPLL
When DPLL operation is enabled, the clock source on the XO pin determines the free-run and holdover
frequency stability and accuracy of the output clocks. The VCBO determines the BAW APLL output clock phase
noise and jitter performance over the 12kHz to 20MHz integration band, regardless of the frequency and jitter of

LMK5C22212AS1
the XO pin input. This increased immunity from reference noise degradation allows the BAW APLL to use a cost-
effective, low-frequency TCXO or OCXO as the external XO input while still maintaining standards-compliant
frequency stability and low loop bandwidth (≤10Hz) required for SyncE and PTP synchronization applications.
The other APLL contain a conventional LC-type VCO which can be optimized for best jitter performance over
the DC to 100kHz integration band by using a wide loop bandwidth with a clean reference and a high phase
detector frequency. When encountering system performance limitations arising from XO frequency or phase
noise, there are unique cascading options to provide a clean high frequency reference for the LC APLL The
LMK5C22212AS1 allows the user to select the divided output from the VCBO (BAW APLL Cascaded) which can
significantly reduce the LC APLL output RMS jitter.
If DCO mode is enabled on a DPLL, a frequency deviation step value (FDEV) can be programmed and used
to adjust (increment or decrement) the FB divider numerator of the DPLL. The DCO frequency adjustment
effectively propagates through the APLL domain to the output clocks and any cascaded DPLL/APLL domains.
The programmed DPLL loop bandwidth (BWDPLL) must be lower than all of the following:
ADVANCE INFORMATION
1. 1/100th of the DPLL TDC rate.

2. 1/10th the APLL loop bandwidth.
3. The maximum DPLL bandwidth setting of 4 kHz.
7.2.2.1 Independent DPLL Operation
In independent DPLL operation, the DPLL can select a reference input (INx) as preferred. DPLL1 and DPLL2
can share the same reference or each select a different reference. At start-up, each APLL locks to the XO
input after initialization and operate in free-run mode. Once a valid DPLL reference input is detected, the DPLL
begins lock acquisition based on the reference priority settings. The TDC in the DPLL compares the phase of
the selected reference input clock and the FB divider clock from the respective VCO and generates a digital
correction word corresponding to the phase error. The correction word is filtered by the digital loop filter (DLF),
and the DLF output adjusts the APLL divider numerator to pull the VCO frequency into lock with the reference
input.
As each DPLL can work independently in this mode, the DPLLs can lock or unlock without impacting other
channels.
When selecting an XO frequency, TI recommends to avoid ratios falling near integer or half integer boundaries
to minimize spurious noise. Selecting an XO frequency that results in an APLL fractional N divider ratio (NUM/
DEN) between the range of 0.125 to 0.45 and 0.55 to 0.875 is best. Higher frequency XO is better for jitter
performance, especially for APLL2 outputs. If the XO frequency or phase noise performance has gap for APLL2,
there is an option to adopt cascaded mode using APLL1 as the reference to APLL2.

LMK5C22212AS1
From XO
DPLL1 APLL1
fTDC fPD1 VCO1
From INx ÷R fVCO1
TDC DLF 5-bit LF
PFD
÷FB ÷N
38-bit
DPLL DCO DCO
ZDM from OUT0

or OUT10
ADVANCE INFORMATION
From XO
DPLL2 APLL2
fTDC fPD1 VCO2
From INx ÷R fVCO2
TDC DLF 5-bit LF
PFD
÷FB ÷N
38-bit
DPLL DCO DCO
ZDM from OUT0

or OUT4
Figure 7-3. DPLL Operation

LMK5C22212AS1
7.2.2.2 APLL Cascaded With DPLL

shows APLL2 in cascaded mode from APLL1. VCO1 is held near the nominal center frequency of 2457.6MHz
while APLL2 acquires lock. Subsequently, APLL1 locks the VCO1 frequency to the external XO input and
operates in free-run mode. Cascaded PLLs lock to a divided frequency from the source VCO. Once a valid DPLL
reference input is detected beyond a minimum valid time, the DPLLs begin lock acquisition. Each DPLL TDC
compares the phase of the selected reference input clock and the FB divider clock from the respective VCO and
generates a digital correction word corresponding to the phase error. At beginning, the TDC simply cancels out
the phase error with no filtering correction word. Then subsequent correction words are filtered by the DLF, and
the DLF output adjusts the APLL N divider numerator to pull the VCO frequency into lock with the reference
input.
Using the VCBO as a cascade source to APLL2 provides the APLL a high-frequency, ultra-low-jitter reference
clock. This unique cascading feature can provide improved close in phase noise performance if the XO/TCXO/
OCXO is a low frequency or has poor phase noise performance. Note that in cascaded DPLL operation the best
ADVANCE INFORMATION
jitter performance and frequency stability is achieved after DPLL1 locked.

DPLL1 lock status impacts the DPLL2 lock status. If APLL1 is in free-run mode or holdover mode, the VCBO
frequency offset ppm value can introduce a similar frequency offset APLL2 outputs even though DPLL2 can stay
in locked status. In this configuration example, verify that DPLL1 and APLL1 are locked first, toggle PLL2 enable
cycle (APLLx_EN bit = 0 → 1) to calibrate VCO2, and then double check PLL2 lock status.
In above example, APLL1 is the upstream PLL, while APLL2 is the downstream PLL. If there are system start-up
requirements on the clock sequencing, APLL2 also can be configured as the upstream PLL.
When cascading PLLs, the downstream APLL can use the DPLL or bypass and power down the DPLL
depending on performance requirements. If DPLL2 is disabled from above APLL cascaded mode, then DPLL1-
only cascade mode can be used (Figure 7-5). In this case, VCO2 can track the VCO1 domain during DPLL1 lock
acquisition and locked modes, allowing the clock domain of APLL2 to be synchronized to the DPLL1 reference
input.
When a DPLL is disabled, using the 24-bit numerator and programmable 24-bit denominator is recommended
instead of the fixed 40-bit denominator to eliminate frequency error from APLL reference to output.
Do not cascade one VCO output to both the DPLL reference and APLL reference of the same DPLL/APLL pair.

LMK5C22212AS1
From APLL2 cascaded to

APLL1
DPLL1 APLL1
fTDC fPD1 VCO1
From INx ÷R fVCO1
TDC DLF 5-bit LF
PFD
÷FB ÷N
38-bit
DPLL DCO DCO
ZDM from OUT0
ADVANCE INFORMATION
or OUT10
From XO
DPLL2 APLL2
fTDC fPD2 VCO2
From INx ÷R fVCO2
TDC DLF 5-bit LF
PFD
÷FB ÷N
38-bit
DPLL DCO DCO

ZDM from OUT0

or OUT4
Figure 7-4. APLL Cascaded With DPLLs Enabled Example

LMK5C22212AS1
From XO
DPLL1 APLL1
From INx fTDC fPD1 VCO1
÷R fVCO1
TDC DLF 5-bit LF
PFD
÷FB ÷N
40-bit
DPLL DCO DCO


ADVANCE INFORMATION
From APLL1
cascaded to APLL2
DPLL2 disabled
DPLL2 APLL2
fTDC fPD2 VCO2
From INx ÷R fVCO2
TDC DLF 5-bit LF
PFD
÷FB ÷N
40-bit
DCO
FDEV DPLL feedback clock
Figure 7-5. APLL Cascaded With DPLL Disabled Example

LMK5C22212AS1
7.2.3 APLL-Only Mode

In APLL-only mode, the external XO input source determines the free-run frequency stability and accuracy of the
output clocks. The DPLL blocks are not used and do not affect the APLLs. APLLs still can operate in cascaded
mode or non-cascaded mode and also have DCO option through control register writes.
The principle of operation for APLL-only mode after power-on reset and initialization is as follows. If APLL2 is in
cascaded mode as shown in Figure 7-5 (DPLL1 also is not used), VCO2 tracks the VCO1 domain. APLLs lock
in APLL priority order using bits: APLLx_STRT_PRTY. Cascading APLL2 from VCO1 provides a high-frequency,
ultra-low-jitter reference clock to minimize the APLL2 in-band phase noise/jitter degradation can otherwise occur
from a lower performance XO/TCXO/OCXO.
If APLL2 is not cascaded as shown in Figure 7-6, VCO2 locks to the XO input in APLLx_STRT_PRTY order after
initialization and operate independent of the APLL1 domain.
For frequency accuracy, using a 24-bit numerator and a programmable 24-bit denominator (PLLx_MODE = 0)
ADVANCE INFORMATION
instead of a fixed 40-bit denominator (PLLx_MODE = 1) is recommended when operating in APLL-Only mode.
From XO
DPLL1 disabled
DPLL1 APLL1
fTDC fPD1 VCO1
÷R fVCO1
TDC DLF 5-bit LF
PFD
÷N
÷FB
24-bit or 40-bit Frac-N
40-bit Frac-N SDM
SDM
40-bit
DCO
From XO
APLL2
fPD1 VCO2
÷R fVCO2
5-bit LF
PFD
÷N
24-bit Frac-N SDM
Figure 7-6. APLL-Only Independent Mode
7.3 Feature Description

The following sections describe the features and functional blocks of the LMK5C22212AS1 .
7.3.1 Oscillator Input (XO)
The XO input is the reference clock for the fractional-N APLLs when the APLLs are not used in cascade mode.
The XO input determines the output frequency accuracy and stability in free-run or holdover modes.
For proper DPLL operation, the XO frequency must have a non-integer relationship with the VCO frequency so
the respective APLL N divider has a fractional divider ratio. For APLL-only mode, the XO frequency can have an
integer or fractional relationship with the VCOs frequencies.

LMK5C22212AS1
For applications requiring DPLL functionality, such as SyncE and PTP/IEEE-1588 for eCPRI, the XO input can
be driven by a TCXO, OCXO, or external traceable clock that conforms to the frequency accuracy and holdover
stability required by the applicable synchronization standard. TCXO and OCXO frequencies of 13MHz, 14.4MHz,
19.44MHz, 24MHz, 25MHz, 27MHz, 38.88MHz, 48MHz, and 54MHz are commonly available and cost-effective
options that allow the BAW APLL to operate in fractional mode for a VCBO frequency of 2457.6MHz.
An XO/TCXO/OCXO source with low frequency or high phase jitter/noise floor has no impact on the BAW APLL
output jitter performance because the VCBO determines the jitter and phase noise over the 12kHz to 20MHz
integration bandwidth. An XO doubler increasing the PFD frequency can be enabled for each APLL to further
optimize close in phase noise performance.
The XO input buffer has programmable input on-chip termination and AC-coupled input biasing configurations as
shown in Figure 7-7. The buffered XO path also drives the input monitoring blocks.
ADVANCE INFORMATION
28pF
XO
S1 S2 100k
VAC-DIFF Differential or
50 100 S3
(weak bias) Single-Ended* XO path
100k
S2
28pF
*Supports a 3.3V
single-ended input swing
Figure 7-7. XO Input Buffer
Table 7-1 lists the typical XO input buffer configurations for common clock interface types.
Table 7-1. XO Input Buffer Modes
INTERNAL SWITCH SETTINGS
XO_TYPE INPUT TYPES
INTERNAL TERM. (S1, S2)(1) INTERNAL BIAS (S3)(2)
0x00 DC (external termination) OFF OFF
0x01 AC (external termination) OFF ON (1.3V)
0x03 AC (internal 100Ω to GND) 100Ω ON (1.3V)
0x04 DC (internal 50Ω to GND) 50Ω OFF
0x05 AC (internal 50Ω to GND) 50Ω ON (1.3V)
0x08 LVCMOS OFF OFF
LVCMOS
0x0C 50Ω OFF
(internal 50Ω to GND)
(1) S1, S2: OFF = External termination is assumed.

(2) S3: OFF = External input bias or DC coupling is assumed.

LMK5C22212AS1
7.3.2 Reference Inputs

The reference inputs (IN0 and IN1) can accept differential or single-ended clocks. Each input has programmable
input type, termination, and DC-coupled or AC-coupled input biasing configurations as shown in Figure 7-8.
Each input buffer drives the reference input mux of the DPLL block. The DPLL input mux can select from any
of the reference inputs. The DPLL can switch between inputs with different frequencies if the frequencies can
be divided-down to a common frequency by DPLL R dividers. The reference input paths also drive the various
detector blocks for reference input monitoring and validation. DC-path switch can bypass internal AC-coupling
capacitors to make low frequency input work robustly.
S4
ADVANCE INFORMATION
7pF
IN0_P/
IN1_P
S1 S2 100k
Differential or
50 100 S3 VAC-DIFF
Single-Ended*
(weak bias) REF path
100k
S2
IN0_N/
IN1_N
S1 7pF
S4
50
Figure 7-8. Reference Input Buffer
Table 7-2 lists the reference input buffer configurations for common clock interface types.
Table 7-2. Reference Input Buffer Modes
INTERNAL REGISTER AND SWITCH SETTINGS
REFx_ITYPE, AC CAPACITOR SINGLE-ENDED SINGLE-ENDED DIFFERENTIAL WEAK BIAS
INPUT TYPE HYSTERESIS,
R68/R67 BYPASS, SELECT, TERM., TERM., (1.3V)
R68[5]
R68[4], S4(1) R68[3] R68[2], S1(2) R68[1], S2(2) R68[0], S3(3)
Differential,
0x00 ext. DC-coupled, 0 0 0 0 0 0
ext. term.
Differential,
0x01 ext. AC-coupled, 0 0 0 0 0 1
ext. term.
Differential,
ext. DC-coupled,
0x02 int. 100Ω diff. 0 0 0 0 1 0
term.,
LVDS/HSDS
Differential,
ext. AC-coupled,
0x03 int. 100Ω diff. 0 0 0 0 1 1
term.,
LVDS/HSDS
Differential,
ext. DC-coupled,
0x04 0 0 0 1 0 0
int. 50Ω to GND
HCSL
Differential,
ext. AC-coupled,
0x05 0 0 0 1 0 1
int. 50Ω to GND,
HCSL

LMK5C22212AS1
Table 7-2. Reference Input Buffer Modes (continued)

INTERNAL REGISTER AND SWITCH SETTINGS
REFx_ITYPE, AC CAPACITOR SINGLE-ENDED SINGLE-ENDED DIFFERENTIAL WEAK BIAS
INPUT TYPE HYSTERESIS,
R68/R67 BYPASS, SELECT, TERM., TERM., (1.3V)
R68[5]
R68[4], S4(1) R68[3] R68[2], S1(2) R68[1], S2(2) R68[0], S3(3)
Single-ended,
ext. DC-coupled,
0x08 int. AC-coupled 0 0 1 0 0 0
70mV threshold,
LVCMOS
Single-ended,
ext. DC-coupled,
0x0C int. AC-coupled, 0 0 1 1 0 0
int. 50Ω to GND,
70mV threshold
Single-ended,
ext. DC-coupled,
0x18 int. DC-coupled 0 1 1 0 0 0
ADVANCE INFORMATION
150mV hysteresis,
LVCMOS
Single-ended,
ext. DC-coupled,
0x28 int. AC-coupled 1 0 1 0 0 0
210mV hysteresis,
LVCMOS
Single-ended,
ext. DC-coupled,
0x38 int. DC-coupled 1 1 1 0 0 0
0mV hysteresis,
LVCMOS
(1) S4: 0 = Differential input amplitude detector can be used for all input types except LVCMOS or single-ended.
(2) S1, S2: 0 = External termination is assumed.
(3) S3: 0 = External input bias or DC-coupling is assumed.
7.3.3 Clock Input Interfacing and Termination
Figure 7-9 through Figure 7-13 show the recommended input interfacing and termination circuits. Unused clock
inputs can be left floating or pulled down.
LVCMOS Rs
LVCMOS Driver XO
LMK Device
LVCMOS Rs
LVCMOS Driver INx_P
INx_N
Figure 7-9. Single-Ended LVCMOS (1.8V, 2.5V, 3.3V) to Reference (INx_P) or XO Input (XO)
Vcco
LVPECL Driver LVPECL LMK Device
50 50
Vcco – 2V
Figure 7-10. DC-Coupled LVPECL to Reference (INx)

LMK5C22212AS1
LMK Device
LVDS Driver LVDS 100Ω
Figure 7-11. DC-Coupled HSDS/LVDS to Reference (INx)
CML
Driver
CML LMK Device
ADVANCE INFORMATION
Figure 7-12. DC-Coupled CML (Source Terminated) to Reference (INx)
50Ω
HCSL LMK Device

Driver HCSL
50Ω
Figure 7-13. HCSL (Load Terminated) to Reference (INx)
Driver RB ( )
LMK Device
Differential
LVDS
CML*
open
open Driver 100
LVPECL 120
HCSL 50 Internal input biasing
RB RB
pull-ups
*CML driver requires 50
Figure 7-14. AC-Coupled Differential to Reference (INx)
7.3.4 Reference Input Mux Selection

For the DPLL block, the reference input mux selection can be done automatically using an internal state machine
with a configurable input priority scheme, or manually through software register control or hardware pin control.
The input mux can select IN0 or IN1 for LMK5C22212AS1 . The priority for all inputs can be assigned through
registers. The priority ranges from 0 to 7, where 0 = ignore (never select), 1 = first priority, 2 = second priority
and 7 = 7th priority. When inputs are configured with the same priority setting, the lower enumeration INx is
given first priority (IN0 → IN1). The selected input can be monitored through the status pins or register.
7.3.4.1 Automatic Input Selection
There are two automatic input selection modes that can be set by register: Auto Revertive and Auto Non-
Revertive.

LMK5C22212AS1
• Auto Revertive: In this mode, the DPLL automatically selects the valid input with the highest configured
priority. If a clock with higher priority becomes valid, the DPLL automatically switches over to that clock
immediately.
• Auto Non-Revertive: In this mode, the DPLL automatically selects the highest priority input that is valid. If a
higher priority input because valid, the DPLL does not switch over until the currently selected input becomes
invalid.
7.3.4.2 Manual Input Selection
There are two manual input selection modes that can be set by a register: Manual with Auto-Fallback and
Manual with Auto-Holdover. In either manual mode, the input selection can be done through register control
(Register DPLLx_MAN_REF_SEL) or hardware pin control (GPIOs).
• Manual with Auto-Fallback: In this mode, the manually selected reference is the active reference until the
reference becomes invalid. If the reference becomes invalid, the DPLL automatically falls back to the highest
priority input that is valid or qualified. If no prioritized inputs are valid, the DPLL enters holdover mode
ADVANCE INFORMATION
(if tuning word history is valid) or free-run mode. The DPLL exits holdover mode when the selected input
becomes valid.
• Manual with Auto-Holdover: In this mode, the manually selected reference is the active reference until the
reference becomes invalid. If the reference becomes invalid, the DPLL automatically enters holdover mode
(if tuning word history is valid) or free-run mode. The DPLL exits holdover mode when the selected input
becomes valid.
The reference input selection flowchart is shown in Figure 7-15.
See Device POR

Configuration Sequence and
PLL Initialization Sequence
DPLL Reference Input

Selection
Yes: Auto
No Input Select Mode No Input Select Mode Revertive
= Manual? = Auto?
Yes: With Yes: Auto LOR on

Auto-Fallback Non-Revertive Selected Input, or No
Higher Priority Input
Valid?
Yes
Loss of Ref (LOR) on No
Selected Input?
Yes Switch to Highest

Priority Reference
Figure 7-15. DPLL Reference Input Selection Flowchart
7.3.5 Hitless Switching

The DPLL supports hitless switching through TI's proprietary phase cancellation scheme with an optional phase
slew control scheme. When hitless switching is disabled, a phase hit equal to the phase offset between the two
inputs is propagated to the output at a rate determined by the filtering of the DPLL bandwidth.
7.3.5.1 Hitless Switching With Phase Cancellation
Typically phase cancellation is enabled during hitless switching to prevent a phase transient (phase hit) from
immediately propagating to the outputs when switching between two frequency-locked reference inputs with a

LMK5C22212AS1
fixed phase offset. The phase cancellation persists indefinitely in the use case scenario when phase slew is not
enabled commonly referred to as phase buildout. The inputs are frequency-locked when the inputs have the
same exact frequency (0-ppm offset), or have frequencies that are integer-related and can each be divided to a
common frequency by integers. The hitless switching specifications (tHITLESS and fHITLESS) are valid for reference
inputs with no wander. In the case where two inputs are switched but are not frequency-locked, the output
smoothly transitions to the new frequency with reduced transient.
7.3.5.2 Hitless Switching With Phase Slew Control
Enabling Phase Slew Control constrains the output phase transient or phase hit during hitless switching and
holdover exit. Users can select DPLLx_PHS1_EN to enable Phase Slew Control to follow the step limits set
in DPLLx_PHS1_THRESH and DPLLx_PHS1_TIMER. When transitioning slowly is desired while tracking the
new input phase, enabling phase slew control removes the phase cancellation or phase build out based on the
programmed timer value and step limits. Similarly when the DPLL switches from APLL-only mode or holdover
mode to DPLL Lock Acquisition mode, or hitless switching with two inputs are not frequency-locked the phase
ADVANCE INFORMATION
slew limits are then applied. When both Phase Cancellation function and Phase Slew Control function are
disabled, a phase hit equal to the phase offset between XO and selected input or between the two inputs at the
moment of switching are then propagated to the output at a rate determined by the DPLL loop bandwidth. In the
case where two inputs are switched but are not frequency-locked Phase Slew Control function can verify that the
output smoothly transitions to the new frequency as the rate the defined by the step limits.
7.3.6 Gapped Clock Support on Reference Inputs
The DPLL supports locking to an input clock that has missing periods and is referred to as a gapped clock.
Gapping severely increases the jitter of a clock, so the DPLL provides the high input jitter tolerance and low loop
bandwidth necessary to generate a low-jitter periodic output clock. The resulting output is a periodic non-gapped
clock with an average frequency of the input with the missing cycles. The gapped clock width can not be longer
than the reference clock period after the R divider (RINx / fINx). The reference input monitors must be configured
to avoid any flags due to the worst-case clock gapping scenario to achieve and maintain lock. Reference
switchover between two gapped clock inputs can violate the hitless switching specification if the switch occurs
during a gap in either input clock.
7.3.7 Input Clock and PLL Monitoring, Status, and Interrupts
The following section describes the input clock and PLL monitoring, status, and interrupt features. The reference
input frequency detector and phase valid detector can not be used at the same time on a single input.

LMK5C22212AS1
XO
Status Bits
EN
Frequency LOS_FDET_XO LOS_FDET_XO
XO Input Monitor
Ref Inputs
IN0
: : REF
: : Mux
÷R PLLs Clock Status
INN
...
Ref Input Monitors

ADVANCE INFORMATION
EN EN
Valid / Invalid ppm Frequency
EN LOR Validation Timer
Late detect window Missing pulse INx Valid LOR_MISSCLK
Starts when LOR 0
EN
Early detect window Runt pulse DPLL LOR_FREQ
Valid time Selected
EN
Input LOR_PH
Jitter threshold Phase valid*
REFSWITCH
4 Detector Status (1 = fault)
INx Status
*Enable for 1-PPS input
Figure 7-16. Clock Monitors for Reference and XO Inputs
7.3.7.1 XO Input Monitoring

The XO input has a coarse frequency monitor to help qualify the input before the monitor is used to lock the
APLLs.
The XO frequency detector clears the LOS_FDET_XO flag when the input frequency is detected within the range
of 9 MHz to 160 MHz to cover the supported XO input frequency range. The XO frequency monitor uses a
RC-based detector and therefore can not precisely determine whether XO input clock has sufficient frequency
stability. A stable XO input verifies successful VCO calibration of APLL2 or APLL1 during the PLL start-up. When
the external XO clock has a slow or delayed start-up behavior TI recommends to force a calibration on APLL2
and APLL1 once the XO input is stable. See Slow or Delayed XO Start-Up for more information.
The XO frequency detector can be bypassed by setting the XO_FDET_BYP bit (shown as EN in Figure 7-16)
so that the XO input is always considered valid by the PLL control state machine. The user can observe the
LOS_FDET_XO status flag through the status pins and status bit. Setting XO_FDET_BYP bit bypasses the
detect, but does not reflect any change to LOS_FDET_XO status flag.
7.3.7.2 Reference Input Monitoring
Each DPLL reference clock input is independently monitored for input validation before the clock is qualified and
available for selection by the DPLL. The reference monitoring blocks include frequency, missing pulse, and runt
pulse monitors. For a 1-PPS input, the phase valid monitor is supported, while the frequency, missing pulse, and
runt pulse monitors are not supported and must be disabled. A validation timer sets the minimum time for all
enabled reference monitors to be clear of flags before an input is qualified.
The enablement and valid threshold for all reference monitors and validation timers are programmable per input.
The reference monitors and validation timers are optional to enable, but are critical to achieve reliable DPLL lock
and optimal transient performance during holdover or switchover events, and are also used to avoid selection of
an unreliable or intermittent clock input. If a given detector is not enabled, the detector does not set a flag and is
ignored. The status flag of any enabled detector can be observed through the status pins for any reference input

LMK5C22212AS1
(selected or not selected). The status flags of the enabled detectors can also be read through the status bits for
the selected input of the DPLL.
7.3.7.2.1 Reference Validation Timer
The validation timer sets the amount of time required for each reference to be clear of flags from all enabled
input monitors before the reference is qualified and valid for selection. The validation timer and enable settings
are programmable.
7.3.7.2.2 Frequency Monitoring
The precision frequency detector measures the frequency offset or error (in ppm) of all input clocks relative
to the XO input frequency, which is considered as the 0-ppm reference clock for frequency comparison.
The valid and invalid ppm frequency thresholds are configurable through the registers. The monitor clears
the REFx_FDET_STATUS flag when the relative input frequency error is less than the valid ppm threshold.
Otherwise, the monitor sets the REFx_FDET_STATUS flag when the relative input frequency error is greater
ADVANCE INFORMATION
than the invalid ppm threshold. The ppm delta between the valid and invalid thresholds provides hysteresis
to prevent the REFx_FDET_STATUS flag from toggling when the input frequency offset is crossing these
thresholds.
A measurement accuracy (ppm) and averaging factor are used in computing the frequency detector register
settings. A higher measurement accuracy (smaller ppm) or higher averaging factor increases the measurement
delay to set or clear the flag, which allows more time for the input frequency to settle, and can also provide better
measurement resolution for an input with high drift or wander. Note that higher averaging reduces the maximum
frequency ppm thresholds that can be configured.
7.3.7.2.3 Missing Pulse Monitor (Late Detect)
The missing pulse monitor uses a window detector to validate input clock pulses that arrive within the nominal
clock period plus a programmable late window threshold (TLATE). When an input pulse arrives before TLATE, the
pulse is considered valid and the missing pulse flag is cleared if set. When an input pulse does not arrive before
TLATE (due to a missing or late pulse), the missing pulse flag is set to disqualify the input.
Typically, TLATE must be set higher than the longest clock period input (including cycle-to-cycle jitter), or higher
than the gap width for a gapped clock. The missing pulse monitor can act as a coarse frequency detector with
faster detection than the ppm frequency detector. The missing pulse monitor is supported for input frequencies
between 2kHz and fVCO/12 and must be disabled when outside this range.
The missing pulse and runt pulse monitors operate from the same window detector block for each reference
input. The status flags for both these monitors are combined by logic-OR gate and can be observed through
status pin. The window detector flag for a reference can also be observed through the corresponding
REFx_MISSCLK_STATUS bit.
7.3.7.2.4 Runt Pulse Monitor (Early Detect)
The runt pulse monitor uses a window detector to validate input clock pulses that arrive within the nominal clock
period minus a programmable early window threshold (TEARLY). When an input pulse arrives after TEARLY, the
pulse is considered valid and the runt pulse flag is cleared. When an early or runt input pulse arrives before
TEARLY, the monitor sets the flag immediately to disqualify the input.
Typically, TEARLY must be set lower than the shortest clock period of the input (including cycle-to-cycle jitter).
The early pulse monitor can act as a coarse frequency detector with faster detection than the ppm frequency
detector. The early pulse monitor is supported for input frequencies between 2 kHz and fVCO/12 and must be
disabled when outside of this range.
Users must enable missing clock detect to use early clock detect. Early clock detect can not be enabled alone.

LMK5C22212AS1
Ideal Reference Period Ideal Edge
Ideal Reference Input

(rising-edge triggered)
Early Pulse (Input disqualified at this input rising edge)
Example A: Input with

Early (Runt) Pulse
Late Pulse (Input disqualified after TLATE)
Example B: Input with

Missing (Late) Pulse
ADVANCE INFORMATION
Gapped Clock (To avoid disqualifying input at the

missing clock cycle, set TLATE window > Gap width)
Example C: Input with

Gap width
Missing (Gapped) Clock
Valid
Invalid
Valid Windows
Valid Window size can be relaxed by increasing the Window size. Early Window
(TEARLY)
Window Step Size = 2 / fVCO Late Window
(TLATE)
Minimum Valid Window

is ±3 × (2 / fVCO)
Figure 7-17. Early and Late Window Detector Examples
7.3.7.2.5 Phase Valid Monitor for 1-PPS Inputs

The phase valid monitor is designed specifically for 1-PPS input validation because the frequency and window
detectors do not support this low frequency. The phase valid monitor uses a window detector to validate 1-PPS
input pulses that arrive within the nominal clock period (TIN) plus a programmable jitter threshold (TJIT). When
the input pulse arrives within the counter window (TV), the pulse is considered valid and the phase valid flag
is cleared. When the input pulse does not arrive before TV (due to a missing or late pulse), the flag is set
immediately to disqualify the input. TJIT must be set higher than the worst-case input cycle-to-cycle jitter.
The phase valid register settings also are valid for 1-PPS ppm error threshold detect. Notice the TJIT also
impacts the worst case ppm error allowed. For example: High_Jitter_Freq = 1/(TIN - TJIT), then Max input
allowable ppm error = (High_Jitter_Freq - Expected_Freq) / Expected_Freq × 1e6.
Ideal Edge Counter resets at Counter time-out (TIN¶¶ > TV).
(TIN < TV ) valid edge (TIN¶ < TV) Input is disqualified here
Ideal Input Period Late Pulse

(Large peak jitter)
TIN TIN¶ TIN¶¶
Example: TIN¶ > TIN TIN¶¶ >> TIN
1-PPS Input
TJIT
Valid Counter (TV) TV

TV = TIN + TJIT TV
Figure 7-18. 1-PPS Input Window Detector Example

LMK5C22212AS1
7.3.7.3 PLL Lock Detectors

The loss-of-lock (LOL) status is available for each APLL and DPLL. The APLLs are monitored for loss-of-
frequency lock only. The DPLL can be monitored for both loss-of-frequency lock (LOFL) and loss-of-phase
lock (LOPL). The DPLL lock threshold and loss-of-lock threshold are programmable for both LOPL and LOFL
detectors. If the BAW APLL loss-of-frequency lock is selected, then paired DPLL is monitored for LOPL only. The
paired DPLL must be enabled for the digital monitoring of the BAW APLL VCBO lock detect.
The DPLL frequency lock detector clears the LOFL flag when the DPLL frequency error relative to the selected
reference input is less than the lock ppm threshold. Otherwise, the lock detector sets the LOFL flag when the
DPLL frequency error is greater than the unlock ppm threshold. The ppm delta between the lock and unlock
thresholds provides hysteresis to prevent the LOFL flag from toggling when the DPLL frequency error is crossing
these thresholds.
The BAW APLL frequency digital lock detector clears the LOFL flag when the VCBO frequency error relative
to the XO reference input is less than the lock ppm threshold. Otherwise, the lock detector sets the LOFL
ADVANCE INFORMATION
flag when the VCBO frequency error is greater than the unlock ppm threshold. Make sure to take the ppm
frequency tolerance of the XO input reference into account when setting the VCBO frequency lock and unlock
thresholds. The ppm delta between the lock and unlock thresholds provides hysteresis to prevent the LOFL flag
from toggling when the VCBO frequency error is crossing these thresholds.
A measurement accuracy (ppm) and averaging factor are used in computing the frequency lock detector register
settings. A higher measurement accuracy (smaller ppm) or higher averaging factor increases the measurement
delay to set or clear the LOFL flag. Higher averaging can be useful when locking to an input with high wander
or when the PLL is configured with a narrow loop bandwidth. Note that higher averaging reduces the maximum
frequency ppm thresholds that can be configured.
The DPLL phase lock detector clears the LOPL flag when the phase error of the DPLL is less than the phase
lock threshold. Otherwise, the lock detector sets the LOPL flag when the phase error is greater than the phase
unlock threshold.
Users can observe the APLL and DPLL lock detector flags through the status pins and the status bits.
PLLs Status Bits
APLL2 Lock APLL2
DPLL Frequency Lock Detectors LOL_PLL
Detector
Lock Unlock
LOFL LOL_PLL
APLL
APLL1 Digital Lock
Thresh Thresh Detector
(ppm) (ppm) APLL1 DLD
XO Lock Unlock
APLL fVCO
fTDC DPLL
Thresh Thresh PLLs Status
(ns) (ns)
LOFL_DPLL
DPLL Phase Lock
Detector LOPL LOPL_DPLL
DPLL
Lock Unlock HIST
Tuning Word History History
Update HLDOVR
DPLLx_HIST_TIMER
Holdover
Thresh Thresh Active
(ns) (ns)
EN Free-run
Tuning Word
Figure 7-19. PLL Lock Detectors and History Monitor

LMK5C22212AS1
7.3.7.4 Tuning Word History

The DPLL domain has a tuning word history monitor block that determines the initial output frequency accuracy
upon entry into holdover. When in holdover, the stability of the reference clock (on XO input) determines the
long-term stability and accuracy of the output frequency. The tuning word can be updated from one of three
sources depending on the DPLL operating mode:
1. Locked Mode: from the output of the digital loop filter when locked
2. Holdover Mode: from the final output of the history monitor
3. Free Run Mode: from the free-run tuning word register (user defined)
When the history monitor is enabled and the DPLL is locked, the device averages the reference input frequency
by accumulating history from the digital loop filter output during a programmable averaging time (TAVG) set by
DPLLx_HIST_TIMER. When a valid reference input becomes invalid, the final tuning word value is stored to
determine the initial holdover frequency accuracy. Generally, a longer TAVG time produces a more accurate initial
holdover frequency.
ADVANCE INFORMATION
If the input reference clock fails and becomes invalid, the history data can be corrupted if the tuning word
continues to update before the fail state is indicated by one of the reference input validation monitors. To avoid
this scenario, any in progress accumulation is ignored and the recent history data is ignored. The most recent
collected average data is discarded such that the actual history used is greater than TAVG but less than 2 × TAVG.
The tuning word history is initially cleared after a device hard reset or soft reset. After the DPLL locks to a new
reference, the history monitor waits for the first TAVG timer to expire before storing the first tuning word value
and begins to accumulate history. The history monitor does not clear the previous history value during reference
switchover or holdover exit. The history can be manually cleared or reset by toggling the history enable bit
(DPLLx_HIST_EN = 1 → 0 → 1), if needed.
Ref Valid Initial start of history Ref Lost Ref Valid
LOR 0 accumulation when LOPL 0 LOR 1 LOR 0
History History Valid: History Valid:

No Valid History History Valid History Valid
Reset TAVG(2) in Use by Holdover TAVG(2) Stored from Holdover
TAVG(0) TAVG(1) TAVG(2) TAVG(3) TAVG(4) TAVG(5) TAVG(6) TAVG(7)
TIGN
Initial holdover
frequency determined Hitless
History Accumulating switch History Accumulating
by averaged history.
Time
Free Run Lock Acq. Locked Holdover Locked

LOFL = 1, LOPL = 1 LOFL = 0, LOPL = 0 LOPL 1 LOFL = 0, LOPL = 0
Figure 7-20. Tuning Word History Windows
When no tuning word history exists, the free-run tuning word value (DPLLx_FREE_RUN) is used and determines
the initial holdover output frequency accuracy.
7.3.7.5 Status Outputs
The GPIO pins can be configured to output various status signals and interrupt flags for device diagnostic and
debug purposes. The status signal, output driver type, and output polarity settings are programmable.
7.3.7.6 Interrupt
Any GPIO pin can be configured as a device interrupt output pin. The interrupt logic configuration is set through
registers. When the interrupt logic is enabled, the interrupt output can be triggered from any combination of
interrupt status indicators, including LOS for the XO, LOR for the selected DPLL input, LOL for APLL1, APLL2,
and the DPLLs, and holdover and switchover events for the DPLLs. When the interrupt polarity is set high, a
rising edge on the live status bit asserts the interrupt flag (sticky bit). Otherwise, when the polarity is set low, a
falling edge on the live status bit asserts the interrupt flag. Any individual interrupt flag can be masked so the
flag does not trigger the interrupt output. The unmasked interrupt flags are combined by the AND/OR gate to
generate the interrupt output, which can be selected on either status pin.

LMK5C22212AS1
When a system host detects an interrupt from the device, the host can read the interrupt flag or sticky registers
to identify which bits are asserted to resolve the fault conditions in the system. After the system faults have been
resolved, the host can clear the interrupt output by writing 1 to the self-clearing INT_CLR field.
INTR INTR INTR INTR

Status Bits Enable Polarity Flag* Mask
LOS_FDET_XO F
LOS_XO F
Status Pins
LOL_PLL F
GPIOx_SEL
LOFL_DPLL F
LOPL_DPLL F
OR INTR
HIST F Gate 0xE Polarity
Type
ADVANCE INFORMATION
HLDOVR F
GPIO GPIOx
Select
REFSWITCH F Other
status
LOR_MISSCLK F
signals
LOR_FREQ F
Live Status Registers Sticky Status Registers

0x0021 to 0x0024 0x029 to 0x02C
*Write 1 to self clearing bit in R49[0]
to clear INTR flag bits
Figure 7-21. Status and Interrupt
7.3.8 PLL Relationships

Figure 7-22 shows the PLL architecture implemented in the LMK5C22212AS1 . The PLLs can be configured in
the different PLL modes described in Section 7.2.1.
When a DPLL combines with an APLL in a feedback loop, the APLL must use the fixed 40-bit denominator.
When the APLL works in an independent loop, like APLL1 in Figure 7-5 or APLLs in Figure 7-6, TI recommends
selecting the 24-bit programmable denominator.
XO ×1, ×2
DPLL APLL
IN0 ÷R fTDC fPD VCO
: : ÷R fVCO
INN ÷R TDC DLF 5-bit LF
PFD
16-bit To post-divider
and
Output Muxes
÷FB ÷N
38-bit
DCO option
DCO
FINC/FDEC
Figure 7-22. PLL Architecture

LMK5C22212AS1
7.3.8.1 PLL Frequency Relationships

The following equations provide the APLL and DLL frequency relationships required to achieve closed-loop
operation. The TICS Pro programming software can be used to generate valid divider settings based on the
desired frequency plan.
Note that any divider in the following equations refers to the actual divide value (or range) and not the
programmable register value.
When DPLL operation is enabled, the calculated DPLL frequency and APLL frequency must be nominally the
same. The DPLL adjustments to the paired APLL N divider 40-bit fixed denominator tracks the selected input
reference source to synthesize the actual clock output desired frequency and phase.
When the APLL operates independently from the paired DPLL, TI recommends the programmable 24-bit
denominator for hybrid synchronization or cascading between frequency domains to maintain 0-ppm frequency
error without DPLL control. In this scenario, the APLL tracks the cascade feedback divider reference from
ADVANCE INFORMATION
another APLL output.

When using ZDM for a PLL, the clock output divider must be accounted for in the VCO frequency calculations.
7.3.8.1.1 APLL Phase Frequency Detector (PFD) and Charge Pump

Equation 1 calculates the phase detector frequency which is used to find the VCO frequency in the APLL VCO
Frequency calculation in Equation 2.
fPD = fXO × DXO / RXO (1)
where
• fPD = APLL phase detector frequency
• fXO: APLL reference is XO frequency or cascaded reference frequency from another APLL.
• DXO: XO input doubler (1 = disabled, 2 = enabled)
• RXO: APLL XO Input R divider value (1 to 32)
APLL2 or APLL1 has programmable charge pump settings from 0mA to 5.8mA in 0.4mA steps. Best
performance from APLL1 is achieved with a charge pump currents of 0.8mA or higher.
7.3.8.1.2 APLL VCO Frequency
The APLL phase locks the APLL VCO to the APLL reference using the applied APLL numerator. Use Equation 2
to calculate the VCO frequency.
fVCO = fPD × (INTAPLL + NUMAPLL / DENAPLL) (2)

• fVCO: VCO frequency
• fPD = APLL phase detector frequency
• INTAPLL: APLL N divider integer value (12 bits, 1 to 212 – 1)
• NUMAPLL: APLL N divider numerator value (40 bits, 0 to 240 – 1, or 24 bits, 0 to 224 – 1 )
• DENAPLL: APLL N divider denominator value (fixed 240, or programmable 1 to 224)
– Avoid integer boundary spurs by keeping the NUM/DEN ratio away from an integer value.
– 0.125 < NUMAPLL / DENAPLL < 0.875 (In DPLL Mode, avoid 0.5)

LMK5C22212AS1
7.3.8.1.3 DPLL TDC Frequency

Equation 3 calculates the TDC frequency which is used to find the VCO frequency in the DPLL VCO Frequency
calculation in Equation 5. Two different TDC frequencies are possible for each DPLL to enable switching
between non-integer related frequencies while keeping the TDC rate high.
fTDC = fINx × DINx/ RINx (3)
fTDC = fINy × DINy / RINy (4)
where
• fTDC: DPLL TDC input frequency (see Equation 3)
• fINx or fINy: INx or INy input frequency or cascaded reference frequency from another APLL.
• RINx or RINy: INx or INy R divider value (16 bits, 1 to 216 – 1)
• DINx or DINy: INx or INy input doubler (2 = disabled and 1 = enabled)
ADVANCE INFORMATION
7.3.8.1.4 DPLL VCO Frequency
The DPLL phase locks the APLL VCO to the DPLL VCO frequency by updating the actual APLL numerator
value. Use Equation 5 to calculate the VCO frequency. Each DPLL can have two different values for DPLL N to
allow locking to the same VCO frequency using two different TDC frequencies. DPLLx_REF#_FB_SEL register
selects which DPLL N value is used.
fVCO = fTDC × (INTDPLL + NUMDPLL/ DENDPLL) (5)
where
• INTDPLL: DPLL FB divider integer value (33 bits, 1 to 233 – 1)
• NUMDPLL: DPLL FB divider numerator value (40 bits, 0 to 240 – 1)
• DENDPLL: DPLL FB divider denominator value (40 bits, 1 to 240)
• N: INTDPLL + NUMDPLL/ DENDPLL
7.3.8.1.5 Clock Output Frequency
Each APLL has a post divider which provides a VCO post divider frequency calculated in Equation 6 or Equation
7. The final output frequency is calculated by dividing from the VCO post divider frequency and the output divide
as calculated in Equation 8. For each output, the output frequency depends on the selected APLL clock source
and output divider value.
APLL2 selected: fPOST_DIV = fVCO2 / PnAPLL2 (6)
APLL1 selected: fPOST_DIV = fVCO1 / PnAPLL1 (7)
OUT[0:11]: fOUTx = fPOST_DIV / ODOUTx (8)
where
• fPOST_DIV: Output mux source frequency (APLL2 or APLL1 post-divider clock)
• PnAPLL2: APLL2 primary "P1" post-divide value (2 to 13) or secondary "P2" post-divide value (2 to 3)
• PnAPLL1: APLL1 post-divide value (1 to 8)
• fOUTx: Output clock frequency (x = 0 to 15)
• ODOUTx: OUTx output bypass or divider value. All outputs have a 12-bit divider with values 1 to (212 - 1). All
outputs except OUT2 and OUT3 have the option to follow the 12-bit divider with a 20-bit SYSREF divider that
can be used to produce 1PPS or other frequencies below 1Hz when the SYSREF output is set for continuous
output.
7.3.8.2 Analog PLLs (APLL1, APLL2)
Each APLL has a 40-bit fractional-N divider to support high-resolution frequency synthesis and very low phase
noise and jitter. Each APLL also has the ability to tune the VCO frequency through sigma-delta modulator (SDM)

LMK5C22212AS1
control in DPLL mode. In cascaded mode, each APLL has the ability to lock the VCO frequency to another VCO
frequency.
In free-run mode, the BAW APLL uses the XO input as an initial reference clock to the VCBO. The PFD of
the BAW APLL compares the fractional-N divided clock with the reference clock and generates a control signal.
The control signal is filtered by the BAW APLL loop filter to generate a control voltage to set the VCBO output
frequency. The SDM modulates the N divider ratio to get the desired fractional ratio between the PFD input and
the VCBO output. The other conventional APLL with the LC VCO operates similar to the VCBO. User can select
the reference from either the VCBO clock or the XO clock.
In DPLL mode, the APLL fractional SDM is controlled by the DPLL loop to pull the VCO frequency into lock
with the DPLL reference input. For example the APLL Cascaded With DPLLs Disabled Example shows the
respective APLL2 deriving the reference from VCO1, then VCO2 is effectively locked to the DPLL1 reference
input, assuming there is no synthesis error introduced by the fractional N divide ratio of APLL2.
ADVANCE INFORMATION
7.3.8.3 APLL Reference Paths

7.3.8.3.1 APLL XO Doubler
The APLL XO doubler can be enabled to double the PFD frequency for the APLL reference. Enabling the XO
doubler adds minimal noise and can be useful to increase the PFD frequency to optimize phase noise, jitter, and
fractional spurs. The flat portion of the APLL phase noise can improve when the PFD frequency is increased.
7.3.8.3.2 APLL XO Reference (R) Divider
Each APLL has a 5-b XO reference (R) divider that can be used to meet the maximum APLL PFD frequency
specification. The divider can also be used to verify the APLL fractional-N divide ratio (NUM/DEN) is between
0.125 to 0.875 (avoid 0.5), which is recommended to support the DPLL frequency tuning range. Otherwise, the R
divider can be bypassed (divide by 1).
7.3.8.4 APLL Feedback Divider Paths
The VCO output of each APLL is fed back to the PFD block through the fractional feedback (N) divider. The
VCO output is also fed back to the DPLL feedback path in DPLL mode. For hybrid synchronization or cascaded
frequency domain architectures each VCO output also can source to the DPLL input reference selection muxes
or as an XO input for other APLLs or through fixed feedback dividers.
7.3.8.4.1 APLL N Divider With Sigma-Delta Modulator (SDM)
The APLL fractional N divider includes a 12-b integer portion (INT), a 40-b numerator portion (NUM), a fixed
40-b or a programmable 24-b denominator portion (DEN), and an SDM. The INT and NUM are programmable.
When an APLL works with a DPLL in a loop, the APLL uses a fixed 40-bit denominator for very high frequency
resolution on the VCO clock. When the APLL works in an independent loop (the paired DPLL is disabled), TI
recommends a 24-bit programmable denominator. The total APLL N divider value is: N = INT + NUM / 240 or INT
+ NUM / 224 .
In APLL free-run mode, the PFD frequency and total N divider for the APLL determine the VCO frequency, which
can be computed with 24-b denominator by Equation 2.
7.3.8.5 APLL Loop Filters (LF1, LF2)
The APLL loop filter components can be programmed to optimize the APLL LBW depending on the phase noise
of the XO input. The BAW APLL supports a programmable LBW from 100Hz to 10kHz (typical range) and the
conventional LC APLL supports a programmable LBW from 100kHz to 1MHz (typical range). Figure 7-23 shows
the APLL loop filter structure between the PFD/charge pump output and VCO control input.

LMK5C22212AS1
Programmable VCO
Loop Filter R3 R4
PFD /
Charge Pump
C1 R2 C3 C4
LF
C2
ADVANCE INFORMATION
Figure 7-23. Loop Filter Structure of Each APLL
The BAW APLL is configured with a narrow LBW by default in TICSPRO and the ROM pages. As a result, the
low jitter VCBO dominates the clock output phase noise in the carrier offset range from 8kHz to around 400kHz.
Using the default APLL loop filter settings listed in Table 7-3, the LBW for each APLL is summarized in Table 7-4.
Table 7-3. Default APLL Charge Pump and Loop Filter Components
DEFAULT VALUES FOR DEFAULT VALUES FOR
COMPONENT LOCATION TYPE
APLL2 APLL1
Charge pump Internal Programmable 3.4mA 2.0mA
C1 Internal Fixed 100pF 100pF
C2 External(1) Fixed 100nF 470nF
C3 Internal Programmable 70pF 70pF
C4 Internal Programmable 70pF 70pF
R2 Internal Programmable 0.183kΩ 0.301kΩ
(1) The external capacitor is connected to the LFx pin of the corresponding APLLx.
Table 7-4. Default APLL LBW (PFD = 96MHz)
APLL VCO RANGE [MHz] LBW [kHz](1)
2 5600 to 5950 152.8 to 137.8
1 2500 4.9
(1) The APLL LBW range corresponds to the VCO range,

respectively.
7.3.8.6 APLL Voltage-Controlled Oscillators (VCO1, VCO2)
Each APLL contains a fully-integrated VCO, which takes the voltage from the loop filter and converts the voltage
into a frequency.
VCO1 uses proprietary BAW resonator technology with a very high quality factor to deliver the lowest phase jitter
and has a tuning range of 2457.6MHz ± 100ppm. VCO2 uses a high-performance LC VCO with a wider tuning
range of 5595MHz to 5950MHz to cover other additional unrelated clock frequencies, if needed.
7.3.8.6.1 VCO Calibration
Each APLL VCO must be calibrated to verify that the PLL can achieve lock and deliver optimal phase
noise performance. VCO calibration establishes an optimal operating point within the VCO tuning range. VCO
calibration is executed automatically during initial PLL start-up after device power-on, hard-reset, or soft-reset
when the XO input is detected by the input monitor. To provide successful calibration and APLL lock, the XO

LMK5C22212AS1
clock must be stable in amplitude and frequency before the start of calibration; otherwise, the calibration can fail
and prevent PLL lock and output clock start-up. Before VCO calibration and APLL lock, the output drivers are
typically held in the mute state (configurable per output) to prevent spurious output clocks.
A VCO calibration can be triggered manually for a single APLL by toggling a PLL enable cycle (APLLx_EN bit
= 0 → 1) through host programming. This can be needed after the APLL N divider value (VCO frequency) is
changed dynamically through programming.
7.3.8.7 APLL VCO Clock Distribution Paths
Each APLL VCO post-divider supports an independently programmable divider.
APLL1 (BAW APLL) has one VCO post-divider paired with an optional divide by 2. The VCO1 post-divider is
comprised of a programmable divide by 8 followed by an optional divide by 2. The APLL1 post-divider clock div8
(÷2 to ÷8) or div8 and div2 (÷10, ÷12,÷14, ÷16) can be distributed to all 4 output banks in LMK5C22212AS1 .
If the system use case requires sourcing multiple frequencies from APLL1 that can not be supported from a
ADVANCE INFORMATION
single post-divider value, then bypass the VCO1 post-divider by setting VCO1 post-divider = 1 and program the
individual channel dividers to obtain the desired output frequencies.
APLL2 (conventional APLL) has one VCO post-divider clock (P1: ÷2 to ÷13) available for distribution to all
outputs.
7.3.8.8 DPLL Reference (R) Divider Paths
Each reference input clock has a dedicated 16-b reference divider to the DPLL TDC block. The R divider output
of the selected reference sets the TDC input frequency. To support hitless switching between inputs with different
frequencies, the R dividers can be used to divide the clocks to a single common frequency to the DPLL TDC
input.
7.3.8.9 DPLL Time-to-Digital Converter (TDC)
The TDC input compares the phase of the R divider clock of the selected reference input and the DPLL feedback
divider clock from VCO. The TDC output generates a digital correction word corresponding to the phase error
which is processed by the DPLL loop filter.
7.3.8.10 DPLL Loop Filter (DLF)
The DPLL supports a programmable loop bandwidth from 10 mHz to 4 kHz and can achieve jitter peaking below
0.1 dB (typical). The low-pass jitter transfer characteristic of the DPLL attenuates the reference input noise with
up to 60-dB/decade roll-off above the loop bandwidth.
The DPLL loop filter output controls the fractional numerator of APLL to steer the VCO frequency into lock with
the selected DPLL reference input.
7.3.8.11 DPLL Feedback (FB) Divider Path
The DPLL feedback path has a programmable prescaler (33 bits, 1 to 233 – 1) and a fractional feedback
(FB) divider. The programmable DPLL FB divider includes a 33-b integer portion (INT), 40-b numerator portion
(NUM), and 40-b denominator portion (DEN). The total DPLL FB divider value is: FBDPLL = INT + NUM / DEN.
In DPLL mode, the TDC frequency and total DPLL feedback divider and prescalers determine the VCO
frequency. Use Equation 5 to calculate the VCO frequency.
7.3.9 Output Clock Distribution
The output clock distribution blocks include five output muxes, eight output dividers, and twelve programmable
differential output drivers in the LMK5C22212AS1 .
The output dividers support output synchronization (SYNC) to allow phase synchronization between two or
more output channels. OUT0 and OUT10 have an optional internal ZDM synchronization feature to support
deterministic input-to-output phase alignment (typically for 1PPS clocks) with programmable offset. See Section
7.3.19.

LMK5C22212AS1
7.3.10 Output Source Muxes

The LMK5C22212AS1 employs 5 output source multiplexers or muxes to distribute frequency sources to the
respective output banks. OUT0 and OUT1 each have a separate 4:1 mux to individually select a source. OUT2
and OUT3 output channels share one 2:1 mux. The output bank OUT4 to OUT7 also share one 2:1 mux and a
third 2:1 mux is shared across the output bank OUT8 to OUT11.
The 4:1 MUX on OUT0 and OUT1 are the most flexible providing selection among APLL1 post divider, APLL2
post divider, buffered XO or reference input as a frequency source. The 2:1 muxes feeding the OUT2 and OUT3
bank or OUT4 to OUT7 bank or OUT8 to OUT11 bank can each select a frequency source from the APLL1 post
divider or the APLL2 post divider.
Table 7-5 lists the available options for the output source mux.
Table 7-5. Output Source Mux Options
OUTPUT SOURCE MUX OPTION OUTPUTS WITH OPTION DESCRIPTION
ADVANCE INFORMATION
Output channel mux is sourced from the
reference input selected by R48[4:0] (0x1 for
REFx OUT0 to OUT1
REF0, 0x2 for REF1) when R78[5] is set to
enable the reference path to OUT0_1.
Output channel mux is sourced from the XO
XO OUT0 to OUT1
input.
APLL1 OUT0 to OUT11
APLL1 post-divider output.
APLL2 OUT0 to OUT11
APLL2 post-divider output.
7.3.11 Output Channel Muxes

After the output source mux, each output channel is sourced from the output channel mux. Table 7-6 lists the
available options for the output channel mux.
Table 7-6. Output Channel Mux Options
OUTPUT CHANNEL MUX OPTION DESCRIPTION
Output clock is sourced directly from the APLL post-divider; the

Bypass
output channel divider is bypassed.
CHDIV Output clock is sourced from the output channel divider.
CH / 2 Output clock is sourced from a divide by 2 channel.
SYSREF Output clock is sourced from the SYSREF divider.
SYSREF + ADLY Output clock is sourced from the SYSREF divider with analog delay.
Output clock is static: OUTP is LOW and OUTN is HIGH.

Note: This state is different than the output enable bit (OUTx_EN) .
Static DC
When the output is disabled (OUTx_EN = 0), the output channel is
tristated (high impedance or Hi-Z).
7.3.12 Output Dividers (OD)

There are one or more output dividers after each output source mux. Each channel in OUT[2:3] has an individual
12-bit channel divider. The OUT[4:5], OUT[6:7], OUT[8:9], OUT[10:11] channels each have an individual 12-bit
output divider cascaded with an optional 20-bit SYSREF divider. The output dividers are used to generate the
final clock output frequency from the source selected by the output mux.
The OUT0 or OUT1 channel combines a 12-bit output channel divider (CD) and a 20-bit SYSREF divider to
support output frequencies from 1Hz (1PPS) to 1250MHz. From VCO to output, the total divide value is the
product of the PLL post-divider (P), output channel divider (CD)and SYSREF divider (SD) values (P × CD × SD).

LMK5C22212AS1
For example, with the BAW APLL post-divider bypassed each 12-bit channel divider (CD) supports output
frequencies from 100kHz to 1250MHz (or up to the maximum frequency supported by the configured output
driver type). The SYSREF divider (SD) can be cascaded down to achieve lower clock frequencies down to 1Hz
(1PPS).
Each output divider is powered from the same VDDO_x supply used for the clock output drivers. The output
divider can be powered down if not used to save power. For each output group in OUT[2:3], OUT[4:5], OUT[6:7],
OUT[8:9], OUT[10:11] the output divider is automatically powered down when both output drivers are disabled.
For the OUT0 or OUT1 channels, the output divider is automatically powered down when the output driver is
disabled.
7.3.13 Output Delay
The LMK5C22212AS1 has the ability to tune output clock phase with delay function. In each channel divider
path, there is a programmable static offset digital delay. With the SYSREF divider selected, the output clock can
ADVANCE INFORMATION
have additional programmable static offset digital delay, SYSREF digital delay and analog delay.
12-b Channel
APLL Divider and
OUTxx
MUX CHDIV static
digital delay
SYSREF/
1-PPS
SYSREF/1-PPS Pulser
20-b Divlder and SYSREF/1-PPS
Dynamic Analog OUTyy
SRDIV Dynamic
Digital Delay Delay
Figure 7-24. Programmable Static and Dynamic Output Delay
7.3.14 Clock Outputs

Each clock output (OUTx_P and OUTx_N) can be individually configured as a Differential Output driver. OUT0 or
OUT1 has the additional capability for two 1.8V or 2.65V LVCMOS Output drivers per output pair. For additional
low frequency single-ended clock outputs, GPIO1 and GPIO2 can be configured to replicate any SYSREF/1PPS
Output divider output from another differential output pair.
Each output channel has a dedicated internal LDO regulator to provide excellent PSNR and minimize jitter and
spurs induced by supply noise. For differential modes, the output clock specifications (such as output swing,
phase noise, and jitter) are not sensitive to the VDDO_x voltage because of the internal LDO regulator of the
channel.
The OUT0 and OUT1 channels (mux, divider, and drivers) are powered through a single output supply
pin (VDDO_0_1). Similarly, OUT2 and OUT3 channels are powered by VDDO_2_3, OUT4 to OUT7 by
VDDO_8_TO_11 and OUT8 to OUT11 by VDDO_8_TO_11. Each output supply pin must always be powered by
3.3V even if the respective outputs are not used.
Unused clock outputs can be disabled to save power.
7.3.14.1 Differential Output
The differential HSDS driver has programmable single-ended peak-to-peak amplitude (VOD) and common-mode
voltage (VCM) settings. The VOD ranges from 0.4V to 1V with a step size of roughly 100mV. There are three VCM
options available: S1, S2, S3, and S2 + S3. The HSDS driver can be AC-coupled for AC-LVPECL output clocks
or other differential outputs. If there is an available VCM setting that meets the receiver requirements, then the
HSDS driver can be DC-coupled, such as for LVDS outputs.
The traditional HCSL output driver is PCIe compliant and requires 50Ω external termination. TI recommends
placing the termination close to the receiver side.
Refer to Table 7-7 for the recommended differential output options and the Electrical Characteristics for the
voltage variation of the VOD and VCM.

LMK5C22212AS1
Table 7-7. Differential Output Options

VOD, TYP [mV] REGISTER
DIFFERENTIAL DRIVER TYPE VCM, TYP [mV] VCM REGISTER SETTING
SETTING
HSDS 400 350 S1
HSDS 400 700 S2
HSDS (LVDS) 400 1250 S3
HSDS 500 400 S1
HSDS 600 450 S1
HSDS 600 800 S2 + S3
HSDS 700 500 S1
HSDS 700 900 S2 + S3
HSDS (AC-LVPECL) 800 550 S1
HSDS (AC-LVPECL) 800 1000 S2 + S3
ADVANCE INFORMATION
HCSL 750 350 N/A
7.3.14.2 LVCMOS Output

OUT0 and OUT1 have the additional capability for two 1.8V or 2.65V LVCMOS drivers per P and N output pair.
Each LVCMOS output can be configured for normal polarity, inverted polarity, or disabled as Hi-Z or static low
level. The LVCMOS output high level (VOH) is determined by the internal programmable LDO regulator voltage of
1.8V or 2.65V for rail-to-rail LVCMOS output voltage swing.
LVCMOS mode is recommended for ASIC or processor clocks which do not have stringent phase noise or jitter
requirements. An LVCMOS output clock is an unbalanced signal with large voltage swing, therefore the clock
can be a strong aggressor and couple noise onto other jitter-sensitive differential output clocks. If an LVCMOS
clock is required from an output pair, configure the pair with both outputs enabled but with opposite polarity (+/–
or –/+) and leave the unused output floating with no trace connected.
7.3.14.3 SYSREF/1PPS Output
The LMK5C22212AS1 can support system reference clocks from 1PPS to 25MHz including JEDEC JESD204B
or JESD204C SYSREF clocks. Any 12-bit output channel divider except OUT2/3 can be cascaded with
an individual 20-bit SYSREF divider. Set flexible SYSREF divider values to generate the same SYSREF/
1PPS frequency on multiple outputs or different frequency multiples of SYSREF/1PPS based on application
requirements. When aligning multiple SYSREF outputs, TI recommends setting SYSREF_REQ_MODE
0x1A[5:4] = 11 for resampling of the SYSREF request. The SYSREF/1PPS can also be replicated on GPIO1 or
GPIO2 if additional single ended outputs are needed. The SYSREF request sample source SYSREF_REQ_SEL
0x1A[3:2] must be set to the same source as desired for SYSREF/1PPS output replication.
The SYSREF divider output signals can be replicated on either GPIO1 and GPIO2 to provide additional single
ended 3.3V CMOS clocks after start-up if desired. To configure the SYSREF/1PPS output replication the GPIO
must be enabled as an output (GPIOx_OUTEN = 1) and one of the SYSREF output to GPIO replication sources
must be active. The SYSREF replication source comes from any one of the SYSREF dividers in use from
OUT0/1, OUT4/5, OUT6/7, OUT8/9, OUT10/11 by register programming (OUT_x_y_SR_GPIO_EN = 1). The
GPIOx replicated SYSREF output is after static digital delay but before the analog and digital delay and pulser.
The output is a continuous frequency as pulsed SYSREF mode is not supported for the GPIOx replica.
There is some small fixed delay skew between the normal SYSREF and GPIO replicated SYSREF. An LVCMOS
output clock is an unbalanced signal with large voltage swing; therefore, the signal can strongly interfere and
couple noise onto other jitter-sensitive differential output clocks.

LMK5C22212AS1
7.3.15 Output Auto-Mute During LOL

Each output driver can automatically mute the clock when the selected output mux clock source is invalid,
as configured by the MUTE enable field. The source can be invalid based on the LOL status of each
PLL by configuring the APLL and DPLL mute control bits (MUTE_APLLx_LOCK, MUTE_DPLLx_LOCK,
MUTE_DPLLx_PHLOCK). When auto-mute is disabled or bypassed (OUT_x_y_MUTE_EN = 0), the output clock
can have incorrect frequency or be unstable before and during the VCO calibration.
7.3.16 Glitchless Output Clock Start-Up
When APLL auto-mute is enabled, the outputs starts up in synchronous fashion without clock glitches once
APLL lock is achieved after any the following events: device power-on, exiting hard-reset, exiting soft-reset, or
deasserting output SYNC.
7.3.17 Clock Output Interfacing and Termination
This section shows the recommended output termination. Unused clock outputs can be left floating and powered
ADVANCE INFORMATION
down by programming.
LMK Device
Receiver
LVCMOS driver
Figure 7-25. LVCMOS Output Termination
100
LMK Device
Receiver
HSDS driver
Figure 7-26. DC-Coupled HSDS/LVDS Output Termination
100
LMK Device
Receiver
HSDS driver
Figure 7-27. AC-Coupled HSDS Output Termination Method 1
LMK Device
Receiver
HSDS driver
50 50
Figure 7-28. AC-Coupled HSDS Output Termination Method 2

LMK5C22212AS1
LMK Device
Receiver
HCSL driver
50 50
Figure 7-29. DC-Coupled HCSL Output Termination
LMK Device
Receiver
ADVANCE INFORMATION
HCSL driver
50 50
Figure 7-30. AC-Coupled HCSL Output Termination

LMK5C22212AS1
7.3.18 Output Synchronization (SYNC)

Output SYNC can be used to phase-align two or more output clocks with a common rising edge by allowing the
output dividers to exit reset on the same PLL output clock cycle. Any output dividers selecting the same PLL
output can be synchronized together as a SYNC group by triggering a SYNC event through the hardware pin or
software bit.
The following requirements must be met to establish a SYNC group for two or more output channels:
• Output dividers have the respective sync enable bit set (OUT_x_y_DIV_SYNC_EN = 1)
• SYSREF dividers have the additional respective sync enable bit set (OUT_x_y_SR_DIV_SYNC_EN = 1),
work with above set (OUT_x_y_DIV_SYNC_EN = 1)
• Output dividers have the output mux selecting the same PLL output
• The PLL (post-divider) output has the sync enable bit set (for example, PLL1_PRI_DIV_SYNC_EN = 1)
• SYNC_EN = 1
A SYNC event can be asserted by either a GPIOx pin programmed for SYNC input with GPIOx_MODE = 31 or
ADVANCE INFORMATION
the SYNC_SW register bit (active high). When SYNC is asserted, the SYNC-enabled dividers are held in reset
and clock outputs are low. When SYNC is deasserted, the outputs from a common PLL starts with the initial
clock phases synchronized or aligned. SYNC can also be used to set a low state on any SYNC-enabled outputs
to prevent output clocks from being distributed to downstream devices until the receiver inputs are configured
and ready to accept the incoming clock.
Output channels with the sync disabled (OUT_x_y_DIV_SYNC_EN = 0) is not affected by a SYNC event and
continues normal output operation as configured. VCO post-divider clocks must be enabled for synchronization
to verify that the driven dividers are synchronized accurately. However, any output deriving a clock from a
reset VCO post-divider is not valid during SYNC, even if the channel divider is not selected for SYNC. VCO
post-dividers not selected for synchronization do not stop running during the SYNC so the post-dividers can
continue to source output channels that do not require synchronization. Output dividers with divide-by-1 (divider
bypass mode) are not gated during the SYNC event.
Table 7-8. Output Synchronization
GPIOx as SYNC PIN
GPIOx_MODE = 31 SYNC_SW
OUTPUT DIVIDER AND DRIVER STATE
R21[6]
GPIOx_POL = 0 GPIOx_POL = 1
1 0 1 Output drivers muted and output dividers reset
1→0 0→1 1→0 SYNCed outputs are released with synchronized phase
0 1 0 Normal output driver/divider operation as configured
7.3.19 Zero-Delay Mode (ZDM)

The DPLL supports an internal ZDM synchronization option to achieve a known and deterministic phase
relationship between the selected DPLL reference input and OUT0, OUT4, or OUT10 clock depending on
configuration and selected DPLL for ZDM.
With ZDM enabled, users can attain zero phase delay between the selected DPLL reference input clock and
the selected zero-delay feedback clock. Figure 7-31 shows how the OUT0 clock can internally feedback to any
DPLL as the zero-delay output clock. ZDM is primarily implemented to achieve deterministic phase relationship
between an input and selected outputs such as 1PPS input to 1PPS outputs or 156.25MHz input to 156.25MHz
outputs.
There is no need to route external clock signals from output to input as the zero-delay feedback clock from
OUT0 is routed internally to the device. OUT4 can be used for DPLL2 internal ZDM feedback .
1PPS phase alignment is able to re-establish with the phase slew control and ZDM. The phase slew control can
reduce the phase build-out back to 0 at a controlled rate. To lock to a 1PPS signal using ZDM mode, the output
static delay or DPLLx_PH_OFFSET can be programmed to zero out the phase error between the 1PPS input
and 1PPS feedback clock. Hitless switching must be disabled when ZDM is used for 1PPS.

LMK5C22212AS1
See DPLL Programmable Phase Delay for an example of how input to output phase error in the
DPLLx_PH_OFFSET field is calculated to apply fine adjustments less than 1 ps.
DPLL + APLL OUT0 Channel
REF ÷R fTDC fVCO ÷OD OUT0
Phase Offset SYNC
DPLLx_PH_OFFSET
Figure 7-31. DPLL ZDM Synchronization Between Reference Input and OUT0
ADVANCE INFORMATION
7.3.20 DPLL Programmable Phase Delay
Users can write to the DPLLx_PH_OFFSET[44:0] register fields to adjust the DPLL phase offset. The phase
offset is a signed 2's complement value with a default setting of 0 and offsets the phase relationship of the
feedback clock to reference clock at the TDC. The phase adjustment is common to all outputs derived from the
DPLLx synchronization domain. DPLLx_PH_OFFSET adjustments occur in one direction. To shift in the negative
direction, subtract the desired time offset from the period of the output clock to get the new phase offset.
Equation 9 and Equation 10 show the formulas to compute the DPLLx_PH_OFFSET field value to vary the
output phase in fine adjustment steps. DPLLx_PH_OFFSET is related to the APLLx VCO period with a scaling
factor for decimation and digital gain.
DPLLx_PH_OFFSET = 2 × DESIRED_TIME_OFFSET × fVCOx × SCALINGDEC (9)
SCALINGDEC = DPLLx_PARAM_B × (DPLLx_PARAM_C + 1) × 232 − DPLLx_PARAM_A (10)
where
• DPLLx_PH_OFFSET: Programmable register value adjusting DPLL output phase
• DESIRED_TIME_OFFSET: Desired DPLL phase adjustment (in seconds)
• fVCOx: VCOx frequency
• SCALINGDEC: Scaling factor accounting for decimation and digital gain parameters
• DPLLx_PARAM_A/B/C: DPLL decimation and gain parameters. For DPLLx_PARAM_A, use a value of 32 in
the equation if the register readback value is 0.
For example, if the user wants to introduce a phase offset of +1ns into DPLL2, use the following settings:
• DESIRED_TIME_OFFSET = +1ns
• fVCOx: = 2500MHz
• SCALINGDEC = 584 × (7 + 1) × 232 − 32 = 4672
• DPLL1_PH_OFFSET = 2 × 1e-9 × 2500e6 × 4672 = 23360
Alternatively, to apply a phase shift in the other direction, such as −1ns to a 25MHz output clock, use the
following settings:
• DESIRED_TIME_OFFSET = 40ns - 1ns = 39ns
– 40ns is the period of the output clock (25MHz).
• fVCOx: = 2500MHz
• SCALINGDEC = 4672
• DPLL1_PH_OFFSET = 2 × 39e-9 × 2500e6 × 4672 = 911040

LMK5C22212AS1
The DPLL parameters of a given configuration can be readback by accessing the registers listed in Table 7-9.
Table 7-9. DPLL Phase Offset Registers
REGISTER ADDRESS
FIELD NAME
(HIGH BYTE TO LOW BYTE)
DPLL1_PH_OFFSET R550, R551, R552, R553, R554, R555
DPLL1_PARAM_A R567
DPLL1_PARAM_B R548, R549
DPLL1_PARAM_C R566
DPLL2_PARAM_A R417
DPLL2_PARAM_C R416
ADVANCE INFORMATION

DPLL1_PARAM_A R267
DPLL1_PARAM_C R266
7.3.21 Time Elapsed Counter (TEC)

The Time Elapsed Counter (TEC) allows the user to make a precise time measurement between two (or more)
events. The events can be either a rising or falling edge of a GPIO pin or a falling edge of the SPI SCS pin.
Any GPIO pin can be programmed for TEC input. Rising or falling polarity can be selected using the GPIO
polarity invert register. After each TEC event, the counter values is captured and the application can read back
a 40-bit value. The elapsed time is calculated based on the difference in the read back values. The accuracy
of the measurement is better than 7.5ns with a total measurement time over 59 minutes depending on exact
configuration. Reading back at least the LSB of the TEC_CNTR is necessary to re-arm the TEC counter capture.
The TEC counter is clocked at a frequency based on APLL1 VCO frequency ÷8 or PLL2 VCO frequency ÷ 20. A
time measurement is performed using the following steps.
1. Reset the TEC counter value. Recommended to reduce chance of counter roll-over between TEC capture
events, but optional. If the reset is not done, the user needs to detect roll-over of counter register which
complicate Equation 11 for elapsed time calculation.
2. Trigger TEC capture event and read back the TEC registers containing the stored counter value.
3. Trigger the TEC capture event a second time and read back the TEC registers containing the stored counter
value.
4. Use Equation 11 to calculate the elapsed time. The worst-case error is twice the TEC counter clock period.
Table 7-10 lists some common TEC clock frequencies/periods and roll-over times.
Elapsed Time = (2nd captured TEC value - 1st captured TEC value) / TEC Clock Rate (11)
The TEC_CNTR register is split across five registers.

Table 7-10. Common TEC Clock Frequencies and Roll-Over Times
PLL SOURCE VCO FREQUENCY TEC CLOCK TEC CLOCK PERIOD (t) ROLL-OVER TIME
FREQUENCY
PLL2 5950MHz 297.5MHz ≅3.361ns ≅61.6 minutes
PLL2 5898.24MHz 294.912MHz ≅3.391ns ≅62.1 minutes
PLL2 5625MHz 281.25MHz ≅3.556ns ≅65.1 minutes
PLL2 5600MHz 280MHz ≅3.571ns ≅65.4 minutes
Figure 7-32. TEC Clock and Counter

LMK5C22212AS1
Figure 7-33 illustrates the states of the Time Elapsed Counter function.
Waiting for Trigger

GPIOx triggers if
TEC_CNTR_TRIG = 1 and
GPIOx selected polarity edge.
…
SPI chip select triggers if
TEC_CNTR_TRIG = 0 and
TEC_CNTR MSB is read.
GPIO Trigger or
Read TEC_CNTR LSB
SPI Trigger
ADVANCE INFORMATION
Captured
Captured trigger event. No more TEC_CNTR_EN = 1
TEC_CNTR_EN = 0
trigger events update TEC_CNTR
value. Captured TEC_CNTR value is
now read back.
TEC_CNTR_EN = 0
Disabled/Reset
TEC_CNTR is disabled.
When re-enabled, counter starts
from 0.
Figure 7-33. State Diagram of TEC
7.3.21.1 Configuring TEC Functionality

1. Select the PLL to drive the Time Elapsed Counter (TEC). The BAW APLL offers the highest accuracy time
measurement due to the highest TEC clock frequency, however, the conventional APLL (LC VCO) provides
slightly longer roll-over times.
• The BAW APLL source is selected by setting REF0_MISSCLK_VCOSEL to 0.
• The conventional APLL source is selected by setting REF0_MISSCLK_VCOSEL to 1.
2. Select GPIO or SPI chip select as a trigger to capture the TEC counter value to TEC_CNTR field. Using a
GPIO does not require any special timing for the SPI SCS pin. Using the GPIO pin for other purposes is
possible, enable the TEC functionality when required.
• GPIO trigger is selected by setting TEC_CNTR_TRIG to 1.
• SPI chip select trigger is selected by setting TEC_CNTR_TRIG to 0.
3. Enable the TEC counter by setting TEC_CNTR_EN to 1.
7.3.21.2 SPI as a Trigger Source
When TEC_CNTR_EN = 1, each SCS falling edge the TEC counter is captured to the TEC_CNTR field.
Subsequent to a SPI transaction which reads from the MSB of the TEC_CNTR field, no falling edge of SCS
captures the TEC counter to the TEC_CNTR field until the LSB of the TEC_CNTR field is read.
Figure 7-34 shows when the TEC is latched during single register reads and Figure 7-35 for a multibyte read.
Figure 7-34 shows that the TEC counter is captured every falling SCS edge until TEC_CNTR MSB is read.

LMK5C22212AS1
Read Read Read Read Read Read Read Read

SPI non- non- TEC TEC TEC TEC TEC non-
Acvity TEC TEC Register Register Register Register Register TEC
Register Register 39:32 31:24 23:16 15:8 7:0 Register
SCS
TEC TEC TEC TEC

counter counter counter counter
latched latched latched latched
to TEC to TEC to TEC to TEC
field field field field
Figure 7-34. TEC Single Byte Read
ADVANCE INFORMATION
Figure 7-35 shows that the TEC counter value can be captured and re-armed for capture during a single
multibyte read, even if the first register read is not the TEC_CNTR registers.
Read Read Read Read Read Read Read Read
SPI non- non- TEC TEC TEC TEC TEC non-
Acvity TEC TEC Register Register Register Register Register TEC
Register Register 39:32 31:24 23:16 15:8 7:0 Register
SCS
TEC TEC
latched latched
Figure 7-35. TEC Multibyte Read

LMK5C22212AS1
7.3.21.3 GPIO Pin as a TEC Trigger Source

A rising edge of a GPIO pin selected for TEC functionality with GPIOx_MODE = 0x27 (TEC_TRIG_SEL)
captures the TEC value to the TEC_CNTR field upon an edge of the selected polarity (GPIOx_POL). No further
updates to the TEC_CNTR field is made by subsequent GPIOx pin edges until the LSB of the TEC_CNTR field
is read. Figure 7-36 shows the timing of using a GPIO to capture TEC values.
Read Read Read Read Read
SPI/I2C Don’t TEC_CNTR TEC_CNTR TEC_CNTR TEC_CNTR TEC_CNTR CSC high
Don’t Care
Acvity Care Register Register Register Register Register condion
39:32 31:24 23:16 15:8 7:0
TEC_CNTR eld
TEC_CNTR eld is no longer updated from a trigger event un l TEC_CNTR LSB read
is no longer
is complete 1 µs updated...
GPIOx don’t
GPIOx GPIOx don’t care
care
ADVANCE INFORMATION
TEC captured TEC captured
Figure 7-36. TEC Captured Using GPIO
7.3.21.3.1 An Example: Making a Time Elapsed Measurement Using TEC and GPIO1 as Trigger
1. Configure TEC registers as desired. In this example:

• REF0_MISSCLK_VCOSEL is 0 so that VCBO frequency / 8 is used for TEC clock rate
• TEC_CNTR_TRIG = 1 for GPIO1 trigger
• TEC_CNTR_CLR = 0 for normal operation
2. Set GPIO1_MODE = 0x27 (TEC_TRIG_SEL) and GPIO1_POL as desired, 0 in this example for active high
input.
3. Provide rising edge on GPIO1 to capture current TEC counter value into the TEC_CNTR field.
4. Read and store the TEC_CNTR field for the first time.
• Example: 1st_captured_TEC_value = 204 354.
5. Provide rising edge on GPIO1.
6. Read and store the TEC_CNTR field for the second time.
• Example: 2nd_captured_TEC_value = 76 516 568
7. Calculate time delta using equation #1 with TEC clock rate of 307.2 MHz.
• 248.412 155 ms = (76 516 568 - 204 354) / 307.2 MHz
• Because the TEC clock rate is 307.2 MHz, the accuracy of the measurement is ±3.26 ns.
7.3.21.4 Other TEC Behavior
The TEC counter continually counts up and periodically rolls over from 240 – 1 to 0.
• The user software must determine if the counter has rolled over in between TEC reads. TI recommends
resetting the TEC counter accordingly by toggling the TEC_CNTR_EN bit before a prospective starting trigger
event, if known.
The REF0_MISSCLK_VCOSEL field also selects which VCO is used by all inputs for the early and missing
reference clock validation, therefore the early and missing input validation registers can need to be re-calculated
if REF0_MISSCLK_VCOSEL is changed. Changing REF0_MISSCLK_VCOSEL or validation calculations during
operation can result in references using the missing pulse or both missing and runt pulse detectors to be
momentarily disqualified and send the DPLL into holdover.
While TEC_CNTR_EN = 0, the TEC counter is held in reset, which is counter value 0. Performing an absolute
time measurement from the moment that TEC_CNTR_EN transitions from 0 to 1 to a future trigger event is also
possible. However the accuracy of this measurement is less than performing a relative measurement caused by
two GPIO or two SPI CSC triggers.

LMK5C22212AS1
7.4 Device Functional Modes

7.4.1 DPLL Operating States
The following sections describe the DPLL states of operation shown in Figure 7-37. The diagram assumes that
holdover is enabled.
See Device POR
(1) Frequency stability after entering Configuration Sequence
Holdover is determined by XO reference Flowchart
stability for duration of Holdover event.
(2) See DPLL Reference Input Select

Flowchart.
Holdover: Free-run (1) No valid input
Frequency accuracy reference available
determined by free-run
tuning word register and
XO accuracy.
Holdover: History (1)

Initial holdover frequency
accuracy determined by
ADVANCE INFORMATION
averaged history data. Valid Input No

Reference Available for
Selection? (2)
Yes
No Valid Input
Lock Acquisition
Reference Available for
(Fastlock)
Selection? (2)
Phase-locked to
Yes selected input
DPLL Locked
Lock Acquisition
DPLL DCO takes effect.
(Hitless)
Yes
Valid Input
No Reference Available for No
Loss of Ref (LOR) on
Selection? (2) Selected Input? (2)
Yes
Holdover: Last Value (1)

Frequency accuracy
determined by last known Is Tuning Word No
DPLL tuning word value. History Enabled?
Yes
No Is Tuning Word
History Valid?
Yes
Figure 7-37. DPLL Operating States
7.4.1.1 Free-Run
After device POR configuration and initialization, APLL automatically locks to the XO clock when the XO input
signal is valid. The output clock frequency accuracy and stability in free-run mode track the frequency accuracy
and stability of the XO input. The reference inputs remain invalid (unqualified) during free-run mode. If the DPLL
has locked, but not yet accumulated a valid history word and the reference is lost, then Free-Run is entered.
7.4.1.2 Lock Acquisition
The DPLL constantly monitors the reference inputs for a valid input clock. When at least one valid input clock
is detected, the PLL channel exits free-run mode or holdover mode and initiate lock acquisition through the
DPLL. The LMK5C22212AS1 supports the Fastlock feature where the DPLL temporarily engages a wider loop
bandwidth to reduce the lock time. When the lock acquisition is done, the loop bandwidth is set to the normal
configured loop bandwidth setting (BWDPLL).

LMK5C22212AS1
7.4.1.3 DPLL Locked

When the DPLL locks, the APLL output clocks are frequency and phase locked to the selected DPLL reference
input clock. While the DPLL is locked, the APLL output clocks is not affected by frequency drift on the XO input.
The DPLL has a programmable frequency lock detector and phase lock detectors to indicate loss-of-frequency
lock (LOFL) and loss-of-phase lock (LOPL) status flags, which can be observed through the status pins or status
bits. When the frequency lock is detected (LOFL → 0), the tuning word history monitor (if enabled) begins to
accumulate historical averaging data used to determine the initial output frequency accuracy upon entry into
holdover mode.
7.4.1.4 Holdover
When a loss-of-reference (LOR) condition is detected and no valid input is available the DPLL enters holdover.
If history is disabled (DPLLx_HIST_EN = 0) the DPLL uses the 2's complement DPLLx_FREE_RUN[39:0] field
which sets holdover frequency relative to the DPLL numerator. Short-term frequency accuracy is based on the
ADVANCE INFORMATION
accuracy of the DPLLx_FREE_RUN field.
If history is enabled (DPLLx_HIST_EN = 1) but the tuning history is not yet valid, then the DPLLx_FREE_RUN
field is used as if DPLLx_HIST_EN is disabled. If the tuning history is valid, the DPLL enters holdover using
historical data to minimize holdover frequency error. See Tuning Word History. In general, the longer the
historical average time, the more accurate the initial holdover frequency assuming the 0-ppm reference clock
(XO input) is drift-free. The stability of the XO reference clock determines the long-term stability and accuracy of
the holdover output frequency.
Upon entry into holdover, the LOPL flag is asserted (LOPL → 1). The LOFL flag reports DPLL frequency versus
reference frequency is in tolerance. In holdover LOFL remains unchanged in holdover and not update until a
valid reference is once again selected.
When a valid input becomes available for selection, the DPLL exits holdover mode and automatically phase lock
with the new input clock without any output glitches.
7.4.2 Digitally-Controlled Oscillator (DCO) Frequency and Phase Adjustment
To support IEEE 1588 and other clock steering applications, the DPLL supports DCO mode to allow precise
output clock frequency adjustment of less than 0.001 ppb/step. DCO can be implemented using DPLL DCO
control or APLL DCO control. While the DPLL is operating in closed-loop mode, DPLL DCO modifies the
effective DPLL numerator. While the DPLL is in holdover or not used, APLL DCO adjusts the effective APLL
numerator.
7.4.2.1 DPLL DCO Control
DCO mode can be enabled (DPLLx_FB_FDEV_EN = 1) when the DPLL is locked.
There are three methods to steer frequency when using the DPLL DCO.
• Register relative adjustment
– Preset the deviation amount in DPLL_FDEV
– Write an 8-bit register to enable increment/decrement by the deviation amount
• GPIO relative adjustment
– Step/Direction GPIOx trigger
– Adjust DPLLx_FB_NUM by programming a deviation amount for each step in pin set direction.
• Register absolute adjustment
– Write the DPLLx_FB_NUM [39:0] based on the frequency control word (FCW)
The DCO frequency step size can be programmed through a 38-bit frequency deviation word register
(DPLL_FDEV bits). The DPLL_FDEV value is an offset added to or subtracted from the current numerator
value of the DPLL fractional feedback divider and determines the DCO frequency offset at the VCO output.
The DCO frequency increment (FINC) or frequency decrement (FDEC) updates can be controlled through
software control (DPLLx_FB_FDEV_UPDATE) or user selectable pin control (GPIOx). DCO updates through

LMK5C22212AS1
software control are always available through I2C or SPI by writing to the DPLLx_FB_FDEV_UPDATE register
bit. Writing a 0 increments the DCO frequency by the programmed step size, and writing a 1 decrements the
DCO frequency by the step size. SPI can achieve faster DCO update rates than I2C because the SPI has faster
write speed.
When DPLL pin control is selected (FDEV_TRIG_DPLLx and FDEV_DIR_DPLLx on GPIOs), a rising edge
on the GPIO pin defined in FDEV_TRIG_DPLLx applies a corresponding DCO update to the DPLL, another
GPIO defined in FDEV_DIR_DPLLx determines the direction of the FDEV trigger. FDEV_DIR_DPLLx = 0 means
positive, FDEV_DIR_DPLLx = 1 means negative. In this way, the GPIO pins functions as the FINC or FDEC
input. The minimum positive pulse width applied to the trigger pins must be greater than 100 ns to be captured
by the internal sampling clock. The DCO update rate must be limited to less than 5 MHz when using pin control.
When DCO control is disabled (DPLLx_FB_FDEV_EN = 0), the DCO frequency offset is cleared and the VCO
output frequency is determined by the original numerator value of the DPLL fractional feedback divider.
ADVANCE INFORMATION
APLL
fTDC DPLL fVCO
FDEV Pin Control

DPLLx_FB_FDEV_EN
GPIOm/TRIG FINC
DCO
Logic FDEC Step
GPIOn/DIR
DPLL_FDEV
FINC/FDEC Register Control
DPLLx_FB_FDEV_UPDATE
I2C/SPI 0x160[0] Write:
0x1F6[0] 0 = FINC The DPLL Numerator is incremented or decremented by the DCO
0x28C[0] 1 = FDEC FDEV step word on the rising-edge of FINC or FDEC.
Figure 7-38. DCO Mode Control Options
7.4.2.2 DPLL DCO Relative Adjustment Frequency Step Size

Equation 12 shows the formula to compute the DPLLx_FB_FDEV register value required to meet the specified
DCO frequency step size in ppb (part-per-billion) when DCO mode is enabled for the DPLL.
DPLLx_FB_FDEV = (Reqd_ppb / 109) × DPLLDEN × fVCOx / fTDCx (12)
where
• DPLLx_FB_FDEV: Frequency deviation value (0 to 238– 1)
• Reqd_ppb: Required DCO frequency step size (in ppb)
• DPLLDEN: DPLL FB divider denominator value (1 to 240, register value of 0 = 240)
• fTDCx: TDCx frequency
7.4.2.3 APLL DCO Frequency Step Size
Users must write to the DPLLx_FREE_RUN register field to adjust the APLL DCO. When DPLLx_HIST_EN = 1,
the relative adjustments are performed. When DPLLx_HIST_EN = 0 the DPLLx_FREE_RUN value is used for
the APLLx DCO numerator. The effective APLLx numerator can be read back from APLLx_NUM_STAT.
Equation 13 shows the formula to compute the DPLLx_FREE_RUN field value required to meet the
specified DCO frequency step size in ppb (part-per-billion) when relative APLL DCO mode is enabled.
DPLLx_FREE_RUN is a signed value and the actual programmed value for a negative number can be
calculated as the 2s complement.
DPLLx_FREE_RUN = (Reqd_ppb / 109) × APLLxDEN × fVCOx / fPDFx (13)
where

LMK5C22212AS1
• DPLLx_FREE_RUN: Frequency deviation value (–239 to 239– 1)

• Reqd_ppb: Required DCO frequency step size (in ppb)
• APLLxDEN: APLL FB divider denominator value (240)
• fPDFx: PLLx phase detector frequency
7.4.3 APLL Frequency Control
The device can also support APLL frequency and phase control through writing the 40-bit register
DPLLx_FREE_RUN[39:0] while the DPLL is in holdover or not used. If the reference clock in a free-run mode or
disabled, the DPLL disconnects with the APLL, but users can still adjust frequency and phase accuracy.
To enable APLL DCO control, set DPLLx_LOOP_EN = 1, and PLLx_MODE = 1 for 40-bit fractional denominator.
DPLLx_EN can be set = 0.
XO ×1, ×2
ADVANCE INFORMATION
DPLL APLL
÷R fTDC fPD VCO
: ÷R fVCO
÷R TDC DLF 5-bit LF
PFD
16-bit To post-divider
and
Output Muxes
÷FB ÷N
38-bit
DCO
FDEV
DPLLx_FREE_RUN
APLLx_NUM (APLL_NUM_STAT) = APLLx_NUM + DPLLx_FREE_RUN
Figure 7-39. APLL DCO Mode
There are two alternative methods in adjusting the APLL DCO.

• Absolute frequency adjustment
– Set DPLLx_HIST_EN = 0
– Effective APLLx_NUM (APLLx_NUM_STAT) = APLLx_NUM + DPLLx_FREE_RUN
• The APLLx_NUM_STAT is a read-only register and can be read back.
• The DPLL loop filter block modifies the APLLx_NUM_STAT based on DPLLx_FREE_RUN value.
– DPLLx_FREE_RUN is a 40-bit 2's complement number
• Relative frequency adjustment
– Set DPLLx_HIST_EN = 1
– DPLLx_FREE_RUN value is fed into the APLLx_NUM at a controlled rate defined by a step size register
and step period register.
– If another DPLLx_FREE_RUN write occurs before the LMK is complete in making the last adjustment, any
remaining steps are lost and the new value begins to feed the APLL numerator.
– A flag is set when the DPLLx_FREE_RUN word is fully fed into the effective APLLx_NUM
(APLL_NUM_STAT).

LMK5C22212AS1
7.4.4 Device Start-Up

7.4.4.1 Device Power-On Reset (POR)
Figure 7-40 shows the device power-on reset (POR) configuration sequence. POR occurs when the PD# pin
is deasserted and reaches a logic high state. After POR, the serial control interface of choice (I2C or SPI) is
selected. The LMK5C22212AS1 supports preconfigured device settings from the factory preprogrammed internal
ROM Page Selection. A programmable EEPROM Overlay provides a flexible start-up of output clocks. Refer to
Programming for after start-up programming details.
Device POR Power-On Reset
Configuration Sequence (POR)
PD# = 0
Hard Reset
ADVANCE INFORMATION
PD# = 1
GPIO1 = 0 Select GPIO1 = 1

communication interface
I2C interface SPI interface

SCS_ADD pin is a SCS_ADD functions
3-level input for I2C as SPI chip select
address select
ROM Selection
GPIO0 and GPIO2 are 3-level inputs used to select start-up ROM.
Selected ROM is function of EEPROM field EE_ROM_PAGE_SEL

plus GPIO pin page adder
EEPROM Overlay
If EEPROM field ROM_PLUS_EE is set, then start-up clocks are set
from EEPROM. Many APLL and output configuration fields are
overwritten from EEPROM.
Device Block Configuration

All blocks reset to initial states.
Register programming available.
SWRST = 1
Hard Reset
SWRST = 0
Normal Operation
See PLL Initialization

Flowchart
Figure 7-40. Device POR Sequence
After start-up, a global SWRST (R23[6]) restarts the device initializtion sequence and APLL calibration state
machine (see Figure 7-41). Issuing the global SWRST is recommended when modifying the APLL registers after
POR to recalibrate all of the APLLs and re-align the output and SYSREF channel dividers.
When toggling the global SWRST, a disruption on the APLL output clocks can occur until the APLLs acquire
lock again. An individual APLLx software reset (APLLx_SWRST) can be issued to avoid disturbing other
APLL clocks. Use the APLLx_SWRST after bring-up when modifying the registers of the individual APLLx.
For example, if only APLL1 registers are changed, then issue an APLL1_SWRST and only APLL1 outputs are
briefly disrupted while APLL2 outputs remain undisturbed.
Issuing a SWRST is not required for the following cases:
• When no register writes are performed after boot-up.

LMK5C22212AS1
• When only the XO input termination type, INx input termination type, output drivers (such as swing level or
channel divider), GPIO pin, status, or DCO registers are modified after boot-up.
• When programming the EEPROM.
Issuing a SWRST is recommended for the following cases:
• When most of the register writes are modified through I2C or SPI (such as during device configuration after
boot-up).
• When the ZDM and SYSREF registers are configured. Not required if only changing the SYSREF divider
value.
• When the APLLx registers are modified and a brief interruption on all of the APLLx clocks is not an issue.
Issuing an individual APLLx_SWRST is recommended for the following cases:
• When the device has been configured with the desired registers and only APLLx registers need to be
modified without disturbing the other APLL output clocks.
ADVANCE INFORMATION
7.4.4.2 PLL Start-Up Sequence
Figure 7-41 shows the general sequence for APLL start-up after POR. This sequence also applies after a
global SWRST or APLLx_SWRST. To provide proper VCO calibration, the APLL reference clock must be stable
in amplitude and frequency prior to the start of VCO calibration. Otherwise, the VCO calibration can fail and
prevent start-up of the APLL and the output clocks.
Device Configured
PLL Initialization Sequence
See Device POR Configuration
Sequence Flowchart
XO Detected
VCO Calibration
APLL(s) Locked
(Free-run from XO)
Program registers Device

through SPI/I2C Re-configuration
Ref. Input
Validation
Valid Input Selected
DPLL
Lock Acquisition
DPLL
Locked
See DPLL Modes and

Input Selection
Flowcharts
Figure 7-41. APLL Initialization Sequence

LMK5C22212AS1
7.4.4.3 Start-Up Options for Register Configuration

The device can boot-up from either of the four listed options. The option selected depends on the system use
case.
1. Option 1: ROM
a. The device boots up from one of the ROM pages, the EEPROM overlay is bypassed, and no I2C
transactions are performed after start-up.
b. Use this option when both DPLL and APLL settings match a ROM page.
2. Option 2: ROM → EEPROM
a. The device boots up from one of the ROM pages, then the EEPROM settings are loaded to the device
and overwrite the XO, APLL, and output driver configuration.
b. Use this option when the desired DPLL settings match a ROM page but the APLL settings do not. Also,
use for free-run mode (APLL only, DPLL disabled) configurations.
3. Option 3: ROM → EEPROM → in-system programming
ADVANCE INFORMATION
a. The device boots up from one of the ROM pages, then the EEPROM settings are loaded to the device
and overwrite the XO, APLL, and output driver configuration. I2C transactions are performed after
start-up to update the remaining registers that are not stored in EEPROM (DPLL, SYSREF, and GPIO).
b. Use this option when the desired DPLL and APLL settings do not match a ROM page.
4. Option 4: ROM → in-system programming
a. The device boots up from one of the ROM pages, the EEPROM overlay is bypassed, and I2C
transactions are performed to overwrite any undesired register value initialized by the ROM selection
(DPLL, SYSREF, GPIO, XO, APLL, and output driver).
b. Use this option when the EEPROM can not be preprogrammed to reduce start-up time or when the
majority of the registers must be configured in-system.
7.4.4.4 GPIO1 and SCS_ADD Functionalities
The device can start-up as either I2C or SPI depending on the 2-level input level sampled on the GPIO1 pin
during POR.
• GPIO1 = 0: I2C Serial Interface is selected and the SCS_ADD pin functions as a 3-level input for the I2C
address select.
• GPIO1 = 1: SPI Serial Interface is selected and the SCS_ADD functions as a SPI chip select.

LMK5C22212AS1
7.4.4.5 ROM Page Selection

At POR, the sum of the GPIO2, GPIO0, and EE_ROM_PAGE_SEL (R20[6:3]) logic states determine which ROM page is used. The
EE_ROM_PAGE_SEL field is stored in EEPROM and has a factory default setting of EE_ROM_PAGE_SEL = 0. All register pages in the ROM are
factory-set in hardware (mask ROM) and are not software programmable by the user. For more details on the register descriptions, refer to the
LMK5B33216 Programmer's Guide.
Table 7-11. ROM Page Selection by GPIO2 and GPIO0
GPIO2 AT POR GPIO0 AT POR ROM PAGE WITH EE_ROM_PAGE_SEL = 0
L L ROM page 0. XO= 48MHz, REFCLK = 156.25MHz and 10MHz, outputs = 100MHz, 122.88MHz, 245.76MHz, 312.5MHz, 491.52MHz.
L H ROM page 1. XO= 48MHz, REFCLK = 10MHz, outputs = 100MHz, 312.5MHz, 491.52MHz.
H L ROM page 2. XO= 48MHz, REFCLK = 10MHz, outputs = 100MHz, 125MHz, 312.5MHz, 491.52MHz.
H H ROM page 3. Low power mode. All PLLs off, all outputs off.
ADVANCE INFORMATION
L M ROM page 4. XO = 54MHz, REFCLK = 30.72MHz, outputs = 30.72MHz, 125MHz, 161.1328125MHz, 122.88MHz, 245.76MHz, 491.52MHz.
M L ROM page 5. XO= 20MHz, REFCLK = 156.25MHz, outputs = 100MHz, 125MHz, 156.25MHz, 245.76MHz, 491.52MHz
ROM page 6. XO= 48MHz, REFCLK = 156.25MHz, outputs = 1 Hz (1-PPS), 25MHz, 100MHz, 122.88MHz, 125MHz, 156.25MHz, 245.76MHz,
M M
491.52MHz
ROM page 7. XO= 48MHz, REFCLK = 156.25MHz, outputs = 1 Hz (1-PPS), 20.48MHz, 25MHz, 100MHz, 122.88MHz, 125MHz, 156.25MHz,
M H
245.76MHz, 491.52MHz
H M ROM page 8. XO= 48MHz, REFCLK = 491.52MHz and 156.25MHz, outputs = 25MHz, 122.88MHz, 125MHz, 156.25MHz, 491.52MHz
Table 7-12. ROM Detailed Description

ROM XO IN0 IN1 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11
0 48 156.25 10 100 100 122.88 245.76 312.5 312.5 312.5 312.5 491.52 1.92(1) 491.52 1.92(1)
1 48 10 10 1.92(1) (3) 491.52(3) 100(3) 100 491.52(3) 491.52(3) 491.52 1.92(1) (3) 122.88(3) 122.88(3) 491.52(3) 1.92(1) (3)
2 48 10 10 1.92(1) (3) 491.52 100 100 1.92(1) (3) 491.52 491.52 1.92(1) (3) 122.88 1.92(1) (3) 491.52 1.92(1) (3)
3 38.88 156.25 10 1.92(1) (3) 25(3) 100(3) 100(3) 156.25(3) 156.25(3) 156.25(3) 156.25(3) 1.92(1) (3) 122.88(3) 1.92(1) (3) 122.88(3)
4 54 30.72 30.72 125 125 30.72 30.72 161.1x(2) 161.1x(2) 161.1x(2) 161.1x(2) 122.88 122.88 245.76 245.76
5 20 156.25 156.25 100 125 156.25 156.25 245.76 491.52 245.76 7.68(1) 491.52 7.68(1) 491.52 7.68(1)
6 48 156.25 156.25 1E-6(1) (3) 125 100 100 25 125(3) 156.25 156.25(3) 245.76(3) 7.68(1) (3) 491.52(3) 7.68(1) (3)
7 48 156.25 156.25 1E-6(1) 125 100 100 25 125 156.25 156.25 245.76 7.68(1) 491.52 7.68(1)
8 48 491.52 156.25 125 25 312.5 156.25 491.52 7.68(1) 491.52 7.68(1) 491.52 7.68(1) 491.52 7.68(1)
(1) The output clock is sourced from the SYSREF channel divider.
(2) The exact output clock frequency is 161.1328125MHz.
(3) The output clock frequency is configured but the output channel is disabled.

LMK5C22212AS1
7.4.4.6 EEPROM Overlay

An integrated EEPROM supports user-customized output clocks on start-up when the ROM pages do not meet
the start-up clocking requirements. The DPLL, SYSREF, and GPIO registers are not set by the EEPROM values
and are instead initialized by the ROM Page Selection. If the loaded DPLL settings from the ROM page are not
valid for a system, the APLLs lock to the XO input instead. The DPLL reference inputs are considered valid and
can lock to the DPLL once the DPLL registers are properly configured.
The device EEPROM overlay can be set by the ROM_PLUS_EE bit (R20[7]), which is stored in EEPROM. The
factory default EEPROM setting for the ROM_PLUS_EE bit is 0.
• ROM_PLUS_EE = 0: The device is started with just the ROM settings.
• ROM_PLUS_EE = 1: The EEPROM overlay overwrites the XO, APLL, and output driver settings initialized
from the ROM page selection.
7.4.5 Programming
ADVANCE INFORMATION
7.4.5.1 Memory Overview

The LMK5C22212AS1 has four memory spaces.
1. Registers – Contains the active register settings currently used by the device.
2. ROM – Contains all register settings (DPLL, SYSREF, GPIO, XO, APLL, and output driver). Has default
ROM pages that are not user programmable. See ROM Page Selection.
3. EEPROM – Contains partial register settings (APLL and output). Can be programmed numerous times
through I2C or SPI (refer to the Absolute Maximum Ratings for the maximum number of programming
cycles). See EEPROM Overlay.
4. SRAM – Contains the same address and data mapping as the EEPROM. Use only for programming the
EEPROM.
Mask ROM
Select ROM Mode (9 Pages)
(Page 0 to 8)
Addr: 0x000 to
0x2000 - Initialize Registers from ROM Page
Data: 8192 bytes
Memory
Interface
PD#
Control/ GPIO0
Status Pins
GPIO1
Device Serial Registers Device Blocks
GPIO2 Control Interface Block Interface (Inputs, PLLs,
and Addr: 0x000 to 0x50A Outputs,
Status Data: 1291 bytes Monitors, etc.)
SCS_ADD
I2C/SPI
Pins SCL/SCK
SDA/SDIO
Memory Memory
Interface Interface
- Write SRAM (Commit Registers)

- Initialize Registers from EEPROM
- Read SRAM
- Read EEPROM
Program
SRAM NVM EEPROM
EEPROM
Addr: 0x00 to 0x7F Addr: 0x00 to 0x7F
Data: 128 bytes Data: 128 bytes
Select EEPROM Mode
Figure 7-42. Device Control, Register, and Memory Interfaces

LMK5C22212AS1
7.4.5.2 Interface and Control

After start-up, a system host device (MCU or FPGA) can use either I2C or SPI to initialize, control, or monitor
the registers and to access the SRAM and EEPROM maps. Some device features can also be controlled and
monitored through the external logic control (GPIOx) and status pins. A 2-byte address and 1-byte data interface
is used for the LMK5C22212AS1 .
In the absence of a host, the LMK5C22212AS1 can self-start from one of the on-chip ROM pages and EEPROM
overlay to initialize the registers upon device POR, see Device Start-Up.
7.4.5.2.1 Programming Through TICS Pro
The TICS Pro software tool for EVM programming has a step-by-step design flow to enter the user-selected
clock design parameters, calculate the frequency plan, and generate the device register settings for the desired
configuration. The register map data file (hex dump in text format) and EEPROM programming sequence can be
exported to enable host programming of the device on start-up.
ADVANCE INFORMATION
If desired, customers can post a TICS Pro setup file (.tcs) to the TI E2E public forum for TI to review and
optimize the configuration settings.
7.4.5.2.2 SPI Serial Interface
When SPI control interface is selected, the device uses a 3-wire SPI with SDIO, SCK, and SCS signals
(SPI_3WIRE_DIS = 0). When using SPI SCS_ADD also can act as a Time Elapsed Counter (TEC) trigger. When
set SPI_3WIRE_DIS = 1, any GPIO can be selected as SDO to support readback with 4-wire SPI.
SPI and GPIO I/O are referenced to the 3.3-V power supply and the output drivers are 3.3-V LVCMOS
compatible. The inputs are 1.8-V, 2.5-V, or 3.3-V LVCMOS compatible. When the SPI host is 3.3-V I/O, either
3-wire or 4-wire can be used without any voltage conversion. When the SPI host is not 3.3-V I/O complaint, the
SDO signal from LMK5C22212AS1 device must be divided to be compatible with the SPI host voltage level. The
SDO pin can also be configured for open drain so the pullup resistors set the read back voltage as desired.
The host device must present data to the device MSB first. A message includes a transfer direction bit ( W/R), a
15-bit address field (A14 to A0), and a 8-bit data field (D7 to D0) as shown in Figure 7-43. The W/R bit is 0 for a
SPI write and 1 for a SPI read.
MSB LSB
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSB Transmitted First
First Out A A A A A A A A A A A A A A A D D D D D D D D
Bit Definition
W/R
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Register Address (15 bits) Data Payload (8 bits) Message Field Definition
Figure 7-43. SPI Message Format
A message frame is initiated by asserting SCS low. The frame ends when SCS is deasserted high. The first bit
transferred is the W/R bit. The next 15 bits are the register address, and the remaining eight bits are data. On
write transfers, data is committed in bytes as the final data bit (D0) is clocked in on the rising edge of SCK. If the
write access is not an even multiple of eight clocks, the trailing data bits are not committed. On read transfers,
data bits are clocked out from the SDO pin on the falling edges of SCK.
7.4.5.2.2.1 SPI Block Register Transfer

The LMK5C22212AS1 supports a SPI block write and block read transfers. A SPI block transfer is exactly (2
+ N) bytes long, where N is the number of data bytes to write or read. The host device (SPI host) is only
required to specify the lowest address of the sequence of addresses to be accessed. The device automatically
increments the internal register address pointer if the SCS pin remains low after the host finishes the initial 24-bit
transmission sequence. Each transfer of eight bits (a data payload width) results in the device automatically
incrementing the address pointer (provided the SCS pin remains active low for all sequences).

LMK5C22212AS1
7.4.5.2.3 I2C Serial Interface

When GPIO1 = 0, the device operates as an I2C client and supports bus rates of 100kHz (standard mode) and
400kHz (fast mode). Slower bus rates can work as long as the other I2C specifications are met.
The five MSBs of the 7-bit I2C address are initialized from the EEPROM at start-up, see EEPROM Programming
With the Direct Writes Method or Mixed Method as well as Five MSBs of the I2C Address and the EEPROM
Revision Number.
The two LSBs of the I2C address are defined by the SCS_ADD pin state at start-up.
Table 7-13 shows the I2C address options based on the EEPROM default for the five MSBs of the I2C address
and the SCS_ADD state.
Table 7-13. I2C Address Options
5 MSBs of I2C
2 LSBs of I2C
ADDRESS (FACTORY SCS_ADD PIN STATE I2C ADDRESS
ADVANCE INFORMATION
ADDRESS
DEFAULT)
0x19 Low 0 0x64
0x19 Vmid 2 0x66
0x19 High 1 0x65

LMK5C22212AS1
Write Transfer
1 7 1 1
S Secondary Address Wr A
8 1 8 1
Register Address High A Register Address Low A
8 1 1
Data Byte A P
Read Transfer
ADVANCE INFORMATION
1 7 1 1
8 1 8 1
1 7 1 1
Sr Secondary Address Rd A
8 1 1
Data Byte A P
Legend
S Sr Start condition sent by controller device | Repeated start condition sent by controller device
Wr Rd Write bit = 0 sent by controller device | Read bit = 1 sent by controller device
A A Acknowledge sent by controller device | Acknowledge sent by peripheral device
P Stop condition sent by controller device
N N Not-acknowledge sent by controller device | Not-acknowledge sent by peripheral device
Data Data
Data Data sent by controller device | Data sent by peripheral device
Figure 7-44. I2C Byte Write and Read Transfers

LMK5C22212AS1
I2C Block Register Transfers

Figure 7-45 shows that the device supports I2C block write and block read register transfers.
Block Write Transfer
1 7 1 1
8 1 8 1
8 1 8 1 1
Data Byte A Data Byte A P

ADVANCE INFORMATION
Block Read Transfer
1 7 1 1
8 1 8 1
1 7 1 1
Sr Secondary Address Rd A
8 1 8 1 1
Data Byte A Data Byte A P
Figure 7-45. I2C Block Register Transfers
7.4.5.3 General Register Programming Sequence

For applications that use a system host to program the initial configuration through I2C or SPI after power up,
this general procedure can be followed:
1. Apply power to the device to start in I2C or SPI mode (see Device Start-Up).
2. Set all outputs to static low to verify that there are no glitches at startup.
a. For all outputs, configure the OUT_x_CONFIGURATION registers.
b. For only OUT0 and OUT1, configure the OUT_x_CONFIGURATION and the OUT_x_STATIC_LOW
registers.
3. Write to all of the registers EXCEPT the following registers:
a. The registers listed in Step 2.
b. R25[0] (SYNC_EN)
c. R21[6] (SYNC_SW)
d. R23[6] (SWRST)
e. (DPLLx_SWRST)
f. (APLLx_SWRST)
4. Perform global, DPLL, and APLL software resets by writing:
a. SWRST = 1
b. APLLx_SWRST = 1
c. DPLLx_SWRST = 1

LMK5C22212AS1
d. SWRST = 0
e. Note: The DPLLx_SWRST and APLLx_SWRST are self-clearing bits.
5. Wait for the APLL or APLLs to lock by polling the PLL loss of lock status registers, LOL_PLLx, before
asserting SYNC_EN and SYNC_SW.
6. Assert SYNC by writing:
a. SYNC_EN = 1
b. SYNC_SW = 1
7. Modify the output registers listed in Step 2: change from static low to the desired output states.
8. Dessert SYNC by writing:
a. SYNC_SW = 0
b. SYNC_EN = 0 (optional and not required)
9. Optional, but recommended: Clear the interrupt (INTR) status flags. These bits are not self-clearing (sticky)
and can get set during start-up while the DPLL and APLL registers are not yet properly configured.
ADVANCE INFORMATION
Alternatively, use the part-specific TICS Pro profile to export a customized register programming sequence for
the currently loaded .tcs file as shown in Figure 7-46.
Figure 7-46. LMK5xxxxxx TICS Pro Programming Page (Screenshot From v1.7.7.4.)
7.4.5.4 Steps to Program the EEPROM

The first step is to program the SRAM with the desired register settings. The next step is to program the
EEPROM through an automatic SRAM to EEPROM transfer. For more details on each step, refer to the listed
sections:
1. Overview of the SRAM Programming Methods
2. EEPROM Programming With the Register Commit Method and
EEPROM Programming With the Direct Writes Method or Mixed Method
7.4.5.4.1 Overview of the SRAM Programming Methods
The register data can be written to the SRAM by any of three methods:
1. Register Commit Method
a. Uses the REGCOMMIT bit to enable the automatic transfer (mapping) of the active registers to SRAM.
b. Modifies the SRAM and EEPROM by using the contents of the active registers.
c. Does not require knowledge of the SRAM and EEPROM mapping.
d. Cannot be used to modify the following EEPROM fields: TARGET_ADR_MSB and EEREV.

LMK5C22212AS1
e. Recommended for most applications and when pre-programming the device.

2. Direct Writes Method
a. Requires direct and manual writes to each SRAM address.
b. Modifies the SRAM and EEPROM without writing to the active register space, which allows the device to
continue normal operation without disruption.
c. Requires knowledge of the SRAM and EEPROM mapping.
d. Can be used to modify the following EEPROM fields: TARGET_ADR_MSB and EEREV.
e. Recommended when programming the EEPROM in-system (such as for a version update) to avoid
output interruption.
f. Recommended when overwriting all of the SRAM.
3. Mixed Method (Register Commit and Direct Writes)
a. Recommended when only modifying select fields in SRAM, such as the TARGET_ADR_MSB and
EEREV.
b. Not recommended when overwriting all of the SRAM through the Direct Writes method.
ADVANCE INFORMATION
7.4.5.4.2 EEPROM Programming With the Register Commit Method

1. Power cycle (toggle PD#).
2. Write to the active registers with the desired configuration and confirm the output clocks behave as
expected.
3. Commit active registers to SRAM by setting R171[6] (REGCOMMIT) to 1.
a. Note: REGCOMMIT is auto-cleared to 0 when the transfer is completed.
4. Enable EEPROM overlay by setting R20[7] (ROM_PLUS_EE) to 1.
5. Unlock EEPROM by setting to R180 (NVMUNLK) to 234.
6. In one transaction:
a. Erase the contents of the EEPROM by setting R171[1] (NVMERASE) to 1.
b. Initiate EEPROM programming to transfer the SRAM contents to EEPROM by setting R171[0]
(NVMPROG) to 1.
c. Note: Step 5 & 6 must be atomic (back-to-back) writes without any other register transactions in-
between. Serial communication interruptions (such as access to other devices on the same bus) is also
not allowed for successful EEPROM programming.
7. Wait for EEPROM programming to finish by polling R171[2] (NVMBUSY) until cleared or wait about 500ms.
a. Note: Do not power down, PD# toggle, or continue to the next step until NVMBUSY is cleared to have a
successful EEPROM programming.
8. Lock the EEPROM by setting NVMUNLK to 0.
9. At the next POR, if the EEPROM programming is successful, the EEPROM program count, R16 (NVMCNT),
increments by 1. Also, if the EEPROM overlay bit is set, the active registers are loaded from EEPROM.
Hex instruction list:
R171 0x00AB40 # Set REGCOMMIT

R20 0x001480 # Enable EEPROM OVERLAY
R180 0x00B4EA # UNLOCK EEPROM
R171 0x00AB03 # ERASE and PROGRAM SRAM contents to EEPROM
while(READ_REG(NVMBUSY) != 0) # NVMBUSY is located in 0xAB, bit 2
R180 0x00B400 # LOCK EEPROM
7.4.5.4.3 EEPROM Programming With the Direct Writes Method or Mixed Method
1. Attain the SRAM mapping of your desired configuration. The SRAM map is generated in TICS Pro. For the
TARGET_ADR_MSB and EEREV mapping, see Five MSBs of the I2C Address and the EEPROM Revision
Number.
2. Mixed method only: Commit active registers to SRAM by setting REGCOMMIT (R171[6]) to 1.
a. Note: REGCOMMIT is auto-cleared to 0 when the transfer is completed.
3. Enable EEPROM overlay by setting R20[7] (ROM_PLUS_EE) to 1.
4. Configure the SRAM address pointer by setting R173[4:0] (MEMADR_12:8) to the 5 MSBs of the SRAM
address.

LMK5C22212AS1
5. Configure the SRAM address pointer by R174 (MEMADR) to the 8 LSBs of the SRAM address.
6. Store the desired data at the specified SRAM address by setting R176 (RAMDAT) to the SRAM data from
the SRAM map.
7. Repeat steps 4-6 for all desired SRAM addresses.
8. Unlock EEPROM by setting to R180 (NVMUNLK) to 234.
9. In one transaction:
a. Erase the contents of the EEPROM by setting NVMERASE (R171[1]) to 1.
b. Initiate EEPROM programming to transfer the SRAM contents to EEPROM by setting NVMPROG
(R171[0]) to 1.
c. Note: Step 5 & 6 must be atomic (back-to-back) writes without any other register transactions in-
between. Serial communication interruptions (such as access to other devices on the same bus) is also
not allowed for successful EEPROM programming.
10. Wait for EEPROM programming to finish by polling R171[2] (NVMBUSY) until cleared or wait about 500ms.
a. Note: Do not power down, PD# toggle, or continue to the next step until NVMBUSY is cleared to have a
ADVANCE INFORMATION
successful EEPROM programming.
11. Lock the EEPROM by setting NVMUNLK to 0.
12. At the next POR, if the EEPROM programming is successful, the EEPROM program count, R16 (NVMCNT),
increments by 1. Also, if the EEPROM overlay bit is set, the active registers are loaded from EEPROM.
Hex instruction example for changing the TARGET_ADR_MSB:
R171 0x00AB40 # Set REGCOMMIT (Mixed Method only)

R20 0x001480 # Enable EEPROM OVERLAY
R173 0x00AD00 # Set 5 MSBs of SRAM address
R174 0x00AE0C # Set 8 LSBs of SRAM address
R176 0x00B019 # Set 5 MSBs of desired I2C address
R180 0x00B4EA # UNLOCK EEPROM

R171 0x00AB03 # ERASE and PROGRAM SRAM contents to EEPROM
while(READ_REG(NVMBUSY) != 0) # NVMBUSY is located in 0xAB, bit 2
R180 0x00B400 # Lock EEPROM
Hex instruction example for changing the EEREV:

7.4.5.4.4 Five MSBs of the I2C Address and the EEPROM Revision Number
Table 7-14 summarizes the SRAM and EEPROM addresses of the TARGET_ADR_MSB and EEREV fields.
These bytes can only be written by EEPROM Programming With the Direct Writes Method or Mixed Method.
Modifying these bytes from the factory default settings is optional.
Table 7-14. User-Programmable Fields in EEPROM
SRAM/EEPROM SRAM/EEPROM
SRAM/EEPROM
ADDRESS BYTE # ADDRESS BYTE # DESCRIPTION
FIELD NAME
(DECIMAL) (HEX)
I2C Target Address MSB Bits
TARGET_ADR_MSB[7:3] can be written to set the five MSBs of the
7-bit peripheral address. TARGET_ADR_MSB[2:0] must be written with
zeros.
12 0x0C TARGET_ADR_MSB TARGET_ADR_MSB can only be modified by programming the SRAM
and EEPROM. The TARGET_ADR_MSB value that is currently used by
the device can be readback by the read-only register, R18.
For more I2C address details, refer to GPIO1 and SCS_ADD
Functionalities and I2C Serial Interface.

LMK5C22212AS1
Table 7-14. User-Programmable Fields in EEPROM (continued)

SRAM/EEPROM SRAM/EEPROM
SRAM/EEPROM
ADDRESS BYTE # ADDRESS BYTE # DESCRIPTION
FIELD NAME
(DECIMAL) (HEX)
EEPROM Image Revision Number.
EEREV can be written to set the EEPROM image revision number or
any customer-specific data for part traceability.
13 0x0D EEREV
EEREV can only be modified by programming the SRAM and
EEPROM. The EEREV value that is currently used by the device can be
readback by the read-only register, R19.
8 Application and Implementation

Note
ADVANCE INFORMATION
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information

8.1.1 Device Start-Up Sequence
Device Power-On Reset (POR) shows the device start-up sequence.
8.1.2 Power Down (PD#) Pin
The PD# pin (active low) can be used for device power down and used to initialize the POR sequence. When
PD# is pulled low, the entire device is powered down and the serial interface is disabled. When PD# is pulled
high, the device POR sequence is triggered to begin the device start-up sequence and normal operation as
depicted in Table 8-1. If the PD# pin is toggled to issue a momentary hard-reset, the negative pulse applied to
the PD# pin must be greater than 200 ns to be captured by the internal digital system clock.
Table 8-1. PD# Control
PD# PIN STATE DEVICE OPERATION
0 Device is disabled
1 Normal operation
8.1.3 Strap Pins for Start-Up

At start-up, voltage level on GPIOs determine the operation mode of the device. GPIO1 selects SPI or I2C mode.
GPIO2 and GPIO0 select ROM page.
8.1.4 Pin States
Table 8-2 shows the different pin states of the device.
Table 8-2. Pin States in Different Stages
PIN NAME POWER STATES POR (SPI) STATES POR (I2C) STATES NORMAL STATES SOFT STATES
DOWN OPERATI RESET
ON
PD# LOW 2-level PD# transitions LOW to PD# transitions LOW to HIGH 2-level HIGH 2-level
input HIGH HIGH input input
GPIO0 Ready for 3-level EEPROM/ 3-level EEPROM/ 3-level See table GPIO N/A
POR input ROM input ROM input
select select
GPIO1 Ready for 2-level VDD 2-level GND 2-level See table GPIO N/A
POR input input input

LMK5C22212AS1
Table 8-2. Pin States in Different Stages (continued)

PIN NAME POWER STATES POR (SPI) STATES POR (I2C) STATES NORMAL STATES SOFT STATES
DOWN OPERATI RESET
ON
GPIO2 Ready for 3-level EEPROM/ 3-level EEPROM/ 3-level See table GPIO N/A
POR input ROM input ROM input
select select
SCS_A DD Ready for 3-level SCS 2-level I2C 3-level 2-level or 3-level input N/A
POR input input address input based on POR
select
SDIO N/A SDIO Data I/O SDA Data I/O SDIO or SDA control interface serial data input/
output based on POR
SCK N/A SCK Clock input SCL Clock input SCK or SCL control interface serial clock input
based on POR
ADVANCE INFORMATION
8.1.5 ROM and EEPROM
Some applications require start-up clocks to operate the entire system at power on. Other applications can
only require a valid clock for the logic device (CPU, ASIC, or FPGA) at power on which can then program
the LMK5C22212AS1 with custom settings if the default ROM configuration does not meet the application
requirements. The LMK5C22212AS1 provides ROM pages to support default output clocks on start-up and
an EEPROM to allow customization of the start-up clocks if the ROM pages do not meet the application
requirements. See ROM Page Selection and EEPROM Overlay for more information.
8.1.6 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
8.1.6.1 Power-On Reset (POR) Circuit
The LMK5C22212AS1 integrates a built-in power-on reset (POR) circuit that holds the device in reset until all of
the following conditions have been met:
• All VDD core supplies have ramped above 2.72 V
• PD# pin has ramped above 1.2 V (minimum VIH)
8.1.6.2 Power Up From a Single-Supply Rail
As long as all VDD and VDDO supplies are driven by the same 3.3V supply rail that ramp in a monotonic
manner from 0V to 3.135V, and the time between decision point 2 and stabilized supply voltage is less than
1ms, then there is no requirement to add a capacitor on the PD# pin to externally delay the device power-up
sequence. Figure 8-1 shows that the PD# pin can be left floating or otherwise driven by a system host to meet
the clock sequencing requirements in the system.
If time between decision point 2 and stabilized supply voltage is greater than 1ms, then the PD# pin must be
delayed. Refer to Power Up From Split-Supply Rails.
As described in Slow or Delayed XO Start-Up, validating the XO reference after PD# decision point 1 is
necessary to provide a successful calibration of the VCOs and to capture a valid DPLL reference reading.

LMK5C22212AS1
Voltage
VDD_IN Decision Point 3:

VDDO_x
3.135V
200k Decision Point 2:
VDD_PLLx/VDD_IN/
PD# VDD_DIG
2.72V
Decision Point 1:
PD#
1.2V
0V
Time
XO Reference: Valid or Invalid
Valid XO REF
ADVANCE INFORMATION
XO REF
Figure 8-1. Recommendation for Power Up From a Single-Supply Rail
8.1.6.3 Power Up From Split-Supply Rails

If VDD or VDDO supplies are driven from different supply sources, TI recommends to start the PLL calibration
after all of the supplies have ramped above 3.135V. This can be realized by delaying the PD# low-to-high
transition. The PD# input incorporates a 200kΩ resistor to VDD_IN and as shown in Figure 8-2. A capacitor
from the PD# pin to GND can be used to form an RC time constant with the internal pullup resistor. This RC
time constant can be designed to delay the low-to-high transition of PD# until all the core supplies have ramped
above 3.135V. Ramping the VDDO supply pins before the VDD supply pins is recommended.
Alternatively, the PD# pin can be driven high by a system host or power management device to delay the device
power-up sequence until all supplies have ramped.
As described in Slow or Delayed XO Start-Up, the XO reference must be valid after PD# decision point 3 to
provide a successful calibration of the VCOs and to capture a valid DPLL reference reading.
Voltage
VDD_IN Decision Point 1:
VDDO_x
200kΩ ≥ 3.135V
PD# Decision Point 2:
VDD_PLLx/VDD_IN/ Delay ≥
VDD_DIG 100µs
CPD# ≥ 2.72V
Decision Point 3:
PD#
≥ 1.2V
0V
Time
XO Reference: Valid or Invalid XO REF Valid XO REF
Figure 8-2. Recommendation for Power Up From Split-Supply Rails

LMK5C22212AS1
8.1.6.4 Non-Monotonic or Slow Power-Up Supply Ramp

In case the VDD core supplies ramp with a non-monotonic manner or with a slow ramp time from 0V to
3.135V of over 100ms, TI recommends to delay the VCO calibration until after all of the core supplies have
ramped above 3.135V. This cam be achieved by delaying the PD# low-to-high transition with one of the methods
described in Power Up From Split-Supply Rails.
If any core supply cannot ramp above 3.135V before the PD# low-to-high transition, issuing a device soft-reset
after all core supplies have ramped is acceptable to manually trigger the VCO calibration and PLL start-up
sequence.
8.1.7 Slow or Delayed XO Start-Up
Because the external XO clock input is used as the reference input for the BAW APLL and conventional
APLL calibration, the XO input amplitude and frequency must be stable before the start of VCO calibration to
provide successful PLL lock and output start-up. If the XO clock is not stable prior to VCO calibration, the VCO
ADVANCE INFORMATION
calibration can fail and prevent PLL lock and output clock start-up.
If the XO clock has a slow start-up time or has glitches on power-up (due to a slow or non-monotonic power
supply ramp, for example), TI recommends to delay the start of VCO calibration until after the XO is stable. This
can be achieved by delaying the PD# low-to-high transition until after the XO clock has stabilized using one of
the methods described in Power Up From Split-Supply Rails. Issuing a device soft-reset is also possible after the
XO clock has stabilized to manually trigger the VCO calibration and PLL start-up sequence.
The BAW APLL/VCBO is factory calibrated and is not sensitive to an invalid XO reference start-up. Upon a valid
XO reference, the BAW APLL/VCBO can acquire lock. When the BAW APLL/VCBO is used in conjunction with
the paired DPLL, the XO must be valid before the paired DPLL reference is validated.
8.2 Typical Application
Figure 8-3 shows a reference schematic to help implement the LMK5C22212AS1 and the peripheral circuitry.
Power filtering examples are given for the core supply pins and independent output supply pins. Single-ended
LVCMOS, LVDS, HSDS, AC-LVPECL, and HCSL clock interfacing examples are shown for the clock input
and output pins. An external CMOS oscillator drives an AC-coupled voltage divider network as an example to
interface the 3.3V LVCMOS output to meet the input voltage swing specified for the XO input. The XO pin of
the LMK5C22212AS1 can accept 3.3V LVCMOS input. The required external capacitors are placed close to the
LMK5C22212AS1 and are shown with the suggested values. External pullup and pulldown resistor options at the
logic I/O pins set the default input states. The I2C or SPI pins and other logic I/O pins can be connected to a host
device (not shown) to program and control the LMK5C22212AS1 and monitor the status.

LMK5C22212AS1
C4, C5, C10, C11, C12 sized for POR brownout
FB1 oponal if IN0 is unused withstand. Values can poten ally be reduced.
FB2 oponal if IN1 is unused
VCC VCC
FB1 0.3A VDD_IN0 FB5 0.5A VDD_XO U1
0402 220 ohm 0402 220 ohm
VDD_DIG 41 VDD_DIG OUT0_P 2 O0_P
C10 44 OUT0_N 3 O0_N
0.1uF 10uF VDD_DIG
FB2 0.3A VDD_IN1 0402 0402 VDD_XO 8 VDD_XO OUT1_P 5 O1_P
0402 220 ohm OUT1_N 4 O1_N
GND VDD_APLL2 23 VDD_APLL2
OUT2_P 12 O2_P
VCC VCC VDD_APLL1 47 VDD_APLL1 OUT2_N 13 O2_N
FB3 0.3A VDD_DIG FB6 0.5A VDD_APLL2
0402 220 ohm 0402 220 ohm VDD_IN0 33 OUT3_P 15 O3_P
VDD_IN0
OUT3_N 14 O3_N
C4 C11 VDD_IN1 37 VDD_IN1
0.1uF 1uF 10uF OUT4_P 24 O4_P
0402 0402 0402 VDDO_01 1 OUT4_N 25 O4_N
VDDO_0_1
GND GND VDDO_23 11 27 O5_P
VDDO_2_3 OUT5_P
OUT5_N 26 O5_N
VCC VCC VDDO_4_5 28 VDDO_4_5
FB4 0.5A VDDOx FB7 0.5A VDD_APLL1 29 O6_P
OUT6_P
0402 220 ohm 0402 220 ohm VDDO_6_TO_11 55 VDDO_6_TO_11 30 O6_N
Place close to pins OUT6_N
C5 C12 32 O7_P
C30 10uF CAP_DIG 40 OUT7_P
10uF 10uF GND CAP_DIG 31 O7_N
0201 OUT7_N
0402 0402
C32 10uF CAP1_APLL2 22 OUT8_P 51 O8_P
GND GND GND CAP1_APLL2 52 O8_N
0402 OUT8_N
Replicate for each VDDO supply C33 10uF CAP2_APLL2 21 CAP2_APLL2
C18 GND 54 O9_P
ADVANCE INFORMATION
group. If a supply group is unused, R9 0402 OUT9_P

From XO/TCXO XO 53 O9_N
connect directly to VCC (ferrite bead C34 10uF CAP3_APLL2 20 OUT9_N
GND CAP3_APLL2
and capacitor may be omied). 33 0402
R10 0.1uF 56 O10_P
C35 10uF CAP_APLL1 48 OUT10_P
Op on for voltage divider if DNP GND CAP_APLL1 57 O10_N
needed. Source must be able to 0402 OUT10_N
drive DC path to ground, or AC 0.1uF 59 O11_P
load to ground with added C39 LF2 19 LF2 OUT11_P
GND 58 O11_N
capacitor a er R9. 0201 LF1 49 LF1 OUT11_N
GND C40 0.47uF
GND
0402 6
+1.5 V to +3.3 V SDIO_MCU R12 SDIO (SDA) NC
IN0_P 34 7
100 IN0/IN1 can accept DC IN0_P NC
or AC coupled inputs. IN0_N 35 IN0_N NC
42
R1 R3 R5 R7 R8 C15 Programmable 43
10.0k 10.0k 10.0k 4.70k 4.70k 33pF terminaon opons for IN1_P 39 NC
IN1_P 44
DNP DNP DNP SDIO (SDA) desired input type. IN1_N 38 NC
IN1_N
SCK (SCL) 45
GND NC
GPIO0 XO 9 46
R13 XO NC
GPIO1 SCK_MCU SCK (SCL)
GPIO2 SDIO (SDA) 16 60
100 Input lters recommended for SPI SDIO NC
PD# SCK (SCL) 17 61
communicaon to prevent SCK NC
C16 cross-contamina on to APLL2 VCO SCS (ADD SEL) 18 SCS_ADD 62
33pF NC
through LF2 pin; not required for I2C
R2 R4 R6 C6 GPIO0 50 63
GPIO0 NC
10.0k 10.0k 10.0k 0201 GPIO1 64 GPIO1
0.01uF GND GPIO2 10 GPIO2
SCS_MCU R14 SCS (ADD SEL) PD# 36 65
PD# GND (DAP)
GND 100
GND GND GND LMK5C22212ARGCR
POR: C17 GND
GPIO0 is input, selects ROM to load (VCC, GND, Float) 33pF
GPIO1 is input, selects SPI mode (VCC) or I2C mode (GND)
GPIO2 is input, selects ROM to load (VCC, GND, Float)
GND
Normal Operaon: Clock Outputs
GPIO0: Programmable GPIO
GPIO1: Programmable GPIO
GPIO2: Programmable GPIO HCSL Example LVPECL/CML Example LVDS/HSDS Example LVCMOS Example
Ox_P Ox_P C36 0.1uF

0201
Ox_N Ox_N C37 0.1uF
0201
Load Load
R11 R15 R16 R17 R19 R20 Ox_P Ox_P R22
50 50 49.9 49.9 49.9 R21 0
100
Ox_N 100
GND GND GND GND

GND
Load Load
Figure 8-3. Reference Schematic Example

LMK5C22212AS1
8.2.1 Design Requirements

In a typical application, consider the following design requirements or parameters to implement the overall clock
solution:
1. Device initial configuration. The device must be configured as either host programmed (MCU or FPGA) or
factory preprogrammed.
2. Device interface, set GPIO1 as desired for I2C or SPI communications interface.
3. XO frequency, signal type, and frequency accuracy and stability. Consider a high-stability TCXO or OCXO
for the XO input if any of the following is required:
a. Standard-compliant frequency stability (such as SyncE, SONET/SDH, IEEE 1588)
b. Lowest possible close-in phase noise at offsets ≤ 100Hz
c. Narrow DPLL bandwidth ≤ 10Hz
4. For each DPLL/APLL domain, determine the following:
a. Input clocks: frequency, buffer mode, priority, and input selection mode
ADVANCE INFORMATION
b. APLL reference: another VCO with Cascaded mode, or XO for Non-cascaded mode
c. Output clocks: frequency, buffer mode
d. DPLL loop bandwidth and maximum TDC frequency
e. If the DCO Mode or ZDM is required
5. Input clock and PLL monitoring options
6. Status outputs and interrupt flag
7. Power supply rails
8.2.2 Detailed Design Procedure
In a typical application, TI recommends the following steps:
1. Use the device GUI in the TICS Pro programming software for a step-by-step design flow to enter the design
parameters, calculate the frequency plan for each PLL domain, and generate the register settings for the
desired configuration. The register settings can be exported (registers hex dump in .txt format) to enable
host programming.
• A host device can program the register settings through the serial interface after power-up and issue a
soft-reset (by SWRST bit) to start the device. Set SW_SYNC before, and clear after SWRST.
2. Tie the GPIO1 pin to ground to select the I2C communications interface, or pull up GPIO1 high to VDD_DIG
through an external resistor to select the SPI communications interface. Determine the logic I/O pin
assignments for control and status functions. See GPIO1 and SCS_ADD Functionalities.
• Connect I2C/SPI and logic I/O pins (1.8V compatible levels) to the host device pins with the proper I/O
direction and voltage levels.
3. Select an XO frequency by following Oscillator Input (XO).
• Choose an XO with target phase jitter performance that meets the frequency stability and accuracy
requirements required for the output clocks during free-run or holdover.
• The LMK5C22212AS1 can directly accept a 3.3V LVCMOS input into the XO pin.
• Power the XO from a low-noise LDO regulator or optimize the power filtering to avoid supply noise-
induced jitter on the XO clock.
• TICS Pro: Configure the XO frequency to match the XO input.

LMK5C22212AS1
4. Wire the clock I/O for each APLL domain in the schematic and use TICS Pro to configure the device settings
as follows:
• Reference inputs: Follow the LVCMOS or differential clock input interface guidelines in Clock Input
Interfacing and Termination.
– TICS Pro: For DPLL mode, configure the reference input buffer modes to match the reference clock
driver interface requirements. See Reference Inputs.
• TICS Pro: For DPLL mode, configure the DPLL input selection modes and input priorities. See Reference
Input Mux Selection.
• TICS Pro: Configure each APLL reference from other VCO domain (Cascaded mode) or XO clock
(Non-cascaded mode).
• TICS Pro: Configure each output with the required clock frequency and APLL domain. TICS Pro can
calculate the VCO frequencies and divider settings for the APLL and outputs. Consider the following
output clock assignment guidelines to minimize crosstalk and spurs:
– OUT[0:1] bank can select any APLL clocks, XO, and DPLL references.
ADVANCE INFORMATION
– OUT[2:3], OUT[4:5], and OUT[6:11] banks can source either APLL1 or APLL2 clocks.
– Group identical output frequencies (or harmonic frequencies) on adjacent channels, and use the
output pairs with a single divider (for example, OUT2/3) when possible to minimize power.
– Separate clock outputs when the difference of the two frequencies, |fOUTx – fOUTy|, falls within the jitter
integration bandwidth (for example, 12kHz to 20MHz). Any outputs that are potential aggressors must
be separated by at least four static pins (power pin, logic pin, or disabled output pins) to minimize
potential coupling. If possible, separate these clocks by the placing them on opposite output banks,
which are on opposite sides of the chip for best isolation.
– Avoid or isolate any LVCMOS output (strong aggressor) from other jitter-sensitive differential output
clocks. If an LVCMOS output is required, use dual complementary LVCMOS mode (+/- or -/+) with the
unused LVCMOS output left floating with no trace.
– If not all outputs pairs are used in the application, consider connecting an unused output to a pair of
RF coaxial test structures for testing purposes (such as SMA, SMP ports).
• TICS Pro: Configure the output drivers.
– Configure the output driver modes to match the receiver clock input interface requirements. See Clock
Outputs.
– Configure any output SYNC groups that need the output phases synchronized. See Output
Synchronization (SYNC).
– Configure the output auto-mute modes, and APLL and DPLL mute options. See Output Auto-Mute
During LOL.
• Clock output Interfacing: Follow the single-ended or differential clock output interface guidelines in Clock
Output Interfacing and Termination.
– Differential outputs can be AC-coupled and terminated and biased at the receiver inputs, or DC-
coupled with proper receivers
– LVCMOS outputs have internal source termination to drive 50Ω traces directly. LVCMOS VOH level is
determined by internal LDO programmed voltage (1.8V or 2.65V).
• TICS Pro: Configure the DPLL loop bandwidth.
– Below the loop bandwidth, the reference noise is added to the TDC noise floor and the XO/TCXO/
OCXO noise. Above the loop bandwidth, the reference noise is attenuated with roll-off up to 60dB/
decade. The optimal bandwidth depends on the relative phase noise between the reference input and
the XO. The APLL loop bandwidth can be configured to provide additional attenuation of the reference
input, TDC, and XO phase noise above the APLL bandwidth.
• TICS Pro: Configure the maximum TDC frequency to optimize the DPLL TDC noise contribution for the
desired use case.
– Wired: A 400kHz maximum TDC rate is commonly specified. This supports SyncE and other use
cases using a narrow loop bandwidth (≤10Hz) with a TCXO/OCXO/XO to set the frequency stability
and wander performance.
– Wireless: A 26MHz maximum TDC rate is commonly specified for lowest in-band TDC noise
contribution. This supports wireless and other use cases where close-in phase noise is critical.

LMK5C22212AS1
• TICS Pro: If clock steering is needed (such as for IEEE-1588 PTP), enable DCO mode for the DPLL loop
and enter the frequency step size (in ppb). The FDEV step register is computed according to APLL DCO
Frequency Step Size. Enable the FDEV_TRIG and FDEV_DIR pin control on the GPIO pins if needed.
• TICS Pro: If deterministic input-to-output clock phase is needed, enable the ZDM as required on OUT0,
OUT4, or OUT10. See Section 7.3.19.
5. TICS Pro: Configure the reference input monitoring options for each reference input. Disable the monitor
when not required or when the input operates beyond the monitor's supported frequency range. See
Reference Input Monitoring.
• Frequency monitor: Set the valid and invalid thresholds (in ppm).
• Missing pulse monitor: Set the late window threshold (TLATE) to allow for the longest expected input clock
period, including worst-case cycle-to-cycle jitter. For a gapped clock input, set TLATE based on the number
of allowable missing clock pulses.
• Runt pulse monitor: Set the early window threshold (TEARLY) to allow for the shortest expected input clock
period, including worst-case cycle-to-cycle jitter.
ADVANCE INFORMATION
• 1PPS Phase validation monitor: Set the phase validation jitter threshold, including worst-case input
cycle-to-cycle jitter.
• Validation timer: Set the amount of time the reference input must be qualified by all enabled input
monitors before the input is valid for selection.
6. TICS Pro: Configure the DPLL lock detect and tuning word history monitoring options for each channel. See
PLL Lock Detectors and Tuning Word History.
• DPLL frequency lock and phase lock detectors: Set the lock and unlock thresholds for each detector.
7. TICS Pro: Configure each status output pin and interrupt flag as needed. See Status Outputs and Interrupt.
• Select the desired status signal selection, status polarity, and driver mode (3.3V LVCMOS or open-drain).
Open-drain requires an external pullup resistor.
• If the Interrupt is enabled and selected as a status output, configure the flag polarity and the mask bits for
any interrupt source, and the combinational OR gate, as needed.
8. Consider the following guidelines for designing the power supply:
• Outputs with identical frequency or integer-related (harmonic) frequencies can share a common filtered
power supply.
– Example: 156.25MHz and 312.5MHz outputs on OUT[4:5] and OUT[6:7] can share a filtered VDDO
supply, while 100MHz, 50MHz, and 25MHz outputs on OUT[0:1] and OUT[2:3] can share a separate
VDDO supply.
• See Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains.

LMK5C22212AS1
8.2.3 Application Curves

Refer to the Typical Characteristics section for phase noise plots as outlined in the Table 8-3.
Table 8-3. Table of Graphs
Output Frequency [MHz] Output Format APLL Source Link to Graph
491.52MHz HSDS BAW Go
312.5MHz HSDS Conventional LC (APLL2) Go

ADVANCE INFORMATION

8.3 Best Design Practices

• Power down unused blocks through registers to minimize power consumption.
• Use proper source or load terminations to match the impedance of input and output clock traces for any
active signals to/from the device.
• Leave unused clock outputs floating and powered down through register control.
• Leave unused clock inputs floating.
• If needed, external biasing resistors (10kΩ pullup to 3.3V or 10kΩ pulldown) can be connected on each GPIO
pin to select device operation mode during POR.
• Consider routing each GPIO pin to a test point or high-impedance input of a host device to monitor device
status outputs.
• Consider using a LDO regulator to power the external XO/TCXO/OCXO source.
– High jitter and spurious on the oscillator clock are often caused by high spectral noise and ripple on the
power supply.
• Include dedicated header to access the I2C or SPI of the device, as well as a header pin for ground.
– This can enabled off-board programming for device bring-up, prototyping, and diagnostics using the TI
USB2ANY interface and TICS Pro software tools.
8.4 Power Supply Recommendations

8.4.1 Power Supply Bypassing
Figure 8-4 shows two general placements of power supply bypass capacitors on either the back side or
the component side of the PCB. If the capacitors are mounted on the back side, 0402 components can
be employed. For component side mounting, use 0201 body size capacitors to facilitate signal routing. A
combination of component side and back side placement can be used. Keep the connections between the
bypass capacitors and the power supply on the device as short as possible. Ground the other side of the
capacitor using a low-impedance connection to the ground plane.

LMK5C22212AS1
ADVANCE INFORMATION
(Does not indicate actual location of the device supply pins)
Figure 8-4. Generalized Placement of Power Supply Bypass Capacitors
8.5 Layout
8.5.1 Layout Guidelines
• Isolate input, XO/OCXO/TCXO and output clocks from adjacent clocks with different frequencies and other
nearby dynamic signals.
• Consider the XO/OCXO/TCXO placement and layout in terms of the supply/ground noise and thermal
gradients from nearby circuitry (for example, power supplies, FPGA, ASIC) as well as system-level vibration
and shock. These factors can affect the frequency stability/accuracy and transient performance of the
oscillator.
• Avoid impedance discontinuities on controlled-impedance 50-Ω single-ended (or 100-Ω differential) traces for
clock and dynamic logic signals.
• Place bypass capacitors close to the VDD and VDDO pins on the same side as the IC, or directly below the
IC pins on the opposite side of the PCB. Larger decoupling capacitor values can be placed further away.
• Place external capacitors close to the CAP_x and LFx pins.
• Use multiple vias to connect wide supply traces to the respective power islands or planes if possible.
• Use at least a 6×6 through-hole via pattern to connect the IC ground/thermal pad to the PCB ground planes.
• See the Land Pattern Example, Solder Mask Details, and Solder Paste Example in Section 11.
8.5.2 Layout Example
Below are printed circuit board (PCB) layout examples that show the application of thermal design practices and
a low-inductance ground connection between the device DAP and the PCB. Place the ground return path for the
supply decoupling capacitors close to the DAP. All OUTx pairs configured as differential signals must be routed
differentially and meet the trace impedance requirements (typically 100 ohm differential).
Figure 8-5. PCB Layout Example for LMK5C22212AS1 , Top Layer

LMK5C22212AS1
ADVANCE INFORMATION
Figure 8-6. PCB Layout Example for LMK5C22212AS1 , Bottom Layer
8.5.3 Thermal Reliability

The LMK5C22212AS1 is a high-performance device. To provide good electrical and thermal performance, TI
recommends to design a thermally-enhanced interface between the IC ground or thermal pad and the PCB
ground using at least a 6×6 through-hole through pattern connected to multiple PCB ground layers (see Figure
8-7).

LMK5C22212AS1
Component Side
VQFN-64
ADVANCE INFORMATION
Solder Mask Thermal Slug
(package bottom)
Internal
Internal Signal Ground
and Power Planes Planes
Thermal
Thermal Vias Dissipation
Pad (back side)
No Solder Mask
Back Side
Figure 8-7. General PCB Ground Layout for Thermal Reliability (8+ Layers Recommended)
9 Device and Documentation Support

9.1 Documentation Support
9.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, LMK5C22212AS1 EVM User's Guide
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.

LMK5C22212AS1
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
ADVANCE INFORMATION
specifications.
10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
November 2024 * Initial Release
11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

LMK5C22212AS1
PACKAGE OUTLINE
RGC0064E SCALE 1.500
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
9.15 A
B
8.85
PIN 1 INDEX AREA
9.15
8.85
ADVANCE INFORMATION
1.0
0.8 C
SEATING PLANE
0.05 0.08 C
0.00
2X 7.5
EXPOSED SYMM
THERMAL PAD (0.1) TYP
17 32
16 33
SYMM 65
2X 7.5 6.25 0.1
60X
0.5
1 48 0.30
PIN 1 ID 64X
64 49 0.18
0.1 C A B
0.5
64X 0.05
0.3
4225008/A 05/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com

LMK5C22212AS1
EXAMPLE BOARD LAYOUT

RGC0064E VQFN - 1 mm max height
( 6.25)
SYMM SEE SOLDER MASK

64X (0.6) DETAIL
64 49
64X (0.24)
1
48
60X (0.5)
(2.875)
TYP
ADVANCE INFORMATION
(R0.05) TYP
(1.19) TYP
SYMM 65 (0.595) TYP
(8.8)
( 0.2) TYP
VIA
16 33
17 32
(0.595) TYP (1.19)
TYP
(2.875)
(8.8)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X
0.07 MIN
0.07 MAX ALL AROUND
ALL AROUND
METAL UNDER
METAL EDGE SOLDER MASK
EXPOSED METAL
SOLDER MASK EXPOSED SOLDER MASK
OPENING METAL OPENING
NON SOLDER MASK

DEFINED SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4225008/A 05/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com

LMK5C22212AS1
EXAMPLE STENCIL DESIGN

RGC0064E VQFN - 1 mm max height
SYMM
64X (0.6) 64 49
64X (0.24)
1
48
60X (0.5)
ADVANCE INFORMATION
(R0.05) TYP
(1.19) TYP
65
SYMM (8.8)
25X ( 0.99)
16 33
17 32
(1.19)
TYP
(8.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL
SCALE: 10X
EXPOSED PAD 65
63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
4225008/A 05/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com

IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated

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LMK5C22212AS1

SNAS922 – NOVEMBER 2024

LMK5C22212AS1 2-DPLL 2-APLL 2-IN 12-OUT Network Synchronizer With

Low Jitter Radio DEVCLK

Radio SYSREF Clocks

Network Sync Clock

GPS/ 10MHz/ 1PPS (opt)

Register I2C or SPI Control Interface

control PCIe REFCLK (opt)

CPU REF_CLK FPGA/CPU

LMK5C22212AS1 Typical System Block Diagram

2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: LMK5C22212AS1

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

4 Pin Configuration and Functions

Figure 4-1. LMK5C22212AS1 RGC Package 64-Pin VQFN Top View

Table 4-1. LMK5C22212AS1 Pin Functions

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Product Folder Links: LMK5C22212AS1

Table 4-1. LMK5C22212AS1 Pin Functions (continued)

IN1_P 39 I Reference input to DPLLx or buffered to OUT0 or OUT1. Refer to Reference

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5

Table 4-1. LMK5C22212AS1 Pin Functions (continued)

POR: See ROM Page Selection

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Product Folder Links: LMK5C22212AS1

5.2 ESD Ratings

5.3 Recommended Operating Conditions

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7

5.4 Thermal Information

5.5 Electrical Characteristics

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Product Folder Links: LMK5C22212AS1

Over Recommended Operating Conditions (unless otherwise noted)

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9

Over Recommended Operating Conditions (unless otherwise noted)

fout < 100MHz, Iout = 4mA 350 400 440 mV

100MHz ≤ fout ≤ 325MHz, Iout = 8mA 680 800 920 mV

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Product Folder Links: LMK5C22212AS1

Over Recommended Operating Conditions (unless otherwise noted)

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11

Over Recommended Operating Conditions (unless otherwise noted)

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Product Folder Links: LMK5C22212AS1

Over Recommended Operating Conditions (unless otherwise noted)

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13

Over Recommended Operating Conditions (unless otherwise noted)

INx = 8kHz, INy = 8kHz, frequency

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Product Folder Links: LMK5C22212AS1

Over Recommended Operating Conditions (unless otherwise noted)

Analog delay absolute accuracy for any

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15

Over Recommended Operating Conditions (unless otherwise noted)

Open Drain Output (GPIO0, GPIO1, GPIO2, SDA)

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Product Folder Links: LMK5C22212AS1

Over Recommended Operating Conditions (unless otherwise noted)

5.6 Timing Diagrams