19L405-COMPUTER ARCHITECTURE

22L210 – DARSHANA

DATAPATH COMPONENT AND CONTROL PATH DESIGN USING

VERILOG

Dissertation submitted on Partial Fulfillment of the requirements of the degree of

BACHELOR OF ENGINEERING
Branch: ELECTRONICS AND COMMUNICATION
ENGINEERING
Affiliated to Anna University

March 2024

DEPARTMENT ELECTRONICS AND

COMMUNICATION ENGINEERING
PSG COLLEGE OF TECHNOLOGY
(Autonomous Institution)
Coimbatore – 641 004

1
 Add and shift multiplication algorithm

Aim:
Design and Simulate Shift and Add Multiplication Algorithm using Verilog HDL
structural level modelling.

HADWARE DIAGRAM:

FLOWCHART:
EXAMPLE PROBLEM:

VERILOG CODE:
DESIGN SOURCE:
module shiftadd(
input signed[7:0]a,//multiplicand
 input signed[7:0]b,//multiplier
output [14:0]result
);
wire [13:0]a1, a2, a3, a4,a5,a6,a7;
wire [7:0]a8;
wire sign;
assign a8= a[7]==0?a:(~a+1);
assign a1=(b[0]==1'b1)?{7'd0,a8[6:0]}:{14'd0};
assign a2=(b[1]==1'b1)?{6'd0,a8[6:0],1'b0}:{14'd0};
assign a3=(b[2]==1'b1)?{5'd0,a8[6:0],2'b0}:{14'd0};
assign a4=(b[3]==1'b1)?{4'd0,a8[6:0],3'b0}:{14'd0};
assign a5=(b[4]==1'b1)?{3'd0,a8[6:0],4'b0}:{14'd0};
assign a6=(b[5]==1'b1)?{2'd0,a8[6:0],5'b0}:{14'd0};
assign a7=(b[6]==1'b1)?{1'd0,a8[6:0],6'b0}:{14'd0};
assign sign=a[7]^b[7];
assign result=
sign==0?{sign,(a1+a2+a3+a4+a5+a6+a7)}:{sign,(~(a1+a2+a3+a4+a5+a6+a7)+1)};
endmodule
TESTBENCH:
module shiftadd_tb();
reg signed[7:0]a;//multiplicand
reg signed[7:0]b;//multiplier
wire [14:0]result;
initial
begin
a=8'b11111001;b=8'b00000110;
#5 a=8'b00000111;b=8'b00001010;
#5 a=8'b00011001;b=8'b00010000;
end
shiftadd sa1(a,b,result);
endmodule

SIMULATION:

RESULT:
Thus Shift and Add Multiplication Algorithm is designed and simulated using
Verilog HDL structural level modelling.
 Booth multiplication algorithm
Aim:
Design and Simulate Booth’s Multiplication Algorithms using Verilog HDL
structural level modelling.

HARDWARE DIAGRAM:

EXAMPLE PROBLEM:
Multiplicand (Br) = 7 (0111)
Multiplier (Qr) = 3 (0011)
VERILOG CODE:
DESIGN SOURCE:

module booth_multiplier(
input[4:0]br,qr,
output [9:0]result);
wire [10:0]out;
wire [4:0]acc;
wire [10:0]out1,out2,out3,out4,out5;
wire [4:0]bs;
wire [10:0]shift1,shift2,shift3,shift4,shift5;
assign acc=5'b0;
assign Qn1=0;
assign bs=(~br)+1'b1;
assign out={acc,qr,Qn1};
assign
shift1=(qr[0]==1'b0&&Qn1==1'b0)|(qr[0]==1'b1&&Qn1==1'b1)?{out}:((qr[0]==1'b0&&Qn1==
1'b1)?({(acc+br),qr,Qn1}):({(acc+bs),qr,Qn1}));
assign out1={shift1[10],shift1[10:1]};
assign shift2=(((out1[1]==1'b0&&out1[0]==1'b0)|(out1[1]==1'b1&&out1[0]==1'b1))?
{out1}:(out1[1]==1'b0&&out1[0]==1'b1)?{(out1[10:6]+br),out1[5:1],out1[0]}:{(out1[10:6]+bs)
,out1[5:1],out1[0]});
assign out2={shift2[10],shift2[10:1]};
assign shift3=(((out2[1]==1'b0&&out2[0]==1'b0)|(out2[1]==1'b1&&out2[0]==1'b1))?
{out2}:(out2[1]==1'b0&&out2[0]==1'b1)?{(out2[10:6]+br),out2[5:1],out2[0]}:{(out2[10:6]+b
s),out2[5:1],out2[0]});
assign out3={shift3[10],shift3[10:1]};
assign shift4=(((out3[1]==1'b0&&out3[0]==1'b0)|(out3[1]==1'b1&&out3[0]==1'b1))?
{out3}:(out3[1]==1'b0&&out3[0]==1'b1)?{(out3[10:6]+br),out3[5:1],out3[0]}:{(out3[10:6]+
bs),out3[5:1],out3[0]});
assign out4={shift4[10],shift4[10:1]};
assign shift5=(((out4[1]==1'b0&&out4[0]==1'b0)|(out4[1]==1'b1&&out4[0]==1'b1))?
{out4}:(out4[1]==1'b0&&out4[0]==1'b1)?{(out4[10:6]+br),out4[5:1],out4[0]}:{(out4[10:6]+
bs),out4[5:1],out4[0]});
 assign out5={shift5[10],shift5[10:1]};
assign result=out5[10:1];
endmodule
TEST BENCH:
module booth_multiplier_tb();
reg [4:0]br,qr;
wire [9:0]result;
initial
begin
br=5'b10111;qr=5'b10011;
#5 br=5'b00111;qr=5'b10011;
#5 br=5'b11011;qr=5'b10011;
end
booth_multiplier b(br,qr,result);
endmodule

SIMULATION:

RESULT:
Thus Booth’s Multiplication Algorithm is designed and simulated using Verilog
HDL structural level modelling.
 MODIFIED BOOTH’S ALGORITHM

AIM:
To design and simulate Modified Booth Algorithm using Verilog HDL Behavioural
level modelling.

FLOWCHART:
SOURCE CODE:

module BOOTH(
input [7:0] a,
input [7:0] b,
input clk,
output reg [15:0] ans
);
reg [8:0]Q;
reg [7:0]M;
reg [15:0]Ac,m;
integer RB,i;
always @(posedge clk)
begin
Q = {a,1'b0};
M = b;
Ac = {16{1'b0}};
for(i=0;i<4;i=i+1)
begin
RB = Q[2*i+1] + Q[2*i] - (2*Q[2*i+2]);
m = {{8{M[7]}},M};
if (RB==1)
begin
m = m << (2*i);
Ac = Ac + m;
end
else if(RB==-1)
begin
 m = (~m)+1;
m = (m<<(2*i));
Ac = Ac + m;
end
else if(RB==2)
begin
m = m<<1;
m = (m<<(2*i));
Ac = Ac + m;
end
else if (RB==-2)
begin
m = m<<1;
m = (~m) + 1;
m = (m<<(2*i));
Ac = Ac + m;
end
end
ans= Ac;
end
endmodule

TEST BENCH CODE:

module booth_tb();
reg [7:0]muld,mlp;
wire [15:0]ans;
reg clk=1;
 always #5 clk=~clk;
initial
begin
mlp=4'b0011;muld=4'b1001;
#10 mlp=4'b0111;muld=4'b0001;
#10 $finish;
end
BOOTH b1(muld,mlp,clk,ans);
endmodule

SIMULATION:

RESULT:
Thus Modified Booth Algorithm has been designed and simulated using Verilog
HDL Behavioural level modelling.
 Restoring division algorithm
AIM:
Design and Simulate Restoring Division Algorithm using Verilog HDL structural
level modelling.

HARDWARE DIAGRAM:

fLOWCHART:
EXAMPLE PROBLEM:

VERILOG CODE:
DESIGN SOURCE:
module restoring(
input [3:0] m,
input [3:0] q,
input [4:0] acc,
output [3:0] result,
 output [4:0] remain
);
wire [8:0]shit1,shit2,shit3,shit4;
wire [8:0]out1,out2,out3,out4;
wire [8:0]out,res;
wire bs=1;
wire [4:0]qs,acc;
assign acc=4’b0;
assign qs=(~q)+1'b1;
assign out={acc,m}<<1;
assign out1={(out[8:4]+qs),out[3:0]};
assign shit1= (out1[8]==1)?({out[8:1],out[0]}<<1):(({out1[8:1],~out1[0]})<<1);
assign out2={(shit1[8:4]+qs),shit1[3:0]};
assign shit2= (out2[8]==1)?({shit1[8:1],shit1[0]}<<1):(({out2[8:1],~out2[0]})<<1);
assign out3={(shit2[8:4]+qs),shit2[3:0]};
assign shit3= (out3[8]==1)?({shit2[8:1],shit2[0]}<<1):(({out3[8:1],~out3[0]})<<1);
assign out4={(shit3[8:4]+qs),shit3[3:0]};
assign shit4= (out4[8]==1)?({shit3[8:1],shit3[0]}<<1):(({out4[8:1],~out4[0]})<<1);
assign res=shit4>>1;
assign result=res[3:0];
assign remain=res[8:4];
endmodule
TEST BENCH:
module restoring_tb();
reg [3:0] m;
reg [3:0] q;
wire [3:0] result;
wire [4:0]remain;
initial
 begin
acc=5'b0;
m=4'd12;q=4'd3;
#5 m=4'd7;q=4'd5;
#5 m=4'd11;q=4'd4;
end
restoring r1(m,q,acc,result,remain);
endmodule

SIMULATION:

RESULT:
Thus Restoring Division Algorithm is designed and simulated using Verilog HDL
structural level modelling.
 NON-RESTORING DIVISION ALGORITHM
AIM:
Design and Simulate Non-Restoring Division Algorithm using Verilog HDL
structural level modelling.

HARDWARE DIAGRAM:

FLOW CHART

:
EXAMPLE PROBLEM:
Divisor: 11
Dividend: 3

VERILOG CODE:
DESIGN SOURCE:

module non_restoring(
input [3:0] q,
input [3:0] b,
output [3:0] result,
output [4:0] remain
);
wire [4:0]acc,bs;
 wire [8:0]shift1,shift2,shift3,shift4,out1,out2,out3,out4,out;
wire [8:0]res;
assign acc=5'b0;
assign bs=(~b)+1;
assign out={acc,q}<<1;
assign out1= (out[8]==0)?({out[8:4]+bs,out[3:1],1'b0}):({out[8:4]+b,out[3:1],1'b0});
assign shift1= {out1[8:1],~out1[8]}<<1;
assign out2=
(shift1[8]==0)?({shift1[8:4]+bs,shift1[3:1],1'b0}):({shift1[8:4]+b,shift1[3:1],1'b0});
assign shift2= {out2[8:1],~out2[8]}<<1;
assign out3=
(shift2[8]==0)?({shift2[8:4]+bs,shift2[3:1],1'b0}):({shift2[8:4]+b,shift2[3:1],1'b0});
assign shift3= {out3[8:1],~out3[8]}<<1;
assign out4=
(shift3[8]==0)?({shift3[8:4]+bs,shift3[3:1],1'b0}):({shift3[8:4]+b,shift3[3:1],1'b0});
assign shift4= {out4[8:1],~out4[8]};
assign res=shift4;
assign result=res[3:0];
assign remain=shift4[8:4];
endmodule
TEST BENCH:
module non_restoring_tb();
reg [3:0] q;
reg [3:0] b;
wire [3:0] result;
wire [4:0] remain;
initial
begin
q=4'd11;b=4'd3;
#5 q=4'd8;b=4'd3;
 #5 q=4'd15;b=4'd3;
end
non_restoring nr1(q,b,result,remain);
endmodule

SIMULATION:

RESULT:
Thus Non-Restoring Division Algorithm is designed and simulated using Verilog
HDL structural level modelling.
 Robertson multiplication algorithm
AIM:
Design and Simulate Robertson algorithm using Verilog HDL structural level
modelling.

HARDWARE DIAGRAM:

FLOWCHART:
EXAMPLE PROBLEM:

VERILOG CODE:
DESIGN SOURCE:
module robertson_al(q,m,result);
input [4:0]q;
input [4:0]m;
output [9:0]result;
wire [5:0]shift1,shift2,shift3,shift4,shift5;
wire [4:0]out1,out2,out3,out4,out5;
wire f,fnew1,fnew2,fnew3,fnew4,fnew5;
wire [4:0]acc,ms;

assign acc=5'b0;
assign f=0;
assign ms=(~m)+1;

assign fnew1=((m[4]&&q[0])||f);
assign shift1= q[0]==1?{fnew1,(acc+m)}:{fnew1,acc};
assign out1={shift1[0],q[4:1]};

assign fnew2=((m[4]&&out1[0])||fnew1);
assign shift2= out1[0]==1?{fnew2,(shift1[5:1]+m)}:{fnew2,shift1[5:1]};
assign out2={shift2[0],out1[4:1]};

assign fnew3=((m[4]&&out2[0])||fnew2);
assign shift3= out2[0]==1?{fnew3,(shift2[5:1]+m)}:{fnew3,shift2[5:1]};
assign out3={shift3[0],out2[4:1]};

assign fnew4=((m[4]&&out3[0])||fnew3);
assign shift4= out3[0]==1?{fnew4,(shift3[5:1]+m)}:{fnew4,shift3[5:1]};
assign out4={shift4[0],out3[4:1]};
assign fnew5=(m[4]^out4[0]);
assign shift5= out4[0]==1?{fnew5,(shift4[5:1]+ms)}:{fnew5,shift4[5:1]};
assign out5={shift5[0],out4[4:1]};

assign result={shift5[5:1],out5};
endmodule
TEST BENCH:
module robertsin_al_tb();
reg [4:0]q;
reg [4:0]m;
wire [9:0]result;
robertson_al al1(q,m,result);
initial
begin
m=5'b01001;q=5'b10111;
#10 m=5'b01000;q=5'b00111;
#10 m=5'b01100;q=5'b10011;
end
endmodule

SIMULATION:
RESULT:
Thus Robeertson Multiplication Algorithm is designed and simulated using Verilog
HDL structural level modelling.
 ALU to perform 12 Arthimetic & 4 Logic operations

Aim:
ALU to perform 12 Arthimetic & 4 Logic operations in verilog using HDL Structural
Level Modelling. ALU to perform 12 Arthimetic & 4 Logic operations in verilog using HDL
Structural Level Modelling.

DESIGN:

4 Bit Alu – Block Diagram

Function Table of Arithmetic unit

One Stage of Logic Unit
 Function Table for combined Arithmetic and logic design

EQUATIONS:
HARDWARE DIAGRAM:
VERILOG CODE:
1-BIT ALU:
module alu_1(a,b,s2,s1,s0,cin,f,carry);
input a,b,s2,s1,s0,cin;
output f,carry;
wire [1:0]r1,r2,r3,r4;
assign r1=a+cin;
assign r2=a+b+cin;
assign r3=a+~b+cin;
assign r4=a-(~cin);
assign
f=(~s2&&~s1&&~s0&&r1[0])||(~s2&&~s1&&s0&&r1[0])||(~s2&&s1&&~s0&&r3
[0])||(~s2&&s1&&s0&&r4[0])||(s2&&~s1&&~s0&&(a||b))||(s2&&~s1&&s0&&(
a^b))||(s2&&s1&&~s0&&(a&&b))||(s2&&s1&&s0&&(~a));
assign
carry=(~s2&&~s1&&~s0&&r1[1])||(~s2&&~s1&&s0&&r2[1])||(~s2&&s1&&~s0&
&r3[1])||(~s2&&s1&&s0&&r4[1]);
endmodule
4-BIT ALU:
module alu_4bit(a,b,s2,s1,s0,cin,f,carry);
input [3:0]a,b;
input s2,s1,s0,cin;
output [3:0]f;
output carry;
wire w1,w2,w3;
alu_1 a1(a[0],b[0],s2,s1,s0,cin,f[0],w1);
alu_1 a2(a[1],b[1],s2,s1,s0,w1,f[1],w2);
alu_1 a3(a[2],b[2],s2,s1,s0,w2,f[2],w3);
alu_1 a4(a[3],b[3],s2,s1,s0,w3,f[3],carry);
endmodule
TESTBENCH:
module alu_4tb();
reg [3:0]a,b;
reg s2,s1,s0,cin;
wire [3:0]f;
wire carry;
initial
begin
a=4'b0110;b=4'b0010;s2=0;s1=1;s0=0;cin=1;
#5 a=4'b0110;b=4'b1010;s2=0;s1=0;s0=0;cin=1;
#5 a=4'b0110;b=4'b1010;s2=0;s1=0;s0=1;cin=0;
#5 a=4'b0110;b=4'b1010;s2=0;s1=0;s0=1;cin=1;
#5 a=4'b0110;b=4'b1010;s2=0;s1=1;s0=0;cin=0;
#5 a=4'b0110;b=4'b1010;s2=0;s1=1;s0=1;cin=0;
#5 a=4'b0110;b=4'b1010;s2=0;s1=1;s0=1;cin=1;
#5 a=4'b0110;b=4'b1010;s2=1;s1=0;s0=0;cin=0;
#5 a=4'b0110;b=4'b1010;s2=1;s1=0;s0=1;cin=0;
#5 a=4'b0110;b=4'b1010;s2=1;s1=1;s0=0;cin=0;
#5 a=4'b0110;b=4'b1010;s2=1;s1=1;s0=1;cin=0;
end
alu_4bit ab1(a,b,s2,s1,s0,cin,f,carry);
endmodule
SIMULATION:

RESULT:
Thus, ALU to perform 12 Arthimetic & 4 Logic operations has been designed and
simulated in verilog using HDL Structural Level Modelling.
 Gray Shaft Encoder using One Hot Controller

Aim:
To Design and Simulate Gray Shaft Encoder using One Hot Controller
in Verilog using HDL Behavioural Modelling.
ASM CHART:

STATE EQUATIONS:
HARDWARE DIAGRAM:

VERILOG CODE:
SOURCE CODE FPR D FLIP FLOP:
module D_FF(
input clk,
input d,
output reg q );
always @ (posedge clk)begin
q<=d;
end
endmodule
SOURCE CODE:
module GRAY_SHAFT(
input a,
input clk,
input b,
output u,
output d
);
wire x1,x2,x3,x4;
D_FF d1(clk,(~a&~b),x1);
D_FF d2(clk,(~a&b),x2);
D_FF d3(clk,(a&~b),x3);
D_FF d4(clk,(a&b),x4);
assign u=x1&(~a&b)||x2&(a&b)||x3&(~a&~b)||x4&(a&~b);
assign d=x1&(a&~b)||x2&(~a&~b)||x3&(a&b)||x4&(~a&b);
endmodule
TEST BENCH CODE:
module gray_shaft_tb();
reg a,b,clk;
wire u,d;
GRAY_SHAFT gs(.a(a),.clk(clk),.b(b),.u(u),.d(d));
initial begin
clk=0;
#10 a=0; b=0;
#10 a=0; b=1;
#10 a=1; b=1;
#10 a=1; b=0;
#10 a=0; b=0;
#10 a=0; b=1;
#10 a=1; b=1;
#10 a=1; b=0;
end
always #1 clk=~clk;
endmodule

SIMULATION:

RESULT:
Thus, Gray Shaft Encoder using One Hot Controller has been designed
and simulated in Verilog using HDL Behavioural Modelling.
 hardwired control logic for
addition/subtraction of signed magnitude
numbers
AIM:
To Design and Simulate a hardwired control logic for addition/subtraction of signed
magnitude numbers using Verilog HDL Behavioural Level.

ALGORITHM:

HARDWARE REALIZATION:
FLOWCHART:

STATE DIAGRAM:
STATE EQUATIONS:

BOOLEAN FUNCTIONS:

HARDWARE DIAGRAM OF CONTROL LOGIC:

HARDWARE DIAGRAM:
VERILOG CODE:
SOURCE CODE:
module ADD_SIGN(
input [3:0] A,
input [3:0] B,
output reg Cin,
output reg sign,
output reg [3:0] Result );
wire Add=1'b0;
always @(A, B, Add)
begin
if (Add)
begin
sign = A[3] ^ B[3];
Result = A + B;
Cin = 0;
end
else if (A[3] == B[3])
begin
sign = A[3];
Result = A + B;
Cin = 0;
end
else if (A[3] == 0)
begin
Result = A - (~B + 1'b1);
Cin = 1;
end
else
begin
sign = B[3];
 Result = (~A + 1'b1) - B;
Cin = 1;
end
end
endmodule
TEST BENCH CODE:
module sign_tb();
reg [3:0]a,b;
wire cin,sign;
wire [3:0]ans;
initial
begin
a=4;b=2;
#10 a=4'b0101;b=4'b1100;
#10 a=4'b1101;b=4'b1100;
#10 $finish;
end
ADD_SIGN s1(a,b,cin,sign,ans);
endmodule

SIMULATION:

RESULT:
Thus, a hardwired control logic for addition/subtraction of signed
magnitude numbers is designed and simulated using Verilog HDL Behavioural
Level.