Digital System Design using Verilog Semester 6

Course Code BEC654A CIE Marks 50

Teaching Hours/Week(L:T:P) 3:0:0 SEE Marks 50
Total Hours of Pedagogy 40 Total Marks 100
Credits 03 Exam Hours 3
Examination type (SEE) Theory
Course objectives:
 Learn different Verilog HDL constructs.
 Familiarize the different levels of abstraction in Verilog.
 Understand Verilog Tasks and Functions.
 Understand Timing and Delay Simulation.
Teaching-Learning Process (General Instructions)
The sample strategies, which the teacher can use to accelerate the attainment of the various course
outcomes are listed in the following:
1. Lecture method (L) does not mean only the traditional lecture method, but a different type of
teaching method may be adopted to develop the outcomes.
2. Show Video/animation films to explain the functioning of various techniques.
3. Encourage collaborative (Group) Learning in the class
4.Ask at least three HOTS (Higher-order Thinking) questions in the class, which promotes critical
thinking
5.Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop
thinking skills such as the ability to evaluate, generalize, and analyze information rather than
simply recall it.
6. Show the different ways to solve the same problem and encourage the students to come up with
their own creative ways to solve them.
7. Discuss how every concept can be applied to the real world - and when that's possible, it helps
improve the students' understanding.
8. Give programming assignments.
Module-1
Overview of Digital Design with Verilog HDL: Evolution of Computer-Aided Digital Design
(CAD), Emergence of HDLs, Typical Design flow, Importance of HDLs, Popularity of Verilog
HDL, Trends in HDLs. (Text 1: 1.1 to 1.6)
Hierarchical Modeling Concepts: Design Methodologies, Top-down and Bottom-up design
methodology, Modules, Instances, Components of a Simulation, Design Block, Stimulus Block
(Test Bench) with example. (Text 1:2.1 to 2.6)
Teaching-Learning Chalk and talk method, Power point presentation
Process RBT Level: L1, L2, L3
Module-2
Basic Concepts: Lexical Conventions, Data Types, System Tasks, Compiler Directives.
(Text 1: 3.1 to 3.3)
Modules and Ports: Modules, Ports, Connecting Ports, Hierarchical Names. (Text 1: 4.1 to 4.3)
Teaching-Learning Chalk and talk method, Power point presentation
Process RBT Level: L1, L2, L3

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 Module-3
Gate-Level Modeling: Gate Types-Modeling using basic Verilog gate primitives, Description of
AND/OR and BUF/NOT type gates. Gate Delays-Rise, Fall and Turn-Off Delays, Min, Max and
Typical Delays. (Text1: 5.1, 5.2 )
Dataflow Modeling: Continuous assignments, Delay Specification, Expressions, Operators,
Operands, Operator Types, Examples (Text 1: 6.1 to 6.5)
Teaching-Learning Chalk and talk method, Power point presentation
Process RBT Level: L1, L2, L3
Module-4
Behavioral Description: Structured Procedures, Initial and Always statements, Procedural
Assignments Blocking and Non-Blocking statements, Conditional statements, Multiway
Branching, Loops, Sequential and Parallel blocks, Examples-4-to-1 Multiplexer, 4-bit Counter.
(Text 1: 7.1, 7.2, 7.4, 7.5, 7.6, 7.7, 7.9.1, 7.9.2)
Teaching-Learning Chalk and talk method, Power point presentation
Process RBT Level: L1, L2, L3
Module-5
Structural Description: Highlights of Structural Descriptions, Organization of Structural
Description, Binding (Text 2: 4.1, 4.2, 4.3, Listings 4.1 to 4.13 only Verilog)
Tasks and Functions: Differences between Tasks and Functions, Declaration and Invocation,
Examples (Text 1: 8.1, 8.2, 8.2.1, 8.2.2, 8.3, 8.3.1, 8.3.2)
Course outcomes (Course Skill Set)
At the end of the course the student will be able to:
1. Understand the Verilog HDL design flow.
2. Describe the basic concepts of Verilog HDL programming.
3. Write Verilog programs in Gate, Dataflow, Behavioral, and structural modeling levels of
Abstraction.
4. Write the programs more effectively using Verilog Tasks and Functions.
5. Perform Timing and Delay Simulation.

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 Assessment Details (both CIE and SEE)
The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester End Exam
(SEE) is 50%. The minimum passing mark for the CIE is 40% of the maximum marks (20
marks out of 50). A student shall be deemed to have satisfied the academic requirements and
earned the credits allotted to each subject/ course if the student secures not less than 35% (18
Marks out of 50) in the semester-end examination (SEE), and a minimum of 40% (40 marks
out of 100) in the sum total of the CIE (Continuous Internal Evaluation) and SEE (Semester
End Examination) taken together.
Continuous Internal Evaluation:
Three Unit Tests each of 20 Marks (duration 01 hour)
1. First test at the end of 5th week of the semester
2. Second test at the end of the 10th week of the semester
3. Third test at the end of the 15th week of the semester
Two assignments each of 10 Marks
4. First assignment at the end of 4th week of the semester
5. Second assignment at the end of 9th week of the semester
Group discussion/Seminar/quiz any one of three suitably planned to attain the COs and POs for
20 Marks (duration 01 hours)
6. At the end of the 13th week of the semester
The sum of three tests, two assignments, and quiz/seminar/group discussion will be out of 100
marks and will be scaled down to 50 marks
(to have less stressed CIE, the portion of the syllabus should not be common /repeated for any
of the methods of the CIE. Each method of CIE should have a different syllabus portion of the
course).
CIE methods /question paper is designed to attain the different levels of Bloom’s
taxonomy as per the outcome defined for the course.
Semester End Examination:
Theory SEE will be conducted by University as per the scheduled timetable, with common
question papers for the subject (duration 03 hours)
1. The question paper will have ten questions. Each question is set for 20 marks.
2. There will be 2 questions from each module. Each of the two questions under a module
(with a maximum of 3 sub-questions), should have a mix of topics under that module.
The students have to answer 5 full questions, selecting one full question from each module.
Marks scored out of 100 shall be reduced proportionally to 50 marks
Suggested Learning Resources:
Text Books:
1. “Verilog HDL: A Guide to Digital Design and Synthesis”, Samir Palnitkar, Pearson education,
Second edition.
1. 2. “HDL programming (VHDL and Verilog)”, Nazeih M Botros, John Wiley India Pvt. Ltd.,
2. 2008.
3. Reference Books:
1. Donald E. Thomas, Philip R. Moorby, “The Verilog Hardware Description Language”,
Springer Science+Business Media, LLC, Fifth edition.
2. Michael D. Ciletti, “Advanced Digital Design with the Verilog HDL” Pearson (Prentice Hall),
Second edition.
3. Padmanabhan, Tripura Sundari, “Design through Verilog HDL”, Wiley, 2016 or earlier

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