21ECE303

St Joseph Engineering College, Mangaluru
An Autonomous Institution
B. E. – Electronics & Communication Engineering
Choice Based Credit System (CBCS) and Outcome Based Education (OBE)
SEMESTER –III
Digital System Design (Integrated)
Course Code 21ECE303 CIE Marks 50
Teaching Hours/Week (L:T:P:S) (3:0:2:0) SEE Marks 50
Credits 04 Exam Hours 03
Course Learning Objectives:
1. Describe the Basic concepts of Boolean Algebra, Verilog HDL and
implement the Boolean expressions using Logic gates.
2. Design and implement Combinational Circuits such as Decoders, Encoders,
Multiplexers, Adders, Subtractors, and Binary Comparators and
demonstrate their HDL Models.
3. Implement various Synchronous sequential Logic Circuits and describe
Synthesizable HDL models of Sequential Circuits.
4. Construct various types of Registers and Counters using Flip-flops.
5. Design circuits at the Register Transfer Level with different levels of
description.
6. Using simulation softwares, test the function of various combinational and
sequential circuits.
Module-1
Introduction to Digital Logic: Minterms & Maxterms (canonical) and standard forms of
Boolean Expressions, 3 & 4 variable K-MAP, SOP & POS Simplifications, Don’t Care
Conditions, Exclusive OR function (Self Study), Parity Generation and Checking.
Hardware Description Language: Introduction, Verilog-Design Encapsulation, Structural
Modeling, Gate Delays, Verilog-User Defined Primitives.
(Text 1 :2.6, 3.2, 3.3, 3.4, 3.5, 3.8, 3.9)
8 Hours
Module-2
Combinational logic: Introduction, Combinational Circuits, Analysis Procedure, Design
Procedure, Binary Adder-Subtractor, Decimal Adder, Binary Multiplier, Magnitude
Comparator, Decoders, Encoders, Multiplexers, HDL Models of Combinational Circuits,
Behavioral Modeling, Writing a Simple Testbench (Only Verilog concepts to be
discussed).
(Text 1 : Chapter 4 except 4.15 )
8 Hours
Module-3
Synchronous Sequential Logic: Introduction, Sequential Circuits, Storage Elements:
Latches, Storage Elements: Flip-Flops, Analysis of Clocked Sequential Circuits,
Synthesizable HDL models of Sequential Circuits (Only Verilog concepts to be discussed),
State Reduction and Assignment, Design Procedure.
(Text 1 - Chapter 5)
8 Hours
Module-4
Registers and Counters: Registers, Shift Registers, Ripple Counters, Synchronous
Counters, HDL Models of Registers and Counters (Only Verilog concepts to be discussed).
(Text 1 : 6.1, 6.2, 6.3, 6.4, 6.6)
8 Hours
Module-5
Design at the Register Transfer Level: Introduction, Register Transfer Level Notation,
RTL Descriptions (Only Verilog concepts to be discussed), Algorithmic State Machines
(ASM’s) (Text 1 :8.1, 8.2, 8.3, 8.4)
Asynchronous Sequential Logic: Circuits with Latches, Design Procedure, Reduction of
State and Flow tables, Hazards (Text 1: 9.3, 9.4, 9.5, 9.7)
8 Hours
List of Laboratory Experiments related to above modules – 2 hours each
PART A (Using discrete components & Trainer Kits)
1. The Simplification of SOP & POS expressions using K Map and Realization using
Basic Gates & Universal Gates.
2. Design and Implementation of Full Adder and Full Subtractor using a) Half adder
and Half Subtractor b) NAND gates.
3. Realization of Code Converters and Multiplexers.
4. Realize Ripple Carry Adder and Carry Look Ahead Adder.
PART B (Using Xilinx Vivado tool)
5. Write a Verilog code and implement Adders & Subtractors.
6. Design Comparators.
7. Realize SR, JK, T & D Flip-Flops.
8. Design Counters & Shift Registers.
9. Design Clock Pulse Generator.
10. Design and implement 4-bit ALU using Verilog program.
11. Design an Open Ended Experiment covering the concept of entire syllabus.
Course Outcomes:
At the end of the course the student will be able to:
21ECE303.1 Develop Simplified Switching Equations using Karnaugh Maps.
21ECE303.2 Design Digital Combinational Control Circuits and Implement those using
HDL Models.
21ECE303.3 Implement Shift Registers & Counters using Latches and Flipflops.
21ECE303.4 Design the Sequential Circuits and Analyze the Problems using State
Diagrams.
21ECE303.5 Illustrate the Digital System Design at the Register Transfer Level.
21ECE303.6 Test the Function of Various Combinational and Sequential Circuits using
Simulation Softwares.
Sl. Name of the Name of Editio

Title of the Book
No. Author/s the n and
Publisher Year
Textbooks
1 Digital Design Morris Mano, Michael Pearson Sixth
with an D. Ciletti Editio
Introduction to the n,
Verilog HDL, 2019
VHDL, and
System Verilog
Reference Books
1 Digital John M Thomso 2001
Logic Yarbrough n
Applications Learnin
and Design g
2 Digital Byeong Kil Cengag First Edition
System Lee,Charles H e 2014
Design Roth,LizzyJohn Learnin
Using g
Verilog
Web links/Video Lectures/MOOCs/papers

1. Virtual Lab :Digital Electronics IITR.
https://de-iitr.vlabs.ac.in/
2. NPTEL Lecture by Prof Roy Choudary, Department of CSE, IIT Kharagpur.
https://nptel.ac.in/courses/117/105/117105080/
3. NPTEL Lecture by Prof Neeraj Goel, IIT Rourkee
(https://onlinecourses.nptel.ac.in/noc21_ee39/preview)
Course Articulation Matrix

Course Program Outcomes (POs)
Outcomes
(COs) P P P P P P P P P PO PO PO PSO PSO
O O O O O O O O O 10 11 12 1 2
1 2 3 4 5 6 7 8 9
21ECE303.1 3 3 - - - - - - - - - 1 2 -
21ECE303.2 3 - 2 - - - - - - - - 1 2 -
21ECE303.3 2 - 2 - - - - - - - - 1 2 -
21ECE303.4 2 2 2 2 - - - - - - - 1 - -
21ECE303.5 - - 2 2 - - - - - 2 - - - -
21ECE303.6 - - - 2 2 - - 2 - 2 - - - -
1: Low 2: Medium 3: High

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St Joseph Engineering College, Mangaluru

Sl. Name of the Name of Editio

Web links/Video Lectures/MOOCs/papers

Course Articulation Matrix

1: Low 2: Medium 3: High

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