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Assignment no 08_solution - Computer Architecture[1]

The document outlines an assignment for a Computer Architecture course, focusing on MIPS architecture principles and exercises related to memory storage, ASCII encoding, and converting MIPS assembly code to machine language. It includes specific examples illustrating design principles such as simplicity, speed, and compromise, along with exercises that require calculating byte addresses and converting strings and assembly code into hexadecimal format. The solutions provided demonstrate the application of these concepts in practical scenarios.

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muhammedtarek160
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© © All Rights Reserved
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Download as PDF, TXT or read online on Scribd
6 views

Assignment no 08_solution - Computer Architecture[1]

The document outlines an assignment for a Computer Architecture course, focusing on MIPS architecture principles and exercises related to memory storage, ASCII encoding, and converting MIPS assembly code to machine language. It includes specific examples illustrating design principles such as simplicity, speed, and compromise, along with exercises that require calculating byte addresses and converting strings and assembly code into hexadecimal format. The solutions provided demonstrate the application of these concepts in practical scenarios.

Uploaded by

muhammedtarek160
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Faculty of Computers and Artificial Intelligence

CS222: Computer Architecture

Assignment no 08
Chapter 6: Architecture
Note: You can check the exercises after the Chapter. In our assignment, we are using the
2nd Edition of “Digital Design and Computer Architecture” By David and Sarah Harris.

Exercise 6.1 Give three examples from the MIPS architecture of each of the
architecture design principles: (1) simplicity favors regularity; (2) make the
common case fast; (3) smaller is faster; and (4) good design demands good
compromises. Explain how each of your examples exhibits the design principle.
Solution:-
(1) Simplicity favors regularity:
• Each instruction has a 6-bit opcode.
• MIPS has only 3 instruction formats (R-Type, I-Type, J-Type).
• Each instruction format has the same number and order of operands (they
differ only in the opcode).
• Each instruction is the same size, making decoding hardware simple.
(2) Make the common case fast.
• Registers make the access to most recently accessed variables fast.
• The RISC (reduced instruction set computer) architecture, makes the com-
mon/simple instructions fast because the computer must handle only a
small number of simple instructions.
• Most instructions require all 32 bits of an instruction, so all instructions are
32 bits (even though some would have an advantage of a larger instruction
size and others a smaller instruction size). The instruction size is chosen to
make the common instructions fast.
(3) Smaller is faster.
• The register file has only 32 registers.
The ISA (instruction set architecture) includes only a small number of com-
monly used instructions. This keeps the hardware small and, thus, fast.
• The instruction size is kept small to make instruction fetch fast.

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

(4) Good design demands good compromises.


• MIPS uses three instruction formats (instead of just one).
• Ideally all accesses would be as fast as a register access, but MIPS archi-
tecture also supports main memory accesses to allow for a compromise be-
tween fast access time and a large amount of memory.
• Because MIPS is a RISC architecture, it includes only a set of simple in-
structions, it provides pseudocode to the user and compiler for commonly
used operations, like moving data from one register to another (move) and
loading a 32-bit immediate (li).

---------------------------------------------------------------------------------------------------
Exercise 6.3 Consider memory storage of a 32-bit word stored at memory word 42 in a byte-
addressable memory.
(a) What is the byte address of memory word 42?
(b) What are the byte addresses that memory word 42 spans?
(c) Draw the number 0xFF223344 stored at word 42 in both big-endian and little-endian
machines. Your drawing should be similar to Figure 6.4. Clearly label the byte address
corresponding to each data byte value.
Solution:-

----------------------------------------------------------------------------------------------------------
Exercise 6.6 Write the following strings using ASCII encoding. Write your final answers in
hexadecimal.
Solution:-

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

(a) SOS
0X 53 4F 53 00
(b) Cool!
0X 43 6F 6F 6C 21 00
(c) (your own name)
AYA Abd Elhamed---------- 0X 41 59 41 20 41 62 64 20 45 6C 68 61 6D 65 64 00

------------------------------------------------------------------------------------------------------------------
Exercise 6.10 Convert the following MIPS assembly code into machine language. Write the
instructions in hexadecimal.
add $t0, $s0, $s1
lw $t0, 0x20($t7)
addi $s0, $0, −10

Solution:-

add $t0, $s0, $s1

Op rs rt rd Shamt Funct
6-bit 5-bit 5-bit 5-bit 5-bit 6-bit
0 16 17 8 0 32
000000 10000 10001 01000 00000 1000000 (0X 02114020)

lw $t0, 0x20($t7)

Op rs rt Imm
6-bit 5-bit 5-bit 16-bit
35 15 8 0x20
100011 01111 01000 0000 0000 0010 0000
(0X 8DE80020)

addi $s0, $0, −10


Op rs rt Imm
6-bit 5-bit 5-bit 16-bit
8 0 16 -10
001000 00000 10000 1111 1111 1111 0110
(0X2010FFF6)
-----------------------------------------------------------------------------------------------------------------

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

Exercise 6.11 Convert the following MIPS assembly code into machine language. Write the
instructions in hexadecimal.
addi $s0, $0, 73
sw $t1, −7($t2)
sub $t1, $s7, $s2

solution:-

addi $s0, $0, 73

Op rs rt Imm
6-bit 5-bit 5-bit 16-bit
8 0 16 73
001000 00000 10000 0000 0000 01001001
(0X20100049)

sw $t1, −7($t2)

Op rs rt Imm
6-bit 5-bit 5-bit 16-bit
43 10 9 -7
101011 01010 01001 1111 1111 1111 1001
(0Xad49fff9)

sub $t1, $s7, $s2

Op rs rt rd Shamt Funct
6-bit 5-bit 5-bit 5-bit 5-bit 6-bit
0 23 18 9 0 34 (0x02f24822)
000000 10111 10010 01001 00000 100010

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

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Faculty of Computers and Artificial Intelligence
CS222: Computer Architecture

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