The 8259 Programmable Interrupt Controller (PIC) manages up to 64 interrupt requests, prioritizes them, and communicates with the CPU using unique vector numbers. It features programmable modes, individual maskability, and does not require an external clock signal. The architecture includes various functional blocks such as control logic, interrupt request registers, and priority resolvers to efficiently handle and service interrupts.
The 8259 Programmable Interrupt Controller (PIC) manages up to 64 interrupt requests, prioritizes them, and communicates with the CPU using unique vector numbers. It features programmable modes, individual maskability, and does not require an external clock signal. The architecture includes various functional blocks such as control logic, interrupt request registers, and priority resolvers to efficiently handle and service interrupts.
The 8259 Programmable Interrupt Controller (PIC) manages up to 64 interrupt requests, prioritizes them, and communicates with the CPU using unique vector numbers. It features programmable modes, individual maskability, and does not require an external clock signal. The architecture includes various functional blocks such as control logic, interrupt request registers, and priority resolvers to efficiently handle and service interrupts.
The 8259 Programmable Interrupt Controller (PIC) manages up to 64 interrupt requests, prioritizes them, and communicates with the CPU using unique vector numbers. It features programmable modes, individual maskability, and does not require an external clock signal. The architecture includes various functional blocks such as control logic, interrupt request registers, and priority resolvers to efficiently handle and service interrupts.
It accepts eight interrupt requests (expandable to 64 by cascading 8 slaves PICs).
It prioritizes the interrupt requests (selects the highest priority request for service).
It issues a single interrupt request to the CPU.
In response to the ̅̅̅̅̅̅̅, it issues a unique type number (vector) for each interrupt request input. In addition, type numbers are programmable.
It has variety of programmable modes of operations.
The interrupt requests are individually maskable.
The 8259 can accept requests from the peripheral, determines priority of incoming request, checks whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt signal to the microprocessor.
It can be used in polled as well as in vectored modes.
The 8259 is static, does not require clock signal.
It can identify the interrupting device.
It can resolve the priority of interrupt i.e. it does not require any external priority resolver.
It can be operated in various priority modes such as fixed priority and rotating priority modes. PIN CONFIGURATION OF 8259 PIC Block Diagram of 8259 PIC: -
The architecture or functional block diagram of the 8259 programmable interrupt
controller is shown in Figure. It includes 8 blocks: control logic, read/write logic, data bus buffer, in-service register, priority resolver, interrupt request register, interrupt mask register, and cascade buffer/comparator.
Data Bus Buffer
The 3-state, bidirectional 8-bit data bus is used to interface the 8259 PIC data bus with the system data bus. Control words and status information are transferred through the data bus buffer. It is internally connected to the data bus and its outer pins D7-D0 are connected to the system data bus directly. The directions of data buffer are decided by read and write control signals. When signal read is activated, then it transmits data to the system. When write signal is activated, then it receives data from the system data bus. This reading and writing operation is achieved by IN and OUT microprocessor instructions. Read/Write Logic This block accepts inputs from system control bus and address bus. The control signals are ̅̅̅̅ and ̅̅̅̅̅, and address signals used are A0 and ̅̅̅. ̅̅̅̅ and ̅̅̅̅̅ are connected to ̅̅̅̅̅, ̅̅̅̅̅̅, or ̅̅̅̅̅̅̅̅̅, ̅̅̅̅̅̅̅̅̅̅ depending on the types of mapping used. ̅̅̅̅ and ̅̅̅̅̅ decide the operation is to be performed, i.e. write data to the 8259 PIC or read data from the 8259 PIC. A0 is directly connected to address lines A1of system address lines. The ̅̅̅̅̅is connected to the chip select decoder; the selection of the 8259 is enabled or disabled by ̅̅̅ signal. If logic 0 is applied on this signal, the 8259 PIC is selected, or when 1 is applied on this signal, the 8259 PIC is rejected.
Control Logic This block has two pins: INT (interrupt) as an output, and ̅̅̅̅̅̅̅ (interrupt acknowledge) as an input. The INT is connected to the interrupt pin of the microprocessor. Whenever a valid interrupt is asserted, this signal goes high. The ̅̅̅̅̅̅̅ is the interrupt acknowledgement signal from the microprocessor.
Interrupt Request Register (IRR)
The interrupt at the IR (Interrupt Request) lines are handled by interrupt request register internally. The Interrupt Request Register (IRR) is used to store all the interrupt levels which are requesting service in it in order to serve them one-by-one on the priority basis.
In-Service Register (ISR)
In-service registers are used to store all the interrupt levels which are being serviced. Each bit of this register is set by the priority resolver and reset by the end of the interrupt command word. The microprocessor can read the contents of this register by issuing appropriate command word.
Priority Resolver (PR)
Priority resolver determines the priorities of the bits set in the IRR. To make decision, the priority resolver looks at the ISR. If the highest priority bit in the ISR is set, then it ignores the new request. If the priority resolver finds that the new interrupt has a higher priority than the interrupt currently being serviced, then it will set the appropriate bit in the ISR and send the INT signal to the microprocessor for the new interrupt request.
Interrupt Mask Register (IMR)
It is a programmable register. It is used to mask unwanted interrupt request by
writing appropriate control word. The IMR operates on the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower priority. The microprocessor can read contents of this register without issuing any command word.
Cascade Buffer/Comparator
This functional block stores and compares the identification numbers (IDs) of all 8259s used in the system. The associated three I/O pins CAS2-CAS0 are outputs when the 8259 is used as a master and the inputs when the 8259 is used as a slave. As a master, the 8259 sends the ID of the interrupting slave device onto the CAS2- CAS0 lines. The slave thus selected will send its programmed subroutine address onto the data bus during the next one or two consecutive ̅̅̅̅̅̅̅ pulses. In buffered mode, it generates a̅̅̅̅ signal. When just one 8259 is used in a system, the cascade lines (CAS0, CAS1, and CAS2) can be left open. CONTROL/COMMAND WORDS OF 8259 The 8259A accepts two types of command words generated by the CPU:
1. Initialization Command Words (ICWs):
Initialization command words (ICWs) needed for various 8259A applications are given in this flowchart form.
According to this flowchart, an ICW I and an ICW2 must be sent to any 8259A in the system.
If the system has any slave 8259As (cascade mode), then an ICW3 must be sent to the master, and a different ICW3 must be sent to the slave.
If the system is an 8086 or if we want to specify certain special conditions, then we have to send an ICW4 to the master and to each slave.
Flowchart of Initialization sequence of 8259 PIC
2. Operation Command Words (OCWs):
These are the command words which command the 8259A to operate in various interrupt modes. These modes are: Fully nested mode Rotating priority mode Special mask mode Polled mode The OCWs can be written into the 8259A any time after initialization.
