DIGITAL DESIGN AND

COMPUTER ORGANIZATION
Introduction

Team DDCO
Department of Computer Science and
Engineering

Merged&Editedby_Aayan
Digital Design And Computer Organisation

Course Code :UE23CS251A

Prerequisites :Basic Electronics, Programming in C
 DIGITAL DESIGN AND COMPUTER ORGANIZATION
Course Objective

The objectives of this course are to provide a sound understanding of:

• Fundamental (combinational and sequential) building blocks of digital logic

circuits.
• Design of more complex logic circuits such as adders, multipliers and register files.
• Design of Finite State Machines based on problem specification.
• Construction, using above logic circuits, of a microprocessor, and its functioning at
the clock cycle level.
• Use of studied digital building blocks to construct more complex systems.

➢ Tools to implement: iVerilog

DIGITAL DESIGN AND COMPUTER ORGANIZATION
Syllabus
Unit 1: Gate-Level Minimization and Combinational Logic-1
Introduction, The map method Four variable K-map, Product of Sums simplification, Don’t Care conditions, NAND and NOR
implementation, Combinational circuits, Analysis procedure Design Procedure, Combinational logic-1: Binary Combinational logic:
Adder –Subtractor, Decimal Adder, Binary multiplier, Magnitude comparator Decoders Encoders, Multiplexers.
Unit 2: Synchronous Sequential Logic - I
Synchronous Sequential Logic: Introduction, Sequential circuits, Storage elements : Latches, Flip flops, Analysis of clocked sequential
circuits, State reduction and assignment, Design procedure Registers and counters: Registers, Shift register, Ripple counters,
Synchronous counters Other counters.
Unit 3: Basic structure of computers, Standard I/O interface, Interrupts
Computer Types, Functional Units: Input Unit, Memory Unit, ALU, Output Unit, Control Unit, Basic operational concepts, Number
representation and arithmetic Operations, Character representation, Memory locations and addresses, Memory Operations ,Instruction
and instruction sequencing ,Addressing modes, Assembly Languages , I/O Operations: Accessing I/O Devices, Interrupts Standard I/O
Interfaces.
Unit 4 : Arithmetic Processing Unit and Control Unit Design: Arithmetic: Multiplication of Positive numbers, Signed operand
Multiplication, Fast multiplication, Integer division, floating point numbers operation and architecture , Some fundamental concepts,
Execution of a complete instruction, Multiple Bus Organization, Hardwired control ,Single-cycle, Multi-cycle processor data path and
control.
DIGITAL DESIGN AND COMPUTER ORGANIZATION
Evaluation Policy

Marks to be
Marks to be conducted for
scaled to
ISA 1 (Units 1 and 2) 40 20
ISA 2 (Units 3 and 4) 40 20
Hackathon 10 10
Laboratory (1–credit) • 10 marks(Mini Project) 20
• 5 marks Quiz conducted for 20 marks,(half
an hour) reduced to 5 marks (conducted
during 12th week)
• 5 Marks continuous evaluation of lab
programs
ESA 100 50
(Questions based on units 1–
4:total of 90 marks
Questions based on
laboratory:total of 10 marks)
Total 120*
*The total of 120 marks will further be scaled down to 100 for grading.
 DIGITAL DESIGN AND COMPUTER ORGANIZATION
What is Engineering?

Engineering
From latin ingenium: innate talent/capacity/intelligence
To design and build structures and machines (with skill/art/expertise/ingenuity)

Objective of Engineering?
Optimize fundamental physical quantities of time, space and energy
In current course, increase logic circuit speed, decrease logic resources required and
decrease power consumed
Perquisites-DDCO

Basic Electronics- the unit 3 of Basic electronics

• Digital Electronics: unit 3 of Basic electronics- Basic gates(review), Boolean Algebra, Boolean laws and theorems,
Simplification of Boolean expressions, Universal gates – NAND and NOR- This is the basics for solving K maps and
representing them in circuits in Unit 1 of DDCO.

• unit 3 of Basic electronics- Arithmetic building blocks – Half and Full Adder, Multiplexers, Demultiplexers, RS Flip-Flop
– Basic idea, NAND Gate latch, Clocked RS and D Flip-Flops. – This is used in sequential Logic design of circuits in unit2
of DDCO

• Using this knowledge the data path and control path of ALU is designed

• Basics of C programming is desired knowledge for Lab-The Verilog language used in created of simple circuits like
adders, multiplexers decoders and design of ALU has syntax similar to the C programming language.
DIGITAL DESIGN AND COMPUTER ORGANIZATION
What is the course about?

Digital Design and Computer Organization: What is the course about?

You have learnt programming in C

Compile hello_world.c

Running program outputs “Hello World!”

From starting a program to the time it displays output What goes on inside your
computer?

That in a nutshell is what DDCO is about

Design, organization and operation of various components in your computer at different

levels of abstractions
 DIGITAL DESIGN AND COMPUTER ORGANIZATION
Course Flow
BASIC ELECTRONICS
(1ST SEMESTER)

DIGITAL DESIGN AND

COMPUTER COMPUTER COMPILER DESIGN COMPUTER VISION
ORGANISATION NETWORKS (6TH SEMESTER) (7TH SEMESTER)
(3RD SEMESTER) (5TH SEMESTER) HIGH INFORMATION
INTRODUCTION TO PERFORMANCE SECURITY
MICROPROCESSOR OPERATING COMPUTING (7TH SEMESTER)
AND COMPUTER SYSTEMS ARCHITECTURE COMPUTER
ARCHITECTURE (5TH SEMESTER) (6TH SEMESTER) SYSTEMS
(4TH SEMESTER) MACHINE PARALLEL PERFORMANCE
LEARNING COMPUTING ANALYSIS
(5TH SEMESTER) (6TH SEMESTER) (7TH SEMESTER)
COMPUTER DIGITAL IMAGE
GRAPHICS AND PROCESSING
VISUALIZATION (6TH SEMESTER)
(5TH SEMESTER)
DIGITAL DESIGN AND COMPUTER ORGANIZATION
Computer Organization & Computer Architecture
programs

device drivers
ABSTRACTION:
instructions Hiding details when they aren’t important
registers
focus of this course

datapaths
controllers

adders
memories

AND gates
NOT gates

amplifiers
filters

transistors
diodes

electrons
Why DDCO?
DIGITAL DESIGN AND COMPUTER ORGANIZATION
Computer Organization & Computer Architecture

Why Digital Design and computer organization is important

• Understanding of hardware essential to design a software

• Logic design and implementation roles in academia and industry

• Microprocessor performance not increasing as it used to

DIGITAL DESIGN AND COMPUTER ORGANIZATION
Computer Organization & Computer Architecture

• Computer Organization refers to the Operational Units and there

interconnections that realize or recognize the specifications of
Computer Architecture.

• Organizational attributes includes Hardware details transparent to the

programmer such as control signals , Interface between computers and
peripherals and the memory technology used.
DIGITAL DESIGN AND COMPUTER ORGANIZATION
Moore’s Law

Moore’s Law Every 18 months or so:

• Number of transistors (per unit chip area) doubles
• Transistor speed doubles
• Transistor power consumption halves
Moore’s law is slowing down:

Source: nextplatform.com

Greater understanding of hardware required to improve performance

Increasing importance of custom hardware accelerators (like Google
Tensor Processing Units)
DIGITAL DESIGN AND COMPUTER ORGANIZATION
Job Description

Position Company Job Profile Job Requirement Remuneration

(approximate)
CPU Design Nvidia Design and implementation of Good understanding of ASIC ₹ 4.5 LPA
Engineer - Corporation modules. design flow ,logic synthesis.
Hardware Come up with micro-architecture,
implement in RTL, and deliver a fully
verified, synthesis/timing clean
design
Logic Design Intel Will be responsible for design and Good knowledge of digital ₹ 4.5 to ₹ 490k
Engineer Bengaluru, development of Graphics, Media logic design LPA
Karnataka and Display IPs as well as discrete IP/ SoC architecture and
Graphics SoCs (GPUs), targeting both microarchitecture.
Client Device and Datacenter
markets.
Job Description 1
Job Description 2 System Software Engineer,
GPU Tools Development
 Job Description 3

Role Description (Role & Responsibilities) Capgemini

1. Mandatory skills 16bit 32bit Microcontroller Microprocessor Firmware Developer
2. Embedded systems Firmware Device driver development experience Programming Strong in C
3. Communication protocols UART CAN SPI Ethernet Modbus TCP IP IDE usage
4. Code composer studio IAR workbench Code warrior RTOS VxWorks FreeRTOS Ti RTOS Bootloader
5. Multi threading concepts Preferred skills Strong in Cplusplus Assembly language experience

Mobiveil: CPU Processor Design

Job Summary:
Bachelors or Masters degree in Computer Science or Electrical/Computer Engineering.

Understanding of general purpose CPU micro architecture, including knowledge of areas

such as processor pipelines, caches, memory hierarchy, and multi-processor systems.
Knowledge and or Experience in RTL Design hardware development using Verilog, ideally block design in a CPU design
project or similar high performance project.

Understanding of CPU instruction set architecture and assembly language.

Familiarity with ARM architecture and micro-architecture for current ARM CPU cores is helpful but not required.

Software development skills and/ or experience is helpful (C/C++, Python/Perl, Shell scripting)
Experience modelling microprocessors using higher-level languages, like C/C++, is helpful but not required
Effective communication skills and the ability to collaborate with a team
DIGITAL DESIGN AND COMPUTER ORGANIZATION
Course Structure

Digital Design
Combinational logic design
Sequential logic design
Computer Organization
Architecture (microprocessor instruction set)
Microarchitecture (microprocessor operation)
THANK YOU

Team DDCO
Department of Computer Science
 DIGITAL DESIGN AND
COMPUTER ORGANIZATION
Gate-Level Minimization and Combinational logic
Department of Computer Science and Engineering
DIGITAL DESIGN AND
COMPUTER ORGANIZATION

Boolean functions, canonical forms and Truth Tables

Department of Computer Science and Engineering

Gate-Level Minimization and Combinational logic
Boolean Functions
What is a Boolean Function?
You have learnt logic gates and truth tables in your first year
What are they? Where do they come form?
What is a Boolean function?
What is a(mathematical) function? • Example: AND function/gate
• Example: Parabola • A function whose domain and range are the set {0, 1}
• Domain and range are set of real • Specified as a truth table:
numbers a b y
• Specified on Cartesian 0 0 0
• Plane 0 1 0
• Specified as a box: 1 0 0
1 1 1
x x2 Specified as a logic gate:
f (x ) = x 2 a y
b
Gate-Level Minimization and Combinational logic
Boolean Functions
Boolean Functions

A Boolean function has:

At least one Boolean variable,
At least one Boolean operator, and
At least one input from the set {0,1}.
It produces an output that is also a member of the set {0,1}.
Gate-Level Minimization and Combinational logic
Boolean Functions
Boolean Function
A Boolean function is described by an algebraic expression consists of
binary variables, the constants 0 and 1, and the logic operation
symbols
EX:

What is value of F1 if x = 1 or if y = 0 and z = 1 ?

A Boolean function expresses the logical relationship between binary

variables and is evaluated by determining the binary value of the
expression for all possible values of the variables
Gate-Level Minimization and Combinational logic
Boolean Functions
• The number of rows in the truth table is 2n , where n is the
number of variables in the function
• binary numbers - counting from 0 through 2n – 1
Gate-Level Minimization and Combinational logic
Boolean Functions

A Boolean function can be transformed from an algebraic expression into a

circuit diagram composed of logic gates connected in a particular structure.
Gate-Level Minimization and Combinational logic
Boolean Functions
• There is only one way that a Boolean function can be
represented in a truth table.
• However, when the function is in algebraic form, it can be
expressed in a variety of ways, all of which have
equivalent logic.

• Boolean algebra, it is sometimes possible to obtain a

simpler expression for the same function and thus reduce
the number of gates in the circuit and the number of
inputs to the gate.
Gate-Level Minimization and Combinational logic
Boolean Functions
• Designers are motivated to reduce the complexity and
number of gates because their effort can significantly
reduce the cost of a circuit.
• What is simplest form of below equation?

Solution:
Gate-Level Minimization and Combinational logic
Boolean Functions
Gate-Level Minimization and Combinational logic
Boolean Functions
Algebraic Manipulation
Gate-Level Minimization and Combinational logic
Boolean Functions
Complement of a Function
Gate-Level Minimization and Combinational logic
Boolean Functions
Complement of a Function
Gate-Level Minimization and Combinational logic
What is a Logic Circuit?
Logic Circuit Example Logic Circuit
a b c y
Multiple logic gates a1 0u
t0 0 0 0 0
combined together, with
1y 0 0 1 0
the output of one gate 0 1 0 0
being connected to the b1 1v
c 1 0 1 1 1
input of another, form a 1 0 0 0
logic circuit Boolean function
1 0 1 1
1 1 0 1
Does a logic circuit 1 1 1 1
Truth table
represent a Boolean
function?
Gate-Level Minimization and Combinational logic
What is Boolean Algebra?
Algebra
In mathematics, an Algebra is composed of four
things: a set of elements, operations on those
elements, identity elements and laws/identities
StandardAlgebra Boolean Algebra
1 Set Real numbers 1 Set {0,1}
2 Operations Add, subtract, multiply, divide 2 Operations AND, OR, NOT
3 Identity elements 0 (for add), 1 (for multiply) 3 Identity elements 1 (for AND),
4 Laws/Identities Commutative, associative, 0 (for OR)
distributive, . .. 4 Laws/Identities Commutative,
associative, distributive, . . .
 Gate-Level Minimization and Combinational logic
Boolean Identities / Laws
Name Law Dual Law
Commutative a ·b = b · a a +b = b +a
Associative (a ·b) · c = a ·(b ·c) (a + b) + c = a + (b + c)
Distributive a ·(b + c) = a ·b + a ·c a + (b ·c) = (a + b) ·(a + c)

DeMorgan’s (a + b) `= a`·b` (a ·b)' = a`+ b`

Principle of Duality
Bool equation remains true if + and · are exchanged, and also 0 and 1 areexchanged
 Gate-Level Minimization and Combinational logic
Boolean Identities / Laws

Name Law Dual Law

Idempotency a ·a = a a +a = a
Identity a ·1 = a a +0 = a
Boundedness a ·0 = 0 a +1 = 1
Complement a ·a = 0 a +a = 1
Absorption a +a ·b = a a ·(a + b) = a
Involution a =a
Useful Identity a + a ·b = a + b a ·(a + b) = a · b

Boolean identities will be used for proving Boolean formula equivalence and logic minimization
Gate-Level Minimization and Combinational logic
From Truth Table to Boolean Formula and its Minimization
Given a combinational logic circuit or Boolean formula, we have
learnt to construct its truth table
But, given a truth table, how to construct a Boolean formula (or
combinational logic circuit) for it?
Also, as there are multiple Boolean formulas / logic circuits for each
truth table, how to pick the minimal one?
Above problem is called logic minimization
• many metrics: smallest, fastest, least power cosumption
• our metric: smallest two level Sum of Products formula
• may be more than one solution
Gate-Level Minimization and Combinational logic
Canonical and Standard Forms

Literal Boolean variable or its complement (ex: c)

Product (or implicant) AND of two or Sum OR of two or more literals

more literals (ex: abc) Maxterm Sum involving all inputs to
Minterm Product involving all inputs to Boolean function
Boolean function a b c maxterm name
a b c minterm name 0 0 0 a+b+c M0
0 0 0 a’b’c’ m0 0 0 1 a +b+c’ M1
0 0 1 a’b’c m1 0 1 0 a +b’+c M2
0 1 0 a’bc’ m2 0 1 1 a +b’+c’ M3
0 1 1 ab’c’ m3 1 0 0 a’ +b+c M4
1 0 0 ab’c’ m4 1 0 1 a’ +b+c’ M5
1 0 1 ab’c m5 1 1 0 a’+b’+c M6
1 1 0 abc’ m6 1 1 1 a’ + b’ + c’ M7
1 1 1 abc m7 Maxterms for three inputs a, b and c
Minterms for three inputs a, b and c
Gate-Level Minimization and Combinational logic
Canonical and Standard Forms
SOP Form
Sum of all minterms(standard product terms) corresponding to a 1 output

SOP Example
Truth table: SOP form Boolean formula:
a b c y minterm name y = a’bc+ ab’c’+ abc’+ abc
0 0 0 0 a’b’c’ m0
y = m3 + m4 + m6 + m7
0 0 1 0 a’b’c m1
0 1 0 0 a’bc’ m2 Sigma (Σ) notation:
0 1 1 1 a’bc m3 y = Σ ( m3 , m4 , m6 , m7 )
1 0 0 1 ab’c’ m4
1 0 1 0 ab’c m5 y = Σ ( 3, 4, 6, 7)
1 1 0 1 abc’ m6 If the Boolean function is called f :
1 1 1 1 abc m7 y = f (a, b, c )
Gate-Level Minimization and Combinational logic
Canonical and Standard Forms
POS Form
Product of all maxterms corresponding to a 0 output

POS Example
Truth table: SOP form Boolean formula:
a b c y maxterm name y = (a+b +c )(a+b +c ’ ) ( a +b ’ + c ) ( a ’ + b + c ’ )
0 0 0 0 a+b+c M0
0 0 1 0 a + b+ c’ M1 y = M0 M1 M2 M5
0 1 0 0 a + b’+ c M2 Pi (Π) notation:
0 1 1 1 a +b ’+ c’ M3 y = Π(M 0 , M 1 , M 2 , M 5 )
1 0 0 1 a’ + b+ c M4
1 0 1 0 a’ +b + c’ M5 y = Π(0, 1, 2, 5)
1 1 0 1 a’+ b’+ c M6 If the Boolean function is called f :
1 1 1 1 a’ + b’ + c’ M7
y = f (a, b, c )
Gate-Level Minimization and Combinational logic
Canonical and Standard Forms
Minterms and Maxterms
Gate-Level Minimization and Combinational logic
Canonical and Standard Forms
Minterms and Maxterms

f1 = x’y’z + xy’z’ + xyz = m1 + m4 + m7

f2 = x’yz + xy’z + xyz’ + xyz

= m3 + m5 + m6 + m7
Gate-Level Minimization and Combinational logic
Canonical and Standard Forms
Sum of Minterms
Gate-Level Minimization and Combinational logic
Canonical and Standard Forms
Sum of Minterms
Gate-Level Minimization and Combinational logic
Canonical and Standard Forms
Product of Maxterms
Gate-Level Minimization and Combinational logic
Canonical and Standard Forms
Conversion Between Canonical Forms
Gate-Level Minimization and Combinational logic
Canonical forms- Quick pointers
Minterm-standard product, forming AND term
Max term- standard SUM, forming OR term
Each maxterm is the complement of its corresponding
minterm and vice versa
Boolean function expressed as sum of minterms or product
of max terms is called canonical form
• The minterms whose sum defines the Boolean function
are those which give the 1’s of the function in a truth
table
Gate-Level Minimization and Combinational logic
Canonical forms- Quick pointers
Find min terms of the following function:
F=A+B`C

Express the Boolean function F = xy + xz as a product of

maxterms. First, convert the function into OR terms by
using the distributive law
Gate-Level Minimization and Combinational logic
Standard forms
Gate-Level Minimization and Combinational logic
Standard forms
THANK YOU

Team DDCO
Department of Computer Science
 DIGITAL DESIGN AND
COMPUTER ORGANIZATION
Gate-Level Minimization and Combinational logic
Department of Computer Science and Engineering
DIGITAL DESIGN AND
COMPUTER ORGANIZATION

The Map Method Four Variable K -Map

Department of Computer Science and Engineering

Gate-Level Minimization and Combinational logic
The Map Method Four Variable K Map
Two-variable K-map.
 Gate-Level Minimization and Combinational logic
The Map Method Four Variable K Map
Two-variable K-map.
• There are four minterms for two variables; hence, the map consists of
four squares, one for each minterm.

• The map is redrawn in (b) to show the relationship between the

squares and the two variables x and y.

• The 0 and 1 marked in each row and column designate the values of
variables.
Gate-Level Minimization and Combinational logic
The Map Method Four Variable K Map
Two-variable K-map.
(a)F(x, y) = 𝚺(3) (b)F(x, y) = 𝚺(1,2,3)

Representation of functions in the K-map.

 Gate-Level Minimization and Combinational logic
The Map Method Four Variable K Map
Two-variable K-map.
• The three squares could also have been determined from
the intersection of variable x in the second row and
variable y in the second column, which encloses the area
belonging to x or y .

• In each example, the minterms at which the function is

asserted are marked with a 1.
Gate-Level Minimization and Combinational logic
The Map Method Four Variable K Map

Three-variable K-map.

Three-variable K-map.
 Gate-Level Minimization and Combinational logic
The Map Method Four Variable K Map

Three-variable K-map.

• The characteristic of this sequence is that only one bit

changes in value from one adjacent column to the next.
• The map drawn in part (b) is marked with numbers in each
row and each column to show the relationship between the
squares and the three variables.
• Gray code ensures that only one variable changes between
each pair of adjacent cells.
Gate-Level Minimization and Combinational logic
The Map Method Four Variable K Map

Three-variable K-map.

Map for Example F(x, y, z) = 𝚺(2, 3, 4, 5) = x’y + xy’.

Gate-Level Minimization and Combinational logic
The Map Method Four Variable K Map

Three-variable K-map.

Map for Example F(x, y, z) = 𝚺(3, 4, 6, 7) = yz + xz’.

Gate-Level Minimization and Combinational logic
The Map Method Four Variable K Map
Three-variable K-map.

Map for F(x, y, z) = 𝚺(0, 2, 4, 5, 6) = z’ + xy’.

 Gate-Level Minimization and Combinational logic The
The Map Method Four Variable K Map
Three-variable K-map.

Map of Example F(x, y, z) = 𝚺(1, 2,3, 5, 7)

A’C + A’B + AB’C + BC = C + A’B.
Gate-Level Minimization and Combinational logic
The Map Method Four Variable K Map
Four-variable K-map.

Four-variable map.
 Gate-Level Minimization and Combinational logic
The Map Method Four Variable K Map
Four-variable K-map.
• The map minimization of four-variable Boolean
functions is similar to the method used to minimize
three-variable functions. Adjacent squares are defined
to be squares next to each other.
• For example, m0 and m2 form adjacent squares, as do
m3 and m11.
• The combination of adjacent squares that is useful
during the simplification process is easily determined
from inspection of the four-variable map:
Gate-Level Minimization and Combinational logic
The Map Method Four Variable K Map
Four-variable K-map.
• One square represents one minterm, giving a term with
four literals.
• Two adjacent squares represent a term with three literals.
• Four adjacent squares represent a term with two literals.
• Eight adjacent squares represent a term with one literal.
• Sixteen adjacent squares produce a function that is
always equal to 1
Gate-Level Minimization and Combinational logic
The Map Method Four Variable K Map
Four-variable K-map.

Map for Example F(w, x, y, z) = 𝚺(0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14) = y’ + w’z’ + xz’.
 Gate-Level Minimization and Combinational logic
The Map Method Four Variable K Map
Four-variable K-map.

Map for Example F(w, x, y, z) = 𝚺(0, 1, 2, 6, 8, 9, 10)

A’B’C’ + B’CD’ + A’BCD’ + AB’C = B’D’ + B’C’ + A’CD’.
 Gate-Level Minimization and Combinational logic
The Map Method Four Variable K Map
Simplification using prime implicants
(a)F(w, x, y, z) (b) F(w, x, y, z)
= 𝚺(0, 2,5,7,8,10,13,15 ) = 𝚺( 0,2, 3,5,7, 8, 9, 10,11,13,15)
=BD+B’D’ =BD+AD+B’C+B’D’
THANK YOU

Team DDCO
Department of Computer Science
 DIGITAL DESIGN AND
COMPUTER ORGANIZATION
Gate-Level Minimization and Combinational logic.

Department of Computer Science and Engineering

DIGITAL DESIGN AND
COMPUTER ORGANIZATION

Product of sums simplification

Department of Computer Science and Engineering

 Gate-Level Minimization and Combinational logic
Product of sums simplification.

Map for Example F(A, B, C, D) = 𝚺(0, 1, 2, 5, 8, 9, 10) = BD + BC + ACD = (A’ + B’)(C’ +

D’)(B’ + D).
Gate-Level Minimization and Combinational logic
Product of sums simplification.
• The minimized Boolean functions derived from the map in
all previous examples were expressed in sum-of-products
form.
• With a minor modification, the product-of-sums form can
be obtained.
• The procedure for obtaining a minimized function in
product-of-sums form follows from the basic properties of
Boolean functions.
Gate-Level Minimization and Combinational logic
Product of sums simplification.
• The 1’s placed in the squares of the map represent the minterms
of the function.
• The minterms not included in the standard sum-of-products form
of a function denote the complement of the function.
• From this observation, we see that the complement of a function
is represented in the map by the squares not marked by 1’s
• If we mark the empty squares by 0’s and combine them into valid
adjacent squares, we obtain a simplified sum-of-products
expression of the complement of the function (i.e., of F ).
• The complement of F gives us back the function F in product-of-
sums form (a consequence of DeMorgan’s theorem)
Gate-Level Minimization and Combinational logic
Product of sums simplification.
Gate implementations of the function
Gate-Level Minimization and Combinational logic
Product of sums simplification.
Truth Table of Function F(x, y, z) =∑m(1,3,4,6).
Gate-Level Minimization and Combinational logic
Product of sums simplification.

Map for the function F(x, y, z)=∑m(1,3,4,6).

 Gate-Level Minimization and Combinational logic
Don’t-care conditions.
(a)F(w, x, y, z)=∑m(1,3,7,11,15) (b)F(w, x, y, z)=∑m(1,3,7,11,15)
+ d(0,2,5) + d(0,2,5)

.
 Gate-Level Minimization and Combinational logic
Don’t-care conditions.

• Functions that have unspecified outputs for some input

combinations are called incompletely specified functions .
• In most applications, we simply don’t care what value is
assumed by the function for the unspecified minterms.
• For this reason, it is customary to call the unspecified
minterms of a function don’t-care conditions

.
THANK YOU

Team DDCO
Department of Computer Science
 DIGITAL DESIGN AND
COMPUTER ORGANIZATION
Gate-Level Minimization and Combinational logic
Department of Computer Science and Engineering
DIGITAL DESIGN AND
COMPUTER ORGANIZATION

NAND and NOR implementation

Department of Computer Science and Engineering

Gate-Level Minimization and Combinational logic
NAND and NOR implementation

Logic operations with NAND gates.

Gate-Level Minimization and Combinational logic
NAND and NOR implementation

• A convenient way to implement a Boolean function with NAND

gates is to obtain the simplified Boolean function in terms of
Boolean operators and then convert the function to NAND logic.

• The conversion of an algebraic expression from AND, OR, and

complement to NAND can be done by simple circuit manipulation
techniques that change AND–OR diagrams to NAND diagrams.
Gate-Level Minimization and Combinational logic
NAND and NOR implementation

Two graphic symbols for a three-input NAND gate.

 Gate-Level Minimization and Combinational logic
NAND and NOR implementation
• The AND-invert symbol has been defined previously and consists of an
AND graphic symbol followed by a small circle negation indicator
referred to as a bubble.

• It is possible to represent a NAND gate by an OR graphic symbol that

is preceded by a bubble in each input.

• The invert-OR symbol for the NAND gate follows DeMorgan’s

theorem and the convention that the negation indicator (bubble)
denotes complementation.
Gate-Level Minimization and Combinational logic
NAND and NOR implementation

Three ways to implement F = AB + CD.

Gate-Level Minimization and Combinational logic
NAND and NOR implementation

Solution to Solved Example F=∑(1,2,3,4,5,7)

 Gate-Level Minimization and Combinational logic
NAND and NOR implementation

The procedure for obtaining the logic diagram from a Boolean function is as follows:

1. Simplify the function and express it in sum-of-products form.

2. Draw a NAND gate for each product term of the expression that has at least two
literals. The inputs to each NAND gate are the literals of the term. This procedure
produces a group of first-level gates.
3. Draw a single gate using the AND-invert or the invert-OR graphic symbol in the
second level, with inputs coming from outputs of first-level gates.
4. A term with a single literal requires an inverter in the first level. However, if the
single literal is complemented, it can be connected directly to an input of the second
level NAND gate.
Gate-Level Minimization and Combinational logic
NAND and NOR implementation
Multi Level NAND Circuits

Implementing F = A(CD + B) + BC’.

 Gate-Level Minimization and Combinational logic
NAND and NOR implementation

The general procedure for converting a multilevel AND–OR diagram into an

all-NAND diagram using mixed notation is as follows:
1. Convert all AND gates to NAND gates with AND-invert graphic symbols.
2. Convert all OR gates to NAND gates with invert-OR graphic symbols.
3. Check all the bubbles in the diagram. For every bubble that is not
compensated
by another small circle along the same line, insert an inverter (a one-input
NAND
gate) or complement the input literal.
Gate-Level Minimization and Combinational logic
NAND and NOR implementation
Multi Level NAND Circuits
Gate-Level Minimization and Combinational logic
NAND and NOR implementation
NOR implementation

Logic operations with NOR gates.

Gate-Level Minimization and Combinational logic
NAND and NOR implementation
NOR implementation
Gate-Level Minimization and Combinational logic
NAND and NOR implementation
NOR implementation
Gate-Level Minimization and Combinational logic
NAND and NOR implementation
Other Two-Level implementation
• Wired logic is a type of digital logic where some logic operations are
carried out by directly coupling the outputs of a single or several logic
gates.
• A logic gate that uses just passive components like diodes and resistors
to implement boolean algebra is known as a wired logic connection. An
AND or an OR gate can be built using wired logic.
IMP
• Open-collector TTL devices are used when it is necessary to have
multiple outputs and one input. For example, an AND gate may have
two inputs and one output. If both inputs are high, then the output will be IMP
high as well. However, if either input is low, then the device will pull the EXAMPLE
output low. This means that several inputs can be read together even
with a single device.
Gate-Level Minimization and Combinational logic
NAND and NOR implementation
Other Two-Level implementation
Wired-AND function: If two or more open
collector gate outputs are coupled together,
any gate with a logic 0 output will pull all
other connected outputs to logic 0,
providing a logic 0 output at output X;
however, if all connected outputs are at logic
1, then X will be at logic 1, the action of an
‘invisible’ AND gate.
Gate-Level Minimization and Combinational logic
NAND and NOR implementation
Other Two-Level implementation
Wired-OR function: It is also feasible to create a
wired-OR function using open collector (or drain)
gates, Negative Logic is used.
The circuit is utilized without employing a physical
OR gate to obtain the Boolean function
(A•B)+(C•D).
Except for the two open collectors NAND gates in
place of the two open collector AND gates, the circuit
is quite similar to the wired-AND circuit.
However, this circuit’s key distinction is the use of
Negative Logic to produce an OR function from what
initially looks to be an AND function.
Gate-Level Minimization and Combinational logic
NAND and NOR implementation
Other Two-Level implementation

Wired logic
(a) Wired-AND logic with two NAND gates
(b) Wired-OR in emitter-coupled logic (ECL) gates.
 Gate-Level Minimization and Combinational logic
NAND and NOR implementation
Other Two-Level implementation

• NAND or NOR gates allow the possibility of a wire connection between the
outputs of two gates to provide a specific logic function. This type of logic is
called wired logic.
• For example, open-collector TTL NAND gates, when tied together, perform
wired-AND logic.
• The wired-AND logic performed with two NAND gates is depicted in
Figure
Gate-Level Minimization and Combinational logic
Other Two-Level Implementations
• The logic function implemented by the circuit of Fig (a) is
F = (AB)’.(CD)’ = (AB + CD)’ = (A’ + B’)(C’ + D’) and is called
an AND–OR–INVERT function.
• Similarly, the NOR outputs of ECL gates can be tied together
to perform a wired-OR function.
• The logic function implemented by the circuit of Fig. (b) is F
= (A + B)’+ (C + D)’ = [(A + B)(C + D)]’ and is called an OR–
AND–INVERT function.
 Gate-Level Minimization and Combinational logic
NAND and NOR implementation

AND–OR–INVERT circuits, F = (AB + CD + E)’.

Gate-Level Minimization and Combinational logic
NAND and NOR implementation

OR–AND–INVERT circuits, F = [(A + B)(C + D)E]’.

Gate-Level Minimization and Combinational logic
NAND and NOR implementation

Table :Implementation with Other Two-Level Forms.

Gate-Level Minimization and Combinational logic
NAND and NOR implementation
EXAPMLE 3.14 (DO IT FROM BOOK)

Other two-level implementations.

F’=(x’y+xy’+z)
F=(x’y+xy’+z)’
 Gate-Level Minimization and Combinational logic
Exclusive-OR Function
The exclusive-OR (XOR), denoted by the symbol , is a logical operation that
performs the following Boolean operation:
x y = xy’ + x’y
The exclusive-OR is equal to 1 if only x is equal to 1 or if only y is equal to 1 (i.e., x
and y differ in value), but not when both are equal to 1 or when both are equal to 0.
(x y)’ = xy + x’y’
 Gate-Level Minimization and Combinational logic
NAND and NOR implementation

Logic diagrams for exclusive-OR implementations.

Gate-Level Minimization and Combinational logic
NAND and NOR implementation

Map for a three-variable exclusive-OR function.

 Gate-Level Minimization and Combinational logic
NAND and NOR implementation

Logic diagram of odd and even functions.

Gate-Level Minimization and Combinational logic
NAND and NOR implementation

Map for a four-variable exclusive-OR function.

Gate-Level Minimization and Combinational logic
Parity Generation and Checking

Even-Parity-Generator Truth Table.

 Gate-Level Minimization and Combinational logic
Parity Generation and Checking
• A parity bit is an extra bit included with a binary message to
make the number of 1’s either odd or even. The message,
including the parity bit, is transmitted and then checked at the
receiving end for errors

• An error is detected if the checked parity does not correspond

with the one transmitted. The circuit that generates the parity bit
in the transmitter is called a parity generator. The circuit that
checks the parity in the receiver is called a parity checker.
Gate-Level Minimization and Combinational logic
NAND and NOR implementation

Logic diagram of a parity generator and checker.

 Gate-Level Minimization and Combinational logic
NAND and NOR implementation

Even-Parity-Checker Truth Table.

THANK YOU

Team DDCO
Department of Computer Science
 DIGITAL DESIGN AND
COMPUTER ORGANIZATION
Gate-Level Minimization and Combinational logic
Department of Computer Science and Engineering
DIGITAL DESIGN AND
COMPUTER ORGANIZATION

Combinational Circuits
Analysis Procedure
Design Procedure

Department of Computer Science and Engineering

 Gate-Level Minimization and Combinational logic
Combinational Circuits
Introduction
• There are two types of Logic Circuits:
• Combinational
• Sequential
• Combinational Circuits consists of logic gates whose output at
any time is function of the present inputs only.
• Sequential Circuits along with logic gates use storage elements.
The value stored in these elements is due to a previous
combination of inputs. Thus the present output of a sequential
circuits depends upon the present and the past inputs.
 Gate-Level Minimization and Combinational logic
Combinational Circuits
• A combinational circuit consists of input variables, logic gates and
output variables.
• For n input variables there will be a total 2 n input combinations and the
pattern of m outputs w.r.t the different combination can be listed in the
form of a truth table.
• A combinational circuit can be represented by a truth table having n
inputs & m outputs or it can be represented by a Boolean function
having m equations one for each output variable.
 Gate-Level Minimization and Combinational logic
Combinational Circuits

Block diagram of combinational circuit

Gate-Level Minimization and Combinational logic
Analysis Procedure
• The analysis starts with a given logic diagram and culminates with
• A set of Boolean functions
• A Truth Table
• or, possibly, an explanation of the circuit operation
• The first step in the analysis is to make sure that the given circuit is
combinational and not sequential.
• The diagram of a combinational circuit has logic gates with no feedback
paths or memory elements.
• A feedback path is a connection from the output of one gate to the input
of a second gate whose output forms part of the input to the first gate.
Gate-Level Minimization and Combinational logic
Analysis Procedure
Analysis Procedure(Boolean Function)
1. Label all gate outputs that are a function of input variables with
arbitrary symbols—but with meaningful names. Determine the
Boolean functions for each gate output.
2. Label the gates that are a function of input variables and previously
labeled gates with other arbitrary symbols. Find the Boolean
functions for these gates.
3. Repeat the process outlined in step 2 until the outputs of the circuit
are obtained.
4. By repeated substitution of previously defined functions, obtain the
output Boolean functions in terms of input variables.
Gate-Level Minimization and Combinational logic
Analysis Procedure
Logic diagram for analysis example
 Gate-Level Minimization and Combinational logic
Analysis Procedure
The Boolean functions for these three outputs are
F2 = AB + AC + BC
T1 = A + B + C
T2 = ABC
Next, we consider outputs of gates that are a function of already defined symbols:
T3 = F2’ T1
F1 = T3 + T2
To obtain F1 as a function of A , B , and C , we form a series of substitutions as follows:
F1 = T3 + T2 = F2’ T1 + ABC = (AB + AC + BC)’(A + B + C) + ABC
= (A’ + B’) (A’ + C’) (B’ + C’) (A + B + C) + ABC
= (A’ + B’C’)(AB’ + AC’ + BC’ + B’C)+ ABC
= A’BC’ + A’B’C + ABC + AB’C’
Gate-Level Minimization and Combinational logic
Analysis Procedure
To obtain the truth table directly from the logic diagram without going
through the derivations of the Boolean functions, we proceed as follows:
1. Determine the number of input variables in the circuit. For n inputs, form
the 2n possible input combinations and list the binary numbers from 0 to
(2n - 1) in a table.
2. Label the outputs of selected gates with arbitrary symbols.
3. Obtain the truth table for the outputs of those gates which are a function
of the input variables only.
4. Proceed to obtain the truth table for the outputs of those gates which
are a function of previously defined values until the columns for all outputs
are determined.
Gate-Level Minimization and Combinational logic
Analysis Procedure
Truth Table for the Logic Diagram
Gate-Level Minimization and Combinational logic
Design Procedure
1.Determine the number of inputs and outputs from the circuit functionality,
then draw a block diagram without the internal details. This is exactly similar
to function prototype in programming.
2.Derive a truth table
3.Simplify the expression
4.Implement the circuit
Code Conversion Example
Design a circuit that converts from a BCD code to excess-3 code.
Motivation:
• Some circuits use excess-3 code and we need to feed this circuit with the
right input.
• Very easy to complement:9-x is obtained by inverting the digits!
Gate-Level Minimization and Combinational logic
Design Procedure

Truth Table for Code Conversion Example.

Gate-Level Minimization and Combinational logic
Design Procedure
Maps for BCD-to-excess-3 code converter.
Gate-Level Minimization and Combinational logic
Design Procedure
BCD-to-excess-3 code converter.
The expressions obtained may be manipulated algebraically for the
purpose of using common gates for two or more outputs
z = D’
y = CD + C’D’ = CD + (C + D)
x = B’C + B’D + BC’D’ = B’(C + D) + BC’D’
= B’(C + D) + B(C + D)’
w = A + BC + BD = A + B(C + D)
Gate-Level Minimization and Combinational logic
Design Procedure
Logic diagram for BCD-to-excess-3 code converter.
Gate-Level Minimization and Combinational logic
Design Procedure
BCD-to-excess-3 code converter.

• Note that the OR gate whose output is C + D has been

used to implement partially each of three outputs.
• Not counting input inverters, the implementation in
sum-of-products form requires seven AND gates and
three OR gates.
• The implementation of Figure in previous slide requires
four AND gates, four OR gates, and one inverter.
Gate-Level Minimization and Combinational logic
Design Procedure
Binary to Gray code converter.
Gray code – also known as Cyclic Code, Reflected Binary Code (RBC),
Reflected Binary (RB) or Grey code – is defined as an ordering of the binary
number system such that each incremental value can only differ by one bit.
Two adjacent code numbers differ from each other by only one bit.
Gate-Level Minimization and Combinational logic
Design Procedure
Binary to Gray code converter. SUPER IMPORTANT

How to Convert Binary to Gray Code

1.The MSB (Most Significant Bit) of the gray code will 4 3 2 1
be exactly equal to the MSB first bit of the given binary
or first bit as A is first bit here
number.
2.The second bit of the code will be exclusive-or (XOR)
of the first and second bit of the given binary number, i.e
if both the bits are same the result will be 0 and if they
are different the result will be 1.
3.The third bit of gray code will be equal to the
exclusive-or (XOR) of the second and third bit of the
given binary number. Thus the binary to gray code
conversion goes on
Gate-Level Minimization and Combinational logic
Design Procedure
Binary to Gray code converter.

G4=A
G3 =A’B+AB’=A⊕B
G2=B’C+BC’=B⊕C
G1=C’D+CD’=C⊕D
Gate-Level Minimization and Combinational logic
Design Procedure
Gray to Binary code converter.
Gray Code to Binary Conversion
1.The MSB of the binary number will be equal to the MSB of the given gray
code.
2.Now if the second gray bit is 0, then the second binary bit will be the same as
the previous or the first bit. If the gray bit is 1 the second binary bit will alter. If
it was 1 it will be 0 and if it was 0 it will be 1.
3.This step is continued for all the bits to do Gray code to binary conversion.
Gate-Level Minimization and Combinational logic
Design Procedure
Gray code to Binary converter.

B4=A
B3 =A’B+AB’=A⊕B
B2=A⊕ B⊕C
B1= A⊕ B⊕ C⊕D
Gate-Level Minimization and Combinational logic
Design Procedure
8 4 -2 -1 to BCD conversion

0
4-3=1
4-2=2
4-3=1
4
8-3=5
8-2=6
8-1=7
8
12-3=9
Gate-Level Minimization and Combinational logic
Design Procedure
8 4 -2 -1 to BCD conversion

W=AB+AC’D’
X =BC’D’+B’D+B’C
Y=C’D+CD’= C⊕D
Z= D
THANK YOU

Team DDCO
Department of Computer Science
 DIGITAL DESIGN AND
COMPUTER ORGANIZATION
Gate-Level Minimization and Combinational logic
Department of Computer Science and Engineering
DIGITAL DESIGN AND
COMPUTER ORGANIZATION

Adder Subtractor Decimal Adder

Department of Computer Science and Engineering

 Gate-Level Minimization and Combinational logic
Adder Subtractor
Binary Adder-Subtractor
• A binary adder–subtractor is a combinational circuit that
performs the arithmetic operations of addition and subtraction
with binary numbers.
• A combinational circuit that performs the addition of two bits is
called a half adder.
• One that performs the addition of three bits (two significant bits
and a previous carry) is a full adder
• The names of the circuits stem from the fact that two half adders
can be employed to implement a full adder.
Gate-Level Minimization and Combinational logic
Adder Subtractor
Binary Adder

• Simple addition consists of four possible elementary

operations:
0+0 = 0
0+1 = 1
1+0 = 1
1+1 = 10 ← Sum has Carry
Half Adder (two ‘2’ input bits)
Full Adder (three ‘3’ input bits)
 Gate-Level Minimization and Combinational logic
Adder Subtractor
Half Adder

• The simplified Boolean functions for the two outputs can be obtained
directly from the truth table. The simplified sum-of-products
expressions are
S = x’y + xy’
C = xy
Gate-Level Minimization and Combinational logic
Adder Subtractor
Truth Table of Half Adder
Gate-Level Minimization and Combinational logic
Adder Subtractor
Implementation of half adder.
 Gate-Level Minimization and Combinational logic
Adder Subtractor
Full Adder

• A full adder is a combinational circuit that forms the arithmetic sum of

three bits. It consists of three inputs and two outputs. Two of the input
variables, denoted by x and y ,represent the two significant bits to be
added.
• The simplified expressions are

S = x’y’z + x’yz’+ xy’z’+ xyz

C = xy + xz + yz
Gate-Level Minimization and Combinational logic
Adder Subtractor
Truth Table of Full Adder
Gate-Level Minimization and Combinational logic
Adder Subtractor

K-map for full adder.

Gate-Level Minimization and Combinational logic
Adder Subtractor

Implementation of full adder in sum-of-products form.

 Gate-Level Minimization and Combinational logic
Adder Subtractor
Full Adder
• The S output from the second half adder is the exclusive-OR of z and
the output of the first half adder, giving
Gate-Level Minimization and Combinational logic
Adder Subtractor

Implementation of full adder with two half adders and an OR gate.

Gate-Level Minimization and Combinational logic
Adder Subtractor
Half Subtractor

Diff= A'B+AB'
Borrow = A'B
Gate-Level Minimization and Combinational logic
Adder Subtractor
Full Subtractor D = A’B’Bin + A’BBin’ + AB’Bin’ + ABBin
= Bin(A’B’ + AB) + Bin’(AB’ + A’B)
= Bin( A XNOR B) + Bin’(A XOR B)
= Bin (A XOR B)’ + Bin’(A XOR B)
= Bin XOR (A XOR B)
= (A XOR B) XOR Bin

Bout = = A’Bin + A’B + BBin

Bout = A’B’Bin + A’BBin’ + A’BBin + ABBin
= Bin(AB + A’B’) + A’B(Bin + Bin’)
= Bin( A XNOR B) + A’B
= Bin (A XOR B)’ + A’B
Gate-Level Minimization and Combinational logic
Adder Subtractor
Binary Adder
• Consider a 4-bit adder. Let's denote Ai and Bi as the input bits
of the two binary numbers and Ci is the carry from previous
bit addition of the numbers.
• We also let Si be the sum and Ci+1 the carry output in the
current addition.
Gate-Level Minimization and Combinational logic
Adder Subtractor
Implementation of Four-bit binary adder can be implemented by
using 4 full adders
Gate-Level Minimization and Combinational logic
Adder Subtractor
Carry Propagation
• In addition of two binary numbers in parallel implies that all the bits
of the augend and addend are available for computation at the same
time.
• The total propagation time is equal to the propagation delay of a
typical gate, times the number of gate levels in the circuit.
• For a n-bit adder, there are 2 n gate levels for the carry to propagate
from input to output.
• Carry propagation time is an important attribute of the adder because
it limit the speed with which two numbers are added. Consider the
circuit of the full adder
Gate-Level Minimization and Combinational logic
Adder Subtractor
Carry Propagation
• Consider the circuit of the full adder. If we define two new binary variables

• Pi=carry propagate
• Gi=Carry generate
• Carry lookahead logic-most widely used technique to reduce the carry
delay time
Gate-Level Minimization and Combinational logic
Adder Subtractor
Full adder with P and G shown.
Gate-Level Minimization and Combinational logic
Adder Subtractor
Logic diagram of carry lookahead generator
Gate-Level Minimization and Combinational logic
Adder Subtractor
Four-bit adder with carry lookahead.
Gate-Level Minimization and Combinational logic
Adder Subtractor
BCD adder
In BCD, it is obvious that the most significant bit (leftmost) is always 0,
and therefore each digit will be confined to the range 0-9.

A BCD adder contains four full-adder circuits in cascade. Each full-adder

is contrived to consider both the two BCD digits being added and a carry-
in from the previous stage. The output of each full-adder produces a sum
bit and a carry-out bit, which becomes the input to the following stage.

When adding BCD numbers, if the sum of two BCD digits is greater than
9, the result is greater than 1001 in binary and hence is not valid in BCD.
A correction needs to be performed by adding 0110 (6 in BCD) to the sum
to get the correct BCD result.
Gate-Level Minimization and Combinational logic
Adder Subtractor
Derivation of BCD adder
 Gate-Level Minimization and Combinational logic
Adder Subtractor
BCD adder
Note: If the sum of two numbers is less than or equal to 9, then the value of
BCD sum and binary sum will be same otherwise they will differ by 6(0110
in binary).
BCD Correction : We are adding “0110” (=6) only to the second half of the table.
The conditions are:
1.If K = 1 (Satisfies 16-19)
2.If Z8Z4 = 1 (Satisfies 12-15)
3.If Z8Z2 = 1 (Satisfies 10 and 11)
So, the logic is
K + Z8Z4 + Z8Z2 = 1
Gate-Level Minimization and Combinational logic
Adder Subtractor
Block Diagram of BCD adder
 Overflow condition
When two numbers with n digits each are added and the sum is a number
occupying n + 1 digits, we say that an overflow occurred

The detection of an overflow after the addition of two binary numbers depends
on whether the numbers are considered to be signed or unsigned.

When two unsigned numbers are added, an overflow is detected from the end
carry out of the most significant position.

Signed numbers
MSB(leftmost bit)- sign
Negative numbers are represented in 2’s complement.

Overflow will not occur if opposite sign

Overflow will occur if same sign
+70 and +80 are eight bit numbers Range: +127 to -128
70 + 80=150 – not in range
-70-80= -150 not in range
Note that the eight-bit result that should have been positive has a negative sign bit (i.e., the
eighth bit) and the eight-bit result that should have been negative has a positive sign bit. If,
however, the carry out of the sign bit position is taken as the sign bit of the result, then the
nine-bit answer so obtained will be correct. But since the answer cannot be accommodated
within eight bits, we say that an overflow has occurred
Gate-Level Minimization and Combinational logic
Adder Subtractor
Four-bit adder–subtractor(with Overflow Detection)
Gate-Level Minimization and Combinational logic
Adder Subtractor

The mode input M controls the operation.

When M = 0, the circuit is an adder, and when M = 1, the circuit becomes a
subtractor.
Each exclusive-OR gate receives input M and one of the inputs of B .
When M = 0, we have B XOR 0 = B. The full adders receive the value of B
, the input carry is 0, and the circuit performs A plus B .
When M = 1, we have B XOR 1 = B’ and C0 = 1. The B inputs are all
complemented and a 1 is added through the input carry.
The circuit performs the operation A plus the 2’s complement of B .
(The exclusive-OR with output V is for detecting an overflow.)
THANK YOU

Team DDCO
Department of Computer Science
 DIGITAL DESIGN AND
COMPUTER ORGANIZATION
Gate-Level Minimization and Combinational logic
Department of Computer Science and Engineering
DIGITAL DESIGN AND
COMPUTER ORGANIZATION

Binary Multipliers and Magnitude Comparator

Department of Computer Science and Engineering

Gate-Level Minimization and Combinational logic
Binary Multipliers

➢ Multiplication of binary numbers is performed in the same way as

multiplication of decimal numbers.

➢ The multiplicand is multiplied by each bit of the multiplier, starting from

the least significant bit. Each such multiplication forms a partial product.

Successive partial products are shifted one position to the left.

➢ The final product is obtained from the sum of the partial products.
Gate-Level Minimization and Combinational logic
Binary Multipliers

Two-bit by two-bit binary multiplier.

 Gate-Level Minimization and Combinational logic
Binary Multipliers

Consider the multiplication of two 2-bit numbers

➢ The multiplicand bits are B1 and B0, the
multiplier bits are A1 and A0,and the product is
C3C2C1C0.
➢ The first partial product is formed by multiplying
B1B0 by A0.
➢ The multiplication of two bits such as A0 and B0
produces a 1 if both bits are 1; otherwise, it
produces a 0. This is identical to an AND
operation. Therefore, the partial product can be
implemented with AND gates as shown in the
diagram.
 Gate-Level Minimization and Combinational logic
Binary Multipliers

➢ The second partial product is formed by

multiplying B1B0 by A1 and shifting one position
to the left.
➢ The two partial products are added with two half-
adder (HA) circuits. Usually, there are more bits
in the partial products and it is necessary to use
full adders to produce the sum of the partial
products.
➢ Note that the least significant bit of the product
does not have to go through an adder, since it is
formed by the output of the first AND gate.
Gate-Level Minimization and Combinational logic
Binary Multipliers

Binary multipliers.

➢ A combinational circuit binary multiplier with more bits can be constructed in a

similar fashion.
➢ A bit of the multiplier is ANDed with each bit of the multiplicand in as many
levels as there are bits in the multiplier.
➢ The binary output in each level of AND gates is added with the partial product of
the previous level to form a new partial product. The last level produces the
product.
➢ For J multiplier bits and K multiplicand bits, we need (J * K) AND gates and (J
– 1) K -bit adders to produce a product of (J + K) bits.
Gate-Level Minimization and Combinational logic
Binary Multipliers

Four-bit by three-bit binary multiplier.

➢ Consider a multiplier circuit that

multiplies a binary number
represented by four bits by a
number represented by three
bits.
➢ Let the multiplicand be
represented by B3B2B1B0 and
the multiplier by A2A1A0.
➢ Since K = 4 and J = 3, we need
12 AND gates and two 4-bit
adders to produce a product of
seven bits
Gate-Level Minimization and Combinational logic
Magnitude Comparators

1 Bit magnitude comparator

A>B : AB’
A<B : A’B
A=B : A’B’ + AB
Gate-Level Minimization and Combinational logic
Magnitude Comparators

2 Bit magnitude comparator

A>B:A1B1’ + A0B1’B0’ + A1A0B0’
INPUT OUTPUT A=B: A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’
A1 A0 B1 B0 A<B A=B A>B : A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’)
0 0 0 0 0 1 0 : (A0B0 + A0’B0’) (A1B1 + A1’B1’)
0 0 0 1 1 0 0 : (A0 Ex-Nor B0) (A1 Ex-Nor B1)
0 0 1 0 1 0 0 A<B:A1’B1 + A0’B1B0 + A1’A0’B0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0
0 1 1 1 1 0 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 0
Gate-Level Minimization and Combinational logic
Magnitude Comparators

➢ A magnitude comparator is a combinational circuit that compares two

numbers A and B and determines their relative magnitudes. The outcome of
the comparison is specified by three binary variables that indicate whether A
> B, A = B, or A < B.
➢ On the one hand, the circuit for comparing two n -bit numbers has 22n entries
in the truth table and becomes too cumbersome, even with n = 3
➢ Consider two numbers, A and B , with four digits each. Write the coefficients
of the numbers in descending order of significance:
A = A3 A2 A1 A0
B = B3 B2 B1 B0
➢ The two numbers are equal if all pairs of significant digits are equal: A3 = B3,
A2 = B2, A1 = B1, and A0 = B0.
Gate-Level Minimization and Combinational logic
Magnitude Comparators

➢ When the numbers are binary, the digits are either 1 or 0, and the equality of
each pair of bits can be expressed logically with an exclusive-NOR function
as
xi = AiBi + Ai Bi for i = 0, 1, 2, 3
where xi = 1 only if the pair of bits in position i are equal (i.e., if both are 1
or both are 0).
Gate-Level Minimization and Combinational logic
Magnitude Comparators

Four-bit Magnitude Comparator

In a 4-bit comparator, the condition of A>B can be
possible in the following four cases.
If A3 = 1 and B3 = 0
If A3 = B3 and A2 = 1 and B2 = 0
If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0
Similarly, the condition for A<B can be possible in
the following four cases.
If A3 = 0 and B3 = 1
If A3 = B3 and A2 = 0 and B2 = 1
If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1
The condition of A=B is possible only when all the
individual bits of one number exactly coincide
with the corresponding bits of another number.
Gate-Level Minimization and Combinational logic
Magnitude Comparators

➢ For equality to exist, all xi variables must be equal to 1, a condition that dictates an
AND operation of all variables:
(A = B)= x3x2x1x0
➢ The binary variable (A = B) is equal to 1 only if all pairs of digits of the two numbers
are equal.
➢ To determine whether A is greater or less than B , we inspect the relative magnitudes
of pairs of significant digits, starting from the most significant position.
➢ If the two digits of a pair are equal, we compare the next lower significant pair of
digits.
➢ The comparison continues until a pair of unequal digits is reached. If the
corresponding digit of A is 1 and that of B is 0, we conclude that A > B.
➢ If the corresponding digit of A is 0 and that of B is 1, we have A < B.
Gate-Level Minimization and Combinational logic
Magnitude Comparators

➢ The sequential comparison can be expressed logically by the two Boolean functions
(A > B) = A3B3’ + x3 A 2B2’ + x3x2A1B1’ + x3x2x1A0B0’
(A < B) = A3’B3 + x3A2’B2 + x3x2A1’B1 + x3x2x1A’0B0
➢ The symbols (A > B) and (A < B) are binary output variables that are equal to 1 when
A > B and A < B, respectively.
➢ The unequal outputs can use the same gates that are needed to generate the equal
output
➢ The four x outputs are generated with exclusive-NOR circuits and are applied to an
AND gate to give the output binary variable (A = B) .
➢ The other two outputs use the x variables to generate the Boolean functions listed
previously. This is a multilevel implementation and has a regular pattern.
THANK YOU

Team DDCO
Department of Computer Science
 DIGITAL DESIGN AND
COMPUTER ORGANIZATION
Gate-Level Minimization and Combinational logic
Department of Computer Science and Engineering
DIGITAL DESIGN AND
COMPUTER ORGANIZATION

Decoders

Department of Computer Science and Engineering

 Gate-Level Minimization and Combinational logic
Decoders
Decoder is a combinational Circuit that converts binary information from n input lines to a n
n
maximum of 2 unique output lines. Decoders presented here are n-to-m line decoder where m < _2
Decoders

Black box with n input lines and 2n output lines

2n outputs
n inputs Binary
Decoder

Decoder are used in binary to octal conversion

Only one output is a 1 for any given input

 Gate-Level Minimization and Combinational logic
Decoders

1:2 Decoder
1:2 decoder symbol: 1:2 decoder logic circuit: 1:2 decoder truth table:
j o0 o1
oo 0 1 0
0 o0
o1 1 0 1
1 o1
j 1:2 decoder Boolean
formula:
j o0 = j
o1 = j
Inputs: j
Output: o0, o1
Gate-Level Minimization and Combinational logic
Decoders
From truth table, circuit for 2x4
decoder is:
F0
X
2-to-4 F1 Note: Each output is a 2-variable
Y Decoder F2 minterm (X'Y', X'Y, XY' or XY)
F3

F0 = X'Y'

F1 = X'Y

F2 = XY'
Truth Table:

X Y F0 F 1 F2 F3 F3 = XY
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
X Y
 Gate-Level Minimization and Combinational logic
Decoders

2:4 Decoder
2:4 decoder symbol: 2:4 decoder logic circuit:
2:4 decoder
truth table: o0
00 o0
j1 j0 o0 o1 o2 o3
01 o1 o1
0 0 1 0 0 0
10 o2 0 1 0 1 0 0
11 o3 1 0 0 0 1 0 o2
1 1 0 0 0 1
o3
j0 j1
2:4 decoder Boolean formula: j0 j1
o0 = j1 j0 o1 = j1 j0
o2 = j1 j0 o = j1 j0
 Gate-Level Minimization and Combinational logic
Decoders

Two to four line Decoder with Enable Input

Start with a 2-bit decoder
Add an enable signal (E) A decoder with enable input
can function as a demultiplexer— a circuit that receives
information from a single line and directs it to one of 2n
possible output lines. The
selection of a specific output is controlled by the bit
combination of n selection lines.
The decoder of Figure shown can function as a one-to-
four-line demultiplexer when E is taken as a data input
line and A and B are taken as the selection inputs

Note: use of NANDs

only one 0 active!
Decoder with enable input is referred to as Decoder-Demultiplexer. if E = 0(active Low)
Decoders include one or more enable to control the circuit operation.
Gate-Level Minimization and Combinational logic
Decoders

3-to-8 Binary Decoder

Truth Table: F0 = x'y'z'
x y z F0 F1 F2 F3 F4 F5 F6 F7
0 0 0 1 0 0 0 0 0 0 0 F1 = x'y'z
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0 F2 = x'yz'
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
F3 = x'yz
1 0 1 0 0 0 0 0 1 0 0
F4 = xy'z'
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
F5 = xy'z

F0
F6 = xyz'
F1
X
F2 F7 = xyz
Y
3-to-8
F3
Z
Decoder F4
F5
F6
x y z
F7
Gate-Level Minimization and Combinational logic
Decoders

Three to Eight Line Decoder

Gate-Level Minimization and Combinational logic
Decoders

Truth Table of Three to Eight Line Decoder

Gate-Level Minimization and Combinational logic
Decoders

3 x 8 decoder constructed with two 2 x 4 decoders.

Gate-Level Minimization and Combinational logic
Decoders

4 x 16 decoder constructed with two 3 x 8 decoders.

Enable can also be active high

In this example, only one decoder can be active at a time.
x, y, z effectively select output line for w
Gate-Level Minimization and Combinational logic
Decoders

Implementing Functions Using Decoders

Any n-variable logic function can be implemented using a single n-to-2n decoder to
generate the minterms
➢ OR gate forms the sum.
➢ The output lines of the decoder corresponding to the minterms of the
function are used as inputs to the or gate.
Any combinational circuit with n inputs and m outputs can be implemented with an
n-to-2n decoder with m OR gates.
Suitable when a circuit has many outputs, and each output function is expressed with
few minterms.
Gate-Level Minimization and Combinational logic
Decoders

Implementation of a full adder with a decoder.

x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

Full adder
S(x, y, z) = S (1,2,4,7)
C(x, y, z) = S (3,5,6,7)
Gate-Level Minimization and Combinational logic
Decoders

Implementing Functions Using Decoders

• A function with a long list of minterms requires an OR gate with a large

number of inputs.
• A function having a list of k minterms can be expressed in its complemented
form F with 2n - k minterms.
• If the number of minterms in the function is greater than 2n/2, then F can be
expressed with fewer minterms.
• In such a case, it is advantageous to use a NOR gate to sum the minterms of F.
The output of the NOR gate complements this sum and generates the normal
output F .
• If NAND gates are used for the decoder, then the external gates must be
NAND gates instead of OR gates. This is because a two-level NAND gate circuit
implements a sum-of-minterms function and is equivalent to a two-level AND–
OR circuit
THANK YOU

Team DDCO
Department of Computer Science
 DIGITAL DESIGN AND
COMPUTER ORGANIZATION
Gate-Level Minimization and Combinational logic
Department of Computer Science and Engineering
DIGITAL DESIGN AND
COMPUTER ORGANIZATION

Encoders

Department of Computer Science and Engineering

Gate-Level Minimization and Combinational logic
Encoders
Encoders n
Encoder is a digital circuit that performs inverse operation of a decoder. An encoder has 2 (or fewer) input lines and n
output lines. The output lines, as an aggregate, generate the binary code corresponding to the input value.
If the a decoder's output code has fewer bits than the input code, the device is usually
called an encoder.
e.g. 2n-to-n

The simplest encoder is a 2n-to-n binary encoder

One of 2n inputs = 1
Output is an n-bit binary number used in octal to binary conversion
Gate-Level Minimization and Combinational logic
Encoders

8-to-3 Binary Encoder Inputs Outputs

I0 I1 I2 I3 I4 I5 I6 I7 y2 y1 y0
1 0 0 0 0 0 0 0 0 0 0
At any one time, only 0 1 0 0 0 0 0 0 0 0 1
one input line has a value of 1. 0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
I0
I1 y 2 = I4 + I 5 + I6 + I7
I2
I3 y 1 = I2 + I 3 + I6 + I7
I4
I5
I6
I7 y 0 = I1 + I 3 + I5 + I7
 Gate-Level Minimization and Combinational logic
Encoders
z = D1 + D3 + D5 + D7
Truth Table of Octal to Binary Encoder
y = D2 + D3 + D6 + D7
x = D4 + D5 + D6 + D7

Need For Priority Encoder:

Ambiguity 1: The encoder has limitation that only one input can be active at any given time. If two inputs are active simultaneously, the output
produces an undefined combination. For example, if D3 and D6 are 1 simultaneously, the output of the encoder will be 111 because all three
outputs are equal to 1. The output 111 does not represent either binary 3 or binary 6.
Solution: To resolve this ambiguity, encoder circuits must establish an input priority to ensure that only one input is encoded. If we establish a
higher priority for inputs with higher subscript numbers, and if both D3 and D6 are 1 at the same time, the output will be 110 because D6 has
higher priority than D3.
Ambiguity 2: Another ambiguity in the octal-to-binary encoder is that an output with all 0’s is generated when all the inputs are 0; but this
output is the same as when D0 is equal to 1.
Solution: The discrepancy can be resolved by providing one more output to indicate whether at least one input is equal to 1.
Gate-Level Minimization and Combinational logic
Encoders

Truth Table of a Priority Encoder

In addition to the two outputs x and y, the circuit has a third output designated by V ; this is a
valid bit indicator that is set to 1 when one or more inputs are equal to 1

The operation of the priority encoder is such that if two or more inputs are equal to 1 at the
same time, the input having the highest priority will take precedence
Gate-Level Minimization and Combinational logic
Encoders

Maps for a Priority Encoder

Gate-Level Minimization and Combinational logic
Encoders

Four input Priority Encoder

Gate-Level Minimization and Combinational logic
Encoders
• 8-to-3 Priority Encoder

• What if more than one input line has a value of 1?

• Ignore “lower priority” inputs.
• Idle indicates that no input is a 1.
• Note that polarity of Idle is opposite from Table 4-8 in Mano

Inputs Outputs
I0 I1 I2 I3 I4 I5 I6 I7 y2 y1 y0 Idle
0 0 0 0 0 0 0 0 x x x 1
1 0 0 0 0 0 0 0 0 0 0 0
X 1 0 0 0 0 0 0 0 0 1 0
X X 1 0 0 0 0 0 0 1 0 0
X X X 1 0 0 0 0 0 1 1 0
X X X X 1 0 0 0 1 0 0 0
X X X X X 1 0 0 1 0 1 0
X X X X X X 1 0 1 1 0 0
X X X X X X X 1 1 1 1 0
Gate-Level Minimization and Combinational logic
Encoders
Priority Encoder (8 to 3 encoder)

Assign priorities to the inputs

When more than one input are asserted, the output generates the code of the
input with the highest priority
Priority Encoder : Priority encoder
H7=I7 (Highest Priority) Priority Circuit Binary encoder
H6=I6.I7’
H5=I5.I6’.I7’ I0 I0 H0 I0
H4=I4.I5’.I6’.I7’ I1 I1 H1 I1
H3=I3.I4’.I5’.I6’.I7’ I2 I2 H2 I2 Y0
Y0
H2=I2.I3’.I4’.I5’.I6’.I7’ I3 I3 H3 I3 Y1
H1=I1. I2’.I3’.I4’.I5’.I6’.I7’ Y1
I4 I4 H4 I4 Y2
H0=I0.I1’. I2’.I3’.I4’.I5’.I6’.I7’ I5 I5 H5 I5
Y2
IDLE= I0’.I1’. I2’.I3’.I4’.I5’.I6’.I7’
I6 I6 H6 I6
Encoder
I7 I7 H7 I7
Y0 = I1 + I3 + I5 + I7
Y1 = I2 + I3 + I6 + I7 IDLE IDLE
Y2 = I4 + I5 + I6 + I7
Gate-Level Minimization and Combinational logic
Encoders

Encoder Application (Monitoring Unit)

Encoder identifies the requester and encodes the value

Controller accepts digital inputs.

Alarm Contoller
Signal Response

Machine 1

Machine 2 Machine
Code
Encoder Controller

Machine n
THANK YOU

Team DDCO
Department of Computer Science
 DIGITAL DESIGN AND
COMPUTER ORGANIZATION
Gate-Level Minimization and Combinational logic
Department of Computer Science and Engineering
DIGITAL DESIGN AND
COMPUTER ORGANIZATION

Multiplexers

Department of Computer Science and Engineering

 Gate-Level Minimization and Combinational logic
Multiplexers

A multiplexer (also called a mux) multiplexes many inputs onto a single output
2:1 Mux
n
2 input lines
n selection lines.
2:1 mux truth table:
2:1 mux logic circuit: 2:1 mux symbol:
i0 i1 j y
0 0 0 0 i0
0 0 1 0 i0 0
o
0 1 0 0 i1 1
0 1 1 1 i1
1 0 0 1 j
1 0 1 0
j
1 1 0 1 Data inputs: i0, i1
1 1 1 1 Control input: j
2:1 mux Boolean formula:
o = j i0 + j i1

A multiplexer is a combinational circuit that selects binary information from one of many input
lines and directs it to a single output line. The
n
selection of a particular input line is controlled by a
set of selection lines. Normally, there are 2 input lines and n selection lines whose bit
combinations determine which input is selected
Gate-Level Minimization and Combinational logic
Multiplexers

Two to One Line Multiplexer

Select an input value with one or more select bits

Use for transmitting data
Allows for conditional transfer of data
Sometimes called a mux
Gate-Level Minimization and Combinational logic
Multiplexers

Quadruple Two to One Line Multiplexer

Gate-Level Minimization and Combinational logic
Multiplexers

4:1 Multiplexer

4:1 mux 4:1 mux logic circuit:

symbol: Data inputs: i0, i1, i2, i3 i0
Control inputs: j 0 , j1
i0 00
i1
i1 01
o o
i2 10 i2
i3 11
i3

j1 j0
j0 j1
4:1 mux Boolean formula:
o = j 1 j 0 i0 + j 1 j 0 i1 + j 1 j 0 i2 + j 1 j 0 i3
Gate-Level Minimization and Combinational logic
Multiplexers

Four to One Line Multiplexer

Gate-Level Minimization and Combinational logic
Multiplexers

4:1 Multiplexer

4:1 mux logic circuit using 2:1 muxes:

4:1 mux
symbol: Data inputs: i0, i1, i2, i3
Control inputs: j 0 , j1 i0
i0 00
i1
i1 01
o
i2 10 o
i3 11
i2
i3
j1 j0
4:1 mux Boolean formula: j0 j1
o = j 1 j 0 i0 + j 1 j 0 i1 + j 1 j 0 i2 + j 1 j 0 i3
Gate-Level Minimization and Combinational logic
Multiplexers

5:1 Mux

A combinational logic circuit having n data inputs, [log2 n| control inputs and one
output, that connects the data input indicated by the control inputs to the output
Gate-Level Minimization and Combinational logic
Multiplexers

Think About It

➢ What is the Boolean formula for a 3:1 mux?

Construct a 3:1 mux using 2:1 muxes
➢ AND, OR and NOT gates
Gate-Level Minimization and Combinational logic
Multiplexers

Implementing a Boolean Function with a Multiplexer

F (x, y, z) = (1, 2, 6, 7)

Connect input variables to select inputs of multiplexer (n-1 for n variables)

Set data inputs to multiplexer equal to values of function for corresponding assignment
of select variables
Using a variable at data inputs reduces size of the multiplexer
Gate-Level Minimization and Combinational logic
Multiplexers

Implementing a four input Function with a 8X1 Multiplexer

F (A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)

 Gate-Level Minimization and Combinational logic
Multiplexers

Graphic symbol for a three-state buffer.

A normal buffer typically has two states: 0 (LOW) and 1 (HIGH). These are the logic levels where the output actively drives the circuit.
A three-state buffer, however, adds a third state called the high-impedance (Z) state, where the output neither drives a HIGH nor
LOW signal. In this state, it acts like it's disconnected from the circuit.

When the control input is active, the buffer passes the input signal (either HIGH or LOW).
When the control input is inactive, the buffer enters the high-impedance (Z) state, essentially
disconnecting its output.

In the high-impedance state, the output is essentially "floating", meaning it has no influence on the bus or other components
connected to it.
Gate-Level Minimization and Combinational logic
Multiplexers
Multiplexers with three-state gates.
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Department of Computer Science

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