4.

1 Introduction
4.2 Why Silicon?
4.3 Crystal Structures and Defects
4.4 From Sand to Wafer
4.5 Epitaxial Silicon Deposition
4.6 Substrate Engineering
4.7 Summary

Objectives
4.1
 Give two reasons why silicon dominate 4.2

 List at least two wafer orientations 4.3

4.4
 List the basic steps from sand to wafer 4.5

 Describe the CZ and FZ methods

4.6
4.7
 Describe two SOI manufacturing methods
 Explain the purpose of epitaxial silicon
 Describe the epi-silicon deposition
process.

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1
 4.1 Introduction
 Crystal Structures 4.1
4.2
All materials are made from atoms. According to the 4.3
arrangement of atoms inside solid materials, there 4.4

are three different material structures: 4.5

4.6
 Amorphous 4.7

• No repeated structure at all

 Polycrystalline
• Some repeated structures
 Single crystal
• One repeated structure
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Amorphous Structure
4.1
4.2
4.3
4.4
4.5
4.6
4.7

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2
 Polycrystalline Structure
4.1
4.2
4.3
Grain 4.4

Boundary 4.5
4.6
4.7

Grain

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Single Crystal Structure

4.1
4.2
4.3
4.4
4.5
4.6
4.7

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3
  In nature, most solid materials are either amorphous or
polycrystalline in structure. Only a few solids have a 4.1
single-crystal structure, and they are usually gem 4.2
stones. 4.3
4.4
 The first transistor was made from polycrystalline Ge.
4.5
However, to make a miniature transistor, a single- 4.6
crystal semiconductor substrate is required. 4.7
• Electron scattering from the grain boundary in a material can
seriously affect p-n junction characteristics.
• Although they are not good for IC chip manufacturing, both
polycrystalline silicon and amorphous silicon can be used to
make solar panels, which directly convert photon energy from
sunlight into electrical power.

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4.2 Why Silicon?

4.1

 Abundant, cheap
4.2
4.3

 Silicon dioxide is very stable, strong 4.4

4.5
dielectric, and it is easy to grow in thermal 4.6
process. 4.7

 Large band gap, wide operation

temperature range.
 For metal-insulator-semiconductor (MIS)
transistors, the SiO2–Si interface has
superior electrical characteristics for MOS

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4
 Name Silicon
Symbol Si 4.1
4.2
Atomic number 14
4.3
Atomic weight 28.0855
4.4
Discoverer Jöns Jacob Berzelius 4.5
Discovered at Sweden 4.6

Discovery date 1824 4.7

Origin of name From the Latin word "silicis" meaning "flint"

Bond length in 2.352 Å
single crystal Si
Density of solid 2.33 g/cm3
Molar volume 12.06 cm3
Velocity of sound 2200 m/sec
Source: http://www.shef.ac.uk/chemistry/web-elements/nofr-key/Si.html

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Hardness 6.5
4.1
Electrical resistivity 100,000 mWcm
4.2
4.3
Reflectivity 28% 4.4
Melting point 1414 C 4.5
4.6
Boiling point 2900 C
4.7
Thermal conductivity 150 W m-1 K-1
Coefficient of linear 2.610-6 K-1
thermal expansion
Etchants (wet) HNO4 and HF, KOH, etc.
Etchants (dry) HBr, Cl2, NF3, etc.
CVD Precursor SiH4, SiH2Cl2, SiHCl3, and SiCl4

Source: http://www.shef.ac.uk/chemistry/web-elements/nofr-key/Si.html

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5
 4.3 Crystal Structures and Defects
4.1
Unit Cell of Single Crystal Silicon 4.2
4.3
4.4
Si 4.5
4.6
Si 4.7

Si

Si

Si

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11

Crystal Orientations: <100>

4.1
4.2
z
4.3
4.4
4.5
4.6
4.7
<100> plane

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12

6
 Crystal Orientations: <111>
4.1
4.2
z
4.3
4.4
4.5
4.6

<111> plane 4.7

<100> plane

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13

Crystal Orientations: <110>

4.1
z 4.2
4.3
4.4
4.5
4.6
4.7
<110> plane

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14

7
 <100> Orientation Plane
4.1
Basic lattice cell Atom 4.2
4.3
4.4
4.5
4.6
4.7

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15

<111> Orientation Plane

4.1
Basic lattice cell Silicon atom 4.2
4.3
4.4
4.5
4.6
4.7

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16

8
 <100> Wafer Etch Pits
4.1
4.2
4.3
4.4
4.5
4.6
4.7

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17

4.1
4.2
4.3
4.4
4.5
4.6
4.7

Most frequent (simulated) morphological features during wet chemical etching. (a) Pyramidal
hillocks on (100). (b) Round shallow pits on (100). (c) Nosed zigzags on vicinal (110). (d)
Triangular pits on (111). (e) Polygonal steps on terraced vicinal (111). (f) Straight steps on
terraced vicinal (111) (cf figures 2(g), 8 (top), 12(f), 14(i) and 13(f) and (a), respectively).
http://iopscience.iop.org/article/10.1088/1367-2630/5/1/400/fulltext/

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18

9
 4.1
<111> Wafer Etch Pits 4.2
4.3
4.4
4.5
4.6
4.7

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19

Etch pits on Si(111) obtained by etching in the

three different etching solutions. 4.1
4.2
4.3
4.4
4.5
4.6
4.7

https://www.google.com.tw/search?q=Si+wafer+etching+pits&rlz=1C1GIWA_enTW683TW683&source=lnms&tbm=isch&sa=
X&ved=0ahUKEwjU3q2vz-DPAhXHqY8KHbHoCiwQ_AUICCgB&biw=1024&bih=555#imgrc=Yfljo821M6v9RM%3A

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10
 4.1
4.2
4.3
4.4
4.5
4.6
4.7

https://www.google.com.tw/
search?q=Si+wafer+etching
+pits&rlz=1C1GIWA_enTW
683TW683&source=lnms&t
bm=isch&sa=X&ved=0ahU
KEwjU3q2vz-
DPAhXHqY8KHbHoCiwQ_
AUICCgB&biw=1024&bih
=555#imgrc=CUex-
gbiwwF8XM%3A

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21

Illustration of the Defects

4.1
Impurity on substitutional site Silicon Atom 4.2
4.3
4.4
4.5
Impurity in 4.6

Interstitial Site 4.7

Silicon
Interstitial

Vacancy or Schottky Defect Frenkel Defect

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11
 4.1
Dislocation Defects 4.2
4.3
4.4
4.5
4.6
4.7

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23

4.4 From Sand to Wafer

4.1
 Quartz sand: silicon dioxide 4.2

 Sand to metallic grade silicon (MGS) 4.3

4.4
 React MGS powder with HCl to form TCS 4.5
4.6
 Purify TCS by vaporization and 4.7

condensation
 React TCS to H2 to form polysilicon (EGS)
 Melt EGS and pull single crystal ingot

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12
 From Sand to Wafer (cont.) 4.1

 Cut end, polish side, and make notch or flat 4.2

4.3
 Saw ingot into wafers 4.4

 Edge rounding, lap, wet etch, and CMP

4.5
4.6

 Laser scribe 4.7

 Epitaxy deposition

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From Sand to Silicon

4.1
4.2
Heat (2000 ° C)
4.3
SiO2 + 2C  Si + 2CO 4.4
4.5
Sand Carbon MGS Carbon oxide 4.6
4.7
OR Heat (2000 ° C)

SiO2 + C  Si + CO2
Sand Carbon MGS Carbon Dioxide

This process generates polycrystalline silicon with about 98~99%

purity called crude silicon or metallurgical-grade silicon (MGS)

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13
 Silicon Purification I
4.1
4.2
4.3
4.4
4.5
4.6
4.7

Heat (300 ° C)

Si + 3HCl  SiHCl3 + H2
MGS Hydrochloride TCS Hydrogen

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Polysilicon Deposition, EGS 4.1

4.2
4.3
4.4
Heat (1100 ° C) 4.5
4.6
SiHCl 3 + H 2
 Si + 3HCl 4.7

TCS Hydrogen EGS Hydrochloride

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14
 Silicon Purification II 4.1
4.2
Process 4.3

Chamber 4.4
EGS
H2 4.5
4.6
4.7
H2 and TCS
Liquid
TCS TCS+H2EGS+HCl

Carrier gas
bubbles

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29

Electronic Grade Silicon 4.1

4.2
4.3
4.4
4.5
4.6
4.7

Source: http://www.fullman.com/semiconductors/_polysilicon.html

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15
  Crystal Pulling: CZ method
4.1
4.2
Single Crystal Silicon Seed 4.3
4.4
Quartz Crucible Single Crystal 4.5
silicon Ingot 4.6
4.7

Molten Silicon
Heating Coils
1415 °C

Graphite Crucible

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CZ Crystal Pullers 4.1

4.2
4.3
4.4
4.5
4.6
4.7

Mitsubish Materials Silicon

Source: http://www.fullman.com/semiconductors/_crystalgrowing.html

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16
 4.1
CZ Crystal Pulling 4.2
4.3
4.4
4.5
4.6
4.7

Source: http://www.fullman.com/semiconductors/_crystalgrowing.html

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4.1
4.2
Video of CZ method 4.3
4.4
4.5
4.6
----Part I 4.7

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17
 4.1
Floating Zone Method 4.2
4.3
4.4
4.5
Poly Si
Molten Silicon 4.6
Rod
Heating Coils 4.7
Movement Heating Coils

Single Crystal
Silicon

Seed Crystal

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35

4.1
4.2
Video of FZ method 4.3
4.4
4.5
4.6
----Part I 4.7

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18
 Comparison of the Two Methods
4.1
 CZ method is more popular 4.2

• Cheaper 4.3
4.4
• Larger wafer size (300 mm in production) 4.5

• Reusable materials 4.6

4.7
 Floating Zone
• Pure silicon crystal (no crucible)
• More expensive, smaller wafer size (150
mm)
• Mainly for power devices.

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37

Ingot Polishing, Flat, or Notch

4.1
4.2
4.3
4.4
4.5
4.6
4.7

Flat, 150 mm and smaller Notch, 200 mm and larger

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19
 4.1
Wafer Sawing 4.2
4.3
4.4
Orientation Coolant
4.5
Notch 4.6
4.7
Crystal Ingot
Saw Blade Ingot
Movement

Diamond Coating

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39

Parameters of Silicon Wafer

4.1
4.2
Wafer Thickness Area Weight
4.3
Size (mm) (mm) (cm2) (grams)
4.4
50.8 (2″) 279 20.26 1.32 4.5
76.2 (3″) 381 45.61 4.05 4.6

100 525 78.65 9.67 4.7

125 625 112.72 17.87

150 675 176.72 27.82
200 725 314.16 52.98
300 775 706.21 127.62
450 925±25* 1590.43 342.77

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20
 4.1
Wafer Edge Rounding 4.2

Wafer movement 4.3

Wafer 4.4
4.5
4.6
4.7

Wafer Before Edge Rounding

Wafer After Edge Rounding

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41

Wafer Lapping 4.1

4.2

 Rough polished 4.3

4.4
 conventional, abrasive, slurry-lapping 4.5

 To remove majority of surface damage

4.6
4.7

 To create a flat surface

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21
 Wet Etch 4.1

 Remove defects from wafer surface 4.2

4.3
 4:1:3 mixture of HNO3 (79 wt% in H2O), HF 4.4

(49 wt% in H2O), and pure CH3COOH. 4.5

4.6
 Chemical reaction: 4.7

3 Si + 4 HNO3 + 6 HF  3 H2SiF6 + 4 NO + 8 H2O

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43

4.1
Chemical Mechanical Polishing 4.2
4.3
Pressure
4.4
Slurry 4.5
4.6
Wafer Holder
Wafer 4.7

Polishing Pad

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44

22
 200 mm Wafer Thickness and Surface
Roughness Changes 4.1
4.2
76 mm 4.3
After Wafer
914 mm 4.4
Sawing 4.5
76 mm 4.6
After Edge 914 mm 4.7
Rounding
12.5 mm
After Lapping 814 mm
<2.5 mm
After Etch 750 mm
Virtually Defect Free
After CMP 725 mm
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45

4.1
4.2
Video of CZ method 4.3
4.4
4.5
4.6
----Part II 4.7

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23
 4.5 Epitaxial Silicon Deposition 4.1
4.2
4.3
Epitaxy 4.4
4.5
4.6
4.7

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47

Epitaxy Grow 4.1

4.2

•Definition 4.3
4.4
4.5
•Purposes 4.6
4.7
•Epitaxy Reactors
•Epitaxy Process

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24
 Epitaxy: Definition 4.1
4.2

 Greek origin
4.3
4.4

 epi:
4.5
upon 4.6
4.7
 taxy: orderly, arranged
 Epitaxial
layer is a single crystal layer on a
single crystal substrate.

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49

Epitaxy: Purpose 4.1

4.2
 Barrier layer for bipolar transistor 4.3

• Reduce collector resistance while keep 4.4

4.5
high breakdown voltage. 4.6

• Only available with epitaxy layer. 4.7

 Improve device performance for CMOS

and DRAM because much lower oxygen,
carbon concentration than the wafer
crystal.

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50

25
 4.1
Epitaxy Application, Bipolar Transistor 4.2
4.3
Emitter Base Collector 4.4
Al•Cu•Si
4.5
SiO2 4.6
+ +
n p n 4.7
p+ p+
n-Epi
Electron flow
n+ Buried Layer
P-substrate

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Epitaxy Application: CMOS

4.1
4.2
4.3
Metal 1, Al•Cu 4.4
4.5
W 4.6
BPSG 4.7

STI n+ n+ USG p+ p+
P-Well N-Well
P-type Epitaxy Silicon
P-Wafer

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26
 Selective Epitaxy Growth (SEG)
4.1
4.2
4.3
SiO2
4.4
Silicon
Silicon substrate 4.5
recess
4.6
4.7

SEG SiGe

SiO2
SEG
SiGe Silicon substrate

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53

4.1
Application of SEG 4.2
4.3
4.4
4.5
4.6
4.7

SEG
SiGe

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27
 4.1
Silicon Source Gases 4.2
4.3
Silane SiH4 4.4
4.5

Dichlorosilane DCS SiH2Cl2 4.6

4.7

Trichlorosilane TCS SiHCl3

Tetrachlorosilane SiCl4

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4.1
Dopant Source Gases 4.2
4.3
Diborane B 2 H6 4.4
4.5

Phosphine PH3 4.6

4.7

Arsine AsH3

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28
 DCS Epitaxy Grow, Arsenic Doping
4.1
Heat (1000 ° C) 4.2

SiH4  Si + 2H2
4.3
4.4

Silane Epi-Si Hydrogen 4.5

4.6
Heat (1100 ° C) 4.7

SiH2Cl2  Si + 2HCl
DCS Epi Hydrochloride

Heat (1100 ° C)
AsH3 As + 3/2 H2
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4.1
Schematic of DCS Epi Grow and 4.2

Arsenic Doping Process 4.3

4.4
4.5
SiH2Cl2
AsH3 4.6
4.7

HCl H2

Si AsH3

As H

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29
 Epitaxial Silicon Growth Rate Trends
Temperature (°C) 4.1
1300 1200 1100 1000 900 800 700 4.2
1.0
4.3
4.4
Growth Rate, micron/min 0.5
4.5
SiH4
0.2 Mass transport 4.6
limited
4.7
0.1 SiHCl3

0.05
Surface reaction limited
0.02 SiH2Cl2

0.01
0.7 0.8 0.9 1.0 1.1
1000/T(K)

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59

p.112

問題：
假如溫度升高到1300℃，矽烷製程的生⾧速率 4.1
4.2
將如何變化？ 4.3

解答： 4.4
4.5
矽烷是高反應性氣體。當溫度超過1200℃時， 4.6
將開始氣相反應(氣相成核，Gas Phase 4.7

Nucleation)
，這樣將會降低磊晶矽的生⾧速率並產生大量粒
子。這個溫度區間必須避免。二氯矽烷和三氯矽
烷的反應性比矽烷低，需要較高的反應溫度並可
以在較高溫度下進行沉積。

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30
  Question:
4.1
For the silane process, if the temperature continues to
4.2
increase to 1300 ◦C, how will the growth rate change? 4.3
 Answer: 4.4
4.5
Silane is a very reactive gas. When the temperature is 4.6
higher than 1200 ◦C, it starts to react in the gas phase 4.7
(gas phase nucleation). This reduces the epitaxy growth
rate and generates huge amounts of particles (a regime
to be avoided at all costs). Dichlorosilane (SiH2Cl2) and
trichlorosilane (SiHCl3) are less reactive than silane; they
have higher reaction temperatures and can deposit at
higher temperatures.

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4.5.3 Epitaxy hardware

4.1
Barrel Reactor 4.2
4.3
Radiation
4.4
Heating 4.5
Coils Wafers 4.6
4.7

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62

31
 4.1
Vertical Reactor 4.2
4.3
4.4
4.5
4.6
Wafers
4.7

Heating Reactants
Coils

Reactants and
byproducts
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63

4.1
Horizontal Reactor 4.2
4.3
Heating Coils
4.4
4.5
4.6
Wafers 4.7

Reactants
Reactants and
byproducts

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32
 4.1
Epitaxy Process, Batch System 4.2

 Hydrogen purge, temperature ramp up 4.3

4.4

 HCl clean 4.5

4.6
 Epitaxial layer grow 4.7

 Hydrogen purge, temperature cool down

 Nitrogen purge
 Open Chamber, wafer unloading, reloading

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65

4.1
Single Wafer Reactor 4.2

 Sealed chamber, hydrogen ambient 4.3

4.4

 Capable for multiple chambers on a 4.5

4.6
mainframe 4.7

 Large wafer size (to 300 mm)

 Better uniformity control

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33
 4.1
Single Wafer Reactor 4.2

Heat 4.3
Heating Lamps
Radiation 4.4
4.5
Wafer
4.6

Reactants 4.7

Reactants &
byproducts

Susceptor Quartz Quartz

Lift Window
Fingers

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4.5.4 Epitaxy process

4.1
Epitaxy Process, Single Wafer System 4.2

 Hydrogen purge, clean, temperature ramp 4.3

4.4
up 4.5
4.6
 Epitaxial layer grow 4.7

 Hydrogen purge, heating power off

 Wafer unloading, reloading
 In-situ HCl clean,

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34
 Why Hydrogen Purge 4.1

 Most systems use nitrogen as purge gas 4.2

4.3
 Nitrogen is a very stable abundant 4.4

 At > 1000 C, N2 can react with silicon

4.5
4.6

 SiN on wafer surface affects epi deposition 4.7

 H2 is used for epitaxy chamber purge

 Clean wafer surface by hydrides formation

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Properties of Hydrogen
4.1
Name Hydrogen
4.2
Symbol H 4.3
Atomic number 1 4.4

Atomic weight 1.00794 4.5

4.6
Discoverer Henry Cavendish
4.7
Discovered at England
Discovery date 1766
Origin of name From the Greek words "hydro" and "genes"
meaning "water" and "generator"
Molar volume 11.42 cm3
Velocity of sound 1270 m/sec
Refractive index 1.000132

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70

35
 4.1
4.2
Melting point -258.99 C 4.3
4.4
Boiling point -252.72 C
4.5
Thermal 0.1805 W m-1 K-1 4.6
conductivity 4.7

Main Epitaxial deposition, wet oxidation, pre metal

applications in deposition reactive clean, and tungsten CVD
IC processing
Main Source H2

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4.1
Defects in Epitaxy Layer 4.2
4.3
Stacking Fault from Stacking Fault form 4.4
Surface Nucleation Substrate Stacking Fault 4.5
4.6
Dislocation Impurity Particle 4.7

Hillock
Epi Layer

Substrate
After S.M. Zse’s VLSI Technology

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36
 4.5.6 Selective epitaxy
4.1
 Another promising development. 4.2
4.3
 Using silicon dioxide or silicon nitride as the
4.4
epitaxy mask; thus, the epitaxial layer only grows 4.5
on the area where silicon is exposed 4.6
4.7
 A characteristic that can help to increase device
packing density and reduce parasitic capacitance.

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73

4.5.6 Selective epitaxy

4.1
4.2
4.3
4.4
4.5
4.6
4.7

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74

37
 4.5.6 Selective epitaxy
 Widely used to deposit SiGe in the pMOS S/D area to help 4.1
create uniaxial compressive strain in the pMOS channel, 4.2
increasing hole mobility and improving pMOS drive current 4.3
and speed. 4.4

 It can also be used to deposit SiC in the nMOS S/D region to 4.5
4.6
help create tensile strain in the nMOS channel, increasing
4.7
electron mobility and improving nMOS drive current and
speed.
 Used in hybrid orientation technology, which allows two
different silicon orientations to be on the same wafer surface,
so that nMOS and pMOS can be built on different crystal
orientations, maximizing carrier mobility and device
performance.
 Will describe in detail in the following section on substrate
 engineering.
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4.6 Substrate Engineering

4.1
Silicon-On-Insulator (SOI) 4.2

 Better device isolation 4.3

4.4

 Higher speed 4.5

4.6
 Higher packing density 4.7

 Better performance
 Bonded
 Oxygen implantation

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38
 4.1
CMOS on SOI Substrate 4.2
4.3
n+ source/drain Gate oxide p+ source/drain
4.4
4.5
4.6
Polysilicon
4.7

p-Si STI n-Si USG

Buried oxide
Balk Si

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Oxygen Implantation SOI

4.1
 Implanted wafers 4.2

• Heavy oxygen ion implantation

4.3
4.4

• High temperature annealing 4.5

4.6
4.7

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39
 Oxygen Ion Implantation 4.1
4.2
4.3
4.4
4.5
4.6
4.7

Silicon with lattice damage

Oxygen rich silicon
Balk Si

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High Temperature Annealing

4.1
4.2
4.3
4.4
4.5
4.6
4.7

Single crystal silicon

Silicon dioxide
Balk Si

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40
 Bonded SOI 4.1

 Two wafers 4.2

4.3
 One grow oxide 4.4

 One implanted with hydrogen

4.5
4.6

 Bond two wafers at high temperature 4.7

 Hydrogen rich silicon has high wet etch

rate
 Wet etch separates two wafers
 CMP to smooth wafer surface

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4.1
Wafer A 4.2
4.3
4.4
4.5
4.6
4.7

Wafer A

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41
 4.1
 Hydrogen Ion Implantation 4.2
4.3
4.4
4.5
4.6
4.7

Hydrogen ions, H+

Wafer A

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4.1
 Hydrogen Ion Implantation 4.2
4.3
4.4
4.5
4.6
4.7

Hydrogen rich layer

Wafer A

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42
 4.1
Wafer B 4.2
4.3
4.4
4.5
4.6
4.7

Wafer B P-wafer

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4.1
Surface Clean 4.2
4.3
4.4
4.5
4.6
4.7

Wafer B P-wafer

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43
 4.1
Oxidation 4.2
4.3
4.4
4.5
4.6
4.7

SiO2
Wafer B P-wafer

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4.1
Wafer Bonding 1 4.2
4.3
4.4
4.5
4.6
4.7
Hydrogen rich layer

Wafer A

SiO2
Wafer B P-wafer

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44
 4.1
Wafer Bonding 2 4.2
4.3
4.4
4.5
4.6
4.7

Hydrogen rich layer

Wafer A

SiO2
Wafer B P-wafer

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4.1
Anneal 4.2
4.3
4.4
4.5
4.6
4.7

Hydrogen induced silicon voids

Wafer A

SiO2
Wafer B P-wafer

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45
 4.1
Wet Etch 4.2
4.3
4.4
4.5
4.6
4.7

Wafer A

SiO2
Wafer B P-wafer

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4.1
Wafer Separation 1 4.2
4.3
4.4
4.5
4.6
4.7

Wafer A

SiO2
Wafer B P-wafer

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46
 4.1
Wafer Separation 2 4.2
4.3
4.4
4.5
4.6
4.7

SiO2
Wafer B P-wafer

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4.1
CMP 4.2
4.3
4.4
4.5
4.6
4.7

Buried SiO2
P-wafer

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47
 Hybrid Orientation Technique
4.1
 Electron has higher mobility in <100> 4.2
orientation silicon 4.3

 Hole has higher mobility in <110> 4.4

orientation silicon 4.5

4.6
 Make NMOS and PMOS in different 4.7
orientation of single crystal silicon and
optimize the device performance.
 SOI wafer with selective epitaxial growth
 Not in mainstream because it is not cost-
effective.

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4.1
Hybrid Orientation SOI Wafer 4.2
4.3
<110> Si 4.4

SiO2 4.5
4.6
<100> Si 4.7

Nitride Nitride
<110> Si
SiO2
<100> Si

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48
 4.1
Hybrid Orientation SOI Wafer 4.2
4.3
<110> Si 4.4

SiO2 4.5
4.6
<100> Si 4.7

STI Poly Si <110> Si

p+ p+ n+ n+ p+ p+
SiO2 <100> Si

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Strained Silicon
4.1
 Strained silicon can help to improve carrier 4.2

mobility 4.3
4.4
 Increase device speed. 4.5
4.6
 Strained silicon wafer manufacturing 4.7

process was developed

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49
 4.1
Strained Silicon Wafer Manufacturing 4.2
4.3
4.4

Strained Silicon 4.5

4.6
Relaxed SiGe 4.7

Gradient SiGe

Si Substrate

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4.6.4 絕緣體上應變矽
(Strained Silicon on Insulator, SSOI) 4.1
4.2
Using the strained silicon wafer described in Fig. 4.3
4.29(a) as wafer A of the bonded SOI process 4.4

(shown in Fig. 4.27), an SSOI wafer can be made. 4.5

4.6
These types of wafers have the high carrier mobility 4.7
of strained silicon and the high device packing
density of SOI (see Fig. 4.30).

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50
 4.6.5 IC技術中的應變矽
(Strained silicon in integrated circuit 4.1
4.2
manufacturing ) 4.3
4.4
4.5
4.6
4.7

Cross section of a CMOS device with selective epitaxial

SiGe for pMOS and tensile stress
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liner for nMOS

101

p.121

選擇性磊晶CMOS元件
4.1
4.2
4.3
4.4
4.5
4.6
4.7

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51
 Figure 4.32 illustrates the cross section of a state-of-the-art 22-
nm high-κ metal gate CMOS with an SEG SiGe pMOS S/G that 4.1
strains the p-channel compressively, and an SEG SiC nMOS 4.2
S/G that strains the n-channel with tensile stress. 4.3
4.4
4.5
4.6
4.7

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Strained Silicon Wafer vs. Local Strain 4.1

 Only the channel needs to be strained. 4.2

 NMOS and PMOS need different type of 4.3

strain to improve carrier mobility 4.4

4.5
• NMOS channel needs tensile strain to 4.6

improve electron mobility 4.7

• PMOS channel needs compressive strain

to improve hole mobility
 Local strain can be achieved with stress line
or SEG.
 Local strain is more cost-effective.

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 Future Trends 4.1

 Larger wafer size

4.2
4.3

 Single wafer epitaxial growth 4.4

4.5
 Low temperature epitaxy 4.6

 Ultra high vacuum (UHV, to 10-9 Torr)

4.7

 Selective epitaxial growth

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4.7 Summary
4.1
 Siliconis abundant, cheap and has strong, 4.2
stable and easy grown oxide. 4.3
4.4
 <100> and <111> 4.5

 CZ and floating zone, CZ is more popular

4.6
4.7

 Sawing, edging, lapping, etching and CMP

 SOI: Bonded and Oxygen implantation

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 Summary 4.1

 Epitaxy: single crystal on single crystal 4.2

4.3
 Needed for bipolar and high performance 4.4

CMOS, DRAM. 4.5

4.6
 Silane, DCS, TCS as silicon precursors 4.7

 B2H6 as P-type dopant

 PH3 and AsH3 as N-type dopants
 Batch and single wafer systems

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