JOURNAL OF LATEX CLASS FILES, VOL. 14, NO.

8, AUGUST 2015 1

FPGA-Based Implementation of the DES Algorithm

on Spartan-7 Series

Abstract—Cryptography has played a crucial role in secure A symmetric cipher is a cipher in which the kyes employed
communication for centuries, evolving from classical ciphers for the message encryption and decryption are identical. The
like the Caesar Cipher to modern encryption techniques. The keys employed in each round are derived from the original
Data Encryption Standard (DES), developed by IBM and stan-
dardized by NIST in 1977, remains a significant cryptographic key which is of 64-bit in length. With an increase in the
algorithm due to its structured Feistel network and balanced key length, the security can be enhanced but the speed of
security-performance tradeoff. This paper presents an FPGA- encryption and decryption will be decreased. Both encryption
based implementation of DES on the Spartan-7 xc7s50csga324- and decryption will employ same number of rounds. DES
1 device, enhancing encryption speed and hardware efficiency. algorithm employs Feistel Cipher Structure for encryption
The design, coded in Verilog and synthesized using the Vivado
Design Suite, incorporates key components such as S-Boxes and and decryption algorithm. Feistel Cipher Structure contains
P-Boxes to introduce confusion and diffusion, ensuring resistance 16 rounds and 16 round keys for each structure.
to cryptanalytic attacks. The proposed fully subpipelined DES This research shows the application of DES algorithm with
architecture achieves optimized resource utilization, consuming the help of a Field Programmable Gate Array (FPGA) and
only 3.58% of LUTs and 2.44% of slice registers while efficiently expounds the versatility of FPGA in hardware-specific applica-
processing 64-bit cryptographic operations. Additionally, synthe-
sis results demonstrate fast execution with a total synthesis time tion prototyping. Spartan-7 xc7s50csga324-1 device is utilized
of 26 seconds and peak memory usage of 586.87 MB, validating for experimentation. Field Programmable Gate Array are chips
the efficiency of FPGA-based DES implementations for real-time that the user can reprogram or configure many times to install
applications. the custom design post-manufacture, unlike ASICs that can be
Index Terms—Cryptography, DES,Symmetric Encryption, S- configured only once prior to manufacture. Once produced, an
Box and P-Box ASIC’s functionality cannot be altered or reconfigured. This
makes FPGAs more efficient and cost-effective compared to
ASICs primarily when multiple iterations of the design are
I. I NTRODUCTION
needed or for tailoring a particular functionality. The whole

T He idea of encrypting messages was there from a very

long period of time in the past of communication, which
was about conveying crucial messages that were capable of
project was coded in Verilog.
The project was created using Vivado Design Suite, simu-
lated designs, generated bitstreams, and programmed devices,
inflicting a great lose to an individual, or an organization, implementation, and debugging. Vivado Design Suite is Xil-
or even the nation. Among the earliest known such methods inx’s design environment for synthesizing, implementing, and
is Caesar Cipher, which was employed by Julius Caesar. In verifying designs on Xilinx FPGAs. It also supports hardware
this technique, every letter in the alphabet was moved by a descriptive language (HDL) like VHDL (Very High-Speed
set number of places. These sets of numbers by which the Integrated Circuit Hardware Description Language), Verilog,
alphabets were moved were only known to the receiver and System Verilog, and even HLS (High-Level Synthesis). The
the sender. design suite provides drag-and-drop design choices using pre-
With the advent of modern cryptography, the application designed IP cores which makes the embedded systems and
of computers has resulted in more complex algorithms for SoC development easier. The functional and timing simulation
encryption and decryption. Data Encryption Standard (DES) is is performed with Vivado Simulator. It accommodates third-
also known as Data Encryption Algorithm (DEA) at times and party hardware simulators like ModelSim, Questa, VCS (Ver-
is a cryptographic algorithm used to protect digital data. IBM ilog Compiler Simulator) to simulate digital circuits designed
invented it during the early 1970s and was formally embraced using HDL. Real-time debugging of FPGAs is performed with
by the National Institute of Standards and Technology (NIST) the help of Vivadi Logic Analyzer. Bitstream files (.bit) are
in 1977. DES, being a legacy encryption algorithm, still created for configuring FPGA. It carries binary data which
manages to have some place to fill in the context of data programs the FPGA’s programmable logic (PL) to execute the
security. The integration of DES and FPGA not only enhances target digital circuit.
the encryption speed, but also assists in the ease of integration
into digital communication systems (? ).
II. L ITERATURE R EVIEW
It took a pioneer step in the advancement of cryptographic
mechanisms. DES is a block cipher that symmetrically en- Siddhardha et al. (2023) designed a Novel Triple DES
crypts every block with a 64-bit message. Such a 64-bit mes- model implemented on a Xilinx Virtex-7 FPGA for high-
sage gets encrypted in several rounds of encryptions utilizing speed network security. Their model demonstrated improved
confusion and diffusion operations employing each round of encryption speed of 33.6 ns and lower power consumption of
the round keys to finally give output as 64-bit cipher text. 0.254 W compared to traditional DES, which required 44.3 ns
JOURNAL OF LATEX CLASS FILES, VOL. 14, NO. 8, AUGUST 2015 2

and 0.467 W. The pipeline complexity resulted in increased attacks, unlike DES and 3DES, which remain vulnerable to
computational efficiency(1). differential and linear cryptanalysis(12).
Mohammed et al. (2022) designed a Simplified DES (S- B. Murali Krishna et al. (2020) present an innovative ap-
DES) model implemented on an Altera Cyclone IV FPGA us- proach to image encryption in ”FPGA Implementation of Im-
ing VHDL. Their model optimized resource utilization, requir- age Cryptology using Reversible Logic Gates.” They propose a
ing only 32 CLB slices while maintaining high throughput and Runtime Linear Feedback Shift Register Logic (RLFSRL) for
low latency compared to traditional DES implementation(2). key generation, combined with reversible logic gates (CNOT,
Yazdeen et al. (2021) conducted a comprehensive review HING, PERES) for encryption and decryption. The study high-
on FPGA implementations for DES and AES encryption, lights FPGA-based benefits like reduced power consumption
highlighting the advantages of FPGA-based encryption over and enhanced security, demonstrating effectiveness through
software implementations. Their study analyzed concurrent hardware synthesis and simulation on Artix-7 FPGA.(13).
and parallel computation techniques to improve encryption
efficiency and demonstrated that FPGA-based encryption sig- M. N. A. Haneen Alabdulrazzaq, “Performance Evaluation
nificantly enhances performance and security(3). of Cryptographic Algorithms: DES, 3DES, Blowfish, Twofish,
Maurya et al. (2021) implemented a DES-secured FPGA and Threefish,” International Journal of Communication Net-
design using a Xilinx Virtex EXCV400e device, optimizing works and Information Security (IJCNIS), vol. 14, no. 1, April
S-box computations. Their model achieved a throughput of 2022. This paper evaluates DES, 3DES, Blowfish, Twofish,
23.10 Gbps, reducing CLB slices to 3,778, and demonstrated and Threefish in terms of computational efficiency, security,
improved encryption speed compared to previous FPGA-based and resource use, showing Blowfish and Twofish outperform
DES implementations(4). DES and 3DES.(14).
Yihan et al. (2021) proposed an improved DES algorithm R. F. Hassan, “New Approach for Modifying DES Algo-
by extending the key length to 128 bits and modifying iterative rithm Using 4-States Multi Keys,” Eng. Tech. J., vol. 28, no.
encryption. Their model enhanced security while outperform- 20, 2010. Hassan proposes a 4-state multi-key modification to
ing 3DES in efficiency, as it required fewer computational DES, enhancing security and resilience to cryptanalysis while
cycles for encryption and decryption operations(5). maintaining computational efficiency.(15).
Roy et al. (2020) designed a pipelined TDES model using
S. M. Kareem, “New Modification on Feistel DES Algo-
Linear Feedback Shift Register (LFSR) for key randomiza-
rithm Based on Multi-Level Keys,” International Journal of
tion, implemented on a Xilinx Virtex-7 FPGA. Their model
Electrical and Computer Engineering (IJECE), vol. 10, no.
improved throughput but required 6220 LUT slices due to
3, pp. 3125-3135, 2020. This study introduces a multi-level
pipeline complexity(6)
key system for Feistel DES, enhancing security and resistance
Zeebaree et al. (2019) proposed two DES-breaking models:
to brute-force and differential cryptanalysis while maintaining
A sequential design with a single processor element. A parallel
practical execution time.(16).
model with 512 processors, which was significantly faster at
breaking the code but required 3816 CLB slices on FPGA(7). A. H. and B. Kumar, “A Review Paper on DES, AES, RSA
Krishna et al. (2017) implemented DES on XC3ES500E Encryption Standards,” in 2020 9th International Conference
FPGA with only 8 rounds instead of 16, reducing resource on System Modeling and Advancement in Research Trends
consumption to 9.7% of available slices. However, despite (SMART), Moradabad, India, 2020. This review analyzes
reducing hardware usage, the design still consumed 374 slices, DES, AES, and RSA encryption standards, highlighting AES
indicating significant resource allocation(8). as the most secure and efficient option.(17).
Chabukswar et al. (2017) proposed an improved DES model M. D. A.-H. Qusay Zuhair Abdulla, “Robust Password
using four different key generation methods (Direct, LFSR, Encryption Technique with an Extra Security Layer,” Iraqi
Chaotic, and 2’s Complement). The implementation leveraged Journal of Science, vol. 64, no. 3, pp. 1477-1486, 2023.
multiplexers instead of f-functions in the S-Boxes, increasing Abdulla proposes a multi-layered encryption technique that
complexity and synchronization issues for 64-bit keys(9). enhances password security and resists brute-force and dictio-
Pandey et al. (2016) successfully implemented DES on a nary attacks.(18).
Xilinx Virtex-5 FPGA with optimized CLB slice usage. Their
approach effectively managed the trade-off between security S. D. M. and A. M. S. Rahma, “Modifying DES Algorithm
and hardware utilization(10). by Using Diagonal Matrix Based on Irreducible Polynomial,”
Soufiane & Seddik (2015) implemented DES using Time Journal of Theoretical and Applied Information Technology,
Variable Sub-Keys on a Xilinx FPGA, achieving a data rate vol. 97, no. 5, 2019. This paper enhances DES security
of 9453.47 Mbps. However, the design required 2046 FPGA by using a diagonal matrix transformation with an irre-
CLB slices and faced synchronization issues(11). ducible polynomial, increasing key complexity and resistance
Radhi & Ogla (2023) conducted an in-depth assessment of to cryptanalysis.(19).
cryptographic algorithms, including DES, 3DES, AES, RSA, Sreeja Rajesh, V. P., “A Secure and Efficient Lightweight
and Blowfish. Their study revealed that Blowfish demonstrated Symmetric Encryption Scheme for Transfer of Text Files Be-
the highest efficiency, requiring the least memory and achiev- tween Embedded IoT Devices,” Symmetry, 2019. Rajesh pro-
ing nearly three times the speed of other algorithms. Moreover, poses a lightweight encryption scheme for IoT, ensuring data
Blowfish exhibited superior security, with no known successful confidentiality with minimal computational overhead.(20).
JOURNAL OF LATEX CLASS FILES, VOL. 14, NO. 8, AUGUST 2015 3

III. M ETHODOLOGY half and the right half, where the right half is passed directly
A. Data Encryption Algorithm to the left 32-bit of the subsequent round, the left half is ex-
ored with the 32-bit result from the Mangler function applied
The original or the first cryptographical algorithm designed
to the right half. The resulting 32-bit is passed to the right
by IBM utilized 128-bit key, later being changed with a 56-bit
32-bit of the subsequent round. In the Mangler function, the
key for fulfilling security and hardware efficiency needs. The
right half, which is of 32 bits in length, is expanded into
plaintext input to the DES encryption algorithm is 64 bit long.
48 bits by expansion permutation and the 56-bit round key,
These 64-bit plaintext were subjected to initial permutation to
which is permuted to 48 48-bit round key is expanded with
place the 64 bit and then brought into 16 rounds of encryption
it. The resulting 48-bit further goes through the substitution
where, two significant operations bring confusion and diffu-
box or S-Box that cuts it down to 32-bit and is provided to
sion onto the input text. Confusion is utilized to render the
the permutation box or p-box. These two operations impart
cipher text as complicated and non-linear as possible. The
confusion and diffusion properties to the text message. All the
confusions are brought in by utilizing Substitution Operations
above process has to be performed for a total of 16 rounds.
such as S-Boxes (Substitution Boxes). These operations place
Each round will have its own round key. Number of rounds
the input bit on the output bit in what appears to be a random
for encryption and decryption should be equal. The number of
fashion, utilizing the lookup table. This makes the process
rounds can be made higher for achieving higher security, but
of decrypting the encryption more complex by methods such
the delay in encryption or decryption of the message increases.
as cryptanalysis. Diffusion is utilized to add redundancy to
The left and right round key for the subsequent round can be
the plain text, on the other hand. This guarantees that an
logically described as:
alteration in the plain text by even a slight amount will make
a large change in the cipher text. In the ideal case, affects half Li = Ri−1 (1)
the cipher text. Diffusion is achieved by the application of
permutation operations, which rearranges or randomly places Ri = Li−1 ⊕ F (Ri−1 , Ki ) (2)
the bits in a manner that hides the patterns in the plain text The Mangler function is defined as a function F., R denotes
from the cipher text. DES uses initial permutation at the begin- round, and K denotes key respectively. And I denotes the
ning of the encryption, final permutation or the inverse initial number of rounds which, in the suggested implementation,
permutation at the end of encryption and round permutation at is 16.
16 rounds, which is responsible for the diffusion. Confusion
and diffusion together ensure security against the linear and
differential cryptanalysis. These characteristics are extremely
important for strong encryption. All of the 16 rounds utilize
a, 56-bit key, all of which have been produced by the same
initial key of 64-bit length. The 64-bit text achieved at the end
of the 16th round is then input into the 32-bit swap operation
and passed on to the inverse initial permutation, the output of
which is the desired 64-bit cipher text. This 64-bit cipher text
can be passed to the decryption algorithm to regain the plain
text.

Fig. 2. Single Round DES Algorithm

C. Key Generation
The size of the primary key is 64 bits, which is equal to the
size of the input plain text. The primary key utilizes the look-
up table to compress it to a 56-bit sub-key by the permutation
algorithm that loses 8 bits out of 64 bits. This gives two 28-bit
halves which are kept in C0 and D0 . The effective key length
of the DES algorithm is thus 56-bit. and the number of key
combinations is 256 . The two halves subsequently undergo
Fig. 1. Encryption Algorithm left-shift operation by 1 or 2 bits, based on the round number.
One shift operation for rounds 1, 2, 9, and 16, and two shift
operations for the other rounds. 56-bit is permuted to obtain a
B. Single Round DES Algorithm 48-bit round key. This process is performed 16 times and thus
In each iteration of the encryption algorithm, the 64-bit of produces distinctive keys per round each 48-bit long, which is
plain text that is originally separated into two halfs: the left subsequently utilized to XOR with the result of the expansion
JOURNAL OF LATEX CLASS FILES, VOL. 14, NO. 8, AUGUST 2015 4

IV. RESULTS
The proposed fully subpipelined DES architecture for a 64-
bit key is implemented on a Xilinx Spartan 7 FPGA. For
synthesis, timing, and power analysis, Xilinx Vivado 2018.1 is
used. For each clock cycle, data blocks of 64 bits are accepted
in the fully subpipelined encryptor. Next, 64-bit output data is
taken for each input block as the cipher text in each clock
cycle. A hardware description language (HDL) is used to
design and implement the DES architecture. The designed
architecture is used to process the 64 bits of cryptography.
The Data Encryption Standard (DES) is a symmetric-key
algorithm that encrypts a 64-bit plaintext using a 56-bit key
Fig. 3. Key Generation in DES
through 16 rounds of Feistel network operations. For the
given input message (0123456789abcdef in hexadecimal) and
key (133457799bbcdff1 in hexadecimal), the DES encryption
permutation within the mangler function for every round of follows a structured process.
encryption. It is guaranteed that whenever there is a change Initially, the 64-bit plaintext undergoes an Initial Permuta-
in the input key, the 16 sub-keys are calculated. tion (IP), which rearranges the bits based on a predefined table.
The permuted data is then split into two 32-bit halves, denoted
as L0 (Left) and R0 (Right). The key scheduling process
D. The S-Box and the P-BOX generates 16 round keys (Ki, i = 1 to 16) from the original
In each round of the Encryption algorithm, the 48-bit output 56-bit key by applying PC-1 permutation, splitting into two
from the expansion permutation is XORed with the 48-bit 28-bit halves, and performing circular left shifts followed by
key as mentioned earlier. The resulting 48-bit is then given PC-2 permutation to derive each 48-bit subkey.
to S-Box to be reduced to 32-bit. There are 8 S-Boxes, each In each round, the right half (R) is expanded to 48 bits
accepting 6-bit input which adds up to 48-bits. In the 6-bit using the Expansion (E) permutation and XORed with the
that each box receives, the first and the last bit represent the corresponding round key (Ki). The result is then substituted
row and the middle 4-bits represent the column. Using this using 8 S-Boxes, reducing it back to 32 bits. The output
information, the output of each S-Box is decided with the help undergoes the P-Permutation, which scrambles the bits further.
of the lookup table. The output is of 4-bit and has the value The result is XORed with the left half (L) from the previous
present in the look up table corresponding to the given row and round, and then L and R swap places for the next round. This
the column. The 4-bit output from each of the S-Boxes adds process repeats for 16 rounds.
up to 32 bits. S-Boxes introduces non-linearity and strengthen After the final round, the two halves are concatenated and
encryption. Now this 32-bit message is given to the P-Box subjected to the final permutation (IP ¡1), producing the final
which performs the permutation Operation. In the P-Box, the 64-bit ciphertext. For the given inputs, the output ciphertext
positions of all 32-bits are changed, making use of the look after DES encryption is 85E813540F0AB405 in hexadecimal.
up table for permutation. Hence, both confusion and diffusion This transformation ensures that even a small change in the
properties are added by the S-Box and the P-Box. input leads to a completely different encrypted output due to
the avalanche effect of DES.
E. Avalanche Effect in DES
Avalanche effect is a significant component of the cryp-
tographic algorithm. It guarantees that a minor alteration
in the input (plaintext or key) causes a dramatic and un-
predictable alteration in the output (ciphertext). In the case
of the Data Encryption Standard (DES), this implies that
a single bit change in plaintext or key should alter about
half of the resulting ciphertext bits.A single change in any
single bit in the input plaintext or key, while it may not
alter the entire ciphertext, will result in huge variations in
subsequent rounds. By the 16th round, about 50 percent of the
ciphertext bits, i.e., approximately 32 bits will shift, providing
greater security. This makes it hard for attackers to deduce Fig. 4. Output for a given value of input
relationships between key, plaintext, and ciphertext. If minor
input changes resulted in determinable output changes, then The DES encryption core was synthesized on a Xilinx
attackers could utilize this to compromise the encryption. The Spartan-7 FPGA, and its hardware consumption was studied
randomness provided by S-Boxes and P-Boxes renders DES to assess the hardware execution efficiency. From the findings,
less susceptible to attacks. the design only utilizes 1168 Slice LUTs, which translates to
JOURNAL OF LATEX CLASS FILES, VOL. 14, NO. 8, AUGUST 2015 5

3.58 percent of the accessible 32,600 LUTs, which is evidence V. DISCUSSION AND CONCLUSION
of an optimized logic deployment. Equally, the 1592 Slice
Registers utilized translate to 2.44 percent of the entire 65,200 This work effectively proves the effective application of
registers, which is evidence that there is minimal usage of flip- the DES encryption algorithm on the Xilinx Spartan-7 FPGA,
flops and sequential logic. confirming its suitability for real-time cryptographic process-
ing. The FPGA resource usage results show that the design
The Block RAM usage is high, with 35 out of 75 tiles uses only 3.58 percent of LUTs and 2.44 percent of slice
occupied, or 46.67 percent, indicating the use of internal registers, leaving ample hardware resources for other security
memory for the storage of intermediate encryption data and features, like Triple DES (3DES) or AES encryption. The DSP
S-box operations. The usage of the Digital Signal Processing and Block RAM usage, standing at 46.67 percent and 33.33
(DSP) block is 40 out of 120 (33.33 percent), indicating that percent, respectively, are indicative of the system’s heavy
a moderate amount of arithmetic operations are carried out dependence on arithmetic operations and internal memory,
in the FPGA fabric. Interestingly, Bonded I/O Buffer (IOB) thereby affirming its capability to support intricate crypto-
usage is 87.62 percent, which reflects intense interaction with graphic computations. The utilization of 87.62 percent IOBs
external data sources, as would be expected in encryption uses further reiterates the high interaction of the design with exter-
where data must be read and written often. In general, these nal data, which suits it for real-time encryption in embedded
findings affirm that the DES core implementation on Spartan- systems.
7 is efficient in terms of resources and has plenty of space for
The synthesis outcomes complement the efficiency of the
other cryptographic features or parallel processing.
Spartan-7, with a quick synthesis time of 26 seconds and aver-
age memory usage (586.87 MB peak usage, 347.53 MB mem-
ory gain), supporting resource-limited applications. The results
show that FPGA-based cryptographic code implementations
represent an attractive alternative to software encryption, with
greater speed, reduced latency, and better side-channel attack
protection.
The findings confirm that the Spartan-7 FPGA can support
DES encryption at low power usage and high processing
performance. The low LUT and register usage and moderate
Fig. 5. FPGA Resource Utilization for DES Core Implementation DSP and Block RAM usage indicate that higher security
features like triple DES (3DES) or AES can be implemented
To evaluate the hardware synthesis efficiency, the synthesis with minimal overhead. In addition, the compact synthesis
time and memory usage metrics were recorded. The FPGA time and memory-managed utilization imply that Spartan-7
synthesis process was completed in 24 seconds (CPU time) is a good candidate for real-time embedded cryptographic
and 26 seconds (elapsed time), highlighting the fast compi- purposes such as secure communication, payment, and IoT
lation and mapping of the DES algorithm onto the Spartan-7 protection.
architecture. The synthesis was performed using Xilinx Vivado These findings validate the feasibility of implementing
2018, and the rapid completion time indicates that the FPGA lightweight cryptographic algorithms on cost-effective FPGAs
fabric supports efficient hardware realization of cryptographic like the Spartan-7, ensuring both hardware efficiency and
operations. performance scalability.
In all, this research justifies the use of the Spartan-7 FPGA
The peak memory usage during synthesis was 586.87 MB,
as a prime platform for lightweight cryptographic computation,
while the memory gain recorded was 347.53 MB. These values
especially for IoT security, financial services, and secure
demonstrate that the synthesis process remains within a rea-
communication networks. Future research can work towards
sonable memory footprint, making it feasible for low-power,
power optimization and incorporation of hybrid models of
embedded FPGA applications. The moderate memory gain
cryptography to achieve more security and effectiveness in
suggests that the design benefits from optimization techniques,
FPGA-based encryption systems.
such as resource sharing and LUT merging, resulting in a
compact and efficient implementation.
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