Module5

Randomization
Text book: Chris Spear
 Randomization Overview
Why Randomize?

 As designs grow it becomes more difficult to test their features

through directed test cases
 Directed test cases checks specific features of a design and can
only detect anticipated bugs
 Directed test case approach is a time consuming exercise

 Directed tests detect only anticipated bugs in the design

Solution is Constrained Random Testcases (CRT) which randomize the input stimulus

Random testing detects the bugs you did not expect in your
design
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 Randomization
• Randomization is the process of making
something random.
• SystemVerilog randomization is the process of
generating random values to a variable.
• Verilog has a $random method for generating the
random integer values-this is good for
randomizing the variables alone, but it is hard to
use in case of class object randomization.
• For easy randomization of class properties,
SystemVerilog provides rand keyword and
randomize() method.
Test Bench
 What to randomize
• Device configurations
• Environment configurations
• Primary Input Data
• Encapsulated input data
• Protocol exceptions, errors and violations
• Delays
• random variables: The class variables which get
random values on randomization are called random
variables.
• In order to make variables as random variables, Class
variables need to be declared using the rand and randc
type-modifier keywords.
• Following types can be declared as rand and randc,
--singular variables of any integral type
--arrays
--arrays size
--object handle’s
• Ex: rand bit [3:0] addr;
- addr is a 4-bit unsigned integer with a range of 0
to 15. on randomization this variable shall be
assigned any value in the range 0 to 15 with equal
probability
- randc keyword
- randc is random-cyclic. For the variables declared
with the randc keyword, on randomization
variable values don’t repeat a random value until
every possible value has been assigned.
• randomization example
• In the previous example,
Two variables addr1 and addr2 of same bit type
are declared as rand and randc respectively,
observe the randomized values of addr1 and
addr2.
• addr1 – takes the random value on every
randomization
addr2 – takes the random value on every
randomization, but takes random value until
every possible value has been assigned
• In order to randomize the object variables, the
user needs to call randomize() method.
• example: object.randomize()
 Randomization in SystemVerilog
• Overview
– Randomization enables users to automatically generate random input
stimulus for functional verification
– SystemVerilog enables user to specify random constrained (legal) values
– Random constraints should be specified using OOP

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 Randomization in SystemVerilog
• rand keyword
– Random variables are declared with the rand keyword
• Their values are uniformly distributed over the specified range
• If unconstrained the variable shall assign any value in the specified range with
equal probability

rand bit [7:0] y; 8-bit unsigned integer with the range 0 to 255

The probability of the same value repeating on successive calls to randomize is 1/256
•If unconstrained y is assigned any value in the range 0 to 255 with equal probability

•The probability of a value occurring on simultaneous calls to randomize is 1/256

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 Randomization in SystemVerilog
• randc keyword
– Random cyclic variables are declared with the randc keyword
• They cycle through all the values in a random permutation of their declared range
• Can only be of the type bit or enum( Typedef enum {READ, WRITE,CONTROL})

• randc randomly iterates over all the values in the range and no value is repeated within an
iteration
– When the iteration finishes, a new iteration automatically starts
randc bit [1:0] y; 2-bit unsigned integer with the range 0 to 3

y can take values 0,1,2,3

initial permutation 0 -> 3 -> 2 -> 1

next permutation 2 -> 1 -> 3 -> 0

next permutation 2 -> 0 -> 1 -> 3

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 Randomization in SystemVerilog
• Simple class with random variables
– The Bus class models a simplified bus with two random variables: addr
and data
– The range1 constraint specifies the limits for the values of addr
• Ensure non conflicting and legal constraints

class Bus
rand bit[15:0] addr; random variable
randc bit[31:0] data; random cyclic: the random solver
constraint range1 {addr>1024; addr<16384;} will not repeat a permutation of
endclass values
Example: Simple class with random variables constraining the random variables to
values between 1024 and 16384

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 Randomization in SystemVerilog
• randomize()function
– Calling randomize() causes new values to be selected for all of the
random variables in an object
• The random values obey the constraints
– randomize function returns a 1 on success and 0 on failure
– Unconstrained variables are assigned any values in their declared range

a bus object is created and

randomized 50 times result of each randomization
is checked

Bus bus=new;
repeat (50) begin
if(bus.randomize()==1)
$display(bus.addr, bus.data);
else
$display (“Randomization failed”);
end
Example: randomize() function example
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 Randomization in SystemVerilog
• The constraint solver
– Solves constraint expressions
– The same seed results in the same random values
• Use a different seed to generate different set of random values
– The solver is specific to the simulation vendor
– Constraint blocks are not procedural codes (begin and end not required)
– Use { } to group multiple expressions.

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 Constraint Details
• Constraint Blocks
– Values of random variables are determined using constraint expressions that are
declared using constraint blocks
• Smart stimulus tests relationships between variables
– They are class members like tasks, functions and variables
– Constraint declaration
• Constraint identifier: is the name of the constraint block.
• Constraint block: is a list of expression statements that restrict the range of variable or
define relations between variables

In the example below randomize() fails sometimes and succeeds sometimes, why?
constraint_identifier constraint_block
Error!!!
rand bit[15:0] addr;
class Bus
bit[15:0] addr;
randc bit[31:0] data;
constraint range1 {addr>1024; addr<16384;}
endclass
Example: Simple constraint example
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 Constraint Details
• Simple expressions
– Constraint variables have to be in a fixed order
• There can be only one relational operator (<, <=, ==, >= or >)
• For multiple variables use multiple expressions

Declare a constraint to solve: 0 < a < b < c

Error!!! wrong way right way

class Bus
rand bit[15:0] a,b,c; class Bus
constraint c1 { 0 < a < b < c; } rand bit[15:0] a,b,c;
endclass constraint c1 { 0 < a;
a < b;
b < c;}
endclass

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 Constraint Details: Example
• Set membership Operator: inside
– If other constraints are absent, all values have an equal probability of
being chosen by the inside operator
– The negated (!) form of inside operator denotes that expression lies
outside the set

addr is between 0 to 100 multiple mutually exclusive

or between 1024 to 16384 constraints can be defined
within one constraint

class Bus
rand bit[15:0] addr;
randc bit[31:0] data;
constraint range1
{
addr inside {[0:100],[1024:16384]};
data > 1000;
data < 10000;
}
endclass
Example: Constraint example with inside operator
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 Constraint Details: Quiz
Declare constraint blocks c1,c2,c3 and c4 so that variable x, a and v get
the values shown:
x takes any values described in the constraint_block :
• x is: 3,5,9,10,11,12,13,14,15,24,25,26,27,28,29,30,31,32
• x is: 3,5,9,10,11,12,13,14,15,24,25,26,27,28,29,30,31,32,
between y and 2y, z
rand integer x,y,z;
constraint c1 {x inside {3,5,[9:15],[24:32];}
constraint c1 {x inside {3,5,[9:15],[24:32],[y:2*y],z};}

• b<=a and a<=c or b<=a<=c

rand integer a,b,c;
constraint c2 {a inside {b,c};}

• c3: v is either 5,10,15,20

• c4: v is never 5,10,15,20
integer fives[0:3] = {5,10,15,20};
rand integer v;
constraint c3 {v inside fives;}
constraint c4 !{v inside fives;}

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 Weighted Distribution
• In constraint blocks, we can control the
occurrence or repetition of the same value on
randomization using dist operator.
• Some values can be allocated more often to a
random variable. This is called as weighted
distribution. Weights will be specified to the
values inside the constraint block.
• Dist operator takes a list of values and
weights, separated by := or :/
 Weighted Distribution
• Distributions: dist operator
– Used to weigh some values more than the others
• Property 1: They are a relational test for set membership
• Property 2: They specify a statistical distribution function for the result
– Can use := or :/ operator
• := specifies that the weight has to be the same for every specified value in the
range
• :/ operator specifies that the weight is to be equally divided between all
values. If there are n values in a range the weight is range_weight/n
– Values can be a single value or range such as [lo:hi]
– The weights are not percentage and do not have to add up to a 100
– Cannot be used with a randc

c1 should be 0 once and 1 five times

Error!!! wrong way right way
rand integer a; rand integer a;
constraint c1 {a inside {0,1,1,1,1,1}); constraint c1 {a dist {0:=1, 1:=5}};

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 Weighted Distribution
• Another example
rand int src, dst;
costraint c1 {
src dist {0:=40, [1:3]:=60};
dst dist {0:=40, [1:3]:/60};
}
Example: Weighted random distribution with dist

src weight dst weight

0 40/220 0 40/100
1 60/220 1 20/100
2 60/220 2 20/100
3 60/220 3 20/100

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 Weighted Distribution: Quiz
• Distributions: dist operator := and :/
• x is 100, 200 and 300 with a weight of 1,2 and 5 respectively

x dist {100:=1, 200:=2, 300:=5}

• x is 100 and 300 with a weight of 1 and 5 respectively

• x is never 200

x!=200;
x dist {100:=1, 300:=5}

• x is 100, 101 , 102 with a weight of 1 each

• x is 200 and 300 with a weight of 2 and 5 respectively

x dist {[100:102]:=1, 200:=2, 300:=5}

• x is 100, 101 , 102 with a weight of 1/3 each

• x is 200 and 300 with a weight of 2 and 5 respectively

x dist {[100:102]:/1, 200:=2, 300:=5}

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 Bidirectional Constraints
• Bidirectional Constraints
– Constraint blocks are not procedural but declarative
• All active at one time

Solve the constraint

30>d>b==c>=25

rand logic [15:0] b,c,d;

Solution b c d
costraint c1 { A 26 26 27
b<d;
c==b; B 26 26 28
d<30;
C 26 26 29
c>=25;
} D 27 27 28
Example: Bidirectional constraints E 27 27 29
F 28 28 29
Solutions for Bidirectional Constraints

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 Conditional Constraints
• Conditional constraint operators
– Constraint provide two constructs for declaring conditional relations
• Implication operator ->
• if…else

if(mode==small)
len<10; mode == small -> len<10;
else if (mode==large) mode == large -> len>100
len>100;

Example: if…else example Example: Equivalent implication example

bit [3:0] a,b; bit [3:0] a,b;

if(a==0) constraint c {(a==0)->(b==1);}
b==1;

Example: if…else example Example: Equivalent implication example

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 Solution Probabilities
• Unconstrained
– Probability of distribution

Solution x y Probability
A 0 0 1/8

class Unconstrained;
B 0 1 1/8
rand bit x; C 0 2 1/8
rand bit [1:0] y;
endclass
D 0 3 1/8
E 1 0 1/8
Example: Class with unconstrained random variables
F 1 1 1/8
There are 8 possible solutions and
G 1 2 1/8
because there are no constraints each has
the same probability H 1 3 1/8
Solutions for Unconstrained class

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 Solution Probabilities
• Implication
– Probability of distribution changes due to the implication operator
– Implication is bidirectional

class Imp1; Solution x y Probability

rand bit x;
rand bit [1:0] y; A 0 0 1/2
constraint c_xy { B 0 1 0
(x==0)->y==0;
} C 0 2 0
endclass D 0 3 0
Example: Class with implication E 1 0 1/8
F 1 1 1/8
G 1 2 1/8
Value of y depends on x. When x is 0, y is 0.
Hence for x=0, y cannot have any other H 1 3 1/8
value and hence the probability of x=0 and Solutions for Imp1 class
y!=0 is 0

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 Solution Probabilities
• Implication and bidirectional constraints
– Probability of distribution changes due to an addition constraint

class Imp_Bid; Solution x y Probability

rand bit x;
rand bit [1:0] y; A 0 0 0
constraint c_xy { B 0 1 0
y>0;
(x==0)->y==0; C 0 2 0
} D 0 3 0
endclass
E 1 0 0
Example: Class with implication and constraint
F 1 1 1/3
G 1 2 1/3
H 1 3 1/3
When x is 0, y is 0 but when y is 0 there Solutions for Imp_Bid class
is no constraint on x. Since implication is
bidirectional, if y was forced to a non
zero value, x would have to be 1. Hence x
can never be 0.

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 Solution Probabilities
• Solve…before
– Solve…before does not change the solution space but changes the probability of
the results

class SolveBefore;
rand bit x;
rand bit [1:0] y;
constraint c_xy {
(x==0)->y==0;
solve y before x;
}
endclass
Example: Class with implication and solve…before

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 Solution Probabilities
class SolveBefore;
rand bit x;
rand bit [1:0] y;
constraint c_xy {
(x==0)->y==0;
solve y before x;
}
endclass
Example: Class with implication and solve…before

Solution y x Unconstrained Solution Probability

Probability Possibility
A 0 0 1/8 1/8
B 0 1 1/8 1/8
C 1 0 1/8 0
D 1 1 1/8 1/4
E 2 0 1/8 0
F 2 1 1/8 1/4
G 3 0 1/8 0
H 3 1 1/8 1/4
Solutions for solve y before x constraint
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 Solution Probabilities
• Solve…before
– Solve…before does not change the solution space but changes the probability of
the results

Solution y x Probability
class SolveBefore;
rand bit x;
A 0 0 1/8
rand bit [1:0] y; B 0 1 1/8
constraint c_xy {
(x==0)->y==0;
C 1 0 0
solve y before x; D 1 1 1/4
}
endclass
E 2 0 0
F 2 1 1/4
Example: Class with implication and solve…before
G 3 0 0
H 3 1 1/4
Solutions for solve y before x constraint

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 Solution Probabilities
• Solve…before

Solution x y Probability
class Imp4; A 0 0 1/2
rand bit x;
rand bit [1:0] y; B 0 1 0
constraint c_xy { C 0 2 0
(x==0)->y==0;
solve x before y; D 0 3 0
} E 1 0 1/8
endclass
F 1 1 1/8
Example: Class with implication and solve…before
G 1 2 1/8
H 1 3 1/8
Solutions for solve x before y constraint

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 Constraints
• Iterative constraints
– Allows arrayed variables to be constrained in a parameterized manner using loop
variables

C1 constraints each element of an array to be in the set [2,4,8,16]

C2 constraints each element of an array to be greater than twice its index

class C;
rand byte A[4];
constraint C1{ foreach (A[i]) A[i]inside {2,4,8,16};}
constraint C2{ foreach (A[j]) A[j]> 2*j;}
endclass

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 Constraints
• Iterative constraints
bit [3:0][2:1] B [5:1][4]
int A [2][3][4];
2 1

3 3 2 1 0

4 5:1

foreach (A[i,j,k])…
4
i iterates from 0 to 1
j iterates from 0 to 2 foreach (B[q,r,,s])…
k iterates from 0 to 3
q iterates from 5 to 1
r iterates from 0 to 3
s iterates from 2 to 1

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• Functions in constraints
Constraints
– Some properties are unwieldy or impossible to express in a single expression
• For instance computing the sum of one’s in a packed array uses a loop
• Without the loop the loop will have to be unrolled
– SystemVerilog allows constraint expressions to include function calls
• Functions cannot contain output or ref arguments
• Functions should be automatic
• Functions that appear in constraints cannot modify the constraints
• Functions shall be called before constraints are solved, and their return values shall be treated as state variables
• Random variables used as function arguments shall establish an implicit variable ordering or priority

class B;
rand int x,y;
constraint C{x<=F(y);} Forces y to be solved before x
constraint D{ y inside {2,4,8};}
endclass

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• Constraint guards
Constraints
– Constraint guards are predicate expressions that function as guards against creation of constraints
• They are not logical relations that have to be satisfied by the constraint solver
• Prevents the solver from generating evaluation errors
– Constraint guards are solved before the constraints and involve
• Constants
• State variables
• Object handle comparisons

The constraint will fail on the last element due to a non existent handle in the linked list
class SList;
rand int n;
constraint sort{n<next.n;}
endclass

if statement acts as a constraint guard

class SList;
rand int n;
constraint sort{if(next!=null)n<next.n;}
endclass

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• Constraint guards
Constraints
– Guard expressions can themselves include sub-expressions that result in evaluation errors
• A 4-state representation is used where
– 0 : false -> Subexpression evaluates to FALSE
– 1 : true -> subexpression evaluates to TRUE
– E: Error -> Subexpression causes an evaluation error
– R: Random -> Expression includes random variables and cannot be evaluated

class D
int x;
endclass
class C;
rand int x,y;
D a,b;
constraint C1{(x<y || a.x > b.x || a.x==5) -> x+y==10;}
endclass

Case a b a.x b.x Constraint

1 !0 0 5 error x+y=10
2 0 - error - always error
3 !0 !0 10 20 ( x<y) -> (x+y==10)
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 Constraints
• Constraint guards

class D
int x;
endclass
class C;
rand int x,y;
D a,b;
constraint C1{(x<y && a.x > b.x && a.x==5) -> x+y==10;}
endclass

Case a b a.x b.x Constraint

1 !0 0 5 error error
2 0 - error - always error
3 !0 !0 5 2 ( x<y) -> (x+y==10)

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 Disabling Random Variables
• Disabling random variables with rand_mode()
– Can be used to control whether a random variable is active or inactive
• When a random variable is inactive it implies that the variable was never declared rand or randc
• rand_mode() method is inbuilt and cannot be overridden

Value Meaning Description

0 OFF Sets the specified variable to inactive so that they are not randomized on
subsequent calls to randomize() method
1 ON Sets the specified variable to active so that they are randomized on
subsequent calls to randomize() method

class Packet;
rand integer src, dst;
endclass

int r;
Packet packet_a=new;
packet_a.rand_mode(0);
packet_a.src.rand_mode(1);
r=packet_a.dst.rand_mode();

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•
Controlling Constraints
Controlling constraints with constraint_mode()
– Can be used to control whether a constraint is active or inactive
• When a constraint is inactive is not considered by randomize()
• All constraints are initially active
• constraint_mode method is built it and cannot be overridden

Value Meaning Description

0 OFF Sets the specified constraint block to inactive so that it is not enforced by
subsequent calls to randomize() method
1 ON Sets the specified constraint block to active so that it is considered by
subsequent calls to randomize() method

class Packet;
rand integer src, dst;
constraint filter{src>2*dst;}
endclass

function integer toggle_rand (Packet p);

if (p.filter.constraint_mode()==1)
p.filter.constraint_mode(0);
else
p.filter.constraint_mode(1);
toggle_rand=p.randomize();
endfunction

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• rand_mode method
• The rand_mode() method is used to disable the
randomization of a variable declared with the
rand/randc keyword.
• rand_mode(1) means randomization enabled
• rand_mode(0) means randomization disabled
• The default value of rand_mode is 1, i.e enabled
• Once the randomization is disabled, it is required to
make rand_mode(1) enable back the randomization
• rand_mode can be called as SystemVerilog method,
the randomization enables/disable .
• Status of a variable can be obtained by calling
vairble.rand_mode().