3.

Assembly programming language

Chapter 3
Assembly programming language

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 3. Assembly programming language 3.1 Introduction to Assembly

3.1 Introduction to Assembly

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 3. Assembly programming language 3.1 Introduction to Assembly

High level versus Assembly

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 3. Assembly programming language 3.1 Introduction to Assembly

High level versus Assembly

High level languages Assembly language
• More programmer friendly. • Lower level, closer to ISA.
• More ISA independent. • Very ISA-dependent.
• Each high-level statement trans- • Each instruction specifies a single
lates to several instructions in the ISA ISA instruction.
of the computer.
• Makes low level programming more
user friendly.
• More efficient code.

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 3. Assembly programming language 3.1 Introduction to Assembly

High level versus Assembly

High-level
language

Assembly
language
Low-level
language
Machine language

Hardware

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 3. Assembly programming language 3.1 Introduction to Assembly

Assembler syntax

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 3. Assembly programming language 3.1 Introduction to Assembly

Assembler syntax

{label[:]} mnemonic operand1, operand2,... {;comment}

Symbols:
⋄ Used as labels, constants, and substitution values and stored in
a symbol table.
⋄ A symbol name is a string of up to 200 alphanumeric characters
(A-Z, a-z, 0-9, $, and ), cannot contain embedded blanks, is
case sensitive.
⋄ The first character cannot be a number.
Labels:
⋄ Labels are symbols.
⋄ Begined in column 1 and is optionally followed by a colon.
⋄ The value of a label is the current value of the Location
⋄ Counter (address within program).
⋄ A label on a line by itself is a valid statement.
⋄ Labels used locally within a file must be unique.
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 3. Assembly programming language 3.1 Introduction to Assembly

Assembler syntax

mnemonic:
⋄ Contains one of the following items: Instruction, directive, pseudo-
instruction.
⋄ Instructions and pseudo-instructions make up the code a pro-
cessor uses to perform tasks.
⋄ Directives provide important information to the assembler that
either affects the assembly process or affects the final output
image.
⋄ Cannot start in column 1. If it does, it is interpreted as a label.
Operands:
⋄ Contains one or more operands.
⋄ An operand may consist of: symbols, constants, expressions.
⋄ Operands are separated with commas.

Comment: Optional.

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 3. Assembly programming language 3.1 Introduction to Assembly

Flexible second operand (Operand2)

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 3. Assembly programming language 3.1 Introduction to Assembly

Flexible second operand (Operand2)

Operand2 can be either of the following:
A constant
Syntax
#constant
where constant is an expression evaluating to a numeric value.
A register with optional shift
Syntax
Rm {, shift}
where: Rm is the register holding the data for the second operand.

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 3. Assembly programming language 3.2 Assembly source code

3.2 Assembly source code

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 3. Assembly programming language 3.2 Assembly source code

Literals

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 3. Assembly programming language 3.2 Assembly source code

Literals
Assembly language source code can contain numeric, string, Boolean, and single
character literals. Literals can be expressed as
Decimal numbers, for example 123.
Hexadecimal numbers, for example 0x7B.
Numbers in any base from 2 to 9, for example 5 204 is a number in base 5.
Floating point numbers, for example 123.4.
Boolean values TRUE or FALSE.
Single character values enclosed by single quotes, for example ’w’.
Strings enclosed in double quotes, for example "This is a string".

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 3. Assembly programming language 3.2 Assembly source code

Common directives

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 3. Assembly programming language 3.2 Assembly source code

Common directives
Directives are not instructions. They are used to divert the manner of the assembling
code.
The common directives include:

ALIGN directive aligns the current location to a specified boundary by padding

with zeros or NOP instructions.
AREA directive is used to mark the start of a section.
The following example defines a single read-only section called ARMex that
contains code:

AREA ARMex, CODE, READONLY ; Name this block of code

DCB directive allocates one or more bytes of memory, and defines the initial
runtime contents of the memory.
ELF (Executable and Linkable Format) sections are independent, named, indi-
visible sequences of code or data.

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 3. Assembly programming language 3.2 Assembly source code

Common directives

END directive informs the assembler that it has reached the end of a source
file.
ENTRY directive declares an entry point to a program.
EQU directive gives a symbolic name to a numeric constant, a register-relative
value or a PC-relative value.
EXPORT or GLOBAL directive declares a symbol that can be used by the linker
to resolve symbol references in separate object and library files. GLOBAL is a
synonym for EXPORT.
INCLUDE or GET directive includes a file within the file being assembled. The
included file is assembled at the location of the GET directive. INCLUDE is a
synonym for GET.
RN directive defines a name for a specified register.
THUMB directive instructs the assembler to interpret subsequent instructions as
Thumb instructions.

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 3. Assembly programming language 3.2 Assembly source code

Assembly source code

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 3. Assembly programming language 3.2 Assembly source code

Assembly source code

An example of an Assembly source code is as follows:

AREA ARMex, CODE, READONLY

; Name this block of code ARMex
ENTRY ; Mark first instruction to execute
start
MOV r0, #10 ; Set up parameters
MOV r1, #3
ADD r0, r0, r1 ; r0 = r0 + r1
stop
MOV r0, #0x18 ; angel_SWIreason_ReportException
LDR r1, =0x20026 ; ADP_Stopped_ApplicationExit
SVC #0x123456 ; ARM semihosting

END

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 3. Assembly programming language 3.2 Assembly source code

Assembly source code

Application entry
The ENTRY directive declares an entry point to the program. It marks the first
instruction to be executed.
Application execution
The application code begins executing at the label start, where it loads the decimal
values 10 and 3 into registers R0 and R1. These registers are added together and
the result placed in R0.
Program end
The END directive instructs the assembler to stop processing this source file. Every
assembly language source module must finish with an END directive on a line by
itself. Any lines following the END directive are ignored by the assembler.

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 3. Assembly programming language 3.3 Move instructions

3.3 Move instructions

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 3. Assembly programming language 3.3 Move instructions

MOV instruction

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 3. Assembly programming language 3.3 Move instructions

MOV instruction
Syntax
MOV{S}{cond} Rd, Operand2
MOV{cond} Rd, #imm16
where:
S is an optional suffix.
cond is an optional condition code.
Rd is the destination register.
Operand2 is a flexible second operand.
imm16 is any value in the range 0-65535 (0x0000 - 0xFFFF).
Operation
Rd ← Operand2
Description
Copy the value of Operand2 into Rd.
Status bits
If S is specified, the N, Z, and C (during the calculation of Operand2) flags according
to the result but the V flag is not affected.
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 3. Assembly programming language 3.3 Move instructions

MOV instruction

 Example 3.1 (MOV instruction)

Copy the value of 0xF9C0 into register R0.

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 3. Assembly programming language 3.3 Move instructions

MOV instruction

Solution:

Code 3.1 (MOV instruction)

Stack_Size EQU 0x00000400

AREA STACK,NOINIT,READWRITE,ALIGN=3

Stack_Mem SPACE Stack_Size

AREA RESET,DATA, READONLY

EXPORT __Vectors
__Vectors
DCD Stack_Mem+Stack_Size
DCD Reset_Handler
ALIGN

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 3. Assembly programming language 3.3 Move instructions

MOV instruction

AREA |.text|, CODE, READONLY, ALIGN=2

THUMB
ENTRY
EXPORT Reset_Handler
Reset_Handler
MOV R0,#0xF9C0
NOP

ALIGN
END

This leads to R0 = 0x0000F9C0.

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 3. Assembly programming language 3.3 Move instructions

MOVT instruction

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 3. Assembly programming language 3.3 Move instructions

MOVT instruction
Syntax
MOVT{cond} Rd, #imm16
where:
cond is an optional condition code.
Rd is the destination register.
imm16 is a 16-bit immediate value.
Operation
Rd ← imm16
Description
MOVT writes imm16 to Rd[31:16], without affecting Rd[15:0]
Status bits
This instruction does not change the flags.

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 3. Assembly programming language 3.3 Move instructions

MOVT instruction

 Example 3.2 (MOVT instruction)

Copy the value of 0xF9C0 into the higher bits of register R0.

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 3. Assembly programming language 3.3 Move instructions

MOVT instruction

Solution:

Code 3.2 (MOVT instruction)

AREA |.text|, CODE, READONLY, ALIGN=2

THUMB
ENTRY
EXPORT Reset_Handler
Reset_Handler
MOVT R0,#0xF9C0
NOP

ALIGN
END

This leads to R0 = 0xF9C00000.

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 3. Assembly programming language 3.3 Move instructions

MOV32 pseudo-instruction

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 3. Assembly programming language 3.3 Move instructions

MOV32 pseudo-instruction
Syntax
MOV32{cond} Rd, expr
where:
cond is an optional condition code.
Rd is the destination register. Rd must not be SP or PC.
expr can be any one of the following:
⋄ symbol: A label in this or another program area.
⋄ #constant: Any 32-bit immediate value.
⋄ symbol + constant: A label plus a 32-bit immediate value.
Operation
Rd ← expr
Description
Load any 32-bit immediate, or to access the whole 32-bit address space.

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 3. Assembly programming language 3.3 Move instructions

MOV32 pseudo-instruction

 Example 3.3 (MOV32 instruction)

Copy the value of 150000 into register R1.

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 3. Assembly programming language 3.3 Move instructions

MOV32 pseudo-instruction

Solution:

Code 3.3 (MOV32 instruction)

AREA |.text|, CODE, READONLY, ALIGN=2

THUMB
ENTRY
EXPORT Reset_Handler
Reset_Handler
MOV32 R0,#150000
NOP

ALIGN
END

This leads to R0 = 0x000249F0 (150000).

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 3. Assembly programming language 3.4 Load/Store Instructions

3.4 Load/Store Instructions

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 3. Assembly programming language 3.4 Load/Store Instructions

LDR instruction

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 3. Assembly programming language 3.4 Load/Store Instructions

LDR instruction
Syntax
LDR{type}{cond} Rt, [Rn {, #offset}] ; immediate offset
LDR{type}{cond} Rt, [Rn, #offset]! ; pre-indexed
LDR{type}{cond} Rt, [Rn], #offset ; post-indexed
LDRD{cond} Rt, Rt2, [Rn {, #offset}] ; immediate offset,
; doubleword
LDRD{cond} Rt, Rt2, [Rn, #offset]! ; pre-indexed, doubleword
LDRD{cond} Rt, Rt2, [Rn], #offset ; post-indexed, doubleword
where:
type can be any one of:
⋄ B: unsigned Byte (Zero extend to 32 bits on loads.)
⋄ SB: signed Byte (LDR only. Sign extend to 32 bits.)
⋄ H: unsigned Halfword (Zero extend to 32 bits on loads.)
⋄ SH: signed Halfword (LDR only. Sign extend to 32 bits.)
⋄ -: omitted, for Word.
cond is an optional condition code.

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 3. Assembly programming language 3.4 Load/Store Instructions

LDR instruction

Rt is the register to load.

Rn is the register on which the memory address is based.
offset is an offset. If offset is omitted, the address is the contents of Rn.
Rt2 is the additional register to load for doubleword operations.
Not all options are available in every instruction set and architecture.

Operation
Register ← Memory
Description
Load value from memory to a register.

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 3. Assembly programming language 3.4 Load/Store Instructions

LDR instruction

 Example 3.4 (LDR instruction)

Copy the value at the address pointed by register R2 into register R3.

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 3. Assembly programming language 3.4 Load/Store Instructions

LDR instruction

Solution:

Code 3.4 (LDR instruction)

Stack_Size EQU 0x00000400

AREA STACK,NOINIT,READWRITE,ALIGN=3

Stack_Mem SPACE Stack_Size

AREA RESET,DATA, READONLY

EXPORT __Vectors
__Vectors
DCD Stack_Mem+Stack_Size
DCD Reset_Handler
ALIGN

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 3. Assembly programming language 3.4 Load/Store Instructions

LDR instruction

AREA |.text|, CODE, READONLY, ALIGN=2

THUMB
ENTRY
EXPORT Reset_Handler
Reset_Handler
MOV32 R2,#0xC0F9A4B0
LDR R3,[R2]
NOP

ALIGN
END

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 3. Assembly programming language 3.4 Load/Store Instructions

LDR instruction

Registers Memory
R0 0xXXXXXXXX 0xC0F9A4B0 0xXXXXXXXX
R1 0xXXXXXXXX
R2 0xC0F9A4B0
R3 0xXXXXXXXX
R4 0xXXXXXXXX
R5 0xXXXXXXXX
... ...

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 3. Assembly programming language 3.4 Load/Store Instructions

LDR pseudo-instruction

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 3. Assembly programming language 3.4 Load/Store Instructions

LDR pseudo-instruction
Syntax
LDR{cond}{.W} Rt, =expr
LDR{cond}{.W} Rt, =label_expr
where:
cond is an optional condition code.
.W is an optional instruction width specifier.
Rt is the register to be loaded.
expr evaluates to a numeric value.
label expr is a PC-relative or external expression of an address in the form
of a label plus or minus a numeric value.

Operation
Register ← Memory
Description
Load a register with either a 32-bit immediate value or an address.
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 3. Assembly programming language 3.4 Load/Store Instructions

LDR pseudo-instruction

 Example 3.5 (LDR pseudo instruction)

Assume there exist 8 bytes of memory named LED codes that is declared as

LED_codes DCB 0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8

Copy the value of the memory LED codes at the location 2 into register R3.

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 3. Assembly programming language 3.4 Load/Store Instructions

LDR pseudo-instruction

Solution:

Code 3.5 (LDR pseudo instruction)

Stack_Size EQU 0x00000400

AREA STACK,NOINIT,READWRITE,ALIGN=3

Stack_Mem SPACE Stack_Size

AREA RESET,DATA, READONLY

EXPORT __Vectors
__Vectors
DCD Stack_Mem+Stack_Size
DCD Reset_Handler
ALIGN

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 3. Assembly programming language 3.4 Load/Store Instructions

LDR pseudo-instruction

AREA |.text|, CODE, READONLY, ALIGN=2

THUMB
ENTRY
EXPORT Reset_Handler
Reset_Handler
MOV R6,#2
LDR R2,=LED_codes
LDR R3,[R2,R6]
NOP

LED_codes DCB 0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8

ALIGN
END

The value of register R3 will be 0x9299B0A4.

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 3. Assembly programming language 3.4 Load/Store Instructions

LDR pseudo-instruction

Remark 3.1
The value of register R3 will be 0x9299B0A4.

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 3. Assembly programming language 3.4 Load/Store Instructions

LDR pseudo-instruction

 Example 3.6 (LDR pseudo instruction)

Assume that we have the following addresses

GPIOA_BASE EQU 0x08000000

MODER EQU 0x00

Copy the value at the address GPIOA BASE+MODER into register R1.

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 3. Assembly programming language 3.4 Load/Store Instructions

LDR pseudo-instruction

Solution:

Code 3.6 (LDR pseudo instruction)

GPIOA_BASE EQU 0x08000000

MODER EQU 0x00

Stack_Size EQU 0x00000400

AREA STACK,NOINIT,READWRITE,ALIGN=3

Stack_Mem SPACE Stack_Size

AREA RESET,DATA, READONLY

EXPORT __Vectors

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 3. Assembly programming language 3.4 Load/Store Instructions

LDR pseudo-instruction

__Vectors
DCD Stack_Mem+Stack_Size
DCD Reset_Handler
ALIGN

AREA |.text|, CODE, READONLY, ALIGN=2

THUMB
ENTRY
EXPORT Reset_Handler
Reset_Handler
LDR R0,=GPIOA_BASE+MODER
LDR R1,[R0]
NOP

ALIGN
END

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 3. Assembly programming language 3.4 Load/Store Instructions

STR instruction

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 3. Assembly programming language 3.4 Load/Store Instructions

STR instruction
Syntax
STR{type}{cond} Rt, [Rn {, #offset}] ; immediate offset
STR{type}{cond} Rt, [Rn, #offset]! ; pre-indexed
STR{type}{cond} Rt, [Rn], #offset ; post-indexed
STRD{cond} Rt, Rt2, [Rn {, #offset}] ; immediate offset,
; doubleword
STRD{cond} Rt, Rt2, [Rn, #offset]! ; pre-indexed, doubleword
STRD{cond} Rt, Rt2, [Rn], #offset ; post-indexed, doubleword
where:
type can be any one of:
⋄ B: Byte.
⋄ H: Halfword.
⋄ -: omitted, for Word.
cond is an optional condition code.

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 3. Assembly programming language 3.4 Load/Store Instructions

STR instruction

Rt is the register to store.

Rn is the register on which the memory address is based.
offset is an offset. If offset is omitted, the address is the contents of Rn.
Rt2 is the additional register to store for doubleword operations.
Not all options are available in every instruction set and architecture.

Operation
Register → Memory.
Description
Store with immediate offset, pre-indexed immediate offset, or post-indexed imme-
diate offset.

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 3. Assembly programming language 3.4 Load/Store Instructions

STR instruction

 Example 3.7 (STR instruction)

Assume that we have the following data area started by

StoredData DCB 0x00

Copy the value of 0xF0C2E7A5 into this data area.

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 3. Assembly programming language 3.4 Load/Store Instructions

STR instruction

Solution:
Code 3.7 (STR instruction)

Stack_Size EQU 0x00000400

AREA STACK,NOINIT,READWRITE,ALIGN=3

Stack_Mem SPACE Stack_Size

AREA RESET,DATA, READONLY

EXPORT __Vectors
__Vectors
DCD Stack_Mem+Stack_Size
DCD Reset_Handler
ALIGN

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 3. Assembly programming language 3.4 Load/Store Instructions

STR instruction

AREA |.text|, CODE, READONLY, ALIGN=2

THUMB
ENTRY
EXPORT Reset_Handler
Reset_Handler
MOV R6,#2
LDR R2,=StoredData
MOV32 R3,#0xF0C2E7A5
STR R3,[R2]
NOP

AREA MyData,DATA, READWRITE, ALIGN=2

StoredData DCB 0x00

ALIGN
END
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 3. Assembly programming language 3.4 Load/Store Instructions

STR instruction

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 3. Assembly programming language 3.4 Load/Store Instructions

STR instruction

 Example 3.8 (STR instruction offset)

Assume that we have the following data area started by

StoredData DCB 0x00

Copy the value of 0xF0C2E7A5 into the StoredData with an offset of 2.

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 3. Assembly programming language 3.4 Load/Store Instructions

STR instruction

Solution:

Code 3.8 (STR instruction offset)

Reset_Handler
MOV R1,#2
LDR R2,=StoredData
MOV32 R3,#0xF0C2E7A5
STR R3,[R2,R1]
NOP

AREA MyData,DATA, READWRITE, ALIGN=2

StoredData DCB 0x00

ALIGN
END
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 3. Assembly programming language 3.4 Load/Store Instructions

STR instruction

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 3. Assembly programming language 3.4 Load/Store Instructions

Pre-indexed addressing

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 3. Assembly programming language 3.4 Load/Store Instructions

Pre-indexed addressing

 Example 3.9 (STR pre indexed)

Repeat Example 3.8 with pre-indexed addressing.

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 3. Assembly programming language 3.4 Load/Store Instructions

Pre-indexed addressing

Solution:

Code 3.9 (STR pre indexed)

Reset_Handler
LDR R2,=StoredData
MOV32 R3,#0xF0C2E7A5
STR R3,[R2,#2]!
NOP

AREA MyData,DATA, READWRITE, ALIGN=2

StoredData DCB 0x00

ALIGN
END

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 3. Assembly programming language 3.4 Load/Store Instructions

Pre-indexed addressing

The offset value 2 was added to the address specified by register R2 (address = R2 +
0x02 = 0x20000000 + 0x02 = 0x20000002). After the STR instruction was ex-
ecuted, the calculated address is written back into register R2 (R2 = 0x20000002).

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 3. Assembly programming language 3.4 Load/Store Instructions

Post-indexed addressing

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 3. Assembly programming language 3.4 Load/Store Instructions

Post-indexed addressing

 Example 3.10 (STR post indexed)

Repeat Example 3.8 with post-indexed addressing.

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 3. Assembly programming language 3.4 Load/Store Instructions

Post-indexed addressing

Solution:

Code 3.10 (STR post indexed)

Reset_Handler
LDR R2,=StoredData
MOV32 R3,#0xF0C2E7A5
STR R3,[R2],#2]
NOP

AREA MyData,DATA, READWRITE, ALIGN=2

StoredData DCB 0x00

ALIGN
END

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 3. Assembly programming language 3.4 Load/Store Instructions

Post-indexed addressing

The offset value 2 was not added to the address specified by register R2 (address
= R2 = 0x20000000). After the STR instruction was executed, the calculated
address is written back into register R2 (R2 = 0x20000002).

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 3. Assembly programming language 3.5 Arithmetic instructions

3.5 Arithmetic instructions

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 3. Assembly programming language 3.5 Arithmetic instructions

ADD instruction

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 3. Assembly programming language 3.5 Arithmetic instructions

ADD instruction
Syntax
ADD{S}{cond} {Rd}, Rn, Operand2
ADD{cond} {Rd}, Rn, #imm12 ; Thumb, 32-bit encoding only
where:
S is an optional suffix. If S is specified, the condition flags are updated on the
result of the operation.
cond is an optional condition code.
Rd is the destination register.
Rn is the register holding the first operand
Operand2 is a flexible second operand.
imm12 is any value in the range 0-4095.
Operation
Rd ← Rn + {Operand2} {imm12}.
Description
Add without Carry.
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 3. Assembly programming language 3.5 Arithmetic instructions

ADD instruction
Status bits
If S is specified, these instructions update the N, Z, C and V flags according to the
result.

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 3. Assembly programming language 3.5 Arithmetic instructions

ADD instruction

 Example 3.11 (ADD instruction)

Let R1 = 0xE0F50000, R2 = 0x60D30000, and R3 = 0x79A70000. Calculate the

sum of registers R1, R2, R3 and store the result into register R1 by using ADD
instructions and check the Carry.

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 3. Assembly programming language 3.5 Arithmetic instructions

ADD instruction

Solution:

Code 3.11 (ADD instruction)

Reset_Handler
MOVT R1,#0xE0F5
MOVT R2,#0x60D3
MOVT R3,#0x79A7
ADD R1,R2
ADD R1,R3
NOP

The obtained result is R1=0xCC6F0000.

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 3. Assembly programming language 3.5 Arithmetic instructions

ADD instruction

 Example 3.12 (ADDS instruction)

Repeat Example 3.11 but using ADDS instructions.

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 3. Assembly programming language 3.5 Arithmetic instructions

ADD instruction

Solution:

Code 3.12 (ADDS instruction)

Reset_Handler
Reset_Handler
MOVT R1,#0xE0F5
MOVT R2,#0x60D3
MOVT R3,#0x79A7
ADDS R1,R2
ADDS R1,R3
NOP

The obtained result is R1=0xCC6F0000.

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 3. Assembly programming language 3.5 Arithmetic instructions

ADC instruction

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 3. Assembly programming language 3.5 Arithmetic instructions

ADC instruction
Syntax
ADC{S}{cond} {Rd}, Rn, Operand2
where:
S is an optional suffix. If S is specified, the condition flags are updated on the
result of the operation.
cond is an optional condition code.
Rd is the destination register.
Rn is the register holding the first operand
Operand2 is a flexible second operand.
Operation
Rd ← Rn + Operand2 + Carry.
Description
Add with Carry.

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 3. Assembly programming language 3.5 Arithmetic instructions

ADC instruction

 Example 3.13
Repeat Example 3.11 but using ADCS instructions and compare the results.

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 3. Assembly programming language 3.5 Arithmetic instructions

ADC instruction

Solution:

Code 3.13 (ADCS instruction)

Reset_Handler
MOVT R1,#0xE0F5
MOVT R2,#0x60D3
MOVT R3,#0x79A7
ADCS R1,R2
ADCS R1,R3
NOP

The obtained result is R1=0xCC6F0001.

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 3. Assembly programming language 3.5 Arithmetic instructions

SUB instruction

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 3. Assembly programming language 3.5 Arithmetic instructions

SUB instruction
Syntax
SUB{S}{cond} {Rd}, Rn, Operand2
SUB{cond} {Rd}, Rn, #imm12 ; Thumb, 32-bit encoding only
where:
S is an optional suffix. If S is specified, the condition flags are updated on the
result of the operation.
cond is an optional condition code.
Rd is the destination register.
Rn is the register holding the first operand
Operand2 is a flexible second operand.
imm12 is any value in the range 0-4095.
Operation
Rd ← Rn - Operand2.
Description
Subtract without carry.
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 3. Assembly programming language 3.5 Arithmetic instructions

 Example 3.14
Let R1 = 0xE0F5. Calculate the subtraction R1-1 and store the result back into
register R1.

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 3. Assembly programming language 3.5 Arithmetic instructions

SUB instruction

Solution:

Code 3.14 (SUB instruction)

Reset_Handler
MOV R1,#0xE0F5
SUBS R1,R1,#1 ; R1--
NOP

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 3. Assembly programming language 3.5 Arithmetic instructions

 Example 3.15 (Practice)

Calculate Y = (0xE0F5 + 0x765C) - (0x827F + 0x123A) using core registers
and store the result into register R1.

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 3. Assembly programming language 3.5 Arithmetic instructions

SUB instruction

Solution:

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 3. Assembly programming language 3.5 Arithmetic instructions

MUL instruction

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 3. Assembly programming language 3.5 Arithmetic instructions

MUL instruction
Syntax
MUL{S}{cond} {Rd}, Rn, Rm
where:
S is an optional suffix. If S is specified, the condition flags are updated on the
result of the operation.
cond is an optional condition code.
Rd is the destination register.
Rn, Rm are registers holding the values to be multiplied.
Operation
Rd ← Rn × Rm.
Description
Multiply with signed or unsigned 32-bit operands, giving the least significant 32 bits
of the result

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 3. Assembly programming language 3.5 Arithmetic instructions

MUL instruction

 Example 3.16
Calculate Y = 0xE0F5 × 0x765C using core registers and store the result into
register R1.

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 3. Assembly programming language 3.5 Arithmetic instructions

MUL instruction

Solution:
Code 3.15 (MUL instruction)

Reset_Handler
MOV R1,#0xE0F5
MOV R2,#0x765C
MUL R1,R1,R2 ; R1 = R1 * R2
NOP

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 3. Assembly programming language 3.5 Arithmetic instructions

MUL instruction

 Example 3.17 (Practice)

Calculate Y = 0xE0F50000 - (0x827F × 0x123A) using core registers and store
the result into register R1.

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 3. Assembly programming language 3.5 Arithmetic instructions

MUL instruction

Solution:

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 3. Assembly programming language 3.5 Arithmetic instructions

UDIV instruction

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 3. Assembly programming language 3.5 Arithmetic instructions

UDIV instruction
Syntax
UDIV{cond} {Rd}, Rn, Rm
where:
cond is an optional condition code.
Rd is the destination register.
Rn is the register holding the value to be divided.
Rm is a register holding the divisor.
Operation
Rd ← Rn / Rm.
Description
Unsigned divide.

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 3. Assembly programming language 3.5 Arithmetic instructions

UDIV instruction

 Example 3.18
Calculate Y = 0xE0F5239B / 0x765C using core registers and store the result into
register R1.

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 3. Assembly programming language 3.5 Arithmetic instructions

UDIV instruction

Solution:

Code 3.16 (UDIV instruction)

Reset_Handler
MOV32 R1,#0xE0F5239B
MOV R2,#0x765C
UDIV R1,R1,R2 ; R1 = R1/R2
NOP

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 3. Assembly programming language 3.5 Arithmetic instructions

UDIV instruction

 Example 3.19 (Practice)

Calculate Y = 0xE0F5239B / 0x765C using core registers, store the result into
register R1 and the redundant into register R2.

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 3. Assembly programming language 3.5 Arithmetic instructions

UDIV instruction

Solution:

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 3. Assembly programming language 3.5 Arithmetic instructions

SDIV instruction

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 3. Assembly programming language 3.5 Arithmetic instructions

SDIV instruction
Syntax
SDIV{cond} {Rd}, Rn, Rm
where:
cond is an optional condition code.
Rd is the destination register.
Rn is the register holding the value to be divided.
Rm is a register holding the divisor.
Operation
Rd ← Rn / Rm.
Description
Signed divide.
Status flags
The condition flags are not affected.
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 3. Assembly programming language 3.5 Arithmetic instructions

SDIV instruction
Overflow
If the signed integer division 0x80000000/0xFFFFFFFF is performed, the pseu-
docode produces the intermediate integer result +231 , that overflows the 32-bit
signed integer range. No indication of this overflow case is produced, and the 32-
bit result written to Rd must be the bottom 32 bits of the binary representation of
+231 . So the result of the division is 0x80000000.

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 3. Assembly programming language 3.6 Logical instructions

3.6 Logical instructions

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 3. Assembly programming language 3.6 Logical instructions

MVN instruction

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 3. Assembly programming language 3.6 Logical instructions

MVN instruction
Syntax
MVN{S}{cond} Rd, Operand2
where:
S is an optional suffix. If S is specified, the condition flags are updated on the
result of the operation.
cond is an optional condition code.
Rd is the destination register.
Operand2 is a flexible second operand.
Operation
Rd ← Bitwise NOT Operand2.
Description
The MVN instruction takes the value of Operand2, performs a bitwise logical NOT
operation on the value, and places the result into Rd.

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 3. Assembly programming language 3.6 Logical instructions

MVN instruction

 Example 3.20
Let R1 = 0xE0F5. Invert bits of register R1.

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 3. Assembly programming language 3.6 Logical instructions

MVN instruction

Solution:

Code 3.17 (MVN instruction)

Reset_Handler
MOV R1,#0xE0F5
MVN R1,R1
NOP

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 3. Assembly programming language 3.6 Logical instructions

MVN instruction
We have

R1 = 0000 0000 0000 0000 1110 0000 1111 0101 = 0x0000E0F5

NOT R1 = 1111 1111 1111 1111 0001 1111 0000 1010 = 0xFFFF1F0A

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 3. Assembly programming language 3.6 Logical instructions

MVN instruction

 Example 3.21 (Practice)

Assume that the value of register R1 represents a negative number in TCR as R1
= 0xFFFFFFFB. Find the absolute value of register R1.

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 3. Assembly programming language 3.6 Logical instructions

MVN instruction

Solution:

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 3. Assembly programming language 3.6 Logical instructions

AND instruction

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 3. Assembly programming language 3.6 Logical instructions

AND instruction
Syntax
AND{S}{cond} Rd, Rn, Operand2
where:
S is an optional suffix. If S is specified, the condition flags are updated on the
result of the operation.
cond is an optional condition code.
Rd is the destination register.
Rn is the register holding the first operand.
Operand2 is a flexible second operand.
Operation
Rd ← Rn AND Operand2.
Description
Logical AND.

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 3. Assembly programming language 3.6 Logical instructions

AND instruction

 Example 3.22
Let R1 = 0xE0F5 and R2 = 0x765C. Calculate (R1 AND R2) and store the result
into register R3.

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 3. Assembly programming language 3.6 Logical instructions

AND instruction

Solution:

Code 3.18 (AND instruction)

Reset_Handler
MOV R1,#0xE0F5
MOV R2,#0x765C
AND R3,R1,R2 ; R3 = R1 AND R
NOP

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 3. Assembly programming language 3.6 Logical instructions

AND instruction
We have

R1 = 1110 0000 1111 0101 = 0xE0F5

R2 = 0111 0110 0101 1100 = 0x765C
---------------------
R1 AND R2 = 0110 0000 0101 0100 = 0x6054

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 3. Assembly programming language 3.6 Logical instructions

AND instruction

 Example 3.23
Let R1 = 0xE0F5. Reset bit 5th of register R1.

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 3. Assembly programming language 3.6 Logical instructions

AND instruction

Solution:

Code 3.19 (AND instruction one bit)

Reset_Handler
MOV R1,#0xE0F5
MOV R2,#0xFFDF
AND R1,R1,R2
NOP

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 3. Assembly programming language 3.6 Logical instructions

AND instruction
We have

R1 = 1110 0000 1111 0101 = 0xE0F5

R2 = 1111 1111 1101 1111 = 0xFFDF
---------------------
R1 AND R2 = 1110 0000 1101 0101 = 0xE0D5

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 3. Assembly programming language 3.6 Logical instructions

AND instruction

 Example 3.24 (Practice)

Let R1 = 0xE0F5. Reset bits 7th and 14th of register R1.

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 3. Assembly programming language 3.6 Logical instructions

AND instruction

Solution:

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 3. Assembly programming language 3.6 Logical instructions

ORR instruction

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 3. Assembly programming language 3.6 Logical instructions

ORR instruction
Syntax
ORR{S}{cond} Rd, Rn, Operand2
where:
S is an optional suffix. If S is specified, the condition flags are updated on the
result of the operation.
cond is an optional condition code.
Rd is the destination register.
Rn is the register holding the first operand.
Operand2 is a flexible second operand.
Operation
Rd ← Rn OR Operand2.
Description
Logical OR.

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 3. Assembly programming language 3.6 Logical instructions

ORR instruction

 Example 3.25
Let R1 = 0xE0F5 and R2 = 0x765C. Calculate (R1 OR R2) and store the result
into register R3.

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 3. Assembly programming language 3.6 Logical instructions

ORR instruction

Solution:

Code 3.20 (ORR instruction)

Reset_Handler
MOV R1,#0xE0F5
MOV R2,#0x765C
ORR R3,R1,R2 ; R3 = R1 OR R2
NOP

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 3. Assembly programming language 3.6 Logical instructions

ORR instruction
We have

R1 = 1110 0000 1111 0101 = 0xE0F5

R2 = 0111 0110 0101 1100 = 0x765C
---------------------
R1 ORR R2 = 1111 0110 1111 1101 = 0xF6FD

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 3. Assembly programming language 3.6 Logical instructions

ORR instruction

 Example 3.26
Let R1 = 0xE0F5. Set bit 10th of register R1.

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 3. Assembly programming language 3.6 Logical instructions

ORR instruction

Solution:
Code 3.21 (ORR instruction one bit)

Reset_Handler
MOV R1,#0xE0F5
MOV R2,#0x0400
ORR R3,R1,R2
NOP

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 3. Assembly programming language 3.6 Logical instructions

ORR instruction
We have

R1 = 1110 0000 1111 0101 = 0xE0F5

R2 = 0000 0100 0000 0000 = 0x0400
---------------------
R1 ORR R2 = 1110 0100 1111 0101 = 0xE4F5

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 3. Assembly programming language 3.6 Logical instructions

ORR instruction

 Example 3.27 (Practice)

Let R1 = 0xE0F5. Set bits 2nd and 12th of register R1.

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 3. Assembly programming language 3.6 Logical instructions

ORR instruction

Solution:

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 3. Assembly programming language 3.6 Logical instructions

BIC instruction

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 3. Assembly programming language 3.6 Logical instructions

BIC instruction
Syntax
BIC{S}{cond} Rd, Rn, Operand2
where:
S is an optional suffix. If S is specified, the condition flags are updated on the
result of the operation.
cond is an optional condition code.
Rd is the destination register.
Rn is the register holding the first operand.
Operand2 is a flexible second operand.
Operation
Rd ← Rn AND NOT Operand2.
Description
Bitwise clear.

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 3. Assembly programming language 3.6 Logical instructions

BIC instruction

 Example 3.28
Let R1 = 0xE0F5. Clear bits 6th and 15th of register R1.

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 3. Assembly programming language 3.6 Logical instructions

BIC instruction

Solution:

Code 3.22 (BIC instruction)

Reset_Handler
MOV R1,#0xE0F5
MOV R2,#0x8040
BIC R1,R2
NOP

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 3. Assembly programming language 3.6 Logical instructions

BIC instruction
We have

R1 = 1110 0000 1111 0101 = 0xE0F5

R2 = 1000 0000 0100 0000 = 0x8040
---------------------
R1 BIC R2 = 0110 0000 1011 0101 = 0x60B5

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 3. Assembly programming language 3.6 Logical instructions

BIC instruction

 Example 3.29 (Practice)

Let R1 = 0xC2D8E0F5. Clear most and least significant bytes of register R1.

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 3. Assembly programming language 3.6 Logical instructions

BIC instruction

Solution:

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 3. Assembly programming language 3.6 Logical instructions

BIC instruction
We have

R1 = 1100 0010 1101 1000 1110 0000 1111 0101 = 0xC2D8E0

R2 = 1111 1111 0000 0000 0000 0000 1111 1111 = 0xFF0000
-----------------------------------------
R1 BIC R2 = 0000 0000 1101 1000 1110 0000 0000 0000 = 0x00D8E0

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 3. Assembly programming language 3.6 Logical instructions

EOR instruction

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 3. Assembly programming language 3.6 Logical instructions

EOR instruction
Syntax
EOR{S}{cond} Rd, Rn, Operand2
where:
S is an optional suffix. If S is specified, the condition flags are updated on the
result of the operation.
cond is an optional condition code.
Rd is the destination register.
Rn is the register holding the first operand.
Operand2 is a flexible second operand.
Operation
Rd ← Rn EOR Operand2.
Description
Logical Exclusive OR.

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 3. Assembly programming language 3.6 Logical instructions

EOR instruction

 Example 3.30
Let R1 = 0xE0F5 and R2 = 0x765C. Calculate (R1 EOR R2) and store the result
into register R3.

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 3. Assembly programming language 3.6 Logical instructions

EOR instruction

Solution:
Code 3.23 (EOR instruction)

Reset_Handler
MOV R1,#0xE0F5
MOV R2,#0x765C
ORR R3,R1,R2 ; R3 = R1 OR R2
NOP

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 3. Assembly programming language 3.6 Logical instructions

EOR instruction
We have

R1 = 1110 0000 1111 0101 = 0xE0F5

R2 = 0111 0110 0101 1100 = 0x765C
---------------------
R1 EOR R2 = 1001 0110 1010 1001 = 0x96A9

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 3. Assembly programming language 3.6 Logical instructions

EOR instruction

 Example 3.31
Let R1 = 0xE0F5. Toggle bits 4th and 9th of register R1.

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 3. Assembly programming language 3.6 Logical instructions

EOR instruction

Solution:
Code 3.24 (EOR instruction toggle bits)

Reset_Handler
MOV R1,#0xE0F5
MOV R2,#0x0210
EOR R3,R1,R2
NOP

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 3. Assembly programming language 3.6 Logical instructions

EOR instruction
We have

R1 = 1110 0000 1111 0101 = 0xE0F5

R2 = 0000 0010 0001 0000 = 0x0210
---------------------
R1 EOR R2 = 1110 0010 1110 0101 = 0xE2E5

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 3. Assembly programming language 3.6 Logical instructions

EOR instruction

 Example 3.32 (Practice)

Let R1 = 0xE0F5. Toggle the least significant byte of register R1.

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 3. Assembly programming language 3.6 Logical instructions

EOR instruction

Solution:

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 3. Assembly programming language 3.7 Shift and rotating instructions

3.7 Shift and rotating instructions

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 3. Assembly programming language 3.7 Shift and rotating instructions

LSL instruction

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 3. Assembly programming language 3.7 Shift and rotating instructions

LSL instruction
Syntax

LSL{S}{cond} Rd, Rm, Rs

LSL{S}{cond} Rd, Rm, #sh

where:
S is an optional suffix. If S is specified, the condition flags are updated on the
result of the operation.
Rd is the destination register.
Rm is the register holding the first operand. This operand is shifted left.
Rs is a register holding a shift value to apply to the value in Rm. Only the
least significant byte is used.
sh is a constant shift. The range of values permitted is 0-31.

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 3. Assembly programming language 3.7 Shift and rotating instructions

LSL instruction
Operation

C ...

Description
LSL provides the value of a register multiplied by a power of two, inserting zeros
into the vacated bit positions.

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 3. Assembly programming language 3.7 Shift and rotating instructions

LSL instruction

 Example 3.33
Let R1 = 0x617EC3A8. Specify the value of register R1 as well as the Carry after
the following code is executed
LSLS R1,#3
and check the result.

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 3. Assembly programming language 3.7 Shift and rotating instructions

LSL instructions

Solution:
Code 3.25 (LSL instruction)

Reset_Handler
MOV32 R1,#0x617EC3A8
LSLS R1,R1,#3
NOP

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 3. Assembly programming language 3.7 Shift and rotating instructions

LSL instruction
Shifting left register R1 by 3 bits.

Carry
x 0 1 1 0 0 0 0 1 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0

... ...
0 0 0

1 0 0 0 0 1 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0 0 0 0
Carry

Finally, we get R1 = 00001011 11110110 00011101 01000000 = 0x0BF61D40.

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 3. Assembly programming language 3.7 Shift and rotating instructions

LSR instruction

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 3. Assembly programming language 3.7 Shift and rotating instructions

LSR instruction
Syntax

LSR{S}{cond} Rd, Rm, Rs

LSR{S}{cond} Rd, Rm, #sh

where:
S is an optional suffix. If S is specified, the condition flags are updated on the
result of the operation.
Rd is the destination register.
Rm is the register holding the first operand. This operand is shifted left.
Rs is a register holding a shift value to apply to the value in Rm. Only the
least significant byte is used.
sh is a constant shift. The range of values permitted is 0-31.

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 3. Assembly programming language 3.7 Shift and rotating instructions

LSR instruction
Operation

C ...

Description
LSR provides the unsigned value of a register divided by a variable power of two,
inserting zeros into the vacated bit positions.

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 3. Assembly programming language 3.7 Shift and rotating instructions

LSR instruction

 Example 3.34
Let R1 = 0x617EC3A8. Specify the value of register R1 as well as the Carry after
the following code is executed
LSRS R1,#6
and check the result.

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 3. Assembly programming language 3.7 Shift and rotating instructions

LSR instructions

Solution:

Code 3.26 (LSR instruction)

Reset_Handler
MOV32 R1,#0x617EC3A8
LSRS R1,R1,#6
NOP

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 3. Assembly programming language 3.7 Shift and rotating instructions

LSR instruction
Shifting right register R1 by 6 bits.

Carry
x 0 1 1 0 0 0 0 1 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0

... ...

0 0 0 0 0 0

1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1 1 1 0
Carry

Finally, we get R1 = 00000001 10000101 11111011 00001110 = 0x0185 FB0E.

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 3. Assembly programming language 3.7 Shift and rotating instructions

ASR instruction

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 3. Assembly programming language 3.7 Shift and rotating instructions

ASR instruction
Syntax

ASR{S}{cond} Rd, Rm, Rs

ASR{S}{cond} Rd, Rm, #sh

where:
S is an optional suffix. If S is specified, the condition flags are updated on the
result of the operation.
Rd is the destination register.
Rm is the register holding the first operand. This operand is shifted left.
Rs is a register holding a shift value to apply to the value in Rm. Only the
least significant byte is used.
sh is a constant shift. The range of values permitted is 0-31.

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 3. Assembly programming language 3.7 Shift and rotating instructions

ASR instruction
Operation

C ...

Description
Arithmetic shift right by n bits moves the left-hand 32-n bits of a register to the
right by n places, into the right-hand 32-n bits of the result. It copies the original
bit[31] of the register into the left-hand n bits of the result.

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 3. Assembly programming language 3.7 Shift and rotating instructions

ASR instruction

 Example 3.35
Let R1 = 0xB17EC3A8. Specify the value of register R1 as well as the Carry after
the following code is executed
ASRS R1,#4
and check the result.

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 3. Assembly programming language 3.7 Shift and rotating instructions

ASR instruction

Solution:

Code 3.27 (ASR instruction)

Reset_Handler
MOV32 R1,#0xB17EC3A8
ASRS R1,R1,#4
NOP

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 3. Assembly programming language 3.7 Shift and rotating instructions

ASR instruction
Arithmetic shift right register R1 by 4 bits.

Carry
x 1 0 1 1 0 0 0 1 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1 1 1 0 1 0 1 0 0 0

... ...

1 1 1 1 1 1 0 1 1 0 0 0 1 0 1 1 1 1 1 1 0 1 1 0 0 0 0 1 1 1 0 1 0
Carry

Finally, we get R1 = 11111011 00010111 11101100 00111010 = 0xFB17 EC3A.

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 3. Assembly programming language 3.7 Shift and rotating instructions

ROR instruction

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 3. Assembly programming language 3.7 Shift and rotating instructions

ROR instruction
Syntax

ROR{S}{cond} Rd, Rm, Rs

ROR{S}{cond} Rd, Rm, #sh

where:
S is an optional suffix. If S is specified, the condition flags are updated on the
result of the operation.
Rd is the destination register.
Rm is the register holding the first operand. This operand is shifted left.
Rs is a register holding a shift value to apply to the value in Rm. Only the
least significant byte is used.
sh is a constant shift. The range of values permitted is 0-31.

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 3. Assembly programming language 3.7 Shift and rotating instructions

ROR instruction
Operation

C ...

Description
Rotate right by n bits moves the left-hand 32-n bits of a register to the right by n
places, into the right-hand 32-n bits of the result. It also moves the right-hand n
bits of the register into the left-hand n bits of the result.

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 3. Assembly programming language 3.7 Shift and rotating instructions

ROR instruction

 Example 3.36
Let R1 = 0xB17EC3A8. Swap the two high bytes for the two low bytes and check
the result.

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 3. Assembly programming language 3.7 Shift and rotating instructions

ROR instruction

Solution:

Code 3.28 (ROR instruction)

Reset_Handler
MOV32 R1,#0xB17EC3A8
RORS R1,R1,#16
NOP

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 3. Assembly programming language 3.7 Shift and rotating instructions

ROR instruction
We obtain R1 = 11000011 10101000 10110001 01111110 = 0xC3A8 B17E.

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 3. Assembly programming language 3.8 Compare instructions

3.8 Compare instructions

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 3. Assembly programming language 3.8 Compare instructions

CMP and CMN instructions

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 3. Assembly programming language 3.8 Compare instructions

CMP and CMN instructions

Syntax

CMP{cond} Rn, Operand2

CMN{cond} Rn, Operand2

where:
cond is an optional condition code.
Rn is the register holding the first operand.
Operand2 is a flexible second operand.

Operation
CMP instruction: Condition flags are updated on the result of (Rn - Operand2).
CMN instruction: Condition flags are updated on the result of (Rn + Operand2).
Description
These instructions compare the value in a register with Operand2. They update
the condition flags on the result, but do not place the result in any register.
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 3. Assembly programming language 3.8 Compare instructions

CMP and CMN instructions

Condition flags
These instructions update the N, Z, C and V flags according to the result.

Remark 3.2
The CMP instruction is the same as a SUBS instruction, except that the result is
discarded.
The CMN instruction is the same as an ADDS instruction, except that the result is
discarded.

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 3. Assembly programming language 3.8 Compare instructions

CMP and CMN instructions

 Example 3.37
Let R1 = 0xE0F5 and R2 = 0x765C. Compare R1 with R2 using CMP and CMN
instructions and check the results.

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 3. Assembly programming language 3.8 Compare instructions

CMP and CMN instructions

Solution:

Code 3.29 (CMP CMN instructions)

Reset_Handler
MOV R1,#0xE0F5
MOV R2,#0x765C
CMP R1,R2
CMN R1,R2
NOP

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 3. Assembly programming language 3.8 Compare instructions

TST and TEQ instructions

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 3. Assembly programming language 3.8 Compare instructions

TST and TEQ instructions

Syntax

TST{cond} Rn, Operand2

TEQ{cond} Rn, Operand2

where:
cond is an optional condition code.
Rn is the register holding the first operand.
Operand2 is a flexible second operand.

Operation
Condition flags are updated on the result of testing the value in a register against
Operand2.
Description
The TST instruction performs a bitwise AND operation on the value in Rn and the
value of Operand2. This is the same as an ANDS instruction, except that the result
is discarded.
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 3. Assembly programming language 3.8 Compare instructions

TST and TEQ instructions

The TEQ instruction performs a bitwise EOR operation on the value in Rn and the
value of Operand2. This is the same as an EORS instruction, except that the result
is discarded.
Condition flags
These instructions update the N and Z flags according to the result but they do
not affect the V flag.

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 3. Assembly programming language 3.9 Conditional instructions

3.9 Conditional instructions

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 3. Assembly programming language 3.9 Conditional instructions

Condition codes

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 3. Assembly programming language 3.9 Conditional instructions

Condition codes
ARM instructions can be executed conditionally by appending a two letter suffix to
the mnemonic. Almost all ARM instructions can be done this way.

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 3. Assembly programming language 3.9 Conditional instructions

Condition codes
Codes Suffix Flags Meaning
0000 EQ Z set Equal
0001 NE Z clear Not equal
0010 CS or HS C set Higher or same (unsigned >= )
0011 CC or LO C clear Lower (unsigned < )
0100 MI N set Negative
0101 PL N clear Positive or zero
0110 VS V set Overflow
0111 VC V clear No overflow
1000 HI C set and Z clear Higher (unsigned >)
1001 LS C clear or Z set Lower or same (unsigned <=)
1010 GE N and V the same Signed >=
1011 LT N and V differ Signed <
1100 GT Z clear, N and V the same Signed >
1101 LE Z set, N and V differ Signed <=
1110 AL Any Always (normally omitted)

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 3. Assembly programming language 3.10 Flow control instructions

3.10 Flow control instructions

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 3. Assembly programming language 3.10 Flow control instructions

B instruction

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 3. Assembly programming language 3.10 Flow control instructions

B instruction
Syntax

B{cond}{.W} label

where:
cond is an optional condition code.
.W is an optional instruction width specifier to force the use of a 32-bit B
instruction in Thumb.
label is a PC-relative expression.

Operation
PC ← [label]
Description
The B instruction causes a branch to label.

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 3. Assembly programming language 3.10 Flow control instructions

B instruction
Condition flags
The B instruction does not change the flags.

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 3. Assembly programming language 3.10 Flow control instructions

B instruction

 Example 3.38
5
X
Calculate Y = n
n=1

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 3. Assembly programming language 3.10 Flow control instructions

B instruction

Solution:
Code 3.30 (B instructions)

Reset_Handler
MOV R1,#1
MOV R2,#0
Loop
ADD R2,R2,R1
ADD R1,R1,#1
CMP R1,#5
BLE Loop
Stop
B Stop

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 3. Assembly programming language 3.10 Flow control instructions

B instruction

Remark 3.3
In Program 3.30, we can see that the instructions in the block

Loop
...

BLE Loop

are iterated 5 times. Since we know in advance these instructions should be executed
how many times, the block of instructions like this is called a counting or for loop.

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 3. Assembly programming language 3.10 Flow control instructions

B instruction

 Example 3.39 (Practice)

Let R1, R2 contain arbitrary values. Find the maximum value of R1 and R2. Store
the maximum value into R3.

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 3. Assembly programming language 3.10 Flow control instructions

B instruction

Solution:

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 3. Assembly programming language 3.10 Flow control instructions

B instruction

 Example 3.40 (Practice)

Find the factorial of 5 and store the result into R0.

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 3. Assembly programming language 3.10 Flow control instructions

B instruction

Solution:

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 3. Assembly programming language 3.10 Flow control instructions

B instruction

 Example 3.41 (Practice)

Assume there exist 8 bytes of memory named SumData that is declared as

SumData DCB 0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8

Find the sum of all these bytes and store the result into register R0.

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 3. Assembly programming language 3.10 Flow control instructions

B instruction

Solution:

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 3. Assembly programming language 3.10 Flow control instructions

BL instruction

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 3. Assembly programming language 3.10 Flow control instructions

BL instruction
Syntax

BL{cond}{.W} label

where:
cond is an optional condition code.
.W is an optional instruction width specifier to force the use of a 32-bit B
instruction in Thumb.
label is a PC-relative expression.

Operation
PC ← [label]
Description
The BL instruction causes a branch to label, and copies the address of the next
instruction into LR (R14, the link register).

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 3. Assembly programming language 3.10 Flow control instructions

BL instruction
Condition flags
The BL instruction does not change the flags.

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 3. Assembly programming language 3.10 Flow control instructions

BX instruction

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 3. Assembly programming language 3.10 Flow control instructions

BX instruction
Syntax

BX{cond} Rm

where:
cond is an optional condition code (cond is not available on all forms of this
instruction).
Rm is a register containing an address to branch to.

Operation
PC ← [Rm]
Description
The BX instruction causes a branch to the address contained in Rm and exchanges
the instruction set.

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 3. Assembly programming language 3.10 Flow control instructions

BX instruction
Condition flags
The BX instruction does not change the flags.

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 3. Assembly programming language 3.10 Flow control instructions

BX instruction

 Example 3.42
Let R1, R2, R3, R4 contain arbitrary values. Store the maximum value of R1 and
R2 into R1 and store the maximum value of R3 and R4 into R3.

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 3. Assembly programming language 3.10 Flow control instructions

BX instruction

Solution:
Code 3.31 (FindMaxSubroutine)

Reset_Handler
MOV32 R1,#0xB17EC3A7
MOV32 R2,#0xB17EC3A8
MOV32 R3,#0x706892AF
MOV32 R4,#0x706892AE

MOV R5,R1
MOV R6,R2
BL FindMax
MOV R1,R5

MOV R5,R3
MOV R6,R4

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 3. Assembly programming language 3.10 Flow control instructions

BX instruction

BL FindMax
MOV R3,R5
Stop
B Stop
FindMax
CMP R5,R6
BLT MaxR6
BX LR
MaxR6
MOV R5,R6
BX LR

ALIGN
END

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 3. Assembly programming language 3.10 Flow control instructions

BX instruction

Remark 3.4 (Subroutine)

Note that in the following code

BL FindMax

...

FindMax
...

BX LR

the FindMax, which includes a sequence of instructions, is called a subroutine. It

can also be called a procedure or a function... in other programming languages.

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 3. Assembly programming language 3.10 Flow control instructions

BX instruction

The instruction
BL FindMax
is a call to execute the sub-routine named FindMax.
The instruction
BX LR
causes a branch to the address contained in link register LR (R14).
By decomposing a program into subroutines, the codes can be restated within the
program or reused by other programmers. Thus, it helps to reduce the cost of
developing and maintaining the program.

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 3. Assembly programming language 3.10 Flow control instructions

BX instruction

 Example 3.43 (Practice)

Find the factorials of 5 and 10. Store the obtained results into R0 and R1.

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 3. Assembly programming language 3.10 Flow control instructions

BX instruction

Solution:

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 3. Assembly programming language 3.10 Flow control instructions

BX instruction

FindFactorial
MUL R2,R2,R3
ADD R3,#1
CMP R3,R4
BHI Done
B FindFactorial

Done BX LR

ALIGN
END

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 3. Assembly programming language 3.11 Stack instructions

3.11 Stack instructions

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 3. Assembly programming language 3.11 Stack instructions

PUSH instruction

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 3. Assembly programming language 3.11 Stack instructions

PUSH instruction
Syntax

PUSH{cond} reglist

where:
cond is an optional condition code (cond is not available on all forms of this
instruction).
reglist is a non-empty list of registers, enclosed in braces. It can contain
register ranges. It must be comma separated if it contains more than one
register or register range.

Description
Push registers onto a full descending stack.

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 3. Assembly programming language 3.11 Stack instructions

POP instruction

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 3. Assembly programming language 3.11 Stack instructions

POP instruction
Syntax

POP{cond} reglist

where:
cond is an optional condition code (cond is not available on all forms of this
instruction).
reglist is a non-empty list of registers, enclosed in braces. It can contain
register ranges. It must be comma separated if it contains more than one
register or register range.

Description
Pop registers off a full descending stack.

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 3. Assembly programming language 3.12 If-Then block

3.12 If-Then block

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 3. Assembly programming language 3.12 If-Then block

Flowchart symbols

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 3. Assembly programming language 3.12 If-Then block

Flowchart symbols
A flowchart consists of function blocks representing input/output data, execution
blocks, and condition checking. The direction of data movement is represented by
arrows.
Starting or
Oval
ending

Parallelogram Input/output

Rectangular Process

Diamond Condition

Flow direction
Line

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 3. Assembly programming language 3.12 If-Then block

Flowchart symbols
Note that the diamond block has 02 output arrows indicating the direction of the
processes corresponding to the test results. If the condition is true, it will be
indicated by a ”+” sign. Otherwise, if the condition is false, it will be indicated by
a ”-” sign.

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 3. Assembly programming language 3.12 If-Then block

Flowchart symbols
An example of a flow chart

Start

R1, R2

R1 = R1 - R2

R1 >= 0 -

max = R1 max = R2

End

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 3. Assembly programming language 3.12 If-Then block

IT block

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 3. Assembly programming language 3.12 If-Then block

IT block
Syntax

IT{x{y{z}}} {cond}

where:
x specifies the condition switch for the second instruction in the IT block.
y specifies the condition switch for the third instruction in the IT block.
z specifies the condition switch for the fourth instruction in the IT block.
cond specifies the condition for the first instruction in the IT block.
The condition switch for the second, third and fourth instruction in the IT
block can be either:
T Then. Applies the condition cond to the instruction.
E Else. Applies the inverse condition of cond to the instruction.

Description
The If-Then (IT) instruction.
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 3. Assembly programming language 3.12 If-Then block

IT block
Status flags
This instruction does not change the flags.

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 3. Assembly programming language 3.12 If-Then block

IT block

 Example 3.44
Assign the value of register R1 - R2 to register to register R3 if the value of register
R1 bigger than that of register R2. Otherwise, store the result of R1 + R2 to register
R3.

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 3. Assembly programming language 3.12 If-Then block

IT block

Solution:
Not using IT block

Code 3.32 (B instruction)

Reset_Handler
MOV R1,#5
MOV R2,#12
CMP R1,R2

BLT Result
SUB R3,R1,R2
B Stop
Result
ADD R3,R1,R2
Stop
B Stop
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 3. Assembly programming language 3.12 If-Then block

IT block
Using IT block

Code 3.33 (IT instruction)

Reset_Handler
MOV R1,#5
MOV R2,#12
CMP R1,R2

ITE GT
SUBGT R3,R1,R2
ADDLE R3,R1,R2
Stop
B Stop

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 3. Assembly programming language 3.12 If-Then block

IT block

 Example 3.45 (Practice)

Let R1, R2 contain arbitrary values. If R1 = R2, store R2 with the sum of R1 + R2
and let R1 = 1. Otherwise, let R2 = R1 - R2 and R1 = 0.

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 3. Assembly programming language 3.12 If-Then block

IT block

Solution:

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 3. Assembly programming language 3.13 Types of loop

3.13 Types of loop

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 3. Assembly programming language 3.13 Types of loop

Types of loop
In the context of programming, a process in which a set of instructions is executed
in a repeated manner is called a loop. The repetition of instructions is also called
iteration.
There are three major types of loops
For loop,
While loop,
and Do-while loop.

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 3. Assembly programming language 3.13 Types of loop

For loop

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 3. Assembly programming language 3.13 Types of loop

The for loop

Start

Condition
false
- End
Condition

Condition +
true
Set of
instructions

Increment/Decrement
a counter

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 3. Assembly programming language 3.13 Types of loop

3.13.1 While loop and Do-while loops

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 3. Assembly programming language 3.13 Types of loop

The while loop

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 3. Assembly programming language 3.13 Types of loop

The while loop

A sequence of instructions in which a block of codes is only executed while some
conditions are still true is called, as the name suggested, a while loop or pre-test
loop. When the conditions are no longer fulfilled, the next instructions after the
while loop will be executed. If the conditions are false at the beginning, there is not
any instruction in the block of codes executed and the block of codes is ignored.

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 3. Assembly programming language 3.13 Types of loop

The while loop

Start

Condition
false
Condition -
Condition +
true

Instruction block

End

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 3. Assembly programming language 3.13 Types of loop

The while loop

 Example 3.46
Suppose that there exist some bytes of memory named Array including zero that
is declared as

Array DCB 0xC0,0xF9,0xA4,0xB0,0x99,0x00,0x82,0xF8

Calculate the sum of the first non-zero bytes.

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 3. Assembly programming language 3.13 Types of loop

The while loop

Solution:
Code 3.34 (Non zero sum)

Reset_Handler
MOV R0,#0 ; Array index
MOV R1,#0 ; Sum
LDR R2,=Array
CalcSum
LDR R3,[R2,R0] ; Array elements
BIC R3,R3,#0xFFFFFF00

CMP R3,#0
BEQ Done
ADD R1,R1,R3
ADD R0,#1
B CalcSum

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 3. Assembly programming language 3.13 Types of loop

The while loop

Done
B Done

Array DCB 0xC0,0xF9,0xA4,0xB0,0x99,0x00,0x82,0xF8,0x

ALIGN
END

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 3. Assembly programming language 3.13 Types of loop

The Do-while loop

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 3. Assembly programming language 3.13 Types of loop

The Do-while loop

A sequence of instructions in which a block of codes is executed before checking
conditions is called a do-while loop or post-test loop. When the conditions are no
longer fulfilled, the next instructions after the do-while loop will be executed. Note
that, in comparison to the while loop, there is at least one instruction in the block
of codes executed even when the conditions are false at the first check.

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 3. Assembly programming language 3.13 Types of loop

The Do-while loop

Start

Instruction block

Condition
true
+
Condition

- Condition
false
End

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 3. Assembly programming language 3.13 Types of loop

The Do-while loop

 Example 3.47
Suppose that there exist some bytes of memory named Array including zero that
is declared as

Array DCB 0xC0,0xF9,0xA4,0xB0,0x99,0x00,0x82,0xF8

Calculate the sum of the bytes until a zero byte is reached.

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 3. Assembly programming language 3.13 Types of loop

The Do-while loop

Solution:
Code 3.35 (Non zero sum)

Reset_Handler
MOV R0,#0 ; Array index
MOV R1,#0 ; Sum
LDR R2,=Array
CalcSum
LDR R3,[R2,R0]
BIC R3,R3,#0xFFFFFF00
ADD R1,R1,R3
ADD R0,#1
CMP R3,#0
BEQ Done
B CalcSum

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 3. Assembly programming language 3.13 Types of loop

The Do-while loop

Done
B Done

Array DCB 0xC0,0xF9,0xA4,0xB0,0x99,0x00,0x82,0xF8,0x

ALIGN
END

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 3. Assembly programming language 3.14 Floating-point unit

3.14 Floating-point unit

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 3. Assembly programming language 3.14 Floating-point unit

FPU functional description

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 3. Assembly programming language 3.14 Floating-point unit

FPU functional description

The FPU fully supports single-precision add, subtract, multiply, divide, multiply and
accumulate, and square root operations. It also provides conversions between fixed-
point and floating-point data formats, and floating-point constant instructions.

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 3. Assembly programming language 3.14 Floating-point unit

FPU registers

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 3. Assembly programming language 3.14 Floating-point unit

FPU registers
The FPU provides an extension register file containing 32 single-precision registers.
These can be viewed as:
Sixteen 64-bit double-word registers, D0-D15.
Thirty-two 32-bit single-word registers, S0-S31.
A combination of registers from the above views.

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 3. Assembly programming language 3.14 Floating-point unit

FPU registers

S0
D0
S1
S2
D1
S3
S4
D2
S5
S6
D3
S7

S28
D14
S29
S30
D15
S31

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 3. Assembly programming language 3.14 Floating-point unit

Coprocessor access control register (FPCCR)

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 3. Assembly programming language 3.14 Floating-point unit

Coprocessor access control register (FPCCR)

Address: 0xE000ED88.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CP10
CP11
Reserved Reserved

r r r r

CPn[2n+1:2n](rw) for n values 10 and 11. Access privileges for coprocessor n. The
possible values of each field are:
0b00: Access denied. Any attempted access generates a NOCP UsageFault.
0b01: Privileged access only. An unprivileged access generates a NOCP fault.
0b10: Reserved. The result of any access is Unpredictable.
0b11: Full access.

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 3. Assembly programming language 3.14 Floating-point unit

Enabling the FPU

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 3. Assembly programming language 3.14 Floating-point unit

Enabling the FPU

The FPU is disabled from reset. You must enable it before you can use any floating-
point instructions.
The example shows an example code sequence for enabling the FPU in both privi-
leged and user modes. The processor must be in privileged mode to read from and
write to the CPACR.
Code 3.36 (Enabling the FPU)

; CPACR is located at address 0xE000ED88

LDR.W R0,=0xE000ED88
; Read CPACR
LDR R1,[R0]
; Set bits 20-23 to enable CP10 and CP11 coprocessors
ORR R1,R1,#(0xF<<20)
; Write back the modified value to the CPACR
STR R1,[R0]

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 3. Assembly programming language 3.14 Floating-point unit

3.14.1 More directives

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 3. Assembly programming language 3.14 Floating-point unit

DCFS and DCFSU directives

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 3. Assembly programming language 3.14 Floating-point unit

DCFS and DCFSU directives

Syntax

{label} DCFS{U} fpliteral{,fpliteral}...

where:
fpliteral is a single-precision floating-point literal.

Description
The DCFS directive allocates memory for word-aligned single-precision floating-point
numbers, and defines the initial runtime contents of the memory. DCFSU is the same,
except that the memory alignment is arbitrary.

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 3. Assembly programming language 3.14 Floating-point unit

DCFD and DCFDU directives

Syntax

{label} DCFD{U} fpliteral{,fpliteral}...

where:
fpliteral is a double-precision floating-point literal.

Description
The DCFD directive allocates memory for word-aligned double-precision floating-
point numbers, and defines the initial runtime contents of the memory. vebtDCFDU
is the same, except that the memory alignment is arbitrary.

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 3. Assembly programming language 3.14 Floating-point unit

3.14.2 Floating-point instruction set

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 3. Assembly programming language 3.14 Floating-point unit

Floating-point instruction syntax

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 3. Assembly programming language 3.14 Floating-point unit

Floating-point instruction syntax

V<operation>{<c>}{<q>}{.<dt>} {<dest>,} <src1>, <src2>

All floating-point instructions begin with a V. This distinguishes instructions in

the Floating-point instruction set from Thumb instructions.
< > any item bracketed by < and > is a short description of a type of value
to be supplied by the user in that position.
{ } any item bracketed by { and } is optional.
<c> is an optional field. It specifies the condition under which the instruction
is executed. If <c> is omitted, it defaults to always (AL).
<q> specifies optional assembler qualifiers on the instruction. The following
qualifiers are defined:
.N meaning narrow, specifies that the assembler must select a 16-bit encoding
for the instruction. If this is not possible, an assembler error is produced.
.W meaning wide, specifies that the assembler must select a 32-bit encoding for
the instruction. If this is not possible, an assembler error is produced.

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 3. Assembly programming language 3.14 Floating-point unit

Floating-point instruction syntax

The <dt> field normally contains one data type specifier. This indicates the
data type contained in
The second operand, if any.
The operand, if there is no second operand.
The result, if there are no operand registers.
The F32 data type can be abbreviated to F.
The F64 data type can be abbreviated to D.

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 3. Assembly programming language 3.14 Floating-point unit

Floating-point instruction syntax

The <dest>, <src1>, and <src2> fields contain register specifiers, or in some cases
register lists. If <dest> is omitted, it is the same as <src1>.
Specifier Usual meaning
<Dd> A double-precision destination register for the result.
<Dn> A double-precision source register for the first operand.
<Dm> A double-precision source register for the second operand.
<Sd> A single-precision destination register for the result.
<Sn> A single-precision source register for the first operand.
<Sm> A single-precision source register for the second operand.
<Rn> An ARM core register, used for an address.
<Rt> An ARM core register, used as a source or destination register.
<Rt2> An ARM core register, used as a source or destination register.

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 3. Assembly programming language 3.14 Floating-point unit

Frequently used FPU instructions

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 3. Assembly programming language 3.14 Floating-point unit

Frequently used FPU instructions

Syntax Operation Description

VABS.F32 Sd,Sm Sd ← |Sm| Absolute value
VADD.F32 Sd,Sn,Sm Sd ← Sn + Sm Addition
VCMP.F32 Sd,<Sm|#0.0> Sd - Sm or Sd - 0.0 and up- Compare
dates FPU flags
VCVT.type.F32 Sd ← Sm FP to integer
VCVT.F32.type Sd ← Sm Integer to FP
VDIV.F32 Sd,Sn,Sm Sd ← Sn/Sm Divide
VLDR.F32 <Dd|Sd>, [Rn] <Dd|Sd> ← [Rn] load from memory
VMOV.F32 Sd,<Sm|#imm> Sd ← <Sm|#imm> Move to float-
register
VMLA.F32 Sd,Sn,Sm Sd ← Sd + Sn × Sm Multiply and accu-
mulate
VMLS.F32 Sd,Sn,Sm Sd ← Sd - Sn × Sm Multiply and sub-
tract

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 3. Assembly programming language 3.14 Floating-point unit

Frequently used FPU instructions

Syntax Operation Description

VMUL.F32 Sd,Sn,Sm Sd ← Sn × Sm Multiply
VNEG.F32 Sd,Sm Sd ← - Sm Negate
VPOP.32 reglist reglist ← Stack Pop from the stack
VPUSH.32 reglist → Stack
reglist √ Push to the stack
VSQRT.F32 Sd,Sm Sd ← Rm Square root
VSTR.32 Sd,[Rn] Sd → [Rn] Store register
VSUB.F32 Sd,Sn,Sm Sd ← Sn - Sm Subtraction

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 3. Assembly programming language 3.14 Floating-point unit

Frequently used FPU instructions

 Example 3.48
Find the area of a circle with radius R = 20m.

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 3. Assembly programming language 3.14 Floating-point unit

Frequently used FPU instructions

Solution:

Code 3.37 (Circle area)

Reset_Handler
LDR R0,=0xE000ED88
LDR R1,[R0]
ORR R1,R1,#(0xF<<20)
STR r1,[R0] ; Enable FPU

LDR R0,=pi
VLDR.F S0,[R0]
LDR R0,=Radius
VLDR.F S1,[R0]

VMUL.F S2,S1,S1
VMUL.F S2,S2,S0
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 3. Assembly programming language 3.14 Floating-point unit

Frequently used FPU instructions

Stop
B Stop

pi DCFS 3.14159
Radius DCFS 20.0

ALIGN
END

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