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    Fully Integrated Frequency Synthesizers

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    Bhanu Partap Sharma
    This document discusses the design challenges of fully integrating frequency synthesizers onto a single chip. It covers different synthesizer architectures like phase-locked loops, delay-locked loops, and direct digital synthesis. Phase-locked loops are still widely used but have issues like on-chip inductors and noise. Fractional-N counters allow for better frequency resolution and noise performance than integer-N. Full integration reduces size and cost but introduces problems with noise coupling and compatibility with manufacturing processes.

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    Fully Integrated Frequency Synthesizers

    Uploaded by

    Bhanu Partap Sharma
    37 views37 pages
    This document discusses the design challenges of fully integrating frequency synthesizers onto a single chip. It covers different synthesizer architectures like phase-locked loops, delay-locked loops, and direct digital synthesis. Phase-locked loops are still widely used but have issues like on-chip inductors and noise. Fractional-N counters allow for better frequency resolution and noise performance than integer-N. Full integration reduces size and cost but introduces problems with noise coupling and compatibility with manufacturing processes.

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    cmosrf-1

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    This document discusses the design challenges of fully integrating frequency synthesizers onto a single chip. It covers different synthesizer architectures like phase-locked loops, delay-locked loops, and direct digital synthesis. Phase-locked loops are still widely used but have issues like on-chip inductors and noise. Fractional-N counters allow for better frequency resolution and noise performance than integer-N. Full integration reduces size and cost but introduces problems with noise coupling and compatibility with manufacturing processes.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    37 views37 pages

    Fully Integrated Frequency Synthesizers

    Uploaded by

    Bhanu Partap Sharma
    This document discusses the design challenges of fully integrating frequency synthesizers onto a single chip. It covers different synthesizer architectures like phase-locked loops, delay-locked loops, and direct digital synthesis. Phase-locked loops are still widely used but have issues like on-chip inductors and noise. Fractional-N counters allow for better frequency resolution and noise performance than integer-N. Full integration reduces size and cost but introduces problems with noise coupling and compatibility with manufacturing processes.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 37

    Fully Integrated Frequency Synthesizers

    Talk outline
    Introduction
    Frequency synthesizer Signal quality Full integration Circuit design challenges

    Talk outline
    Different Synthesizer Architectures
    Phase-Locked Loop Delay-Locked Loop Direct Digital Synthesis Combinations

    Conclusion

    A Frequency Synthesizer?
    A versatile circuit for creating the necessary frequencies in a radio circuit, employing a reference frequency

    A Frequency Synthesizer?
    Most radio systems employ channels: User must be able to access any of them Sometimes fast jumping is necessary

    ...

    N-1 N

    f1 f2

    fN-1 fN

    Signal Quality?
    We want clean spectrum
    carrier P(f)

    fc

    10

    Signal Quality?
    In practice:
    YO U CAN T F ILT ER

    carrier P(f) spur

    TH EM

    OU T!!

    phase noise

    fc

    14

    Signal Quality:
    To specify acceptable signal quality, most radio systems specify a spectral mask
    P(f)

    Maximum allowed sideband level

    fc

    15

    Full Integration?
    Compact radio: Single chip radio:

    19

    Full Integration?
    System: System-on-a-Chip:

    21

    Full Integration?
    Reasons for full integration:
    Minimize power consumpiton Minimize the final product size External components may have too large parasitic capacitances

    24

    Circuit Design Challenges?


    Available transistors and passive components are not optimal for RF circuits The PLL VCO inductor and the loop filter capacitor are the problem components No RF models available Intra-chip noise sources

    28

    Different Synthesizer Architectures


    Several different principles are known Not all are suitable for full integration

    29

    The Phase-Locked Loop


    PLL resembles a classical feedback control system
    Only the VCO and the counter operate at the high frequency
    fref PFD CP LPF VCO fout

    CTR

    31

    The Phase-Locked Loop


    The Phase-Frequency Discriminator (CFD) and the Charge Pump (CP)
    Convert phase error to a current pulse Low operating frequency, easy analog design
    i fref PFD CP

    32

    The Phase-Locked Loop


    The Loop Filter
    Usually passive, to reduce noise High density capacitors needed Bandwidth determines the PLL settling time
    i LPF v

    35

    The Phase-Locked Loop


    The VCO
    Typical: negative-Gm LC Problem: spiral inductor Q
    Supply voltage

    VCO

    M3

    M4

    Control voltage output 2.4 GHz output 2.4 GHz

    37

    The Phase-Locked Loop


    Many important VCO parameters...
    Tuning range Phase noise VCO constant Linear f/V response? Tail current Noise immunity ...

    VCO

    38

    The Phase-Locked Loop


    The frequency counter
    Several alternatives

    fref

    VCO PFD CP LPF fout

    CTR

    39

    The Phase-Locked Loop


    The frequency counter: integer-N
    Simple and popular The PLL multiplies fref by integer numbers: fout = ( NP + S ) fref
    CTR
    Dualmodulus prescaler Program counter P Swallow counter S Channel selection

    From VCO

    (N+1)/N

    To PDF
    Reset

    Modulus control

    41

    The Phase-Locked Loop


    The frequency counter: integer-N
    Reference frequency = channel separation Problem: spurs at f = fc fref Slow PLL settling because of narrow BW
    P(f)

    fc

    44

    The Phase-Locked Loop


    The frequency counter: fractional-N

    45

    The Phase-Locked Loop


    The frequency counter: fractional-N
    fout = fref (N + a ), where a is rational number Frequency step smaller than fref Allows higher fref and wider loop BW Faster PLL settling time Wide BW helps suppressing phase noise skirt

    50

    The Phase-Locked Loop


    The frequency counter: fractional-N
    Fractional spurs typically 30 dBc

    P(f)

    fc

    51

    The Phase-Locked Loop


    The frequency counter: fractional-N
    Suppressing fractional spurs: Randomizing the modulus control Noise shaping by modulator

    53

    The Phase-Locked Loop


    The frequency counter: phase switching
    Fast prescaler Long analog RF path, challenging design

    56

    The Phase-Locked Loop


    How about NO frequency counter?
    we can just pick the correct edge

    fref APD CP LPF

    VCO fout

    58

    The Phase-Locked Loop


    How about NO frequency counter?
    simple circuit, small Cin Aperture Phase Detector (APD)

    59

    The Delay-Locked Loop


    No oscillator!

    60

    The Delay-Locked Loop


    DLL properties:
    Noise spectrum fundamentally different: no phase error accumulation Noise spectrum does not directly depend on the quality of the on-chip inductors Many active circuits, power hungry?

    63

    Direct Digital Synthesis

    65

    Direct Digital Synthesis


    DDS is very versatile: No settling time, the output frequency change is immediate The output signal phase is also known immediately after a frequency jump

    67

    Direct Digital Synthesis


    However, there are penalties: Accumulator clock frequency higher than the synthesized frequency High dynamic power consumption Spurious frequency components

    70

    Combinations

    Dual loop

    SSB mixer inside the PLL

    72

    Other methods
    Previously described methods can be combined Methods like direct analog synthesis are not suitable for full integration

    73

    Conclusions
    Full integration is desireable Reducing size of the end product Reducing price of the end product Full integration = new problems process compatibility noise coupling Fully integrated synthesizers already exist for several applications

    76

    References:
    B. Razavi: "Challenges in the Design of Frequency Synthesizers for Wireless Applications", IEEE Custom Integrated Circuit Conference 1997 G. Chien, P.R. Gray: "A 900-MHz Local Oscillator Using a DLL-Based Frequency Multiplier Technique for PCS Applications", IEEE Journal of Solid-State Circuits, VOL.35, NO.12, DECEMBER 2000 A.R. Shanani et al.: "Low-Power Dividerless Frequency Synthesis Using Aperture Phase Detection", IEEE Journal of Solid-State Circuits, VOL.33, NO.12, DECEMBER 1998 N. Krishnapura, P. R. Kinget: A 5.3-GHz Programmable Divider for HiPerLAN in 0.25-m CMOS, ", IEEE Journal of Solid-State Circuits, VOL.35, NO.7, JULY 2000 B. Razavi: "RF Microelectronics", Prentice Hall 1998, ISBN 0-13-887571-5 J. Craninckx, M. Steyaert: "Wireless CMOS Frequency Synthesizer Design", Kluwer Academic Publishers 1998, ISBN 07923-8138-6 T.H. Lee: "The Design of CMOS Radio Frequency Integrated Circuits", Cambridge University Press 1998, ISBN 0-52163922-0

    77

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