Digital Computer: Hardware Software
Digital Computer: Hardware Software
Digital Computer: Hardware Software
It is a fast electronic calculating machine that accepts digitized input information, processes it according to a list of internally stored instructions, and produces the resulting output information.
Firmware:
Program: it is a set of instruction designed to perform a particular task. Data: it is collection of raw facts and figures Information: is processed data
computer organization deals with how the various hardware components interact with each other to perform various functionalities architecture is an abstract model of a computer system whereas computer organization expresses the realization of the architecture. architecture describes what the computer does and organization describes how it does it. Architecture and organization are independent. You can change the organization of a computer without changing its architecture. for ex- a 64 bit architecture can be internally organized as a true 64-bit machine or as a 16-bit machine that uses four cycles to handle 64 bit value.
Computer Organization
Processor
Memory
Input
Output
BUS
Input unit: It performs the following functions: It accepts instruction and data from outside world(user). It converts these instructions and data in computer acceptable form. It supplies the converted instruction and data to computer system for further processing Some input devices are keyboard, mouse, joystick,trackball Output unit It accepts the results produced by a computer, which are in coded form and hence, we cannot easily understand them. It converts these coded results to human acceptable form. It supplies the converted results to outside world. Some output devices are printer, plotter Storage unit: A storage unit holds Data and instructions required for processing which were received from input devices. Intermediate results of processing Results for output, before they are released to an output device. Central Processing unit Brain of the computer system Function Fetch instructions from memory Examine Execute Consists of 3 functional units Control Unit (CU) ALU Registers Control unit It manages and co-ordinated the entire computer system. It fetches instructions from memory, interprets the instruction and issues signals causing other units of the system to execute them. Arithmetic Logic Unit Performs arithmetic operations Performs logical operation
Registers: Very high speed memory units in the cpu for storing very small amount of data
Categories: General purpose register are those which are used by the programmer to store data. all CPUs will have one register called Accumulator. Special purpose The special purpose registers are used by the CPU for temporary storage of data for calculations and other purposes. Ex.:
Program Counter(PC) It keeps track of the execution of a program It points to the next instruction to be executed Instruction Register(IR) It contains the instruction, which is ready to be decoded and executed Memory Address Register(MAR) It holds the address of the location to be accessed Memory Buffer Register(MBR) It contains the data to be written into or read out of the addressed location CPU Program Counter Control Unit MAR Memory Arithmetic Logic Unit Instruction Register General Purpose Register
MBR
Von-Neuman Architecture:-
Control Unit
Von Neumann architecture -characteristics One processor Use of stored programs Sequential processing of instructions Single Instruction, Single Data stream (SISD) mode The Advantages of this architecture is that it treats data and programs alike meaning the same mechanisms to fetch data and the programs. The disadvantage is the same bus used for both program as well the data leads to so called Von Neumann bottleneck. Data & Program, both stored in the same place.
Harvard Architecture
Control Unit Address Bus Address Bus Arithmetic Logic Unit Program Bus Registers Data Bus
Program Memory
Data Memory
Data & program stored separately. The Advantages of this architecture is the clear separation of the data region and the code region. Also the separate data and program busses are used. Hence speeding up the process. Disadvantages could be the separate mechanisms to fetch data and the programs.
Memory Locations And Addresses The memory of a computer can be represented as a collection of words . A word is referred to a group of n bits. A word of data can be stored and retrieved in a single basic operation. Word lengths. typically ranges from 16 to 64 bits. If the word length of a computer is 32 bits, a single word can store a 32 bit 2s complement number or four ASCII characters, each occupying 8 bits. Accessing the memory to store or retrieve a single item of information require a distinct address of each item location. A 24 bit address generates an address of 2 24 location. Byte Addressability A byte is always 8 bits but the word length typically ranges from 16 to 64 bits. It is impractical to assign distinct addresses to individual bit locations in the memory. The most practical assignment is to have successive addresses refer to successive byte locations in the memory is called byte-addressable memory. There are two ways that byte address can be assigned across words names big-endian little-endian
0 4
1 5
2 6
3 7
. . .
2 k-4 2 k-3 2 k-2 2 k-1 3 7 2 6 1 5 0 4
. . .
2 k-1 2 k-2 2 k-3 2 k-4 big-endian is used when lower byte addresses are used for the more significant bytes of the word. Little endian is used when lower bytes addresses are used for the less significant bytes of the word. If the word length is 16 bytes, aligned words begin at byte addresses 0,2,4... If the word length is 64 bytes, aligned words begin at byte addresses 0,8,16... A number usually occupies one word. It can be accesses in the memory by specifying its word address An individual characters can be accessed by their address. Execution Cycle The execution process of the instruction stored in the memory happens in three phases. Fetch Phase Contents of PC are transferred to MAR Main memory is accessed and current instruction is fetched into MBR Instruction is transferred from MBR to IR Decode Phase Opcode of the instruction is decoded Contents of PC are incremented by 1(in case of 1 byte instruction or equal to the no. of bytes of the instruction currently being executed.)
Execution phase follows ( specific to the given instruction ) Execute Phase Execute the instruction Store the results in the proper place (go to the fetch phase to begin executing the next instruction)
ADD R1, R2 Memory CPU Control Unit Instruction Decoder 6 5 IR R2 GPR R3 R4 MBR 4 3 7 Special Registers Program Counter 1 + 8 MAR 2 5000 1A
R1
Instruction categories 1. Arithmetic InstructionEx.: Add, Sub, Mul etc. 2. Logical instructionsInstructions doing comparison operations. 3. Program control InstructionsEx.: Jump to some memory location where the code is place & return etc. 4. I/O Instructions-Ex.: In, Out 5. Data transfer instructions Register-Memory / memory-Register Register- Register Memory-Memory Measures of CPU performance MIPS -is a measure of the speed of the processor. Clock Speed is another metric used to measure performance. FLOPS is a measure of the speed of the Floating Point Unit (FPU) which is a co-processor unit. Memory: Memory
Internal Memory
Main Memory
Cache Memory
Secondary Memory
RAM
ROM
Internal Cache
External Cache
Main Memory: It is also called primary memory It contains the program to be executed It is a volatile memory Accessing speed of data is faster than the secondary memory RAM and Rom are type of main memory RAM
Random Access Memory It is also a volatile memory means it keeps the information as long as power supply is on. It is both read and write memory It possess random access property means any location can be accessed randomly and takes same amount of time to access any location
ROM
Read Only Memory It is a non-volatile memory It is a type of read only memory means it contents can be read out Usually setup information are stored in it
Cache Memory To overcome the speed mismatch between CPU and main memory cache memory is used. It is placed in between main memory and CPU It contains a copy of the portion of main memory Processor when need some information first checks cache If not found in cache, the block of memory containing the needed information is moved to the cache
CPU
Secondary Memory It is non-volatile memory It stores the programs and data permanently Sequential access memory Speed of accessing data is slower Types of secondary memory Hard disk
These are placed separately along with Yes the CPU (in the cabinet) and are usually not portable. The Floppy disks are portable. These Yes come in smaller sizes compared to Hard Disk.
Yes
40 GB ,80 GB
Floppy disk
Yes
1.44 MB
CD ROM
Compact Disc, Read Only Memory Yes (CD-ROMs) are portable. These are typically read-only, meaning they could be used only to read the contents. This is simillar to CD-ROMs except Yes that it is also used to write the information on to the special CD-ROM which are of Read-Write type.
No
650-700MB
CD Read/ Write
Yes
650-700 MB
Comparison of different types of memory Storage type Internal Memory Implementation features Very high speed devices, located within CPU(chip); expensive, and volatile. Very costly, hence limited in capacity. Contents Example Typical Size Registers will be few in number. The internal Cache could be 256 KB or 512 KB 256 MB 512 MB
Primary Memory
High speed devices (but slower than the internal CPU registers) located outside the CPU (on the motherboard), Less costlier compared to internal memory. Usually larger in capacity. Low speed, Nonvolatile, low cost. Huge in capacity.
Entire (almost) program contents being executed; holds small volume of data.
Secondary Memory
40GB 80 GB
Memory Hierarchy
Registers
SPEED, COST
Cache Memory
Main Memory
Secondary Memory
SIZE
Bus A group of Parallel wires that serve as a connecting path for several devices is called a bus. In addition to the lines that carry the data , the bus must have lines for address and control purposes. Address bus carry the address of destination . Control bus is to control the operation (read/write). The simplest way to interconnect functional units is to use a single bus. All units are connected to the bus. Only two units can actively use the bus at any given time because the bus can be used for only one transfer at a time. The advantage of the single bus structure is its low cost and its flexibility for attaching peripheral devices. Systems that contain multiple buses achieve more concurrency in operations by allowing two or more transfers to be carried out at same time. This leads to better performance but at an increased cost. Addressing A way of accessing memory locations which contain the data for processing . modes of addressing Implied addressing Immediate addressing Direct or absolute addressing Indirect addressing Base index addressing Segment register addressing
Implied addressing Operands are specified implicitly in the definition of the instruction Instruction specifies a fixed and unvarying address Example:-DEC (Decrement A register)
Control Unit 2
1 3 DEC ALU
1. 2. 3. 4.
The CU decodes the instruction (fetch and decode phase) The CU then fetches the contents of the register A The value of the A will be transferred to the ALU The ALU then decrements this value and updates the register A
Immediate addressing In it, data is a part of instruction itself. Example:-MOVE #100H, R1 Here the data 100h is moved to R1. The following steps are involved in the execution of this instruction. The CU decodes the instruction (fetch and decode phase) The data 100H available with the instruction is sent to RegisterR1. R1
Control Unit 2
MOVE
#100H
R1
Direct or absolute addressing The address where data is available is part of the instruction Ex.: MOVE 30A4, R175MOVE
Control Unit R1 3
30A4 1
75
MOVE
30A4H
R1
Indirect addressing Problem of direct addressing :the change in the location of the program is associated with the change in all absolute memory references. Solution : is to represent the address of the data indirectly. are two ways to do it: 1. Register Indirect Addressing :the address of the data is stored in a Register. Ex. MOVE [R2], R1
Control Unit
R2 2 3 30A4 75 4
MOVE
[R2]
R1
R1
2. Memory Indirect Addressing : the address of the data is stored in another memory location Ex. MOVE [7010], R1 Control Unit 30A4 75 3 1 MOVE [7010] R1 2 7010 30A4 4
R1
Base index addressing Ex.: MOVE [BX] + [Ri], R1 4 3 + Adder ALU 3 3000 20A4 Memory
3000
75 5 R1
) address.
(relative
Segment 3
Segment 4
3 3 50000 1000
Segment 1 (code)
0 MOVE [SR]
Segment 3 75
R1