CISC & RISC

ARCITECTURES

BY:

• Maytham Ahmed Hashim

main points:
• Introduction to CPU Arcitecture
• The Evolution of CPU Designs
• Instruction Set Complexity
• Execution Speed and Performance
• Pipeline Architecture
• Memory and Register Usage
• Instruction Decoding and Control Units
• Real-World Applications
• Comparison between CISC and RISC Architectures
• Future Trends
• Conclusion
• References
 Introduction to CPU Architecture
In the world of computer architecture :

1-CISC (Complex Instruction Set Computing) 2-RISC (Reduced Instruction Set Computing)
CISC processors are known for their complex instruction sets, capable of RISC processors, on the other hand, employ a simpler instruction set,
performing a wide range of operations with a single instruction. focusing on efficiency and speed. Their streamlined approach prioritizes
rapid execution.

These architectures represent different approaches to achieving high performance, efficiency, and versatility in processing.
 The Historical Development of CISC
Early 1960s - 1970s
1 CISC began as a way to handle the limited and costly memory of early computers. It used complex instructions, allowing one command to
do multiple tasks, which saved memory and simplified programming.

IBM System/360 (1964)

2 This was an early CISC system, designed with many complex instructions to support a range of business and
scientific tasks.

GOAL
3 CISC aimed to make programming easier by building complex instructions into the hardware,
though this made processors slower.

First Applications and Usage

4 CISC: Used in early mainframes and desktop computers, like IBM
mainframes and Intel’s x86 processors.
The Historical Development of RISC

Late 1970s - 1980s

Researchers at IBM and UC Berkeley noticed that simpler instructions could run faster. This led to the development of
1
RISC, which used fewer, simpler commands to improve speed.

IBM 801 Project and RISC I

2 IBM tested this idea with the 801 project, while Berkeley developed the RISC I processor. Both aimed to
execute simpler instructions faster.

Goal
3 RISC aimed for higher speed and efficiency by focusing on a smaller set of commands, each
completing in one clock cycle.

First Applications and Usage

4 Initially used in research, it then spread to workstations and servers, like Sun’s SPARC
and IBM’s PowerPC. Today, it’s also common in mobile devices for its efficiency.
 Instruction Set
Complexity
CISC RISC
CISC processors prioritize versatility, offering a RISC architectures emphasize simplicity and
wide array of instructions that can perform efficiency, employing a reduced set of
complex operations in a single step. This often instructions that focus on performing basic
leads to a more intricate design with a greater operations quickly and effectively. This
number of instructions. streamlined approach often translates to a
simpler processor design and faster execution
speeds.
 Execution Speed and
Performance
CISC Complexity 1
The large instruction set
and complex decoding
2 RISC Efficiency
can slow down execution
RISC's simplified
in CISC processors.
instructions and pipeline
architecture enable faster,
Modern Balance 3 more efficient processing.
Hybrid designs combine
CISC and RISC principles
to achieve optimal
performance.
Pipeline Architecture

CISC Challenges
Complex CISC instructions require multiple pipeline stages,
introducing latency and hazards.

RISC Elegance
RISC's simpler instructions enable a streamlined
pipeline with fewer stages and higher throughput.

Hybrid Approaches
Modern CPUs use dynamic pipeline
reconfiguration to adapt to CISC and
RISC workloads.
 Memory and Register Usage

CISC instructions often require fetching RISC architectures emphasize efficient register
multiple data elements from main memory, usage, reducing memory access and improving
which can slow down processing. performance.

The choice between CISC and RISC significantly impacts performance. While CISC offers complex instructions, RISC's streamlined approach,
relying heavily on registers, has become prevalent in modern processors.
 Instruction Decoding and
Control Units

CISC Complexity
CISC processors require sophisticated decoders and control units to handle their complex
instruction sets.

RISC Simplicity
RISC architectures feature streamlined instruction decoding and control logic.

Hybrid Designs
Modern CPUs use a combination of CISC and RISC techniques for efficient decoding and
control.
 Real-World Applications

Servers Smartphones Embedded Systems

CISC processors are well-suited for RISC architectures are dominant in the RISC-based microcontrollers are widely
general-purpose computing tasks, mobile market, providing efficient used in IoT devices and industrial
powering many enterprise servers. performance while consuming less automation.
power.
 Comparison Between CISC and RISC
CISC RISC

Instruction Set Features a large, complex instruction set, often Utilizes a smaller, streamlined instruction set, enabling
Complexity requiring multiple clock cycles for execution. faster execution with fewer clock cycles.

Hardware Complexity Needs more complex hardware to handle multi-step Has simpler hardware since the instructions are less complex.

instructions.

Performance and Performance can be hampered by the complexity of Faster execution speeds result from the efficient
Execution Speed decoding instructions. pipeline design and simplified instruction set.

Pipeline Efficiency Pipelines are longer and more complex, leading to Pipelines are shorter and simpler, resulting in fewer
potential hazards and stalls. hazards and increased efficiency.

Memory and Register Heavily reliant on memory access for data operations, Operations are predominantly register-centric, allowing
Usage which can be slower. for faster data manipulation and reduced memory
access.

Application Use Frequently used in desktop and server environments, Common in high-performance and power-sensitive
where complex operations and backward compatibility applications, such as mobile devices.
are important.
 Future Trends

Convergence of Concepts Modern Processors Continued Innovation

As computer architecture evolves, we see Modern processors leverage the This dynamic landscape promises
a convergence of CISC and RISC strengths of both CISC and RISC to continued innovation and advancements
principles. deliver optimal performance and in the years to come.
efficiency.
 Conclusion
In summary, while CISC and RISC architectures offer distinct
advantages, the modern landscape is characterized by a
convergence of concepts. Modern CPUs effectively leverage
the strengths of both approaches to deliver optimal
performance and efficiency. The future promises exciting
innovations in computer architecture, continually pushing the
boundaries of what is possible.
Refrences:

1 Heath, Steve."Microprocessor Architectures: RISC, CISC, and DSP.

2 IEEE Journals & Magazine "RISC versus CISC" - IEEE Journals & Magazine (IEEE Xplore)
[Link]

3 SpringerLink "CISC and RISC Architectures: An Overview"

- SpringerLink [Link]

4 Stanford University "RISC vs. CISC" - Stanford University ([Link])

[Link]

5 IEEE Xplore "Power Struggles: Revisiting the RISC vs. CISC Debate" - IEEE Xplore
[Link]

6 Springer "Guide to RISC Processors" - Springer

[Link]