Embedded Systems - 7

BM 3551 – EMBEDDED SYSTEMS
AND IoMT
UNIT 1 : INTRODUCTION TO EMBEDDED
SYSTEM DESIGN
Topic : RISC , CISC
Ms. S. Indu
AP / BME
Reduced Introduction Set Computer (RISC)
RISC stands for Reduced Instruction Set Computer Processor, a
microprocessor architecture with a simple collection and highly customized set
of instructions.
• It is built to minimize the instruction execution time by optimizing and
limiting the number of instructions.
• It means each instruction cycle requires only one clock cycle, and each
cycle contains three parameters: fetch, decode and execute.
• The RISC processor is also used to perform various complex instructions by
combining them into simpler ones.
• RISC chips require several transistors, making it cheaper to design and
reduce the execution time for instruction.
Examples of RISC processors are SUN's SPARC, PowerPC, Microchip PIC

processors, RISC-V.
Importance of RISC Processors
RISC processors exhibit certain distinct features. They include :
• Few Powerful Instructions

• Single clock Cycle execution (for most instruction)
• Register-based execution
• Highly Pipelined Superscalar Architecture
• Fixed Instruction Format and fixed length instruction
• Large register set or register windows
• Hardwired control Unit
• Highly Integrated Architecture
Advantages of RISC Processor:
• The RISC processor's performance is better due to the simple and limited number
of the instruction set.
• It requires several transistors that make it cheaper to design.
• RISC allows the instruction to use free space on a microprocessor because of its
simplicity.
• RISC processor is simpler than a CISC processor because of its simple and quick
design, and it can complete its work in one clock cycle.
Disadvantages of RISC Processor:
• The RISC processor's performance may vary according to the code executed
because subsequent instructions may depend on the previous instruction for their
execution in a cycle.
• Programmers and compilers often use complex instructions.
• RISC processors require very fast memory to save various instructions that require
a large collection of cache memory to respond to the instruction in a short time.
RISC Architecture
1. The RISC functions are to be kept simple as possible until there is the
requirement of complexity. If new operations need to be added then it
should be evaluated that if execution time of an instruction increases by 10
per cent then the size of the code should reduce 10 per cent. This is
required to balance the simplicity of the code.
2. A simple instruction may be executed at the same speed as that of a

microinstruction because micro-instructions stored in the control unit
cannot be faster than simple instructions. This is due to the fact that the
cache is built on the same technology as control unit.
3. The runtime library of RISC has all the characteristics of functions in

microcode, except that it is easier to change. In general micro codes are
difficult to change.
4. Pipelined execution gives a peak performance of one instruction every
step. The longest step determines the performance rate of the pipelined
machine, so ideally each pipeline step should take the same amount of
time.
5. RISC compilers try to remove as much work as possible during compile

time so that simple instructions can be used. For example, RISC
compilers try to keep operands in registers so that simple register-to-
register instructions can be used. RISC compilers keep operands that will
be reused in register, rather than repeating a memory access or a
calculation. They, therefore, use LOADs and STOREs to access memory
so that operands are not implicitly discarded after being fetched.
Therefore, the RISC architecture were designed with the following
features :
One instruction per cycle : A machine cycle is the time taken to fetch two
operands from register, perform the ALU operation on them and store the result
in a register.
 With such simple instruction execution rather than micro-instructions, it can
use fast logic circuits for control unit, thus increasing the execution
efficiency further.
Register-to-register operands : In RISC machines the operation that access

memories are LOAD and STORE. All other operands are kept in registers. This
design feature simplifies the instruction set and, therefore, simplifies the control
unit.
 For example, a RISC instruction set may include only one or two ADD
instructions (e.g. integer add and add with carry.
 Another benefit is that RISC encourages the optimization of register use, so
that frequently used operands remain in registers.
Simple addressing modes : Another characteristic is the use of simple
addressing modes. The RISC machines use simple register addressing having
displacement and PC relative modes. More complex modes are synthesized in
software from these simple ones. Again, this feature also simplifies the
instruction set and the control unit.
Simple instruction formats : RISC uses simple instruction formats. Generally,

only one or a few instruction formats are used. In such machines the
instruction length is fixed and aligned on word boundaries. In addition, the
field locations can also be fixed. Such an instruction format has a number of
benefits. These are :
 It simplifies the control unit
 Simple fetching as memory words of equal size are to be fetched
 Instructions are not across page boundaries.
Thus, RISC is potentially a very strong architecture.

Performance using optimizing compilers : As the instructions are simple the
compilers can be developed for efficient code organization also maximizing
register utilization etc. Sometimes even the part of the complex instruction can
be executed during the compile time.
High performance of Instruction execution : While mapping of HLL to

machine instruction the compiler favours relatively simple instructions. In
addition, the control unit design is simple and it uses little or no micro-
instructions, thus could execute simple instructions faster. Simple instructions
support better possibilities of using instruction pipelining.
RISC Pipelining
Pipelining, a standard feature in RISC processors, is much like an assembly
line. Because the processor works on different steps of the instruction at the
same time more instructions can be executed in a shorter period of time.
Different processors have different numbers of steps, they are basically
variations of these five, used in the MIPS R3000 processor :
i. fetch instructions from memory

ii. read registers and decode the instruction
iii. execute the instruction or calculate an address
iv. access an operand in data memory
v. write the result into a register
Pipelining is used for enhancing the overall performance.

Complex Instruction Set Computing
The CISC Stands for Complex Instruction Set Computer, developed by the
Intel.
• It has a large collection of complex instructions that range from simple to
very complex and specialized in the assembly language level, which takes a
long time to execute the instructions.
• So, CISC approaches reducing the number of instruction on each program
and ignoring the number of cycles per instruction.
• It emphasizes to build complex instructions directly in the hardware because
the hardware is always faster than software.
• However, CISC chips are relatively slower as compared to RISC chips but
use little instruction than RISC.
Examples of CISC processors are VAX, AMD, Intel x86 and the System/360.
Characteristics of CISC Processor:
Following are the main characteristics of the RISC processor:

• The length of the code is shorts, so it requires very little RAM.
• CISC or complex instructions may take longer than a single clock cycle to
execute the code.
• Less instruction is needed to write an application.
• It provides easier programming in assembly language.
• Support for complex data structure and easy compilation of high-level
languages.
• It is composed of fewer registers and more addressing nodes, typically 5 to
20.
• Instructions can be larger than a single word.
• It emphasizes the building of instruction on hardware because it is faster to
create than the software.
CISC Processors Architecture:
• The CISC architecture helps reduce program code by embedding multiple

operations on each program instruction, which makes the CISC processor
more complex.
• The CISC architecture-based computer is designed to decrease memory
costs because large programs or instruction required large memory space
to store the data, thus increasing the memory requirement, and a large
collection of memory increases the memory cost, which makes them more
expensive.
Advantages of CISC Processors:
• The compiler requires little effort to translate high-level programs or

statement languages into assembly or machine language in CISC processors.
• The code length is quite short, which minimizes the memory requirement.
• To store the instruction on each CISC, it requires very less RAM.
• Execution of a single instruction requires several low-level tasks.
• CISC creates a process to manage power usage that adjusts clock speed and
voltage.
• It uses fewer instructions set to perform the same instruction as the RISC.
Disadvantages of CISC Processors:
• CISC chips are slower than RSIC chips to execute per instruction cycle on
each program.
• The performance of the machine decreases due to the slowness of the clock
speed.
• Executing the pipeline in the CISC processor makes it complicated to use.
• The CISC chips require more transistors as compared to RISC design.
• In CISC it uses only 20% of existing instructions in a programming event.

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BM 3551 – EMBEDDED SYSTEMS

Topic : RISC , CISC

Examples of RISC processors are SUN's SPARC, PowerPC, Microchip PIC

RISC processors exhibit certain distinct features. They include :

• Few Powerful Instructions

Disadvantages of RISC Processor:

2. A simple instruction may be executed at the same speed as that of a

3. The runtime library of RISC has all the characteristics of functions in

5. RISC compilers try to remove as much work as possible during compile

Register-to-register operands : In RISC machines the operation that access

Simple instruction formats : RISC uses simple instruction formats. Generally,

Thus, RISC is potentially a very strong architecture.

High performance of Instruction execution : While mapping of HLL to

i. fetch instructions from memory

Pipelining is used for enhancing the overall performance.

Following are the main characteristics of the RISC processor:

• The CISC architecture helps reduce program code by embedding multiple

• The compiler requires little effort to translate high-level programs or

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