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    PPT4 - Module 1

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    sammy C
    CISC processors have complex instruction sets that allow them to directly operate on memory, reducing the need for machine instructions. However, this complexity increases processor design complexity and instruction execution times. RISC processors use a reduced instruction set with simpler, register-based instructions that can be executed in one cycle due to optimizations like pipelining. While requiring more instructions, RISC improves speed by reducing processor complexity and instruction execution times.

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    PPT4 - Module 1

    Uploaded by

    sammy C
    18 views15 pages
    CISC processors have complex instruction sets that allow them to directly operate on memory, reducing the need for machine instructions. However, this complexity increases processor design complexity and instruction execution times. RISC processors use a reduced instruction set with simpler, register-based instructions that can be executed in one cycle due to optimizations like pipelining. While requiring more instructions, RISC improves speed by reducing processor complexity and instruction execution times.

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    Computer Architecture

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    PPT4 - Module 1 (2)

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    CISC processors have complex instruction sets that allow them to directly operate on memory, reducing the need for machine instructions. However, this complexity increases processor design complexity and instruction execution times. RISC processors use a reduced instruction set with simpler, register-based instructions that can be executed in one cycle due to optimizations like pipelining. While requiring more instructions, RISC improves speed by reducing processor complexity and instruction execution times.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    18 views15 pages

    PPT4 - Module 1

    Uploaded by

    sammy C
    CISC processors have complex instruction sets that allow them to directly operate on memory, reducing the need for machine instructions. However, this complexity increases processor design complexity and instruction execution times. RISC processors use a reduced instruction set with simpler, register-based instructions that can be executed in one cycle due to optimizations like pipelining. While requiring more instructions, RISC improves speed by reducing processor complexity and instruction execution times.

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    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 15

    ClSC & RISC

    CISC is an acronym for Complex


    Instruction Set Computer
    CISC
    • Since the earliest machines were programmed in assembly
    language and memory was slow and expensive, CISC
    eliminates the need for generating machine instructions to the
    processor.
    • A CISC processor offers a built-in ability to do this.
    • Chips that are easy to program and which make efficient use of
    memory.
    • Example microprocessor :
    • Intel 80x86 and Motorola 68K series
    CISC
    • CISC was developed to make compiler development simpler.
    • It shifts most of the burden of generating machine instructions to
    the processor.
    • For example, instead of having to make a compiler write long machine
    instructions to calculate a square-root, a CISC processor would have
    a built-in ability to do this.
    CISC Characteristics
    • This is the direct result of having instructions which can operate
    directly on memory
    • CISC architectures directly use the memory, instead of a register file.

    • This architecture uses cache memory for holding both data and
    instructions.
    • Thus, they share the same path for both instructions and data.
    • CISC has instructions with variable length format. Thus, the number
    of clock cycles required to execute the instructions may be varied.
    CISC architectures directly use the memory, instead of a
    register file.
    CISC RISC
    Add 1:1,2:2 Load Loca, R1
    Load Locb, R2
    Add R1,R2,R3
    Store R3, LoCc
    Memory Cell for CISC

    1 2 3
    1 2
    2 5
    CISC Architecture
    RISC (Reduced Instruction Set Computer)
    Architecture
    • Although CISC reduces usage of memory and compiler, it requires more complex
    processor to implement the complex instructions by itself.
    • In RISC architecture, the instruction set of processor is simplified to reduce the
    execution time.
    • It uses small and highly optimized set of instructions which are generally register
    to register operations.
    • The speed of the execution is increased by using smaller number of
    instructions.
    • This uses pipeline technique for execution of any instruction.
    What is RISC?
    • It is a type of microprocessor architecture
    • It utilizes a small, highly-optimized set of instructions.

    History

    The first RISC projects came from IBM, Stanford, and UC-Berkeley in the late 70s and
    early 80s.

    The IBM 801, Stanford MIPS, and Berkeley RISC 1 and 2 were all designed with a similar
    philosophy which has become known as RISC.
    Architecture
    Certain design and Characteristics features of
    RISC
    • One cycle execution time:

    • RISC processors have a CPI (clock per instruction) of one cycle.

    • This is due to the optimization of each instruction on the CPU and a technique called PIPELINING

    • Pipelining:

    • A technique that allows for simultaneous execution of parts, or stages, of instructions to more
    efficiently process instructions

    • Large number of registers:

    • the RISC design philosophy generally incorporates a larger number of registers to prevent in large
    amounts of interactions with memory
    Summary
    End

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