Vsia Signal Integrity

VSI Alliance
TM
Signal Integrity VSI Specification

Version 2.0 (IMP 1 2.0) Signal Integrity Sub Development Working Group
[SI sub-DWG of the Implementation DWG] Released January 2004
Signal Integrity Document Sub-Development Working Group

Members of the Signal Integrity Sub-Development Working Group: Motorola Intel Corporation IBM Cadence Design Systems, Inc. ARM Phillips VSIA Japanese Special Interest Group Infineon Lucent COMLsi The participants include analog/mixed-signal designers, mixed-signal VC providers, Process Design Kit engineers, EDA developers, CAD Research engineers, and Microprocessor designers.
Active Contributors: Juan-Antonio Carballo (Chair)... IBM Raminderpal Singh. .....................................................................IBM Prashant Saxena .Intel Corporation Francois Clement. Cadence Design Systems, Inc. Steffen Rochel Cadence Design Systems, Inc. Savithri Sundareswaran .. Motorola Kaushik Gala . Motorola Chanhee Oh .Motorola
Previous Contributors: Paul Hoxey ... ARM plc David Overhauser . Cadence Design Systems, Inc. Takahide Inoue .VSIA Japanese Special Interest Group Special acknowledgment goes to the following: Henry Chang, Chair of the VSIA AMS DWG ...Cadence Design Systems, Inc. Paul van de Wiel ..Philips Research Laurence H. Cooke VSIA Also, the team would like to thank: The VSIA AMS DWG membership Kang Lee .Lucent Microelectronics Silvia Straehle .... Infineon Technologies Thomas Brandtner .. Infineon Technologies Raj Nair..... .ComLSI
VSI Alliance (IMP 1 2.0)
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Signal Integrity VSI Specification Version IMP 1 2.0 (IMP 1 2.0)
Notice
The VSI Alliance (VSIA) is the copyright owner of the VSIA IP identified above. The VSIA will make royalty-free copyright licenses for this IP available to VSIA Members. Non-members must pay a fee for the copyright license. Use of the IP by members and non-members of the VSIA is subject to the terms of the license. You are not entitled to use the VSIA IP unless you agree to the terms of the license (and, if applicable, pay the fee). The license terms are set forth on the website of the VSIA at http://www.vsi.org. THE VSIA IP IS PROVIDED BY VSIA ON AN AS-IS BASIS, AND VSIA HAS NO OBLIGATION TO PROVIDE ANY LEGAL OR TECHNICAL ASSISTANCE IN RESPECT THERETO, TO IMPROVE, ENHANCE, MAINTAIN OR MODIFY THE VSIA IP, OR TO CORRECT ANY ERRORS THERE IN. VSIA SHALL HAVE NO OBLIGATION FOR LOSS OF DATA OR FOR ANY OTHER DAMAGES, INCLUDING SPECIAL OR CONSEQUENTIAL DAMAGES IN CONNECTION WITH THE USE OF THE VSIA IP BY SUBSCRIBER. VSIA MAKES NO REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, INCLUDING WITHOUT LIMITATION, ANY WARRANTY AS TO INFRINGEMENT, OR THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. SUBSCRIBER SHOULD BE AWARE THAT IMPLEMENTATION OF THE VSIA IP MAY REQUIRE USE OF A SUBJECT MATTER COVERED BY PATENT OR OTHER INTELLECTUAL PROPERTY RIGHTS OF THIRD PARTIES. NO LICENSE, IMMUNITY OR OTHER RIGHT IS GRANTED BY THIS LICENSE IN ANY SUCH THIRD-PARTY RIGHTS. NEITHER VSIA NOR ITS MEMBERS TAKE ANY POSITION WITH RESPECT TO THE EXISTENCE OR VALIDITY OF ANY SUCH RIGHTS.
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Table of Contents
1. Overview ..
1.1 Scope . 1.2 Assumptions .
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1 1
1.3 Methodology Description for VC Usage 1.4 Referenced IP 1.5 Definition of Terms 1.6 Summary of Deliverables
1.6.1 Key to Deliverables Level of Requirements 1.6.2 Definitions of Deliverables Table Columns 1.6.3 Summary of Deliverables Table
1.2.1 Technology . 2 1.2.2 Product trends 2 1.2.3 Design Methods 2 1.2.4 Organization of document . 3 1.2.5 Relationship to I-V and AMS Specifications 3
4 4 5 6
6 7 7
2. Specification of Deliverables . 10
2.1 Interconnect Crosstalk (Voltage Noise and Delay Variance) 10
2.1.1 Overview ..... 10 2.1.2 Electrical data 10 2.1.2.1 Maximum permissible noise propagating into input ports . 10 2.1.2.2 Maximum permissible external (to VC) crosstalk coupling and effective aggressor slew for failure- and delay-critical sensitive nets (if any) inside VC 11 2.1.2.3 Maximum noise possible at output ports (due to propagation) 11 2.1.2.4 Electrical characteristics for strong potential aggressors (for OTH signals) 11 2.1.2.5 Electrical characteristics for failure- or delay-critical sensitive VC nets12 2.1.2.6 Best and worst case slew permissible at input ports 12 2.1.2.7 Best and worst case slew at output ports (and variation with load) 12 2.1.2.8 Maximum permissible load/distributed RC driven by output ports 12 2.1.3 Physical data 13 2.1.3.1. Location of failure- or delay- sensitive interconnect VC polygons 13 2.1.3.2. Location of strong potential OTH aggressors lying within VC 13 2.1.3.3 Location of top-layer/peripheral supply and ground wires 14 2.1.3.4 No-fly zone /external shielding requirements 14 2.1.3.5 Safe regions for OTH signals (possibly classified by slew) 14 2.1.4 Timing data 14 2.1.4.1. Variation of timing arcs within VC with external crosstalk 14 2.1.4.2. Transition windows available at output ports 15 2.1.4.3. Transition windows required at input ports 15 2.1.4.4. Transition windows for strong potential aggressors (for OTH signals) or failure/delay critical sensitive nets lying within VC 15 2.1.5 Logical data 15 2.1.5.1. Mutex/One-hot relationships required between input signals 15 2.1.5.2. Mutex/One-hot relationships available between output signals 16
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2.2 Signal Electromigration
2.2.1 Electrical Data 2.2.1.1. Current density limits on metal and via layers 2.2.1.2. Max load for electromigration limits on outputs 2.2.1.3. Max slew rate for electromigration limits on inputs 2.2.1.4 Max Switching factor 2.2.1.5. Drive Strength 2.2.1.6. Input Load . 2.2.2 Physical Data .
16 17 17 17 17 17 18 18
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2.3 Supply and Ground Grid Noise & Electromigration .
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2.3.1 Overview 18 2.3.2 Electrical data Specification 18 2.3.2.1 Specification Requirements for Static Power Model 18 2.3.2.2 Specification Requirements for Dynamic Power Model 19 2.3.3 Physical data 20 2.3.3.1 External Geometrical data of the supply and ground nets (supply and ground ports)20 2.3.3.2 Internal Geometrical data of the supply and ground nets 21 2.3.4 Timing data 21 2.3.4.1 Variation in timing on output pins (delay & edge rates) due to IR drop in power grid 21 2.3.4.2 Variation in timing on input pins (setup/hold time) due to IR drop in power grid 22 2.3.5 Multiple power supplies for analog blocks, multi Vt circuits, pads 22 2.3.6 Supply and Ground Electromigration Verification 22
2.4 Substrate Noise and Coupling 23

2.4.1 Overview 2.4.2 Electrical data 2.4.2.1. Block-level impedance model . 2.4.2.2. Noise sources for aggressor access ports . 2.4.2.3. Maximum allowed noise for each victim access port 2.4.3 Physical data 2.4.3.1 Regions 2.4.3.2. Substrate access ports . 23 23 23 24 24 25 26 27
2.5 SI Requirements Document
28
3. Design Guidelines .
28
3.1 Interconnect Crosstalk (Voltage Noise and Delay Variance) 28 3.2 Inductance effects 30 3.3 Signal Electromigration 32 3.4 Supply and Ground Grid Noise & Electromigration . 33 3.5 Substrate Noise and Coupling 35 3.6 Other Important SI Effects 36
3.4.1 IR-drop in the Supply and Ground Wires (Grid) .. 33
Appendices . 38
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A Implementation of Specifications on an Example Design .. 38 A.1 Overview of SoC Design . 38 A.2 Example Deliverables 39 B Table mapping implementation deliverables 47 C Interconnect-centric existing standards analysis 49 D Glossary of Acronyms 57 E Bibliography 58
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1. Overview
1.1 Scope
The scope of this document is to specify and explain deliverables, data formats, associated design guidelines, and example designs for the signal-integrity (SI) issues of both digital and analog mixed-signal virtual components (VC) in SoC design. This specification is focused on SI issues in the communication between the VC authors and integrators for the integration of Digital and Analog Mixed-Signal blocks (VC) in SoC designs, including design of the interface. It is assumed that the virtual components are provided for integration as hard blocks. The scope of the work is defined by the boundary conditions, and is currently limited to supply and power grids, interconnect crosstalk, and substrate coupling, both for uniformly doped silicon substrates and silicon substrates with an EPI layer on heavily doped bulk substrates. This document also discusses the issues related to power grid and signal electromigration. Issues such as IC package noise are very important to understanding the noise SI issues in SoC design, but consistent with other VSIA specification documents, they are currently out-of-scope. This specification focuses on the 0.18um process generation dealing with issues that may occur down to 0.07um and beyond. The SI issues covered in this document are experienced in processes >0.18um, and much of this document can be applied to help VC transfer in these technologies. However, the focus of this work is on a specific technology node range that meets the design requirements of the majority of VC authors and integrators. The scope of this document has been bounded by the following considerations: (a) Current and future severity and seriousness of the issues, (b) Verifiability before manufacturing on silicon, (c) Appropriateness for the documented information between the VC author and integrator. With respect to Version 1.0, this document incorporates (a) the addition of a table in Appendix B, mapping SI deliverables to AMS and I-V deliverables, (b) an analysis of emerging and existing standards, and their SI extensions in Appendix C, with a view toward future unified wire models, (c) further content across the document about the impact of inductance on crosstalk and supply noise, and (d) separation of the Signal EM sub-section from the crosstalk section (Sections 2.2 and 2.1, respectively).
1.2
Assumptions
The following assumptions attempt to identify SI problems in SoC designs, and how specifications provide value to designers. The assumptions are divided into three categories: technology, product trends, and design methods.
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Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
VSI Alliance (IMP 1 2.0) 1.2.1 Technology The following assumptions are made about the severity of the SI problems from a technology or process point of view:
As published in the annual International Technology Roadmap for Semiconductor (ITRS) [ITRS], CMOS process technology progress is still marching toward the UDSM area. According to the 1999 ITRS document, the 2002 process generation will reach 0.13um, and then 90nm in a few years. Because of necessity of the non-linear shrink of dimensions, signal interference between neighboring wires become more tangible and make SoC behavior unstable. Although new metal materials such as copper can delay many problems by a process generation or so, thinner and narrower metal layers are required for power supply and ground wires, so some key
signal interconnects may suffer from electromigration problems.
1.2.2 Product Trends In the past, the semiconductor industry and system manufacturers have enjoyed performance improvements through Moores law. Now, leading edge products are looking for chips containing multi-million gates running at speeds close to 2GHz. These performance and packaging density needs lead to severe design challenges:
Rising power density will cause both static and dynamic thermal interferences between VCs. High slew rate and narrow skew margins for high performance chips make designs unmanageable in terms of hard-to-predict signal interference between neighboring interconnects.
1.2.3 Design Methods It is very common that the chip designs over a few million gates are developed through concurrent and collaborative work of several design teams either in the same or different organizations, or even in different businesses. This causes additional difficulty in necessary information sharing and feedback among the participating designers. Categories of this information include:
Electrical information, such as static or dynamic voltage changes on the block power supply and ground terminals, allowance of noise level on the block input terminals, and possible noise levels on the block output terminals Physical layout information, such as the location of noise-sensitive or aggressive wires, blockage for the chip-level interconnect, allowable space for signal feed-through, and supply and ground wire connection strategy to ensure sufficient current capacity for block internal supply and current feed-through Timing information, such as the slew allowance on block input terminals
Above all, these specifications attempt to make the work of designers and design-managers easier when they have to share their designs with internal or Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
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VSI Alliance (IMP 1 2.0) external partners. In one sense, these specifications define not only the necessary information flow from VC author to integrator, but also the information flow from VC integrators and manufacturers to VC authors. 1.2.4 Organization of Document This document has been written for designers experienced in the SI issues covered. The document does not discuss the background to the issues. For an in-depth tutorial on each of the issues, as well as advanced coverage of the topics, the reader is referred to [Singh01]. In the preparation of this document, attention has been paid to the way in which the specifications will be read. It is understood that readers have very different technical backgrounds and requirements, and may not need to read all the sections. For example, analog and process engineers may read only Section 3.3, Substrate Noise and Coupling, as they try to author or integrate analog VCs. Conversely, microprocessor designers may be only interested in Section 2.1, Interconnect Crosstalk (Voltage Noise and Delay Variance) and Signal Electromigration. With this understanding in mind, the document has been structured such that there is no direct overlap between the sections, so that each section can be read separately. The document is divided into sections relating to the following SI issues: Interconnect Crosstalk (Voltage Noise and Delay Variance) and Signal Electromigration, Supply and Ground Noise and Electromigration, and Substrate Noise and Coupling. 1.2.5 Relationship to I-V and AMS Specifications The SI specification overlaps into design scopes covered by the ImplementationVerification (I-V) and Analog Mixed-Signal (AMS) specifications. Therefore, it is important that the reader understands the emphasis and focus of this document, and how to apply the specifications from each area effectively. The I-V and AMS documents cover the broad requirements for designing and integrating digital and analog VCs. The SI work overlays important (and many times critical) requirements above the ones described in those documents, and as such borrows many of the formats from them (see Appendix B). Figure 1 below shows a high-level flow for using the various specification documents in an SoC design.
Analog/MS VC
AMS Spec SI Spec
Digital VC
I-V Spec SI Spec
VC Integration
Figure 1: High-level Methodology for Using the Specifications for SI, I-V, and AMS
This document uses different attributes of the formats to specify SI-related deliverables. For example, SDF, SPEF, VC Hspice, and GDSII are commonly referred to in all three documents. This allows the reader to accomplish compliance with the use of standard formats.
1.3
Methodology Description for VC Usage
SI issues are very much related to issues in the physical silicon process. For example, detailed information about the target process is necessary for VC authors to make SI data useful for VC integrators. It is also crucial for building first-time success for VCs in the target SoC. In some cases, especially for high performance design, VC authors need to define SI specifications such that the VC integrator is able to understand the conditions in which the VC will work. VC integrators sometimes explore details of the VC to be used, but they are often restricted by business conditions. In any case, it is necessary to have compact yet sufficiently precise abstracted SI models, since full SI verification is too expensive in actual SoC designs.
1.4
Referenced IP
Similar to other VSIA specifications, the proposed approach is to leverage existing standards (publicly available industry-wide formats and models) as much as possible. However, it has been observed that there is a need to select and combine parts of existing intellectual property (IP) to build concise and consistent specifications. The following standards are used in this specifications document, as deliverables:
Spice: VC Hspice 1.0a (Spice)
Owner: Synopsys Corporation Status: Licensed through VSIA Technology Contribution Agreement Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
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VSI Alliance (IMP 1 2.0) http://www.vsi.org

GDSII: GDSII Stream Format 6.0.0
Owner: Cadence Design Systems, Inc. Status: Licensed through VSIA Technology Contribution Agreement http://www.vsi.org
SPEF: IEEE P1481, 1998
Owner: IEEE Status: IEEE Ballot Standard http://www.eda.org/dpc

SDF: IEEE P1497
Owner: IEEE Status: IEEE Ballot Standard http://www.eda.org/sdf

VC LEF: VC LEF 5.5
Owner: Cadence Design Systems, Inc. Status: Licensed through VSIA Technology Contribution Agreement http://www.vsi.org
PDEF: IEEE P1481, 1998
Owner: IEEE Status: IEEE Ballot Standard http://www.eda.org/dpc
1.5
Definition of Terms
For clarity, the following terms are defined below. For a detailed listing of acronyms used in this document, see Appendix C, Glossary of Acronyms. A complete Definition of Terms can be found in the VSIA Taxonomy Document [VSIA]. RTL source Defines the VC source description, and is the primary input for the implementation and verification of the VC within a system-chip design. Basic delay model Defines timing specification of the VC. Timing analysis model Defines the static timing characteristics of the VC. Power model Defines the power specification of the VC. Peripheral interconnect model (PIM) Specifies the interconnection RCs for the peripheral interconnect between the physical I/O ports and the internal gates of the VC. Physical blocks A model of the physical implementation of the VC and the system chip. VC port The pad or point of interconnection between the VC and the system chip.
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VSI Alliance (IMP 1 2.0) Behavioral model Describes the component function and timing without describing the internal structure. Cell-level netlist A structural interconnection of design objects ranging from simple logic gates to complex functions. Circuit-level netlist A structural interconnection of semiconductor devices such as transistors, resistors, and capacitors. Crosstalk Any deviation from the ideal signal waveform propagating in an interconnect wire caused by signal transitions in other wires in the neighborhood. Slew The slope of a digital signal propagating in an interconnect (in voltage change per unit time). Transition window The temporal interval containing every instant within a clock cycle at which a specified signal transition may occur. Miller Coupling Factor In the context of interconnects, the multiplier used for the capacitive coupling from neighboring wires to account for the impact on the delay because of their simultaneous switching. Timing arc The input pin to output pin delay between the pins of a VC or cell. Mutex A logical guarantee of the mutual exclusivity of the transitions of two signals. One hot A set of signals such that exactly one of them is active at any instant.
1.6
Summary of Deliverables
Note that Appendix A includes an example design that applies the specifications listed below. SI in SoC designs is an emerging topic, so many of the specifications are currently defined as Document, with some Comments provided where appropriate. Many of the comments discuss possible standards that may not yet be endorsed by VSIA. It is expected that future specifications and standards will address emerging industry standards. The formats specified in this document complement those of other DWGs in VSIA. However, the formats in this document do not directly overlap other VSIA documents, including the I-V and AMS specifications. Where formats are specified differently from AMS, I-V, and VCT, the format is necessary due to additional information specifically needed for SI. Section 1.2.5 describes the use-model of this document, with relation to the AMS and I-V specifications. 1.6.1 Key to Deliverables M Mandatory CM Conditionally Mandatory R Recommended CR Conditionally Recommended Where CM or CR has been specified, the condition is provided in the appropriate sub-section in Section 2 of this document. Where document and any other formats are specified, all are required, as opposed to Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
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VSI Alliance (IMP 1 2.0) any one of the formats being acceptable to meet the deliverable. 1.6.2 Definition of Columns in Summary of Deliverables Table Section The section number referred to Deliverable A summary of the deliverable Currently Used Formats Standards used in current design flows VSIA Specified Format The VSIA endorsed and specified format. Where two formats are specified, both are required. SI Hard The Level of Requirement. All deliverables for this document are for Hard VCs only. Comply Enables the user to check off requirements when using this table Comments The conditions for the relevant deliverables
1.6.3 Summary of Deliverables Table With respect to version 1, this table separates the interconnect crosstalk section and the signal electromigration section.
Table 1: Summary of Deliverables Table (Continued)
Section Deliverable Currently Used Formats 2.1. 2.1.2 2.1.2.1. Interconnect Crosstalk (Voltage Noise and Delay Variance) Electrical data Maximum permissible noise propagating into input ports VC Hspice CM If available, in otherwise document Section 2.4 VSIA Specified Format SI Hard Comply Comments

2.1.2.2. Maximum permissible external (to VC) crosstalk coupling and effective aggressor slew for failure- and delay-critical sensitive nets (if any) inside VC SPEF, Document CM If available, in
otherwise document Section 2.4
2.1.2.3.
Maximum noise possible at output ports (due to propagation/coupling within VC)
VC Hspice
CM
If
available, in
2.1.2.4. 2.1.2.4.1 2.1.2.4.2 2.1.2.5
Electrical characteristics for strong potential lying within VC I/O Driver Models Interconnect Models . Electrical characteristics for failureor delay-critical sensitive nets lying within VC VC Hspice, SPEF VC Hspice, SPEF VC Hspice, SPEF Hspice, Document Document VC Hspice, M M R R R R R
2.1.2.5.1 2.1.2.5.2 2.1.2.6. 2.1.2.6.1 2.1.2.6.2 2.1.2.7. 2.1.2.7.1 2.1.2.7.2 2.1.2.8.
I/O Driver Models Interconnect Models Best and worst case slew permissible at input ports VC Min/max Slew Limits Input environment models Best and worst case slew available at output ports (and its variation with load) Min/max Slew Limits Driver Models Maximum permissible load/distributed RC that can be driven by output ports
Document VC Hspice, SPEF
M M M
2.1.3. 2.1.3.1. 2.1.3.2. 2.1.3.3 2.1.3.4 2.1.3.5 2.1.4.
Physical data Location of failure- or delay-critical sensitive interconnect polygons inside VC Location of strong potential aggressors (for OTH signals) lying within VC Location of top-layer/peripheral supply and ground wires inside VC No-fly zone or external shielding requirements Safe regions for OTH signals (possibly classified by slew) Timing data PDEF PDEF M R PDEF M PDEF M PDEF M

2.1.4.1. Variation of timing arcs within VC with external crosstalk SDF CM If available, in
2.1.4.2. 2.1.4.3. 2.1.4.4.
Transition windows available at output ports Transition windows required at input ports Transition windows for strong potential aggressors (for OTH signals) or failure/delay critical sensitive nets lying within VC
SDF SDF SDF
M M M
2.1.5. 2.1.5.1. 2.1.5.2. 2.2. 2.2.1. 2.2.1.1. 2.2.1.2. 2.2.1.3. 2.2.1.4 2.2.1.5 2.2.1.6 2.2.2 2.3. 2.3.2. 2.3.2.1 2.3.2.2 2.3.3. 2.3.3.1 2.3.3.2 2.3.3 2.3.4.1 2.3.4.2 2.3.4.3 2.3.5 2.3.6 2.4.
Logical data Mutex/One-hot relationships required between input signals Mutex/One-hot relationships available between output signals Signal Electromigration Electrical Data Current density limits on metal and via layers Max load for electromigration limits on outputs Max slew rate for electromigration limits on inputs Max Switching factor Drive Strength Input Load Physical Data Supply and Ground Grid Noise & Pathmill cfg files Pathmill cfg files Document M Document M
Document VC Hspice SDF VC Hspice Document Document GDSII
M M R R M M M
Electromigration Electrical data Specification Specification Requirements for Static Power Model Specification Requirements for Dynamic Power Model Physical data External Geometrical data of the supply and ground nets (supply and ground ports) Internal Geometrical data of the supply and ground nets Timing data Variation in timing on output pins (delay & edge rates) due to IR drop in power grid Variation in timing on input pins (setup/hold time) due to IR drop in power grid Variation in Timing due to inductive noise Multiple power supplies for analog blocks, multi Vt circuits, pads Supply and Ground Electromigration Document M Verification Substrate Noise and Coupling Symopsys .lib file Symopsys .lib file .lib file Document Document CR M Document R Document M Document M VC LEF M Document R Document M

2.4.2. 2.4.2.1. 2.4.2.2. Electrical data Block-level impedance model Noise sources for aggressor access ports Maximum allowed noise for each victim access port Physical data Regions Substrate access ports SI Requirements Document Annotated GDSII 2.5. Document M Document Document M M VC Hspice VC Hspice VC Hspice M M M
2.4.2.3.
2.4.3. 2.4.3.1 2.4.3.2.
2. Specification of Deliverables
2.1 Interconnect Crosstalk (Voltage Noise and Delay Variance)
2.1.1 Overview Although the techniques used to combat crosstalk vary from one design/integration house to another, it is possible to abstract the issues that are common to all interconnect crosstalk scenarios. The data that needs to be communicated for effective control of crosstalk effects across the boundary of the VC can be listed at a level high enough to be largely independent of the signal integrity methodologies and algorithms employed by the designers and integrators. Ideally, it includes some metrics for the maximum permissible noise pulse (along with slew and transition window requirements) at the input ports and the maximum noise pulse possible at the output ports (along with slews and transition windows and their variation with external load). The VC author can also specify external no-fly zone/shielding requirements. The goal is to present a simplified yet reasonably accurate model for the VC while still preserving its gray/black box nature. In a similar vein, although crosstalk due to the board and packaging is out of the scope of this document, it is important to note that some interface modeling may be required even for these levels of the hierarchy in order to analyze and optimize crosstalk accurately. Furthermore, since long global wires at the chip integration level are typically more prone to crosstalk than local VC wires, it is good practice for the VC authors to identify and communicate any data within the VC that can be exploited by the chip integrator to make the global convergence easier and the design more crosstalk- immune. For potential victim/aggressorwires, the electrical data should be cross-referenced to corresponding geometric and/or timing data; however, VC hiding issues may dictate that some or all of these wires not be identified logically. In such scenarios, it may make sense to merely index the wires of interest without th naming them (or giving them dummy names), and then cross-referencing all the relevant data for the i wire of interest across the various specification files. 2.1.2. Electrical data
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Since noise is primarily an electrical phenomenon, VC authors should abstract and communicate electrical and parasitic parameters for ports as well as nets/paths on which they anticipate noise problems. In general, the electrical data includes wire parasitics for the selected wires, along with output impedance for their drivers and the input impedances for their receivers. Another issue that merits some debate is the noise model itself. This is currently an area of active research both within academia and industry. Models range from simple noise peaks to accurate waveforms. It is expected that different applications will opt for different levels of accuracy in their noise model, depending on the anticipated severity of the crosstalk experienced by them. 2.1.2.1. Maximum permissible noise propagating into input ports This documents the VC authors assumption about the worst case noise pulse at the VC inputs that can safely propagate into the VC without causing any failures (with the external crosstalk being specified as documented in 2.1.2.2 below). It must be guaranteed by the chip integrator for the VC to function correctly. Depending on the noise model adopted, this data item can vary from a simple mV peak specification or combination of pulse width and peak to a piecewise linear (PWL) waveform. CONDITIONALLY MANDATORY Specifications: VC Hspice (for noise waveforms, assumes pulse limits can be expressed) Condition: VC Hspice format is available. Otherwise, provide document in Section 2.4.
2.1.2.2. Maximum permissible external (to VC) switching cross-coupling and effective aggressor slew for failure- or delay-critical sensitive nets (if any) inside VC This data item specifies the maximum switching cross-coupling capacitance that can be safely experienced by sensitive nets within the VC (for a given pulse width/height) without creating negative slacks/races. This data item should be interpreted either in conjunction with data about its physical location and timing windows (see 2.13.1 and 2.1.4.4 below) as well as on electrical characteristics of the sensitive VC nets (see 2.1.2.5 below), or in the context of broad safe zones required around the VC (when the safe zone is predicated on the absence of exceptionally strong over the hierarchy (OTH) aggressors; see 2.1.3.4 and 2.1.3.5 below.
CONDITIONALLY MANDATORY Specifications: SPEF to capture distributed coupling if required; else, a mere maximum permissible capacitance value for each sensitive net. Effective aggressor slew represented in mV/ps. Condition: SPEF format is available. Alternatively, document can be provided if the SPEF format is not available. Comments: Indicate None in the SI Requirements Document (Section 2.4) if no instances exist. 2.1.2.3. Maximum noise possible at output ports (due to propagation/coupling inside VC) This documents the worst case noise pulse that the integrator can expect at the VC outputs, and helps the integrator accurately analyze the noise/delay experienced by the global wires connected to these ports (and to propagate the noise into downstream logic along these wires). CONDITIONALLY MANDATORY Specifications: See specifications for 2.1.2.1 above. 2.1.2.4. Electrical characteristics for strong potential aggressors (for OTH signals) lying inside VC This data, although optional, can help the chip integrator to achieve global convergence by avoiding the layout ofsensitive OTH inter-VC wires in high risk regions dominated by strong intra-VC aggressors that would otherwise not be visible. It should include a model for the driver as well as the interconnect. This
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data item should be interpreted in conjunction with the corresponding physical data item 2.1.3.2. Comments: Indicate None in the SI Requirements Document (Section 2.4) if no instances exist. 2.1.2.4.1 Driver Models RECOMMENDED Specifications: VC Hspice. 2.1.2.4.2 Interconnect Models RECOMMENDED Specifications: SPEF.2.1.2.5. Electrical characteristics for failure - or delay-critical sensitive nets lying inside VC As with 2.1.2.4, this optional item can help the chip integrator analyze sensitive VC wires that would otherwise not be visible, in order to ensure that global wires close to these wires are not strong enough to cause failures within the VC. It should include models for the driver, the interconnect and the receivers. Comments: Indicate None in the SI Requirements Document (Section 2.4) if no instances exist. 2.1.2.5.1 Driver Models RECOMMENDED Specifications: VC Hspice. 2.1.2.5.2 Interconnect Models RECOMMENDED Specifications: SPEF. 2.1.2.6. Best and worst case slew permissible at input ports If the transition slopes of the input signals of the VC are too high, it can cause them to act as unexpectedly strong aggressors within the VC. Conversely, too low slopes can cause them to be victimized severely. The permissible slew range at the input ports documents the assumptions made by the VC author and must be guaranteed by the VC environment for the VC to function correctly as advertised. 2.1.2.6.1 Min/max Slew Limits MANDATORY Specifications: Document Comments: To be specified in units of mV/ns in the SI Requirements Document 2.1.2.6.2 Input environment models MANDATORY Specifications: VC Hspice Comments: A model for the environment driving the port. 2.1.2.7. Best and worst case slew available at output ports (and its variation with load) The slew ranges at the output ports can be used by the integrator to accurately analyze the noise/delay experienced by the global wires connected to these ports (and to propagate the noise into downstream logic along these wires). Comments: Note that this data is usually also included in the standard timing view of the VC. 2.1.2.7.1 Min/max slew limits
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MANDATORY Specifications: Document Comments: To be specified in units of mV/ns in the SI Requirements Document 2.1.2.7.2 Driver models MANDATORY Specifications: VC Hspice Comments: For driver modeling (to compute variation of slew with load)
2.1.2.8. Maximum permissible load/distributed RC that can be driven by output ports Although this data is required primarily by the timing/performance models of the VC, it is also valuable in a signal integrity context, since it ensures that the signals in the wires inside the VC that feed the output ports do not become unexpected victims due to deterioration in the slew caused by excessive load. This data could be combined with 2.1.2.7, since the driver model can lead to min/max slew rate an output can drive. MANDATORY Specifications: SPEF. Comment: Note that this data item is usually also included in the standard timing view of the VC. 2.1.3. Physical data Physical data complements electrical data (and, at times, timing data) for potential aggressors and victims within the VC, thus providing sufficient visibility into the VC to enable reasonably accurate signal integrity analysis.
Strong potential aggressor within VC (cross-referenced in timing and electrical data if required) Weak potential victim within VC (cross-referenced in timing and electrical data if required) No fly zone
Figure 2.1.1 Physical data to be communicated (cross-referenced with electrical/timing data) It can also be used to specify broad external shielding requirements for sensitive signals within the VC. 2.1.3.1. Location of failure- or delay-critical sensitive interconnect polygons inside VC This data indicates the physical regions of the VC that must be protected from external aggressors, and should be specified in conjunction with the electrical (and possibly timing) properties of these interconnects, as described in 2.1.2.5 and 2.1.4.4. A coarser (and more conservative) way of representing this is through external shielding requirements and designated no-fly zones as described in 2.1.3.4 below. 13

MANDATORY Specifications: PDEF Comments: Indicate None in the SI Requirements Document (Section 2.4) if no instances exist. 2.1.3.2. Location of strong potential aggressors (for OTH signals) lying inside VC This is the other side of the coin from 2.1.3.1 that dealt with potential victims within the VC. In contrast, this item deals with potential aggressors within the VC and should be specified in conjunction with electrical (and possibly timing) data for these aggressors that can be used by the chip integrator to decide whether or not to route sensitive global wires in the vicinity of these aggressors. MANDATORY Specifications: PDEF Comments: Indicate None in the SI Requirements Document (Section 2.4) if no instances exist. 2.1.3.3 Location of top-layer/peripheral supply and ground wires inside VC This data allows the chip integrator to exploit the Vdd and Vss wireswithin the VC to provide shielding for sensitive global wires routed close to the VC. MANDATORY Specifications: PDEF 2.1.3.4 No-fly zone or external shielding requirements This documents the assumptions made by the VC author about the absence of external aggressors while designing the VC, and must be guaranteed by the chip integrator. It could involve constraints ranging from OTH supply and ground wires required in certain designated tracks to supply or ground planes or non-metalized blockages covering designated areas over the VC. MANDATORY Specifications: PDEF Comments: Indicate None in the SI Requirements Document (Section 2.4) if no instances exist. 2.1.3.5 Safe regions for OTH signals (possibly classified by slew) This data item generalizes the constraints described in 2.1.3.4 by designating safe tracks or regions for global wires routed over/through the VC Thus, it identifies the preferred corridors for OTH signals based on their susceptibility to crosstalk from within the VC (as determined by their slew). In some sense, this data item is a usage guideline for the chip integrator based on the intra-VC aggressor data communicated in 2.1.3.2. RECOMMENDED Specifications: PDEF. Also, associated with each safe region should be a document describing the min/max slew ranges (in mV/ns) for which it is safe.
2.1.4. Timing data Timing data about sensitive/strong VC nets and VC ports complements physical and electrical data described in the previous two sections (2.1.2 and 2.1.3) to enable the integrator to respect the assumptions made by the VC author while converging the VC design, It also helps plan around potential problems in global nets due to crosstalk from within the VC. However, we note that with increasing clock frequencies, transition window widening due to crosstalk and process variation, it is often difficult to guarantee temporal separation of transitions without any underlying logical exclusivity relationship.
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2.1.4.1. Variation of timing arcs within VC with external crosstalk The pin-to-pin delays (timing arcs) within the VC are computed with certain assumptions on the extent of crosstalk that the VC wires experience from signals outside the VC. Therefore, it is important to document how these delays vary with external crosstalk. Thus, associated with each timing arc within the VC should be a formula or lookup table describing the delay variation with external coupling. However, since the VC author may not wish to explicitly identify candidate victim wires within the VC, it may be possible to give only a range for the delay variation of the timing arc. Thus, unlike the case of delay variation with external load, the chip integrator will be unable to explicitly compute the exact delay for any given integration environment. (Also see 2.1.6.1 below). CONDITIONALLY MANDATORY Specifications: SDF (for delay variation range) Condition: SDF format is available. Otherwise, provide document in Section 2.4. 2.1.4.2. Transition windows available at output ports This enables the chip integrator to both to carry out less conservative timing analysis by assuming Miller Coupling Factors (MCFs) of 1 for pairs of adjacent nets with non-overlapping timing windows as well as to use such signals as relative shields for each other. (Also see 2.1.5.2 below). MANDATORY Specifications: SDF Comments: Note that this data item is usually also included in the standard timing view of the VC. 2.1.4.3. Transition windows assumed at input ports This describes the non-overlapping timing windows, if any, for the input signals that have been exploited by the VC designer to enable VC convergence that must be enforced by the integration environment. (Also see 2.1.5.1 below). MANDATORY Specifications: SDF Comments: Note that this data item is usually also included in the standard timing view of the VC.
2.1.4.4. Transition windows for strong potential aggressors (for OTH signals) or failure/delay critical sensitive nets lying inside VC This data, coupled with physical and electrical data for sensitive or exceptionally strong nets within the VC, will allow the integrator to avoid placing strongly switching global wires in the immediate vicinity of sensitive VC wires as well as sensitive global wires in the immediate vicinity of strong aggressors within the VC. Thus, this data also formalizes any assumptions about the lack of external aggressors that the VC author might have made while designing sensitive interconnects within the VC. (Also see 2.1.2.2, 2.1.2.4, 2.1.3.1 and 2.1.3.2 above).
MANDATORY Specifications: SDF Comments: Note that this data item is usually also included in the standard timing view of the VC. Indicate None in the SI Requirements Document (Section 2.4) if no instances exist. 2.1.5. Logical data Logical relationships among the interface signals, where available, can help make the timing and noise analyses less conservative by allowing the use of mutually exclusive signals as relative shields, thus enabling easier convergence of the design. This allows MCFs of 1 to be used between the coupling
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mutex signals (i.e. signals that are mutually exclusive logically, for example, phase separated signals), rather than the more conservative MCFs used for pairs of wires without guaranteed temporal separation. In a similar vein, one-hot signals (i.e. sets of signals such as the outputs of decoders that are guaranteed to have at most one signal switching at any time) can also be used to make the timing and noise analyses less conservative. 2.1.5.1. Mutex/One-hot relationships required between input signals These are logical and phase separation relationships among the input signals exploited by the VC designer that must be enforced by the VCs external environment. (Also see 2.1.4.3 above). MANDATORY Specifications: Document. Comments: Pathmill CFG files could also be used. Indicate None in the SI Requirements Document (Section 2.4) if no instances exist. 2.1.5.2. Mutex/One-hot relationships available between output signals These are logical and phase separation relationships available among the VC output signals that are available for the chip integrator to use as a substitute for explicit shielding or to enable tighter timing analysis. (Also see 2.1.4.2 above). MANDATORY Specifications: Document. Comments: Pathmill CFG files could also be used. Indicate None in the SI Requirements Document (Section 2.4) if no instances exist.
2.2
Signal Electromigration
Overview The specifications that follow are restricted to simple electromigration checks based on current density limits. The approach is to determine the current densities across each wire segment, and then to apply limit checks to determine if the segment fails for electromigration. In order to perform electromigration checks, VC authors and integrators need to have information on metal layers, wire segment size, and positions. Figure 3 shows a simplified model of the specifications required for signal electromigration checks by the VC integrator. VC authors must provide driver and load models along with the switching characteristics.
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Signal Net - varying current densities
Driver Model
Load
w l
Wire Segment
Figure 3: Simplified View of Model for Signal Electromigration 2.2.1 Electrical Data
Electromigration checks require the knowledge of complete circuit behavior. Apart from the general electrical parameters like drive impedance, receiver load, and wire parasitics, the following information must be specified. The unidirectional currents have non-zero DC currents causing electromigration due to DC current stress. Hence, DC current limits need to be specified. An electromigration failure due to wire self-heating also happens, due to bi-directional currents. These are mainly specified using the peak- and RMS AC-current limits. MANDATORY Specifications: Document, describing Average, Peak, RMS, width-dependent ACand DCcurrent density limits for each metal and via layer. Temperature dependency of these limits may be included as well. Comments: Note that these current density limits are generally process-specific data. The VC author must ensure that the wiring within the VC is sufficient for the maximum receiver load. Alternatively, the VC author may specify the maximum load on the receiver to ensure electromigration checks by the integrator. In addition to specifying maximum load for individual outputs, it may be necessary to specify maximum total receiver load for the VC. The latter is intended for the situations where individual output load are within the specified limit but their total load is large enough to cause electromigration violations on signal or supply wiring within the VC. MANDATORY Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
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2.2.1.1.1 Current Density Limits on Metal and Via Layers
2.2.1.2 Maximum Load for Electromigration Limits on Outputs
VSI Alliance (IMP 1 2.0) Specifications: VC Hspice. The input slew rate defines the switching rate within I/O and cells. Limits must be defined, such as how fast an input signal can switch to avoid electromigration-related problems in VCs. RECOMMENDED Specifications: Document. Comments: SDF (the maximum transition time specified) could also be used. For more accurate
modeling, a more sophisticated input waveform description could be considered.
2.2.1.3 Maximum Slew Rate for Electromigration Limits on Inputs
The switching factor defines how consistently the signal switches within a given clock cycle. The factor is defined as the average number of switches per clock. The currents in the nets are dependent on the switching factor at both inputs and outputs. Note that there could be multiple clocks within a given block, so it is necessary to specify a maximum switching factor. RECOMMENDED Specifications: VC Hspice. Comments: Specifying complete input waveforms can derive the switching factor (although this requires
more sophisticated models).
2.2.1.4 Maximum Switching Factor
The drive strength of the output drivers of an VC needs to be modeled. With this information, the nets connected to the output pins can be verified in context. The drive strength model could be a simple linear model, but more sophisticated descriptions are often necessary and should be considered. MANDATORY Specifications: Document. Comments: Synopsys .lib could be used if input capacitance is not voltage-dependent. This information
should be shared with the noise models.
2.2.1.5 Drive Strength
Input load is required to enable verification of the nets connected to the input pins of a VC in context. Typically, this information is already contained within the timing models. MANDATORY Specifications: Document. Comments: Synopsys .lib could be used.
2.2.2 Physical Data
2.2.1.6 Input Load
The required data includes all geometrical information for the signal nets, including net names, wire segment positions, and layer information. In order to protect the VC physical data, information about the input and output nets of an VC, together with the load and input slew rate information, should be sufficient to enable electromigration checking for the integrated VC. MANDATORY Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
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VSI Alliance (IMP 1 2.0) Specifications: GDSII. Comments: The physical information required can be derived from GDS, but should be preprocessed in order to enable a simple and consistent usage. It is recommended to use extended Spice equivalent binary format containing connectivity information and parasitic RC information, including layer and wire-segment size and position. No standard exists for this format.
2.3
Supply and Ground Grid Noise and Electromigration
2.3.1 Overview In this section, specifications are provided for dealing with supply and ground grid noise and electromigration. See Section 3.2 for a detailed discussion of these issues. 2.3.2 Electrical Data Specification
2.3.2.1 Specification Requirements for Static Power Model
Internal supply and ground grid model. Only a resistance model is required. The model can be simple and highly reduced, up to a complete R extract of the supply and ground grid. The VC creator will supply the model or models. There could also be a series of models with increasing complexity, allowing the integrator to select the most appropriate one for a given stage of the design cycle. The integrator will build an R network for the complete system power grid using these models and the supply and ground connectors, which determine the connection to the supply and ground grids. The resistance model will define the electrical behavior between the supply and ground connectors. Comments: A binary format compatible with an RLC model is required. The model must contain resistance data, connectivity, and geometrical data, including layer information. There is currently no standard covering the proposed format. A commercial example is the power grid libraries by vendors such as Cadence Design Systems (formerly Simplex Solutions). Minimum and maximum voltages, which must be applied to supply and ground ports to ensure correct internal operation. The minimum voltage should be defined for different conditions. For example, there should be a minimum worst case DC voltage and a minimum average supply voltage. This information allows validation at VC boundaries. Spatial distribution of the minimum voltages within a VC must be provided in order to ensure proper operation. Define areas within the VC, where the VC requires a minimal voltage. If it is allowed to collapse the area into a single point (a device contact), then the VC creator can decide which resolution is required. On the other extreme, the VC creator may decide to provide only one value for the whole area of the VC. The information may be used in early design stages such as floorplanning, but is required during physical verification. This enables validation of the VC in design context. Spatial distributed maximum voltages for ground nets must also be defined. Comments: In the future, a binary format is required, consistent with the internal supply and ground grid model. Currently, no such standard exists.
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Static spatial power consumption model. In order to consider the effect of the system power distribution network on the behavior of a VC, the spatial distribution of the power consumption within a VC needs to be modeled. For standard cells, a uniform distribution may be sufficient. However, for larger VCs, the distribution will affect the IR drop distribution within the VC, depending on the resistive path from each supply and ground port (connector) to the supply and ground pads. The power consumption model must include the information where the power sinks are connected to the supply and ground grid. The power consumption model should also include the average device capacitance existing between supply and ground grids. (See Figure 4.) Several power consumption models may be supplied with the VC, describing average- and peak-power consumption. Comments: The model will potentially contain a large amount of information, so a binary file format is preferable. Currently no standard exists. Note: It is assumed that power consumption is independent of voltage drop, in order to simplify the modeling. For standard cells or other small VCs, the power consumption model and the definition of spatial distribution of the minimum supply and ground noise (or minimum supply voltage) could be simplified.
MANDATORY Specifications: Document. There could be a simple format defining current sources for each consumer, but the file format would have to be upward-compatible with the dynamic spatial power consumption model.
2.3.2.2 Specification Requirements for Dynamic Power Model
For internal supply and ground grid models, the approach is equivalent to the static power model described in Section 2.2.2.1. However, an RLC model rather than an R model is required to model the dynamic behavior of the supply and ground grid. The RLC parasitics can be derived from the layout data. The minimum and maximum voltage supply are the same as in the static model. The spatial minimum and maximum voltages are the same as in the static model. The time-varying spatial power-consumption model includes time dependency. Rather than using a time-independent power model, this model has time-dependency, which allows a more accurate representation of power consumption within the VC. The dynamic power-consumption model captures effects such as simultaneous switching. The generalized power-consumption model should also include the time-dependent device capacitance between supply and ground grids, as shown in Figure 4. The current source is used to model the power consumption of a device or cell, and can be constant or time varying. The generalized model also contains a time-varying device capacitance in series with a resistance modeling of the shielded signal-line capacitance.
MANDATORY Specifications: Document.
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Figure 4: Generalized Power Consumption Model
2.3.3 Physical Data As described in Section 2.2.2.1, it is necessary to preserve the geometrical shapes of the power ports for a VC. For validation and inspection purposes, it is also necessary to retain an abstraction of the layout information for the VC internal supply and ground grid.
2.3.3.1 External Geometrical Data of the Supply and Ground Nets (Supply and Ground Ports)
The specification must contain information about the geometric shape and the location and layer of all power ports to a VC. The VC author will assume that they connected to the power grid when the VC is integrated into a system. The geometrical data must be taken into account when the system-level supply and ground-grid network are created. MANDATORY Specifications: VC LEF. Comments: Annotated GDSII should be considered.
2.3.3.2 Internal Geometrical Data of the Supply and Ground Nets
The internal supply and ground grids are modeled internally as a RLC netlist or a simplification thereof. The electrical model must retain geometrical and layer information in order to enable electromigration checking within the VC. This validation is required for the VC within the design context. MANDATORY Specifications: This information is specified in Section 2.2.2.2. The internal supply and ground grid models must contain the connectivity information between the internal supply and ground grid with the supply and ground ports of the VC. 2.3.4 Timing Data This section discusses timing variation on the I/O of the VC caused by supply and ground noise. Timing violations may be the cause of internal failures, but they are not seen as timing errors from the outside. Conversely the VC may be functionally correct internally, but timing variation of the I/O could cause a failure in the system in which Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
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VSI Alliance (IMP 1 2.0) the VC is placed. It is the responsibility of the VC creator to take into account the timing variation caused by internal activity within the VC. The effect could be caused by an IR drop in the internal power grid, or by coupling between signal nets. Information may be provided about the timing variance in the clock characteristics within the VC due to its internal power and ground noise. Clock skew and jitter often result from these supply and ground level variations. The VC creator must obtain worst-case numbers when characterizing the VC. Usually only a large block has sufficient internal power routing for this to be an issue. For standard cells, the IR drop in the power grid is external to the VC. After integrating a VC into a system, the IR drop in the supply and ground grid to the VC will cause timing variation, such as increased cell delay. There are several options to model this. First, the timing model can have a voltage input, such that the voltage supplied to the VC is a variable in the timing arcs of the VC. This would be practical for standard cells, where transistors are close to the supply and ground connectors. But for large VCs with a complex internal supply and ground grids, it is more difficult to obtain a simple voltage relationship, and a different approach is required. Second, the VC author can create a whole series of timing models at different voltages, such as the support supply range. The integrator will need tools to select the closest timing model for a given voltage, or will have to extrapolate between two models. Third, the VC author may provide the signal edge placement characteristics or timing variation as a function of not just the inputs, but also as a function of the supply and ground levels separately rather than just the difference.
2.3.4.1 Variation in Timing on Output Pins (Delay and Edge Rates) Due to IR Drop in Power Grid
For output pins (or I/O pins driving out), the variation in timing will affect output delay (CLK to output transition), as well as edge rate or slope of the transition. MANDATORY Specifications: Document. Comments: Synopsys .lib could be used. Potentially, ALF should be considered.
2.3.4.2 Variation in Timing on Input Pins (Setup and Hold Time) Due to IR Drop in Power Grid
As with input signals there is variation for setup and hold time. RECOMMENDED Specifications: Document. Comments: Synopsys .lib could be used. Potentially, ALF should be considered.
2.3.4.3 Variation in Timing due to inductive noise
Supply and ground noise can be caused by the lumped inductance and capacitance associated with the power grid. The voltage noise induced due to this effect can be Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
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VSI Alliance (IMP 1 2.0) approximated by Delta-I * sqrt(L/C). Depending upon the inductance contributed by the supply and ground pathways, this may appear as a supply droop, a ground bounce, or a combination of both. For high-performance VCs, this noise may result in functional system errors. A high-performance VC author may thus choose to include a corner-case model for comprehensive verification of the VC functionality in the presence of inductance noise. To this end, a time- and voltage-dependent power consumption model, the lumped power loop inductance in the supply and ground paths and the VC de-coupling capacitance between supply and ground can be used to compute the resulting supply noise. Timing models that capture the independent effects of varying the two supply nodes can be used to detect potential errors. CONDITIONALLY RECOMMENDED Specifications: Document describing model and its usage. Comments: .lib and ALF could potentially be used. 2.3.5 Multiple Power Supplies for Analog Blocks, Multi-Vt Circuits, and Pads MANDATORY Specifications: Document the proposed modeling approach, which can be applied for blocks with multiple power supplies, such as analog blocks, multi-Vt circuits, and pads. Comments: The model content must capture each supply and ground grid within the VC. It is assumed that multiple power supplies can be individually described and verified with the proposed approach. 2.3.6 Supply and Ground Electromigration Verification The proposed modeling approach enables verification of IR drop and electromigration. When the VC is placed in a system, the geometry of the global supply and ground net can be calculated. Together with the internal supply and ground grids of all VCs, the current distribution in the supply network can be calculated. Based on the current distribution and physical information, the current densities can be derived and compared to process limits. Unlike signal electromigration verification, where mostly AC current density limits need to be considered, DC current density limits must be considered for supply and ground grid electromigration verification. Electromigration verification should not only consider current density limits, but should allow for statistical budgeting based on mean-time-to-failure (MTF). MANDATORY Specifications: Document; the current density limits specifications must conform to the current density limit specification for signal electromigration. Comments: Model parameters enabling the calculation of MTF, such as parameters used in Blacks equations should be specified. Simple text format can be used to define the process-dependent electromigration parameters.
2.4
Substrate Noise and Coupling

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VSI Alliance (IMP 1 2.0) 2.4.1 Overview In this section, specifications are provided for dealing with substrate noise and coupling. See Section 3.3 for a detailed discussion of the issues and design guidelines. 2.4.2 Electrical Data An impedance model connecting all noise sources with substrate access ports describes a block electrically. Either current or voltage in time or frequency domain can be used to describe sources. If only a transient or harmonic model is available, it should be accurate enough to allow for conversion with Fourier transform. On the one hand, transient information is necessary for mixed-signal applications. For example, when integrating an ADC in a noisy digital environment, the noise level just before and during sampling of analog data is important. A small noise level during this time can significantly degrade performance. Outside this critical gap, noise immunity is much greater. On the other hand, it is sometimes more relevant to describe how noise varies with frequency. This is typically the case when RF blocks are integrated in a SoC design. In the case of an LNA, a small noise falling in the frequency band can deteriorate the noise figure dramatically, while twice this noise level is likely to have no impact outside this frequency band.
2.4.2.1 Block-level Impedance Model
A block-level impedance model should include impedances between substrate access ports and ground and noise sources. As an example, this model can be provided in the form of a Spice netlist. For a victim access port, this model can be as simple as a single component. The componentresistor or capacitoris connected between access port and ground. In addition, for an aggressor access port, the model must include the internal noise source. MANDATORY Specification: VC Hspice. Comments: At the moment, the example proposed previously does not fit with the physical description and the design guidelines for integration. The impedance model does not describe the connection from access port to substrate. That is, an access port is by definition directly connected to the substrate. A better example is being developed to explain how the impedance model is used to represent how the circuit (the device bulks and power supplies) is connected to the substrate.
2.4.2.2 Noise Sources for Aggressor Access Ports
Noise sources can be split into device and supply noise. On the one hand, device noise is produced inside the VC block by switching devicesthrough capacitive coupling or impact ionization. On the other hand, supply noise is generated at the system level by the sum of currents flowing through the power supply grid (as dynamic IR drop) or through package inductances (power-supply bouncing). Power-supply noise requires system-level modeling. Device noise sources are described as either Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
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VSI Alliance (IMP 1 2.0) independent-voltage or current For each source, one of the following items must be provided:

sources.
Static noise information. In this case, noise level is assumed constant and independent of time or frequency. Transient noise information. This could be provided as a PWL description using Spice syntax. A timing reference must be provided to allow for correct summation of all access port contributions. The time reference could be provided as a delay with respect to clock edges. Harmonic content. This is difficult to describe using standard Spice syntax. One suggestion is to have the block author provide detailed Fourier data. A second proposition is to deliver a PWL representation with respect to frequency. For some simple cases, such as a VCO, a single sinusoidal source or a set of sources can be used to represent noise. In any case, noise is represented by either magnitude and phase, or by real and imaginary parts.
MANDATORY Specification: VC Hspice. Comments: The choice of Spice format seems straightforward for the impedance model. It should also be sufficient to describe constant noise sources and time-dependent sources. Nonetheless, there is no easy way to describe harmonic sources. Noise sensitivity on victim nodes can be provided as a Spice comment using a specific format that is yet to be defined.
2.4.2.3 Maximum Allowed Noise for Each Victim Access Port
For each block model, the maximum allowed noise level can be specified in the form of branch current or node potential. This data can be provided as a constant static value, or as a dynamic representation using transient and frequency dependence. A constant value represents the maximum noise threshold that a victim port might sustain. However, using a constant sensitivity threshold might be too conservative, and can lead to unfeasible designs. Dynamic sensitivity description should be preferred for best integration flexibility. For specific victims, such as the sample-and-hold stage in an ADC, the maximum allowed noise varies with time. In such a case, the acceptable noise level should be provided as a function of time, with respect to an author-specified clock edge. Some victims are more sensitive at certain frequencies. This is typically the case for RF blocks. For such applications, a description of sensitivity as a function of frequency is required. MANDATORY Specification: VC Hspice. Comments: This choice seems straightforward for the impedance model. It should also be sufficient to describe constant noise sources and time-dependent sources. Nonetheless, there is no easy way to describe harmonic sources. Noise sensitivity on victim nodes can be provided as a Spice comment using a specific format that is yet to Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
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VSI Alliance (IMP 1 2.0) be defined. 2.4.3 Physical Data Physical information is fully characterized by attaching connectivity informationsuch as net nametogether with geometrical shape and doping profile for each access port. Depending on the hierarchical view (transistor, gate, or system level), a substrate access port can represent the bulk connection of either a single device, a logical gate, or a functional block. Access ports can also be placed in different substrate regions, such as default substrate, n-well, deep n-well, and triple-well. This requires specific data sets to connect region geometries with doping information as well as biasing conditions. Figure 5 illustrates an example of physical data. Regions are labeled R1 through R4, and substrate access ports (SAP) are named SAP1 through SAP6. The lower-right corner holds analog functions protected by a triple-well (R3). SAP4 represents the bulk of a sensitive device. SAP3 contacts R3 to an analog power supply. R1 corresponds to a guard band connected to ground through SAP5. The noisy section is made up of three areas. First, noise is injected through SAP1 (such as a large MOS buffer) and SAP2 (such as ground bounce on a power supply). Second and third, R2 and R4 are floating wells protecting sensitive circuitry (such as switched capacitors), while R4 includes important lateral resistivity variations that are modeled by SAP6.
Region SAP6 SAP1 R4 SAP2 SAP5 1 2 3 4 SAP 1 2 3 4 5 6
Doping Profile N-Well Deep N -Well Triple -Well N-Well Doping Profile Diffusion Contact Contact Diffusion Contact Contact
Bias 3.3V 1.8V 0V, 1.8V 1.8V Net Name N1 N2 G1 S3 G2 --
SAP3 R2 R1
Block Geometry Region Substrate Access Port
R3 SAP4
Figure 5: Physical Data Examples 26
VSI Alliance (IMP 1 2.0) Figure 5 shows how the combination of substrate regions and substrate access ports (SAP) describe the structure of the substrates. Shape geometries (coordinates) are not included.
2.4.3.1 Regions
Regions are used to define global change in doping profiles. Typically, a region indicates how many PN junctions are stacked vertically in specific locations of the block. Vertical superposition of PN junctions identifies the types of wells, such as a single well or triple well. A region characteristic is therefore the doping data. In addition, one needs to account for the actual PN junction biasing that affects substrate parasitics. One set of biasing information must be provided for each vertical stack of PN junctions. Hence, a triple-well structure is described with two bias voltages. Region bias is provided with geometry information, although this information is electrical in nature. This is because biasing does not inject noise, but it does impact the RC substrate model similar to the way geometry does. MANDATORY Specification: Document. Comments: Annotated-GDSII Format (AGF) can be used for geometry, along with cross-reference files for electrical and technology data. Although GDSII is a well-established format, there is no standard for the annotated version. It may be necessary to select the most popular version from among several different versions. One issue is cross-reference with technology data, as end users are unlikely to get doping information from the foundry. Nevertheless, commercial solutions exist for extracting substrate parameters from doping profiles. Each profile is represented in the substrate parameter file with a dedicated data subset and a specific identifier. Cross-referencing technology data with AGF therefore attaches each region shape with a profile identifier from the substrate parameter file.
2.4.3.2 Substrate Access Ports
This dataset provides geometrical shapes, a doping profile identifier, and a net name for each access port. Geometry is used to localize the access port. It is described in a 3-D coordinate system. This is necessary when a VC abstraction includes a significant vertical portion of silicon. When this is the case, lateral sidewall noise transfer needs to be taken into account. Sidewall access ports are necessary if the VC author needs to hide how technology has been used, such as to implement proprietary substrate protection techniques. When process information must be hidden, a significant vertical portion of silicon is embedded inside the VC description. Moreover, doping profile information attached to substrate access ports starts several microns below the interface between oxide and silicon. Therefore, significant current flows through the VC sidewalls, and specific access ports are required to capture this effect, as illustrated in Figure 6.
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VC electrical model provided by author
VDD
VN
VSS
SAP1
SAP2
SAP3
SAP4
Sidewall access port
SAP1 SAP2 SAP3
SAP4
Bottom access port
Bulk substrate modeled at system
-level by integrator
Figure 6: Using Sidewall Substrate Access Ports to Connect to VC Noise Model
Doping profile information identifies the substrate depth at which the VC is connected to the system substrate. This also provides information about vertical doping variations, starting from the bottom access port. This is necessary to account for strong resistivity gradients, for instance with surface and buried implants. Doping data also provides a clear description of PN junctions. Net name information makes the connection between geometrical and electrical data possible. It is not necessary to have a net name associated with all access ports. Some access ports might only be provided to account for lateral doping variations, such as shown by access port SAP6 in Figure 5. MANDATORY Specification: Document. Comments: See Section 2.3.2.1.
2.5
SI Requirements Document
The SI Requirements document contains three sections that are equivalent to sections 2.1, 2.2, and 2.3 in this specification. These sections of the SI Requirements document should contain suggested alternatives to the deliverables described in sections 2.1, 2.2, and 2.3 of the SI specification. Every section and sub-section should exist, and if no documentation or data is available, the appropriate indication of None should be specified. MANDATORY Specification: Document.
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3. Design Guidelines
3.1 Interconnect Crosstalk (Voltage Noise and Delay Variance)
Interconnect crosstalk can be defined as any deviation from the ideal signal waveform propagating in an interconnect wire caused by signal transitions in other wires in the neighborhood. This influence is currently primarily due to the capacitive coupling between the victim net and one or more aggressor nets, although inductive coupling is also beginning to show up as a problem in cutting edge custom designs. Since ASIC and SoC designs tend to lag cutting edge custom designs by a generation or two, inductive noise is not yet a major problem for these designs. Therefore, this document focuses solely on capacitive crosstalk, since it is felt that the detailed analysis of inductive noise in the context of SoC designs over the next few years will be important only for power grid and clock design, with inductive noise in signals being adequately controllable by a fine-grained template power grid. Capacitive crosstalk is manifested either as a degradation of interconnect delays resulting in a lowered operating frequency for the chip, or in outright failure of the chip. When two neighboring signals transition simultaneously, they can affect each others slew rate (and consequently, transition delay) depending upon their transition directions, relative driver strengths and wire parasitics. Thus, two signals transitioning in the same direction will tend to speed each other up, whereas two signals transitioning in opposite directions will slow each other down. Delay degradation on critical nets can lower the operating frequency of the chip appreciably. This is in contrast to the failure effect of crosstalk that causes the chip to fail even at lowered frequencies. The failure effect is caused by the voltage pulse induced on a quiescent victim net due to one or more aggressor nets switching in its neighborhood. This pulse can cause failure due to spurious transitions in non-restoring logic such as domino circuits. Failure can also occur due to hold time violations in sequential elements caused by signals being sped up due to crosstalk, or these accelerated signals racing through open latches or asynchronous interfaces. The delay degradation and failure impacts of crosstalk are depicted in Figure 3.1.1.
Noise
pulse
Coupling Delay
Figure 3.1.1: Crosstalk due to a switching aggressor net on a neighboring (quiescent or switching) victim net. (The signal transition in the aggressor is shown in red and labeled A, whereas the (non-distorted) signal in the victim is shown in blue and labeled V.)
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The problem of interconnect crosstalk is getting worse with each process generation, mainly due to the non-ideal scaling of wires. Since wires grow relatively narrower and taller with each generation (in order to keep their resistance manageable), the ratio of the coupling capacitance of a wire to its total capacitance is increasing with each generation. Although the move from aluminum to copper can halt this deterioration for a generation, successive generations will again have to tackle the same issues. Therefore, it is becoming increasingly important to account for coupling during timing and noise analyses. Besides forcing the timing analysis to deal with considerably more data (on neighboring nets), the unpredictability of the transition state of neighboring nets also has the secondary undesirable effect of widening the transition windows of the signals. Furthermore, the larger error margins required in successive generations because of larger fractions of the total capacitance being (unpredictable) coupling capacitance also makes the convergence of high performance designs more and more difficult. Unlike digital designers, analog designers have already been worrying about interconnect crosstalk for years. The signal waveform distortion caused by crosstalk can often cause analog circuits to fail. This problem is especially acute in symmetric analog circuits such as sense amplifiers and current mirrors. On the process technology front, the number of layers does not have much of an impact on the capacitive aspects of crosstalk noise (because of the relative shielding provided to a layer by adjacent layers). However, with increasing layer count, the analysis of current return paths and inductive noise becomes more complicated. Difficult as the crosstalk problem is for traditional ASIC and custom designs, it becomes even more critical for SoC designs because of data hiding issues arising from VC protection concerns. As a result, much of the detailed data for signals within a VC desired by the chip integrator to analyze and optimize OTH (over-the-hierarchy) global signals cannot be made available by the VC author, resulting in conservative design frequencies and increased challenges during design convergence. Indeed, the visibility required into the VC by the integrator in order to create a noise-safe design would at times involve a fine tradeoff with VC protection issues. However, fortunately, it is often possible to reveal the electrical/physical/timing information for a wire and its driver and receiver(s) without divulging any logical information about them. The goal here is to present a simplified yet reasonably accurate model for the VC while still preserving its gray/black box nature. Another issue worth keeping in mind is that even approximate signal integrity analysis involves dealing with huge amounts of data; therefore, it is important to strike a balance and specify parasitic and other data only for nets that are truly at risk for noise-problems. Furthermore, it is desirable to communicate this data in the least amount of detail that can be effective; thus, for instance, the geometric view of a potential victim net in a VC should be communicated through flylines corresponding to its major trunks, rather than through a complete list of polygons that constitute the routing of the net. At the same time, the VC author should identify and communicate any data within the VC that can be exploited by the chip integrator to make the global convergence easier. The basic approaches to handling crosstalk noise are either by controlling the signal slew (by driver/receiver sizing or repeater insertion), or by reducing the ratio of bad coupling capacitance of a net to its total capacitance (by wire engineering). The first approach is usually used for timing optimization of the circuit, with its noise optimization being a secondary objective function, whereas the second approach is used specifically for noise optimization when the sizing and repeater insertion is insufficient by itself to overcome noise effects. Wire engineering can include techniques like the insertion of additional Vdd and/or Vss wires for use as shields, permutation of the order of the signals in a routing region to exploit logically or temporally exclusive signals as relative shields, wire spacing, and, to a smaller effect, wire tapering. Since exact analysis and optimization of each wire is often too expensive to be practical (and is often not possible across the boundary of the VC due to lack of visibility/information about neighboring wires), coarse level techniques like reserving an entire layer as a shielding layer around the VC, or identifying specific no-fly zones above the VC can be used. Furthermore, feedthroughs (due to OTH wiring) in layers that are also used by the VC may be restricted to tracks that have been explicitly reserved for them and certified by the VC author as being safe (rather than being routed opportunistically wherever tracks are available). In general, since coupling is only
30

going to get worse with shrinking geometries, it is more important to have a correct-by-construction design style that focuses on reducing coupling rather than relying on measuring it accurately and then fixing problems as they occur. As mentioned earlier, capacitive crosstalk can be handled at each stage from pre-layout sizing to global routing to detailed routing. Generally, crosstalk problems are difficult to identify but easy to fix early on. In contrast, they become much easier to identify as one moves down the physical design flow; however, there is correspondingly less flexibility available to fix them at these later stages.
3.2 Inductance Effects

In addition to parasitic capacitance, interconnect inductance can impact signal integrity in high performance custom designs. Although detailed analysis of inductive noise in the context of SoC designs over the next few years will be important only for power grid and clock design, fast inductance analysis of all signals can serve the same purpose as fast noise analysis (using filters). Parasitic interconnect inductance tends to speedup signals, leading to faster slew rates, and also introduces undershoots/overshoots which deteriorate monotonicity and integrity of the signals as shown below. Inductive crosstalk is a secondary effect, and usually affects signal integrity to a lesser degree than capacitive crosstalk.
RC RLC
If the victim is silent, inductive crosstalk will add-on in magnitude to the capacitive crosstalk, while intially delaying the signal. This inductive behavior is depicted below. When both victim and agreesor signals are active, the inductive crosstalk will be either positively or negatively correlated with the caapcitive crosstalk, depending on the relative switching directions of the two signals.
A RC RLC V
The inductance impact gets worse with the use of wider and longer metal interconnects, reduction in metal resistance due to use of copper and higher frequency operation. Thus, it is necessary to model inductive effects, particularly for critical, global signals in high performance VLSI designs. 31
Inductance Modeling & Analyis Inductance is a property of a current loop/path, instead of a single wire. Thus, to accurately measure and model the inductance for a signal, it is necessary to know the current return paths during switching. However, given the complex mesh of power/ground networks in VLSI designs, and the wide array of parasitic effects resulting from such structures, it is virtually impossible to predict the current loops for any signal. This is the over-riding difficulty in analyzing inductive effects. A variety of academic and industry tools and methodologies have been proposed to extract, model and analyze inductance. Existing timing analysis tools cannot accurately model inductive effects, since they do not model power/ground return paths, and since inductive coupling is not a local phenomenon like capacitive coupling. With increasing layer count, the analysis of current return paths and inductive noise becomes more complicated. VC From the VC perspective, inductive crosstalk is subject to the same concerns as capacitive crosstalk namely, data hiding issues, SoC integration, amount of data, etc. As with the capacitive crosstalk, the goal is to present a simplified yet reasonably accurate model for the VC while still preserving its gray/black box nature. Minimizing Inductive Effects
Inductive effects can be minimized either by controlling the return paths (by inserting power/ground shields), or by reducing the effective inductance (by splitting up wide wires, running shorter interconnect lengths between repeaters, etc). Shields are effective solutions for critical global signals such as clocks, where the additional shield metal utilization and routing resources are worth the large benefit obtained for signal integrity issues. However, for general signals, shields are an expensive option. Instead, the designer must limit wire widths and lengths (by inserting periodic repeaters) to minimize inductive effects. Wide busses are particularly susceptible to inductive crosstalk. For such topologies, the best approach is to insert periodic power and ground shields between bunches of bus signals. This provides close-by return paths for the signals, thus reducing area of the current loops, thereby minimizing inductive noise.
3.3
Signal Electromigration
Due to increases in operating frequencies and current densities along with decreasing metal widths, electromigration has become a major challenge. Electromigration is a phenomenon of accumulation or depletion of material as a result of a large surge or repeated surges of current through a wire segment. The phenomenon can result in change in wire resistances (either for supply, ground, or signal net) or cause functional failures due to disconnections or shorts in signal nets. This section focuses on signal electromigration. Signal electromigration eventually leads to electrical failure, thus reducing the circuit lifetime, and, hence, the reliability of the design. Several different types of failures can be caused on the interconnect due to electromigration. A failure could be the result of the micro-structural properties of the material (of conductor). This is random in nature, and needs to be dealt with using statistical models. A different type of electromigration failure could be the result of a local thermal process, Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
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VSI Alliance (IMP 1 2.0) that is, a failure due to a change in the temperature in a segment of the interconnect. The thermal process is typically the result of an increase in the current density of that segment. The current density in a wire segment depends on the characteristics of the driver and the wires switching characteristics. (See Figure 3.) The switching information also defines the direction of the current flow. The current crowding in a wire segment results in thinning of that wire segment (as shown in Figure 3). This increases its resistance, resulting in higher voltage drop, more power dissipation, and local heat-up. This further accelerates the process of thinning, causing the wire segment to finally break. There are various sophisticated models (still under study) that predict the time-to-failure due to signal electromigration. A simple approach for VC authors and integrators is to restrict to simple current-density limit checks on each wire segment in the interconnect. In addition to widening wire width, a simple but effective measure to improve electromigration property is to maximize the number of contacts and vias placed on a junction of two different wiring layers (as layout rule allows). Multiple vias or arrays of vias increase reliability by providing redundancy when some of them fail.
3.4
Supply and Ground Grid Noise and Electromigration
The supply and ground grid are the wires or tracks that supply power to all devices within a VC. Usually there are two nets, Vdd and Gnd, within a VC. For blocks with more than one supply and ground connection, multiple supply and ground nets must be supported in the context of noise and electromigration modeling. This specification is not restricted to VCs with physical layout, but also includes soft macros with layout generated on the fly. A parameterized model for this kind of VC is provided, and the model can be used to define the specification for the hardening of the VC. The VC can range from a single standard cell with a few devices to a complex CPU with many millions of devices. Although the focus is on digital VCs, the concept described below can be applied to analog VCs as well. The goal is to discuss the electrical interaction between VCs through the global supply and ground grid, and what information needs to be modeled to allow a VC integrator to construct and verify a top-level supply and ground grid that can supply the necessary power to all VCs. Two examples will be considered. First, a standard cell, which is typically a small VC with a simple logic function. Many thousands or even millions of these cells are placed in rows on a chip. Current can flow though each instance, but most of the current flowing through a standard cell is not used within the cell, but supplies power to other standard cells in the row. On the other extreme, a complex CPU core has a complex internal power grid with several external connections. Most of the power will be consumed within the block, although there might be a feed-through current. The consumed power will probably be state dependent. All VCs have power ports. Current is supplied through these ports to the transistors within the VC through the internal supply and ground nets. If there are multiple ports (which is commonly the case), current flowing through the VC between the ports must also be considered. If several VCs have their power ports wired to create global Vdd Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
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VSI Alliance (IMP 1 2.0) and Gnd nets, there will be complex interactions between all VCs. Each one draws current from the supply and ground grid, and causes current flow within internal supply and ground grids of other VCs. In the simplest case, this flow can be considered static or constant in time. The static model can be defined as a purely R network, plus average or worst-case power consumption within the VC. For improved accuracy, a dynamic model can be considered, which models internal switching and time-dependent currents. The dynamic model requires an RLC network with a description of the dynamic power consumption in the VC. 3.4.1 IR-drop in the Supply and Ground Wires (Grid) The VC creator will verify any physical VC, either in isolation or in a specific test bench, according to the VC creators design methodology. The VC creator will make assumptions about how the VC is connected to the global supply and ground network. However, when the VC is integrated within a system, the power-supply connectors will be connected to the supply and ground pads by a resistive supply and ground network. There will be a voltage drop through this resistive network, which will reduce the voltage seen by the VC. This IR drop might cause the operation voltage inside the VC to be too low to assure correct functional operation. To complicate matters, the voltage drop may not be the same for all ports. Also, within the VC, the supply and ground grids will be resistive, so there will be variation within the VC. The absolute IR drop as well as the variation of IR drop within a VC could become a cause for failure. In addition, current flowing through the VC to supply power to other VCs affects the IR drop within the VC. This all leads to very complex interaction between VCs. Consider a simple case of rows of standard cells, with the power being supplied at either end. The voltage drop increases toward the middle of the rows. Each standard cell requires a model of the resistance of the supply and ground wires through the cell. After the integrator has laid them out, the resistance of the row can be computed along with the voltage drop. The VC requires a minimum voltage value at which it will operate correctly. This value can be compared with the actual supplied voltage. The principle for larger VCs is the same. In the previous paragraph, it was assumed that other VCs on the global supply and ground grids do not draw current, so the voltage drop is caused purely by the resistance of the supply and ground grids and current flowing within the VC being considered. This is a simplified model, as other VCs have switching activity drawing current from the supply grid. Wherever a global grid connects VCs, activity in one VC causes current flow that affects the voltage supply of other VCs. This adds an extra level of complexity for the VC integrator. As an example, consider the row of standard cells again. The cells in the middle of rows see voltage-supply variation on their power connectors, depending on the switching of all the other cells between them and the external power supply. The effect is also visible in the opposite direction; that is, the cells at both outer ends of the row suffer from voltage variations, due to altering current caused by switching of the center cells. In order to enable the accurate modeling of the electrical behavior for supply and ground grid noise analysis the following information needs to be captured: Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
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The geometrical shape of the supply and ground ports for a VC. It is assumed that the P and R system can connect to the supply and ground network of the VC only through the supply and ground ports. A simplistic approximation is to define a resistor for each port, in order to capture the effect that each cell creates an IR drop due to the current flowing through the cells. However, this approach becomes inaccurate if ports are overlapped, or if additional routing is added to the ports as shown in Figure 8 and Figure 9. Therefore, it is advisable to retain the geometrical shape of the supply and ground ports within the model for a VC, in order to obtain an accurate calculation of the parasitic elements for supply and ground wires. The electrical network describing the supply and ground network within a VC, for example, the internal supply and ground grid. The electrical network can be extracted from the layout of the VC, and can either be described as a simple resistor network or extended to an RLC network in order to capture the dynamic effects. Power consumption, including spatial distribution within a VC. Consider the case of a row of standard cells as a VC. Each cell switches at a different rate driving a different load, so the power consumption in each cell is different. Therefore it is important, especially for larger VCs, to model the spatial distribution of the power consumption. A more realistic example of the average spatial power-consumption distribution is shown in Figure 10.
Global Route Supply Port of VC
Figure 8: Interaction Between Supply Port Geometries of VC and Global Routing
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Figure 9: Placement and Routing Configurations of VCs Affecting Parasitic Resistivity
Figure 10: Thermal Plot of Spatial Distribution of Power Consumption in a VC
3.5
Substrate Noise and Coupling
For substrate noise and coupling, each block acts as a noise source, a noise victim, or both. Noise generation and collection varies with block electrical characteristics functionality, architecture, topology, and so onas well as with fabrication technology. Noise transfer is a function of block physical placements together with the fabrication process. Therefore, communication between VC author and VC integrator must include electrical, geometrical, and technology information. Electrical information is essential for describing substrate noise. Nevertheless, substrate noise can be generated and collected by various means and in different locations of a single VC. Therefore, geometrical (or physical) and electrical data must be combined to model substrate issues correctly. This is achieved by describing each VC as a set of geometrical access ports, together with the electrical model connected to each access port. The electrical model might change from one fabrication process to the other. Therefore, technology information for which the electrical characteristics are valid must also be provided. Authors might need to hide a portion of the physical substrate within the VC model. Therefore, the physical data description must determine what substrate portion is included inside the VC model, and what part is left for modeling at the system level. In such a case, internal VC biasing can impact substrate current flow at the system level by modulating well depletion width. It is important that authors and integrators understand this issue. Either the author must ensure that well modulation is kept inside the VC model, or all required data must be provided to integrators to simulate the impact of VC bias changes on substrate flow at the system level. Optionally, to address accuracy versus speed trade-offs, authors might have to provide various hierarchical views for a single VC. For instance, a first view could associate one access port with each function while a second view could have more access ports corresponding to sub-functions. The first view is used to get a quick estimation of noise margins. This ensures that the VC works properly when the Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
36
VSI Alliance (IMP 1 2.0) estimated noise margin is large. When the estimated noise margin is very small, more accuracy is required to ensure that specifications are met. The additional accuracy is provided by the second access port view. Practically, hierarchical views might include transistor-, gate-, and system-level views.
3.6
Other Important SI Effects
The following list describes issues that are under discussion for future development of SI-related specifications and standards produced by the VSIA. These items will be addressed after this specification version has been released. Items for study, for possible inclusion in version 2.0 of the SI specification, include the following:
A flowchart for implementation of specifications, emphasizing integration with existing standard SoC flows. More focus on 0.13-micron processes and beyond, including issues such as EMI, hierarchical voltage drop, and multiple supply ground. An easy, standardized way of cross-referencing information in various standards without necessarily identifying the data logically. More discussion of the impact of inductance on interconnect crosstalk, and identification of the corresponding relevant data communication issues in SoC design. Support of emerging and existing standards, and their SI extensions, for example, ALF. Development of a unified model for a wire for VC input and output. Closer integration of SI work with the AMS and I-V documents. (See Section 1.2.5 for background on the current use-model of documents.) The specification information that may trigger intellectual property issues. For example, some signal strength requirements or physical information may reveal too much about a VC. Further refining of issues and specifications related to embedded voltage islands Identification of design sensitivity to various physical, electrical and timing specifications, in order to be able to make optimizations and correct decisions at system-level design and integration. Certain manufacturing processes like CMP and tiling impact crosstalk and noise significantly. It may be good to look at these issues in the future. Development of standardized (possibly parameterized) models for noise. An analysis of SI issues when some or all of the VCs are soft.
Other items for investigation include the following:
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Appendices
A. Implementation of Specifications on an Example Design A.1 Overview of SoC Design
The figure below shows an abstract view of the design that is used in this Appendix. A more complete description is found in [Lee99]. This design has been chosen due to its complex mixed-signal content. It is representative of the type of SoC designs that need SI specifications in order for the integration to be successful.
Micro-Controller
JTAG/HDS Sync Serial SIM Interface Async Serial Timer 1K x32 SRAM Programmable Interrupt Controller DMA External Bus Real Time Clock Customer ASIC ASIC Interface ADC PLL Vdd/Gnd C Core 8K x16 DPRAM 48K x16 Flash ECCP Timer Power DSP1600 Core
DSP
HDS Breakpoint / Trace PLL Vdd/Gnd
CSP
AFC DAC DAI Voiceband Vdd/Gnd Baseband
BMU
Programmable Peripheral Interface
CSP Interface Bio CSP Core
Vdd/Gnd
Serial CSM
PHIF
Vdd/Gnd
Figure 11: High-Level Block View of Example Design for SI Specification (Figure 11 is reproduced with permission from K. Lee, Lucent Technologies.)
Key analog and mixed-signal blocks in this design include the PLL, the serial and ASIC interfaces, DACs and ADCs, and all supply voltage-related circuits. These blocks can be both sensitive victims of noise sources and a source of noise themselves. The high level of integration of the chip is also a cause for concern with respect to supply-voltage degradation. Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
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VSI Alliance (IMP 1 2.0) However, the power supply level (around 3V) is somewhat high for todays standards, which may slightly simplify problems induced by supply voltage. Also, the chip contains multiple frequencies, which implies the availability of various harmonics that could interfere with each other through the substrate or interconnect. Finally, the presence of low-Vt devices in the design makes it more sensitive to input noise, both from performance and from power consumption. Thus, this is a very relevant example to illustrate SI-related integration issues and necessary standards. In order to minimize noise coupling through interconnects and the substrate between the substrate and digital sections, separate routing and multiple pins were used for the analog digital power and ground domains and substrate. Barrier wells were also created between the various analog blocks and digital blocks.
A.2
Examples of Deliverables
A.2.1 Interconnect Crosstalk (Voltage Noise and Delay Variance) A.2.1.2. Electrical data A.2.1.2.1. Maximum permissible noise propagating into input ports CONDITIONALLY MANDATORY Specifications: VC Hspice (for noise waveforms) Example: For the data/control busses between microcontroller, DSP, and CSP, specify the worst-case injected noise, in terms of:
- VC Hspice PWL model
A.2.1.2.2. Maximum permissible external (to VC) switching cross-coupling and effective aggressor slew for failure- or delay-critical sensitive nets (if any) inside VC
MANDATORY Specifications: SPEF to capture distributed coupling if required; else, a mere maximum permissible capacitance value for each sensitive net. Effective aggressor slew represented in mV/ps. Example: For each failure- or delay-critical nets inside the CSP, specify - Maximum permissible lumped coupling capacitance in fF OR SPEF description of maximum permissible distributed coupling capacitance, AND - the effective aggressor slew (averaged over all relevant aggressors) in mV/ps. A.2.1.2.3. Maximum noise possible at output ports (due to propagation/coupling inside VC) CONDITIONALLY MANDATORY Specifications: See specifications for 2.1.2.1 above. Example: For each output port of the microcontroller and DSP (mainly the data busses), specify worst-case noise generated by the VC, in terms of
- VC Hspice PWL model
A.2.1.2.4. Electrical characteristics for strong potential aggressors (for OTH signals) lying inside VC RECOMMENDED Specifications: VC Hspice for driver, SPEF for interconnect.
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Example: For each strong aggressor within the DSP, specify the worst-case electrical characteristics for - Driver using VC Hspice models, and - Interconnect using SPEF models A.2.1.2.5. Electrical characteristics for failure- or delay-critical sensitive nets lying inside VC RECOMMENDED Specifications: VC Hspice for driver, SPEF for interconnect and receivers Example: For each failure- or delay-critical nets inside the CSP, specify worst-case electrical characteristics for - Driver using VC Hspice models, and - Interconnect and - Receivers using SPEF models A.2.1.2.6. Best and worst case slew permissible at input ports MANDATORY Specifications: Document specifying min/max slew limits in mV/ns, possibly along with a VC Hspice model for the environment driving the port. Example: For each input port of the DSP, specify best and worst case slew, using - Slew limits in mV/ns - VC Hspice model for input driver
A.2.1.2.7. Best and worst case slew available at output ports (and its variation with load)
MANDATORY Specifications: Document specifying min/max slew limits in mV/ns, VC Hspice for driver modeling (to compute variation of slew with load) Example: For each output port of the DSP, specify best and worst case slew, using - Slew limits in mV/ns - VC Hspice for driver A.2.1.2.8. Maximum permissible load/distributed RC that can be driven by output ports MANDATORY Specifications: SPEF. Example: For each output port of the DSP (especially the data busses), specify maximum drivable load - SPEF model for distributed RC A.2.1.3. Physical data A.2.1.3.1. Location of failure- or delay-critical sensitive interconnect polygons inside VC MANDATORY Specifications: PDEF Example: For each failure- or delay-critical interconnect inside the CSP, specify location of route in PDEF format A.2.1.3.2. Location of strong potential aggressors (for OTH signals) lying inside VC MANDATORY 40

Specifications: PDEF Example: For each strong aggressor interconnect inside the DSP, specify location of route in PDEF format A.2.1.3.3 Location of top-layer/peripheral supply and ground wires inside VC MANDATORY Specifications: PDEF Example: Specify location of top-level supply and ground wires inside the microcontroller and DSP, in PDEF format (Note: The top metal layer could be different among VCs) A.2.1.3.4 No-fly zone or external shielding requirements MANDATORY Specifications: PDEF Example: Specify prohibition of external aggresors for the PLL block in the DSP/microcontroller, in terms of - Required OTH power/ground wires - Power/ground planes - Non-metalized blockages over the PLL using PDEF format A.2.1.3.5 Safe regions for OTH signals (possibly classified by slew) RECOMMENDED Specifications: PDEF Example: Specify constraints on global wires routed over the DSP, in terms of - OTH safe tracks - OTH safe regions A.2.1.4. Timing data A.2.1.4.1. Variation of timing arcs within VC with external crosstalk CONDITIONALLY MANDATORY Specifications: SDF (for delay variation range) Example: Specify the variation of a) Main frequency of the PLLs in the DSP/microcontroller b) MIPS for DSP c) Microcontroller pin-to-pin delays, with external crosstalk using either lookup tables or closed-form formula in text format, OR delay variation ranges in SDF format. A.2.1.4.2. Transition windows available at output ports MANDATORY Specifications: SDF Example: Specify the earliest and latest arrival times at the output ports of the microcontroller, DSP and CSP using SDF format A.2.1.4.3. Transition windows requiredat input ports MANDATORY
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Specifications:SDF. Example: Specify the earliest and latest arrival times assumed at the input ports of the microcontroller, DSP and CSP in SDF format
A.2.1.4.4. Transition windows for strong potential aggressors (for OTH signals) or failure/delay critical sensitive nets lying inside VC
MANDATORY Specifications: SDF Example: For sensitive or strong nets inside the DSP, specify transition (switching) windows in SDF format. A.2.1.5. Logical data A.2.1.5.1. Mutex/One-hot relationships required between input signals MANDATORY Specifications: Document. Example: Specify mutex relationships for the data/control busses between the microcontroller, DSP and CSP. A.2.1.5.2. Mutex/One-hot relationships available between output signals MANDATORY Specifications: Document. Example: Specify mutex relationships for the data/control busses between the microcontroller, DSP and CSP. A.2.2 A.2.2.1 A.2.2.1.1 Signal Electromigration Electrical Data Current Density Limits on Metal and Via Layers
MANDATORY Specifications: Document. Example: Specify both at the VC and block level and at the chip level. Specify Average, Peak, and RMS, width-dependent AC- and DC-current density limits for each metal and via layer.
A.2.2.1.2
MANDATORY Specifications: Spice. Example: For each VC output (especially for high-current carriers like PLL output), specify the maximum load to be driven, such that electromigration limits are not exceeded. RECOMMENDED Specifications: Document.
A.2.2.1.3 Maximum Slew Rate for Electromigration Limits on Inputs
Maximum Load for Electromigration Limits on Outputs
42
VSI Alliance (IMP 1 2.0) Example: For each VC input (especially for fast-switching control signals in CSP and DSP), specify the maximum slew rate expected, such that electromigration limits are not exceeded.
A.2.2.1.4
RECOMMENDED Specifications: VC Hspice. Example: For each VC input and output (especially for frequently switching signals in CSP and microcontroller), specify the switching factor, to measure the worst-case switching activity. MANDATORY Specifications: Document. Example: For all output pins of each VC, especially for pins related to global nets, specify the drive strength (using linear or more complex models) to allow the integrator to analyze the nets driven by the output pins. This enables the clock nets between the PLL and other VCs to ensure accurate top-level delay and skew analysis. MANDATORY Specifications: Document. Example: For all input pins of each VC, especially for pins related to global nets, specify the input load (using .lib format) to allow the integrator to analyze the nets loaded by the input pins. This enables the clock nets between the PLL and other VCs to ensure accurate top-level delay and skew analysis.
A.2.2.2 A.2.2.1.6 Input Load A.2.2.1.5 Drive Strength
Maximum Switching Factor
MANDATORY Specifications: GDSII. Example: GDSII data for physical location of important nets within each VC (such as PLL and DSP Core). A.2.3 Supply and Ground Grid Noise and Electromigration
A.2.3.1 Overview
Physical Data
(This section intentionally left blank.)

A.2.3.2 Electrical Data Specification A.2.3.2.1 Specification Requirements for Static Power Model
MANDATORY Specifications: Document. Example: Specify supply and ground grid models (with electrical and physical information) for digital VCs (such as DSP Core and Microcontroller Core), as well as Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
43
VSI Alliance (IMP 1 2.0) for analog VCs (such as PLL, ADC, and CSP filters). For each VC, this includes resistance models (ranging from equivalent impedance to complete multi-layer grid), minimum and maximum voltage (or IR drop) values, and distribution of voltages in space (and across metal layers, if possible). Also, each VC must have a power-consumption model, which facilitates easy and relatively accurate top-level power grid design and analysis. Note: Depending on the type of VC, the model details can vary significantly. For example, it is easier to provide an efficient supply and ground grid model for the DSP core, but more difficult to model the analog filters in the CSP. Similarly, current-consumption models for the microcontroller core are much harder to develop, due to their dependence on actual switching activity. However, it must be ensured that the VC model is easy to use at the integration level, so that chip-level power grid analysis is feasible.
A.2.3.2.2 Specification Requirements for Dynamic Power Model
Specifications: Document. Example: Each VC must have an RLC model instead of a R model. Extraction of L and C for supply and ground is easier for simple analog blocks, but much more complicated for DSP or microcontroller cores. The transistors in these cores provide a significant amount of device-decoupling capacitance, which affects supply and ground voltages. However, the extraction of this capacitance must be done under correct assumptions of switching activity.
A.2.3.3 Physical Data
MANDATORY Specifications: VC LEF. Example: For each VC, physical data is required for the supply and ground nets and ports to allow power-grid design at the chip level. For VCs containing a grid topology, the VC creator can provide topmost metal layer ports.
A.2.3.3.2 Internal Geometrical Data of the Supply and Ground Nets
A.2.3.3.1 External Geometrical Data of the Supply and Ground Nets (Supply and Ground Ports)
MANDATORY Specifications: This is specified in Section 2.2.2.2. Example: For each VC, physical data is required for the supply and ground nets and ports to allow power-grid design at chip level. For VCs containing a grid topology, the VC creator can provide topmost metal layer ports.
A.2.3.4 Timing Data
MANDATORY Specifications: Document. Example: Specify variation in timing for each VC output (such as clock skew and jitter for PLLs) due to IR drop in the power grid. This can be critical to circuit operation, Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.
44
A.2.3.4.1 Variation in Timing on Output Pins (Delay and Edge Rates) Due to IR Drop in Power Grid
VSI Alliance (IMP 1 2.0) especially for clock nets and critical control signals between VCs.
A.2.3.4.2 Variation in Timing on Input Pins (Setup and Hold Time) Due to IR Drop in Power Grid RECOMMENDED
Specifications: Document. Example: Specify variation in timing for each VC input (especially for data busses between VCs) due to IR drop in power grid.
A.2.3.4.3 Variation in Timing Due to Inductive Noise CONDITIONALLY RECOMMENDED
Specifications: Document. Example: Specify variation in timing for each VC input due to LdI/dt in power grid.
A.2.3.5 Multiple Power Supplies for Analog Clocks, Multi-Vt Circuits, and Pads
MANDATORY Specifications: Document. Example: Analog blocks (such as filters in the CSP and PLLs) might require the VC creator to specify multiple power-supply details, using the static- or dynamic-power models. The VC creator must also provide summary data, to distinguish between multiple supplies.
A.2.3.6 Supply and Ground Electromigration Verification
MANDATORY Specifications: Document the current-density limits. Specifications must conform to the current-density limit specification for signal electromigration. Example: For each VC (especially for VCs with high switching activity such as DSP core and PLLs), the current-density limits must be specified for supply and ground grids. A.2.4 Substrate Noise and Coupling
A.2.4.1 Overview
(This section intentionally left blank.)

A.2.4.2 Electrical Data A.2.4.2.1 Block-level Impedance Model
MANDATORY Specification: VC Hspice. Example: VC Hspice netlist, including an L-shaped RC model for substrate impedance.
A.2.4.2.2 Noise Sources for Aggressor Access Ports
MANDATORY Specification: VC Hspice.
45
VSI Alliance (IMP 1 2.0) Example: Two voltage sources should be expressed in VC Hspice PWL syntax: one for the PLLs sinusoidal switching noise, and the other for supply noise. MANDATORY Specification: VC Hspice. Examples: Assume the same PLL in the same GSM mixed-signal chip described in Section A.2.3.1.2. For such a PLL, the electrical specification would include each of the following: Spice text describing the impedance from access ports to the substrate in the form of an RC L-shaped network Spice text describing amplitude and phase for a voltage source representing the sinusoidal switching noise generated by the oscillator in this PLL sub-block, together with another source representing the di/dt noise caused by the supply as a sum of PWL sinusoids PWL Spice text representing the maximum allowed noise as a sum of 10 harmonics that may interfere with the PLLs main oscillation frequency (in the hundredths of MHz)
A.2.4.3 Physical Data A.2.4.2.3 Maximum Allowed Noise for Each Victim Access Port
MANDATORY Specification: Document. Example: Single n-well set of regions, for example, a chips PLL pMOS devices. Otherwise, specify the substrate region. MANDATORY Specification: Document. Example: Assume a PLL for the DSP core in a GSM mixed-signal chip. For such a PLL, the physical specification would include an annotated GDSII file indicating the doping profile regions for the analog PLL blocks (phase detector, charge pump, filter, and oscillator), the substrate access ports for its noise model (probably an analog model that produces sinusoidal noise waveforms), and proper cross references to the electrical and technology data. In this example, it is assumed that the PLL block is embedded in a single n-well region (for its pMOS devices), corresponding to a CMOS process biased at 3V. A.2.5 SI Requirements Document MANDATORY Specification: Document. Example: Documentation covering Sections 2.1 through 2.3, including all of the sub-sections, should be provided here.
46 A.2.4.3.2 Substrate Access Ports
A.2.4.3.1 Regions
B. Table Mapping Implementation Deliverables

The multiple implementation aspects involved in implementing a system-on-a-chip (SoC) are not completely independent from each other. For consistency purposes, the following table maps the SI deliverables to related deliverables in the other two VSIA implementation documents (IV and AMS). While most deliverables are not equivalent, there are a few related items, specifically some: documents (test requirements/constraints, sensitivities); abstractions (e.g., OLA): timing analysis models; electrical models (Spice, SPEF): Cell/circuit netlists, Certain power models; physical information (GDSII/DEF/LEF): power/ground, layout, routing obstructions; The specification user should note these overlapping deliverables between documents, to ensure any specification implementation avoids redundancies.
SI Deliverable (format)
Interconnect Crosstalk (Voltage and Delay) and Signal EM, Electrical data Maximum permissible noise propagating into input ports (VC Hspice) Maximum permissible external (to VC) crosstalk coupling and effective aggressor slew for failure- and delay-critical sensitive nets (if any) inside VC (SPEF, Document) Maximum noise possible at output ports (due to propagation/coupling within VC) (VC Hspice) Electrical characteristics for strong potential lying within VC I/O Driver Models (VC Hspice) Interconnect Models (SPEF) Electrical characteristics for failure- or delay-critical sensitive nets lying within VC (VC Hspice, SPEF) I/O Driver Models (VC Hspice) Best and worst case slew permissible at input ports VC (Hspice, Document) Min/max Slew Limits (Document) Input environment models (VC Hspice) Best and worst case slew available at output ports (and its variation with load)
IV Deliverable (format)
No redundancy No redundancy No redundancy
AMS Deliverable (format)

No redundancy
No redundancy
No redundancy No redundancy
No redundancy
Peripheral (SPEF)
No redundancy
Analog and Digital Electrical Port Model (VC Hspice) Peripheral (SPEF)
No redundancy
No redundancy No redundancy No redundancy No redundancy No redundancy
No redundancy No redundancy No redundancy No redundancy No redundancy
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Maximum permissible load/distributed RC that can be driven by output ports (SPEF) Physical data Location of failure- or delay-critical sensitive interconnect polygons inside VC (PDEF) Location of strong potential aggressors (for OTH signals) lying within VC (PDEF) Location of top-layer/peripheral supply and ground wires inside VC (PDEF) No-fly zone or external shielding requirements (PDEF) Safe regions for OTH signals (possibly classified by slew) (PDEF) Timing data Variation of timing arcs within VC with external crosstalk (SDF) Transition windows available at output ports (SDF) Transition windows required at input ports (SDF) Transition windows for strong potential aggressors (for OTH signals) or failure/delay critical sensitive nets lying within VC (SDF) Logical data Mutex/One-hot relationships required between input signals (Document) Mutex/One-hot relationships available between output signals (Document) Signal Electromigration Electrical Data Current density limits on metal and via layers (Document) Max load for electromigration limits on outputs (VC Hspice) Max slew rate for electromigration limits on inputs (SDF) Max Switching factor (VC Hspice) Drive Strength (Document) Input Load (Document) Supply and Ground Grid Noise & Electromigration Electrical data Specification Specification Requirements for Static Power Model (Document) No redundancy No redundancy
No redundancy
No redundancy
No redundancy No redundancy No redundancy No redundancy
No redundancy No redundancy No redundancy No redundancy No redundancy No redundancy
No redundancy No redundancy No redundancy No redundancy No redundancy No redundancy
Black/Gray Box, circuit, and cell level Power Model Requirements Verilog, EDIF- netlist, VHDL, SPEF, Spice
Power Supplies (document)
48

Specification Requirements for Dynamic Power Model (Document)
Black/Gray Box, circuit, and cell level Power Model Requirements Verilog, EDIF- netlist, VHDL, SPEF, Spice
Power and ground (VC LEF)
Physical data External Geometrical data of the supply and ground nets (supply and ground ports) (VC LEF) Internal Geometrical data of the supply and ground nets (Document) Timing data Variation in timing on output pins (delay & edge rates) due to IR drop in power grid (Document) Variation in timing on input pins (setup/hold time) due to LdI/dt noise in power grid (Document) Multiple power supplies for analog blocks, multi Vt circuits, pads (Document) Supply and Ground Electromigration Verification (Document) Substrate Noise and Coupling Electrical data Block-level impedance model (VC Hspice) Noise sources for aggressor access ports (VC Hspice) Maximum allowed noise for each victim access port (VC Hspice) Physical data Regions (Document) Substrate access ports (Document) SI Requirements Document (Document) No redundancy No redundancy No redundancy No redundancy No redundancy
No redundancy
Power, Ground, and Substrate interconnect Constraints (doc) Power and Ground LEF/DEF.
No redundancy
No redundancy
No redundancy
No redundancy
No redundancy
No redundancy
No redundancy
Substrate Sensitivity/ constraints (document)

C. Interconnect-centric existing standards analysis

An analysis of existing standards from the interconnect perspective was made, in order to help understand some of the interconnect related issues in this document. The conclusions are presented here: Findings: it is probably not reasonable to use a single format or standard. We recommend keeping existing standards and extend them when needed (e.g.
49
VSI Alliance (IMP 1 2.0) ALF++). Key formats: SPEF and ALF seem to be the most related formats at this time.
Desired features for interconnect modeling: First, interface features are needed (interconnect-centric IP block interface definition); second, elctrical-type features are needed (resistance, inductance, capacitance).
C.1 Introduction
System-on-a-Chip (SoC) design and integration is becoming increasing complex because of (a) large and complex functionalities embedded into a single chip, (b) an increasing number of interconnections, and (c) an ever larger amount of mixed signal designs with analog and digital blocks embedded on the same chip. The evaluation of the increasingly critical signal integrity (SI) effects is strongly dependent on the complex interactions between these integrated blocks. Specifically, wiring connections play a critical role in evaluating SI effects. As a result, it is becoming very difficult to use conventional methodologies to evaluate SI effects, since these methodologies are primarily device-centric. An "interconnect centric" approach is necessary to evaluate signal integrity issues. The term signal integrity (SI) here is used loosely to describe effects including power grid noise, crosstalk noise, substrate noise, and electromigration. In this document, we aim at finding a interconnect-centric model for specifications that can be used by both the IP/library designer as well as SoC integrator. We examine related modeling standards and we describe whether these standards meet the requirements of interconnect-centric SoC component modeling. For the sake of generality, we achieve this goal while avoiding process, design/methodology or tool-specific standards.
C.2 Goals
This document is aimed to define (a) a basic model for describing the necessary interconnect-related parameters required to characterize SI effects, and (b) a set of standard SoC design specifications based on this model. We first evaluate existing standards for reasons of reuse and extensibility. If necessary, we then consider the definition of new standards or modeling specifications. An interconnect-centric modeling standard must satisfy the following requirements:
blocks in an interconnect-centric manner. Hierarchy. The specifications standard must work at multiple levels of abstraction or detail, from system/RTL level to gate-level and below. Physical. The model must account for physical design characteristics, including wire placement and area. Electrical. The model must account for electrical characteristics that directly determine SI performance. Technology. The model must account for technology characteristics, including statistical on-chip and across-chip variations. Methodology. The parameters in the model must be easily incorporated in the tools that deal with
Interfaces: The proposed model needs to accommodate the definition of interfaces to/from IP
50

interconnect, both for synthesis and verification tasks.
C.3 Evaluation of existing standards

A short description is provided below for a set of existing formats and standards that could potentially be used to describe characteristics of IP-related interconnect.
SIPPs
Standard Interconnect Performance Parameters (SIPPs) is a standard that identifies interconnect process parameters required for performance analysis, aimed at process characterization. Although process characterization is a mandatory step for modeling interconnect for various design effects, evaluation of SI issues require not only process characterization, but also design parameters.
ALF
The Advanced Library Format [ALF] was mainly designed for the ASIC industry. Although it includes timing, power and functional parameters, the format does not include a detailed cell specific physical data, or information about the IP component characteristics (hard versus soft IP). Also, the format does not allow for the encapsulation of design characteristics
CHDStd
The Chip Hierarchical Design System technical data standard is based on a model that supports a number of requirements, including separate cell libraries and process characterization data. It is supported through OLA including cell function, delay calculation, power calculation and front-end cell characteristics. Cell characteristics include logical, physical and electrical.
SPEF
The Standard Parasitics Exchange Format (SPEF) provides for detailed and high-level parasitic information, including best, typical and worst values in the same file. The standard is based on an extension of prior parasitics exchange formats. Several semiconductor vendors use it and some commercial design automation tools support it. Attention has been given to reducing file size.
PDES
The Product Data Exchange format (PDES) is a data description and format standard under development for the exchange of data needed to fully describe a product and its manufacturing process. It describes the shared information at the core of manufacturing related activities. While this format represents information at various levels, and interconnect information could in theory be extracted from a PDES file, it is unlikely that PDES can be used by conventional design methodologies for interconnect modeling.
PLIB
The Physical Library Format (developed by Synopsys), provides information on physical
51

synthesis, RC estimation, Design and Antenna Rules. It is a physical library format which extends the open source Liberty format. It is intended to support physical synthesis, floorplanning, RC extraction, placement and routing. PLIB is intended to accurately model RC estimation and wire route estimation. PLIB leverages aspects of earlier standards like LEF and GDSII. The goal is to provide a single library database for all steps from RTL to GDSII. While LEF is a more popular library format, it can be translated to PLIB. We observe that the purpose of these formats ans standards range from parasitic modeling to library modeling to process modeling. None of these formats and standards can independently cover all aspects and abstraction levels of SoC IP interconnect modeling.
C.4 IMS (Interconnect Modeling Standards)

In order to understand the requirements for a single hypothetical interconnect modeling standard, necessary characteristics of the interface description for an IP block are described next by virtue of an example block shown in Figure 1.
Figure C.1 Graphical description of IP block interface.
Note that each of these wires can be on different layers. The Figure distiguishes three basic kinds of interface nodes: Power/ground nodes, clocking nodes, and signal nodes. Assuming these types of nodes are considered interconnect, they will have very different interconnect modeling requirements. Specifically, the definition of certain electrical characteristics will be different (application also determines need, but is not the focus of this document). For example, for the case of power grid noise modeling (one of the three aspects defined in our SI specification), the following electrical characteristics will be defined in some level of detail: Voltage limits
52

Current limits Conductance Inductance Capacitance
It is possible that for certain under-90 nanometer technologies the inductance portion might not be critical. Similarly, related to these electrical characteristics, the following interface characteristics will be defined differently: Input location of wires Output location of wires Current drawn at each port (optional). Current limits (Electromigration). Voltage limits at each port (optional). Input/output timing constraints per port
For power grid noise example, the last definition (timing constraints) will generally not be necessary, while for crosstalk noise it will be critical. Similar modeling parameters can be specified for the rest of the SI issues. These parameters need to be standard to ease communication between IP designers and integrators. Please refer to VSIA document v1.0 for more details on various parameters. The focus in this document will be the interconnect model parameter specification
C.5 Illustrative Standard Comparison

We have observed that, despite the variety of existing formats, there is not a current standard that can cover all aspects of SoC IP interconnect modeling. Each standard has its own strengths, however. Specifically, formats such as ALF are very powerful in modeling wiring and voltage/current characteristics (see examples in Appendix). Thus all current standards taken together, the majority of interconnect requirements may be met (not all of them, e.g., certain substrate-induced coupling definitions). To accomplish all of our requirements, we observe that the most effective angles that can be used to tackle this problem are (a) a library modeling perspective, that assumes each IP block to be a library cell, and (b) the parasitics modeling perspective, where the focus is on modeling the wires that affect the IP block. To gain insight into the synergies and differences between these two angles, we provide a comparison below of two popular formats, SPEF and ALF, that reflect these two angles. SPEF ALF (supported by SIPPs) Can specify interconnect as RLCs including Very flexible. The interconnect abstractions coupled capacitors. Useful for back-end design. can be captured including coupled capacitors. Can capture physical characteristics: wire area, layer definitions and spatial coordinates. No standard way to capture the interface There is no standard way to capture the mapping (however, the ports can be identified) interface mapping. The format does not support specification of any The format can be easily extended to specify voltage/current limits on various ports voltage and current limits on various ports.
53

It does not support any parameterized variations Parameterized variations can be incorporated. to the interconnect specifications. Can be used with extensions by the IP designer, Can be used by both IP integrator and IP but it can significantly limit the IP integrator. creator. May be limited by block size.
SI issues comparison
SI issues Crosstalk Noise ALF advantages ALF Drawbacks SPEF Advantages SPEF Drawbacks Back-end focus -
Power grid Noise Substrate Noise Electromigration
Flexible (can capture coupling) Parametrized variations ok
Less back-end focus
Can specify RLC interconnects No parametrized variations Back-end focus Back-end focus Back-end focus
Could support V/I limits on ports Could support V/I limits on ports
No support of V/I limits on ports No support of V/I limits on ports
C.6 Recommendations
Based on our analysis of existing formats and standards, it does not seem reasonable to try to accomplish all interconnect modeling goals at all abstraction levels with a single format or standard. Therefore, we suggest that keeping the following standards when possible, and extending them when needed (e.g., defining SPEF++ and ALF++), may be the best approach to be followed. Specifically, we suggest extending each standard with the minimum set of features that achieve satisfaction of the electrical and interface definitions necessary for interconnect modeling: Interfaces: definition of IP block interfaces in an interconnect-centric manner. Electrical. Voltage, current, resistance, inductance, and capacitance.
With respect to the rest of the requirements, we believe they have been automatically addressed in our recommendation or present a lower priority: Technology. While technology characteristics are important, there are standards being developed to address them (e.g., GDSIII). Methodology. This requirement is met as we are recommending an extension of existing standards.
Other possible long-term extensions of existing formats need to address the following issues: Inclusion of process variations including CMP, ILD thickness variations etc. These are also important but unlikely to be critical until sub-90 nanometer technologies
54

Support of state-dependent information (e.g., state-dependent capacitances).
C.7 ALF Examples

CELL my_cell { PIN A { 37.9; PINTYPE = digital; CAPACITANCE = 4.8; RESISTANCE = PORT p1 { VIEW = physical; } // see Section 9.10 PORT p2 { VIEW = none; } // see Section 9.10
} PIN B { PINTYPE = digital; CAPACITANCE = 2.6; } PIN gnd { PINTYPE = supply; SUPPLYTYPE = ground; }
WIRE my_boundary_parasitics { CAPACITANCE = 1.3 { NODE { A.p1 gnd } } CAPACITANCE = 2.8 { NODE { A.p2 gnd } } RESISTANCE = 65 { NODE { A.p1 A.p2 } } CAPACITANCE = 0.7 { NODE { A.p1 B } } CAPACITANCE = 1.9 { NODE { B gnd } } }
LIBRARY my_library { WIRE my_wlm { CAPACITANCE { HEADER { CONNECTIONS { TABLE { 2 3 4 5 10 20 } } AREA { TABLE { 1000 10000 100000 } } } TABLE { 0.03 0.06 0.08 0.10 0.15 0.25 0.05 0.10 0.15 0.18 0.25 0.35 0.10 0.18 0.25 0.32 0.50 0.65 } } AREA { HEADER { CONNECTIONS { TABLE { 2 3 4 5 10 20 } } AREA { TABLE { 1000 10000 100000 } } } TABLE { 0.3 0.6 0.8 1.0 1.5 2.5 0.5 1.0 1.5 1.8 2.5 3.5 1.0 1.8 2.5 3.2 5.0 6.5 } } } CELL my_cell { AREA = 1.5; PIN my_input { DIRECTION = input; CAPACITANCE = 0.1; }
55

PIN my_output { DIRECTION = output; CAPACITANCE = 0.0; }
WIRE my_interconnect_model { NODE n0 { NODETYPE = source; } NODE n2 { NODETYPE = driver; } NODE n4 { NODETYPE = receiver; } NODE n5 { NODETYPE = sink; } NODE vdd { NODETYPE = power; } NODE vss { NODETYPE = ground; } RESISTANCE R1 { NODE { n0 n1 } } RESISTANCE R2 { NODE { n1 n2 } } RESISTANCE R3 { NODE { n2 n3 } } RESISTANCE R4 { NODE { n3 n4 } } RESISTANCE R5 { NODE { n4 n5 } } CAPACITANCE C1 { NODE { n1 vss } } CAPACITANCE C2 { NODE { n2 vss } } CAPACITANCE C3 { NODE { n3 vss } } CAPACITANCE C4 { NODE { n4 vss } } CAPACITANCE C5 { NODE { n5 vss } } } WIRE interconnect_model_with_coupling { NODE aggressor_source { NODETYPE = driver; } NODE victim_source { NODETYPE = driver; } NODE aggressor_sink { NODETYPE = receiver; } NODE victim_sink { NODETYPE = receiver; } NODE vdd { NODETYPE = power; } NODE gnd { NODETYPE = ground; } CAPACITANCE cc { NODE {aggressor_sink victim_sink}} CAPACITANCE cv { NODE {victim_sink gnd }} RESISTANCE rv { NODE {victim_source victim_sink}} VECTOR ( 01 aggressor_sink -> ?* victim_sink -> *? victim_sink ) { /* xtalk noise model */ } VECTOR (( 01 aggressor_source <&> 01 victim_source )-> 01 aggressor_sink -> 01 victim_sink) { /* xtalk DELAY model */ } } VOLTAGE { PIN = victim_sink; MEASUREMENT = peak; CALCULATION = incremental; HEADER {SLEWRATE tra { PIN = aggressor_sink; } VOLTAGE va { NODE {vdd gnd} } }
56

EQUATION { (1-EXP(-tra/(rv*cv)))*va*rv*cc/tra } }
D. Glossary of Acronyms
AC ADC AGF ALF AMS API ASIC CMOS CSP DC DSP EPI GHz GSM I/O (or IO) IP ITRS LNA MCF MTF OLA PLL PWL OTH OVI PDEF PIN RF RMS Alternating current Analog-to-digital converter Annotated GDSII format OVI Advanced Library Format, http://www.eda.org/alf/ Analog mixed-signal Application program interface Application-specific integrated circuit Complementary metal oxide semiconductor Control signal processor Direct current Digital signal processor Epitaxial substrate layer Giga-Hertz Global system for mobile communications Input, output Intellectual property International Technology Roadmap for Semiconductors, http://www.sematech.org/ Low-noise amplifier Miller Coupling Factor Mean-time-to-failure Open Library API, http://www.si2.org/OLA/olaoverview.htm Phase-locked loop Piece-wise linear Over-the-hierarchy Open Verilog International, now called Accellera, http://www.accellera.org/ Physical Design Exchange Format Peripheral interconnect model Radio frequency Root mean square
57
VSI Alliance (IMP 1 2.0) SAP SDF SI SPEF UDSM VC VC-LEF VCO Vt Substrate access port Standard Delay Format Signal integrity Standard Parasitic Exchange Format Ultra-deep sub-micron Virtual component Virtual component library exchange format Voltage-controlled oscillator Threshold voltage
E. Bibliography
[Singh01] Singh R., Signal Integrity Effects in Custom IC and ASIC Designs, IEEE Press and Wiley and Sons, 11/2001. Note: This book is a compilation of tutorial and leading-edge papers covering all of the SI issues in this specification. As such, it is an appropriate reference text. More details of the book can be found at http://parasitics.com. [Lee99] Single GSM Mixed-Signal Superchip with 96k Bytes FLASH and Low Power Micro-Controller, K. Lee, B. Ng, A. Wang, R. Kuhn, D. Johnson, R. Kohler, Custom Integrated Circuits Conference 1999, pp. 103-106. [ITRS] International Technology Roadmap for Semiconductors, http://www.sematech.org/. [VSIA] http://www.vsi.org/library/specs/summary.htm [ALF] Advanced Library Format for ASIC Technology, Cells, & Blocks, Version 2.0, December 14, 2000
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Signal Integrity VSI Specification

Signal Integrity Document Sub-Development Working Group

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VSI Alliance (IMP 1 2.0)

Signal Integrity VSI Specification Version IMP 1 2.0 (IMP 1 2.0)

VSI Alliance (IMP 1 2.0)

VSI Alliance (IMP 1 2.0)

2.2 Signal Electromigration

2.3 Supply and Ground Grid Noise & Electromigration .

2.4 Substrate Noise and Coupling 23

2.5 SI Requirements Document

VSI Alliance (IMP 1 2.0)

VSI Alliance (IMP 1 2.0)

Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.

signal interconnects may suffer from electromigration problems.

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I-V Spec SI Spec

Methodology Description for VC Usage

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Owner: IEEE Status: IEEE Ballot Standard http://www.eda.org/sdf

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VSI Alliance (IMP 1 2.0)

otherwise document Section 2.4

Maximum noise possible at output ports (due to propagation/coupling within VC)

otherwise document Section 2.4

2.1.2.4. 2.1.2.4.1 2.1.2.4.2 2.1.2.5

2.1.2.5.1 2.1.2.5.2 2.1.2.6. 2.1.2.6.1 2.1.2.6.2 2.1.2.7. 2.1.2.7.1 2.1.2.7.2 2.1.2.8.

Document VC Hspice, SPEF

2.1.3. 2.1.3.1. 2.1.3.2. 2.1.3.3 2.1.3.4 2.1.3.5 2.1.4.

Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.

VSI Alliance (IMP 1 2.0)

otherwise document Section 2.4

2.1.4.2. 2.1.4.3. 2.1.4.4.

SDF SDF SDF

Document VC Hspice SDF VC Hspice Document Document GDSII

Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.

VSI Alliance (IMP 1 2.0)

2.4.3. 2.4.3.1 2.4.3.2.

Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.

VSI Alliance (IMP 1 2.0)

Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.

VSI Alliance (IMP 1 2.0)

Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.

VSI Alliance (IMP 1 2.0)

Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.

VSI Alliance (IMP 1 2.0)

Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.

VSI Alliance (IMP 1 2.0)

Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.

VSI Alliance (IMP 1 2.0)

Copyright 2004 by the VSI Alliance, Inc. All Rights Reserved.

VSI Alliance (IMP 1 2.0)

2.2.1.1.1 Current Density Limits on Metal and Via Layers

2.2.1.2 Maximum Load for Electromigration Limits on Outputs

2.2.1.3 Maximum Slew Rate for Electromigration Limits on Inputs