VLSI Design with VHDL Modeling for Synthesis

Prof. Jing-Yang Jou National Chiao Tung University Department of Electronics Engineering E-mail: jyjou@faculty.nctu.edu.tw Tel: (03)5731850 Fax: (03)5710580 Home Page: http://eda.ee.nctu.edu.tw/jyjou

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History
VHSIC Hardware Description Language
Very High Speed Integrated Circuits

Requirements generated in 1981 from VHSIC program Version 7.2 in 1985 (IBM, Texas Instruments, Intermetrices) Proposed IEEE standard 1986 IEEE standard 1076 adopted in December 1987 IEEE standard 1076-1993 finalized in 1993

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What is VHDL ?
A Formal Hardware Description Language Can express digital systems in different domains
Behavior Structure

Can support all level of abstraction

Algorithm RTL Gate Switch

Timing can be explicitly specified

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VHDL
A simulation language A synthesis language
RT-level synthesis

A test-synthesis language
BSDL

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Description Styles
Behavioral style
Adding two binary number

Data flow style

Logic equations

Structural style
Interconnection of gates

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Synthesis Subset

Data-flow kernel behavioral

structure

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Books
A VHDL Primer, (Revised Edition) J. Bhasker, ISBN 013184478, Prentice Hall, 1994 Digital Systems Design Using VHDL, Charles H. Roth, Jr., ISBN 0-534-95099-X, PWS Publishing Company HDL Chip Design, Douglas J. Smith, ISBN 0-96519343-8, Doone Publications Web: http://www.doone.com Digital Design and Modeling with VHDL and Synthesis, K. C. Chang, ISBN 0-8186-7716-3, IEEE Computer Society Press
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Design Entity
Primary hardware unit in VHDL (a component) Has well-defined inputs and outputs Performs a well-defined function Can represent an entire system, a board, a chip, a logic gate, etc. Consists of an interface (entity declaration) together with a corresponding behavior (architecture body)

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Entity and Architecture

Separate interface specification from implementation A design may have more than one implementation, or architecture

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Different Architectures
architecture DATA_FLOW of COMPARE is begin C<=not(A xor B) end DATA_FLOW architecture BEHAVIORAL of COMPARE is begin process(A, B) begin if(A = B) then C <= 1; else C <= 0; end if; end process; end;
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Entity Declaration
Specifies the interface of entity to outside environment.

entity DECODER2x4 is port (A, B, ENABLE: in BIT; Z: out BIT_VECTOR(0 to 3)); end DECODER2x4;
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Entity Declaration

entity FullAdder is port (A, B, CIN: in bit; SUM, COUT: out bit); end FullAdder; Format: entity ent_name is [generic (generic_list);] [port (port_list);] {common_declarations} end [ent_name];
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Ports
Provide channels for communication between the design entity and its environment Mode is in, out, inout, or buffer Buffer:
- Same as inout - Can be updated by at most one source

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Architecture Body
Specifies relationship between inputs and outputs Structure, data-flow, behavioral or mixed
Syntax: architecture arch_name of entity_name is {declarations} -- Declarations of items that are available -- for use within the block begin {statements} -- All are concurrent statements that execute -- asynchronously with respect to each other end [arch_name];
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Description Styles
Structural: Set of interconnected components
Structure explicit May be hierarchical

Data-flow: Set of concurrent statements

Represents behavior Implies structure

Behavioral: Sequential program statements

Represents behavior No structure information

Any mix of above

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Behavior + Structure Modeling

entity FA_MIX is port ( A, B, CIN,: in BIT; SUM, COUT: out BIT); end; architecture MIXED of FA_MIX is component MY_XOR port ( A, B: in BIT; Z: out BIT); end component; signal S1: BIT; begin X1: My_XOR port map (A, B, S1); process (A, B, CIN) variable TEMP1, TEMP2, TEMP3: BIT;

component declaration component instantiation sequential behavior

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Behavior + Structure Modeling

begin TEMP1 := A and B; TEMP2 := B and CIN; TEMP3 := A and CIN; COUT<= (TEMP1 or TEMP2) or TEMP3; end process; SUM <= S1 xor CIN; end;

concurrent behavior

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Data Type
A data type is characterized by a set of values and a set of operations Subtype: subset of a type; a type with constraint

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Predefined Types
bit Boolean integer real character time 0 or 1 False or True -(231-1) to + (231-1) -1.0E38 to + 1.0E38 d, 7 integer ns (ps, ms, sec, min, hr)

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Subtypes
Subset of a primary type, type with a constraint
Used for range checking A value belongs to a subtype if it belongs to the type and satisfies the constraint

Does not define a new type

Set of operations of a subtype includes all operations defined on the type

Predefined: NATURAL, POSITIVE

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Type Declaration
Enumeration type: User-defined values
type MVL is (0, 1, X, U, Z); type INSTR is (LOAD, STORE, ADD, SUB, MUL, DIV); subtype ARITH_INSTR is INSTR range ADD to DIV; signal CLOCK: MVL;

Integer type: Integer numbers

type INDEX is range 0 to 15; subtype MINI_INDEX is INDEX range 0 to 7; constant ORIGIN: INDEX := 10;

Floating-point type: Real numbers

type SMALL_REAL is range 1.0 to 15.5; variable DIAMETER: SMALL_REAL;

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Type Declaration
Physical type: Represents measurement of some quantity
type CAPACITANCE is range 0 to 1E8 units pf; -- base unit uf = 1000 pf; mf = 1000 uf; end units;

An example of usage:
variable K: CAPACITANCE; K := 5 mf;

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Type Declaration
Array type:
Constrained array type
type ADDR_WORD is array (0 to 63) of BIT;

Unconstrained array type

type FIFO_STD is array (INTEGER range <>) of ADDR_WORD; variable FastFIFO: FIFO_STD (0 to 127);

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Literals
Integer: 56, 2E2, 54_3, 0
2#101_101#, 16#FA#

Real: 16.26, 0.0, 0.002, 3_1.42 Physical: (abstract) unit_name

100 ns, 10 V, 50 sec

Character: A, Enumeration: literal of enumeration types String: <--->, YOU, This is an example Bit-string: B | O | X | bit_value
XFF0, B1101, O327
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Data Objects

A data object holds a value of a specified type

variable COUNT: INTEGER;

Four classes of objects:

Constant: Single value of a type; set before simulation begins and then cannot be changed Variable: Single value of a type; assigned a new value using a variable assignment statement Signal: Has a current value and a set of future values; scheduled a future value using a signal assignment statement File (1993): Contains a sequence of values Read, Write, and Append modes; Read and Write procedures are used to access value

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Object Declaration
Declare an object, its type, its class, and optionally to assign it a value Constant declarations:
constant CYCLE_TIME: TIME := 100 ns; constant NULL_OP_CODE: BIT_VECTOR := O052;

Variable declarations:
variable INDEX: INTEGER range 0 to 99 := 20; variable MEM: BIT;

Signal declarations:
signal RW: BIT := 1;

Default value is TLEFT

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File Object Declaration

File declarations (1993):
type VECTORS is file of BIT_VECTOR; type STRINGS is file of STRING; file inout_vec_file: VECTORS open APPEND_MODE is vec.file; file in_str_file: STRINGS open READ_MODE is strings.file;

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VHDL
Identifier
Case insensitive Contains letters, numbers and underscore _ Start with a letter Cannot end with _ C123 ab_12

Statement terminated with ; Comments follow --

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Reserved Words
abs access after alias all and architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic guarded if in inout is label library linkage loop

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Reserved Words
map mod nand new next nor not null of on open or others out package port procedure process range record register rem report return select severity signal subtype then to transport type units until use variable wait when while with xor

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Arrays
type SHORT_WORD is array (15 downto 0) of bits; signal DATA_WORD: SHORT_WORD; variable ALT_WORD: SHORT_WORD:= 0101010101010101; variable ONE_WORD: SHORT_WORD:= (other=>1); type intvec is array (nature range <>) of integer; signal intvec5: intvec (1 to 5):= (3,2,6,8,1);

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Arrays
Type matrix3x3 is array (1 to 3, 1 to 3) of integer; variable matrixA: matrix3x3:= ((1, 2, 3), (4, 5 ,6), (7, 8, 9)); matrixA: 1 2 3 4 5 6 7 8 9 matrixA(3,2) is 8
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Array Objects
type optype is (add, sub, div, mul); type timing is array (optype range <>, optype range <>) of TIME: constant ALUtiming: timing:=

-- add sub div mul

((10 ns, 20ns, 25ns, 32 ns), --add (20 ns, 15ns, 20ns, 45 ns), --sub (45 ns, 20ns, 30ns, 50 ns), --div (35 ns, 45ns, 50ns, 35 ns), --mul

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Array Objects
--named notation
type oparray is array (optype <>) of NATURAL; signal OpCode: oparray; OpCodes<= (add=>1, sub=>2, div=>3, mul=>4);

--mixed notation
type matrix is array (INTEGER range <>, INTEGER range <>) of integer; signal DiagMatrix: matrix (5 to 8, 6 to 9);

DiagMatrix <= ((6 =>1, others =>0), (7 =>1, others =>0), (8 =>1, others =>0), (9 =>1, others =>0);
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Aggregates
Array
variable OP_CODES:BIT_VECTOR(1 to 5); OP_CODES:= 01000;
A string literal is assigned

OP_CODES:= (0, 1, 0, 0, 0);

Positional association is implicit

OP_CODES:= {2=>1, others=>0);

Named association

OP_CODES:= (others=>0);
All values set to 0

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Aggregates
Record
type PIN_TYPE is range 0 to 10; type MODULE is record SIZE: INTEGER range 20 to 200; CRITICAL_DLY: TIME; NO_INPUTS: PIN_TYPE; NO_OUTPUTS:PIN_TYPE; end record variable NAND_COMP: MODULE; NAND_COMP:= (50, 20 ns, 3, 2);

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Logical Operators
not, or, nor, and, nand, xor:
Apply to BIT/BOOLEAN, 1-D of BIT/BOOLEAN Operands must be of the same type and same length Operation is performed on matching elements of the arrays Equal precedence executed from left to right

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Logical Operators
Example:
entity BITWISE is port (A: in bit_vector(6 downto 0); B: in bit_vector(6 downto 0); Y: out bit_vector(6 downto 0); Z: out bit_vector(6 downto 0)); end entity BITWISE;

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Logical Operators
architecture Behavior of BITWISE is begin process(A, B) begin Y(0) <= A(0) and B(0); --Binary AND Y(1) <= A(1) or B(1); --Binary OR Y(2) <= A(2) nand B(2); --Binary NAND Y(3) <= A(3) nor B(3); --Binary NOR Y(4) <= A(4) xor B(4); --Binary XOR Y(5) <= A(5) xnor B(5); --Binary XNOR Y(6) <= not A(6); --Unary negation Z <= A nor B; --Vector operation end process; end architecture Behavior;
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Relational Operators
=, /=,<, <=, >, >=:
Apply to any types Result is BOOLEAN Operands of the same type, different lengths are OK

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Relational Operators
Example:
entity COMPARISON is port (A, B, C: in bit_vector(2 downto 0); D, E, F: in bit_vector(3 downto 0); Y: out bit); end entity COMPARISON;

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Relational Operators
architecture Behavior of COMPARISON is begin process(A, B, C, D, E, F) begin if ((A=B) and ((C>D) or not (E<=F))) then Y<=1; else Y<=0; end if; end process; end architecture Behavior;
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Arithmetic Operators
+, -, *, /, **, mod, rem, abs:
Apply to numeric types (Integer, Real) Some synthesis support

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Arithmetic Operators
Example
entity ARITHMETIC is port (A, B: in integer range 7 downto 0; Y1: out integer range 15 downto 0; Y3: out integer range 63 downto 0; Y2, Y4, Y5: out integer range 7 downto 0); end entity ARITHMETIC;

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Arithmetic Operators
architecture Behavior of ARITHMETIC is begin process (A, B) begin Y1 <= A + B; -- Addition Y2 <= A - B; -- Subtraction Y3 <= A * B; -- Multiplication Y4 <= A / B; -- Division Y5 <= A mod B; -- Modulus of A divided by B end process; end architecture Behavior;
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Shift and Rotate

Predefined for one-dimensional array of type bit or Boolean SLL, SRL
Fill in typeLEFT (0 or False)

SLA
Fill in right most bit

SRA
Sign extension

ROL, ROR

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Shift and Rotate

A is bit_vector equal to 10010101
A sll 2 is 01010100 (filled with 0) A srl 3 is 00010010 (filled with 0) A sla 3 is 10101111 (filled with right bit) A sra 2 is 11100101 (filled with left bit) A rol 3 is 10101100 A ror 5 is 10101100

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Shift and Rotate

Example
entity SHIFT is port (A: in bit_vector(7 downto 0); Y1, Y2, Y3, Y4, Y5, Y6: out bit_vector(7 downto 0)); end entity SHIFT;

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Shift and Rotate

architecture Behavior of SHIFT is constant B: integer := 2; begin process (A, B) begin Y1 <= A sll B; -- Logical shift left Y2 <= A srl B; -- Logical shift right Y3 <= A rol B; -- Logical rotate left Y4 <= A ror B; -- Logical rotate right Y5 <= A sla B; -- Arithmetic shift left Y6 <= A sra B; -- Arithmetic shift right end process; end architecture Behavior;
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VHDL Operators
1. Binary logic operators
and or nand nor xor xnor
bit, Boolean, bit_vector, Boolean_vector

2. Relational operators
= /= < <= > >=
Result is Boolean = and /=: any type Others: numeric or enumerated type

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VHDL Operators
3. Shift operators
sll srl sla sra rol ror
Applied to bit_vector and Boolean_vector

4. Adding operators
+ & (concatenation)
+ and : any numeric types &: vectors

5. Unary sign operators

+

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VHDL Operators
6. Multiplying operators
/ mod rem
and /: integer and real mod and rem: integer

7. Miscellaneous operator
not abs
: raise integer or real to integer power abs: absolute value of a numeric operand

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Precedence
Class 7 is the highest Left to right for the same class Use () to change the order

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Precedence
(A & not B or C ror 2 and D)=110010 The operator order is: not, &, ror, or, and,=
A=110, B=111, C=011000, D=111011 Not B=000 A & not B=110000 C ror 2=000110 (A & not B) or (C ror 2)=110110 (A & not B) or (c ror 2) and D =110010 [A & not B or C ror 2 and D)=110010:]=True

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