MPC555UM

Freescale Semiconductor, Inc.
MPC555 / MPC556
Freescale Semiconductor, Inc...
USERS MANUAL
Revised 15 October 2000
Copyright 2000 MOTOROLA; All Rights Reserved
For More Information On This Product, Go to: www.freescale.com
MPC555 / MPC556
USERS MANUAL
Revised 15 October 2000
Copyright 2000 MOTOROLA; All Rights Reserved
Paragraph Number
TABLE OF CONTENTS
PREFACE Section 1 OVERVIEW
Page Number
1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 MPC555 / MPC556 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.1 RISC MCU Central Processing Unit (RCPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.2.2 Four-Bank Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.3 U-Bus System Interface Unit (USIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.2.4 Flexible Memory Protection Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.5 448 Kbytes of CDR MoneT Flash EEPROM Memory (CMF) . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.6 26 Kbytes of Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.7 General-Purpose I/O Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2.8 Two Time Processor Units (TPU3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2.9 18-Channel Modular I/O System (MIOS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2.10 Two Queued Analog-to-Digital Converter Modules (QADC) . . . . . . . . . . . . . . . . . . . . . 1-4 1.2.11 Two CAN 2.0B Controller Modules (TouCANs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.2.12 Queued Serial Multi-Channel Module (QSMCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.3 MPC555 / MPC556 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Section 2 SIGNAL DESCRIPTIONS

2.1 Packaging and Pinout Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 Pin Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.3.1 USIU Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.3.1.1 ADDR[8:31]/SGPIOA[8:31]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 2.3.1.2 DATA[0:31]/SGPIOD[0:31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.1.3 IRQ[0]/SGPIOC[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.1.4 IRQ[1]/RSV/SGPIOC[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.1.5 IRQ[2]/CR/SGPIOC[2]/MTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.1.6 IRQ[3]/KR/RETRY/SGPIOC[3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.1.7 IRQ[4]/AT[2]/SGPIOC[4]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.1.8 IRQ[5]/SGPIOC[5]/MODCK[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.1.9 IRQ[6:7]/MODCK[2:3]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.1.10 TSIZ[0:1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.1.11 RD/WR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.3.1.12 BURST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.3.1.13 BDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.3.1.14 TS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.3.1.15 TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 MPC555 / MPC556 USERS MANUAL TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA iii

Paragraph Number Page Number
2.3.1.16 TEA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.3.1.17 RSTCONF/TEXP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.1.18 OE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.1.19 BI/STS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.1.20 CS[0:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.1.21 WE[0:3]/BE[0:3]/AT[0:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 2.3.1.22 PORESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.1.23 HRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.1.24 SRESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.1.25 SGPIOC[6]/FRZ/PTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.1.26 SGPIOC[7]/IRQOUT/LWP[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.1.27 BG/VF[0]/LWP[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.1.28 BR/VF[1]/IWP[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.1.29 BB/VF[2]/IWP[3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.1.30 IWP[0:1]/VFLS[0:1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.1.31 TMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.1.32 TDI/DSDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.1.33 TCK/DSCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.1.34 TDO/DSDO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.1.35 TRST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.1.36 XTAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.1.37 EXTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.1.38 XFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.1.39 CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.1.40 EXTCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.1.41 VDDSYN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.1.42 VSSSYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.1.43 ENGCLK/BUCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.2 QSMCM PADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.2.1 PCS0/SS/QGPIO[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.2.2 PCS(1:3)/QGPIO[1:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.2.3 MISO/QGPIO[4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.2.4 MOSI/QGPIO[5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.2.5 SCK/QGPIO[6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.2.6 TXD[1:2]/QGPO[1:2]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.2.7 RXD[1:2]/QGPI[1:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.2.8 ECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.3 MIOS PADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.3.1 MDA[11], [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.3.2 MDA[12], [14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.3.3.3 MDA[15], [27:31]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.3.3.4 MPWM[0:3], [16:19] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.3.3.5 VF[0:2]/MPIO32B[0:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 MPC555 / MPC555 USERS MANUAL TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA iv

2.3.3.6 VFLS[0:1]/MPIO32B[3:4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.3.3.7 MPIO32B[5:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.4 TPU_A/TPU_B PADS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.4.1 TPUCH[0:15]_[A:B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.4.2 T2CLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.5 QADC_A/QADC_B PADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.5.1 ETRIG[1:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.5.2 AN[0]/ANW/PQB[0]_[A:B]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.5.3 AN[1]/ANX/PQB[1]_[A:B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 2.3.5.4 AN[2]/ANY/PQB[2]_[A:B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.5.5 AN[3]/ANZ/PQB[3]_[A:B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.5.6 AN[48:51]/PQB[4:7]_[A:B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.5.7 AN[52:54]/MA[0:2]/PQA[0:2]_[A:B]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.5.8 AN[55:59]/PQA[3:7]_[A:B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.5.9 VRH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.5.10 VRL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.5.11 VDDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.5.12 VSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.6 TOUCAN_A/TOUCAN_B PADS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.6.1 CNTX0_[A:B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.6.2 CNRX0_[A:B] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.7 CMF PADS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.7.1 EPEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.7.2 VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.7.3 VDDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.7.4 VSSF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.8 GLOBAL POWER SUPPLIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.8.1 VDDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.8.2 VDDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.8.3 VDDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.8.4 VSSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.3.8.5 KAPWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2.3.8.6 VDDSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2.3.8.7 VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2.4 Reset State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2.4.1 Pin Functionality Out of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2.4.2 Pad Module Configuration Register (PDMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 2.4.3 Pin State During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2.4.4 Power-On Reset and Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2.4.5 Pull-Up and Pull-Down Enable and Disable for 5-V Only Pins . . . . . . . . . . . . . . . . . . . . 2-30 2.4.6 Pull-Up and Pull-Down Enable and Disable for 3-V / 5-V Multiplexed Pins . . . . . . . . . . 2-30 2.4.6.1 PRDS Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2.4.6.2 Encoded 3-V / 5-V Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 MPC555 / MPC555 USERS MANUAL TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA v

2.4.6.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 2.4.7 Special Pull Resistor Disable Control (SPRDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 2.4.8 Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 2.5 Pad Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 2.5.1 Pad Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 2.5.2 Three-Volt Output Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 2.5.2.1 Type A Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 2.5.2.2 Type B Interface (Clock Pad) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 2.5.3 Three-Volt Input Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 2.5.3.1 Type C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 2.5.3.2 Type CH Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 2.5.3.3 Type CNH Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 2.5.3.4 Type D Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 2.5.4 Three-Volt Input/Output Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 2.5.4.1 Type E Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 2.5.4.2 Type EOH Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 2.5.4.3 Type F Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 2.5.4.4 Type G Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44 2.5.5 Five-Volt Input/Output Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 2.5.5.1 Type H Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 2.5.5.2 Type I Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46 2.5.5.3 Type IH Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48 2.5.5.4 Type J Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49 2.5.5.5 Type JD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49 2.5.6 Type K Interface (EPEE Pad) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 2.5.7 Analog Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 2.5.7.1 Type L Interface (QADC Port A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 2.5.7.2 Type M Interface (QADC Port B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52 2.5.7.3 Type N Interface (ETRIG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53 2.5.8 Pads with Fast Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53 2.5.8.1 Type O Interface (QSMCM Pads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53 2.5.8.2 Type P Interface (TPU and MIOS Pads) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54 2.5.9 5V Input, 5V Output Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55 2.5.9.1 5V Output (Type Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-55 2.5.9.2 Type R Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56 2.5.9.3 5V Output for Clock Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 2.6 Pad Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 2.7 Pin Names and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
Section 3 CENTRAL PROCESSING UNIT

3.1 RCPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 RCPU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
MPC555 / MPC555 USERS MANUAL
TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com
MOTOROLA vi

3.3 Instruction Sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.4 Independent Execution Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.4.1 Branch Processing Unit (BPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.4.2 Integer Unit (IU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.4.3 Load/Store Unit (LSU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.4.4 Floating-Point Unit (FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.5 Levels of the PowerPC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.6 RCPU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.7 PowerPC UISA Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 3.7.1 General-Purpose Registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.7.2 Floating-Point Registers (FPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.7.3 Floating-Point Status and Control Register (FPSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.7.4 Condition Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 3.7.4.1 Condition Register CR0 Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.7.4.2 Condition Register CR1 Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 3.7.4.3 Condition Register CRn Field Compare Instruction . . . . . . . . . . . . . . . . . . . . . . 3-17 3.7.5 Integer Exception Register (XER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 3.7.6 Link Register (LR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 3.7.7 Count Register (CTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.8 PowerPC VEA Register Set Time Base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 3.9 PowerPC OEA Register Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.9.1 Machine State Register (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 3.9.2 DAE/Source Instruction Service Register (DSISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.9.3 Data Address Register (DAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 3.9.4 Time Base Facility (TB) OEA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.9.5 Decrementer Register (DEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 3.9.6 Machine Status Save/Restore Register 0 (SRR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.9.7 Machine Status Save/Restore Register 1 (SRR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 3.9.8 General SPRs (SPRG0SPRG3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.9.9 Processor Version Register (PVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 3.9.10 Implementation-Specific SPRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.9.10.1 EIE, EID, and NRI Special-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.9.10.2 Floating-Point Exception Cause Register (FPECR) . . . . . . . . . . . . . . . . . . . . . . . 3-26 3.9.10.3 Additional Implementation-Specific Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.10 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 3.10.1 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29 3.10.2 Recommended Simplified Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 3.10.3 Calculating Effective Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33 3.11 Exception Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 3.11.1 Exception Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 3.11.2 Ordered Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 3.11.3 Unordered Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-34 3.11.4 Precise Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 MPC555 / MPC555 USERS MANUAL TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA vii

3.11.5 Exception Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 3.12 Instruction Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36 3.13 PowerPC User Instruction Set Architecture (UISA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 3.13.1 Computation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 3.13.2 Reserved Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 3.13.3 Classes of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 3.13.4 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 3.13.5 The Branch Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 3.13.6 Instruction Fetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 3.13.7 Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 3.13.7.1 Invalid Branch Instruction Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 3.13.7.2 Branch Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 3.13.8 The Fixed-Point Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 3.13.8.1 Fixed-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 3.13.9 Floating-Point Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 3.13.9.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 3.13.9.2 Optional instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 3.13.10 Load/Store Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 3.13.10.1 Fixed-Point Load With Update and Store With Update Instructions. . . . . . . . . . 3-41 3.13.10.2 Fixed-Point Load and Store Multiple Instructions . . . . . . . . . . . . . . . . . . . . . . . . 3-41 3.13.10.3 Fixed-Point Load String Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 3.13.10.4 Storage Synchronization Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 3.13.10.5 Floating-Point Load and Store With Update Instructions . . . . . . . . . . . . . . . . . . 3-41 3.13.10.6 Floating-Point Load Single Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 3.13.10.7 Floating-Point Store Single Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 3.13.10.8 Optional Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 3.13.10.9 Little-Endian Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 3.14 PowerPC Virtual Environment Architecture (VEA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 3.14.1 Atomic Update Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 3.14.2 Effect of Operand Placement on Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 3.14.3 Storage Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 3.14.4 Instruction Synchronize (isync) Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-42 3.14.4.1 Enforce In-Order Execution of I/O (eieio) Instruction . . . . . . . . . . . . . . . . . . . . . . 3-43 3.14.5 Timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 3.15 POWERPC Operating Environment Architecture (OEA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 3.15.1 Branch Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 3.15.1.1 Machine State Register (MSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 3.15.1.2 Branch Processors Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 3.15.2 Fixed-Point Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 3.15.2.1 Special Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 3.15.3 Storage Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 3.15.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 3.15.4.1 System Reset Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 MPC555 / MPC555 USERS MANUAL TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA viii

3.15.4.2 Machine Check Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 3.15.4.3 Data Storage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 3.15.4.4 Instruction Storage Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 3.15.4.5 Alignment Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 3.15.4.6 Floating-Point Enabled Exception Type Program Interrupt . . . . . . . . . . . . . . . . . 3-46 3.15.4.7 Illegal Instruction Type Program Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 3.15.4.8 Privileged Instruction Type Program interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 3.15.4.9 Floating-Point Unavailable Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 3.15.4.10 Trace Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 3.15.4.11 Floating-Point Assist Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 3.15.4.12 Implementation-Dependent Software Emulation Interrupt . . . . . . . . . . . . . . . . . 3-48 3.15.4.13 Implementation-Specific Instruction Storage Protection Error Interrupt . . . . . . . 3-49 3.15.4.14 Implementation-Specific Data Storage Protection Error Interrupt . . . . . . . . . . . 3-50 3.15.4.15 Implementation-Specific Debug Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-51 3.15.4.16 Partially Executed Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52 3.15.5 Timer Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53 3.15.6 Optional Facilities and Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53
Section 4 BURST BUFFER

4.1 Burst Buffer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 Burst Buffer Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3 Instruction VocabularyBased Compression Model Main Principles . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3.1 Compression Model Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3.2 Model Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.3 Vocabulary Based Instruction Compression Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.4 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3.5 Compressed Code Address Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.3.6 Compressed Address Format Direct Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 4.3.7 Compressed Address Format Indirect Branches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.3.8 Compression Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.3.9 Decompression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.3.10 Compression Environment Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.4 Modes Of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 4.4.1 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.4.2 Slave Operation.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.4.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.4.4 Debug Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.4.5 Standby Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.4.6 Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.4.7 Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.5 Exception Table Relocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 4.5.1 Exception Table Relocation Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
MOTOROLA ix

4.6 Burst Buffer Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 4.6.1 Region Base Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 4.6.2 Region Attribute Registers MI_RA[0:3] Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 4.6.3 Global Region Attribute Register Description (MI_GRA) . . . . . . . . . . . . . . . . . . . . . . . . 4-23 4.6.4 BBC Module Configuration Register (BBCMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Section 5 UNIFIED SYSTEM INTERFACE UNIT

5.1 Module Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 SIU Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3 USIU Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.4 USIU PowerPC Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Section 6 SYSTEM CONFIGURATION AND PROTECTION

6.1 System Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.1.1 USIU Pins Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.1.2 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3 6.1.3 Arbitration Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.2 External Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.2.1 Operation of External Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.2.2 Address Decoding for External Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.3 USIU General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 6.4 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.4.1 SIU Interrupt Sources Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-11 6.5 Hardware Bus Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.6 MPC555 / MPC556 Decrementer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.7 MPC555 / MPC556 Time Base (TB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13 6.8 Real-Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14 6.9 Periodic Interrupt Timer (PIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15 6.10 Software Watchdog Timer (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 6.11 Freeze Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.12 Low Power Stop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.13 System Configuration and Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.13.1 System Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.13.1.1 SIU Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.13.1.2 Internal Memory Map Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 6.13.1.3 External Master Control Register (EMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.13.2 SIU Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.13.2.1 SIPEND Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.13.2.2 SIU Interrupt Mask Register (SIMASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 6.13.2.3 SIU Interrupt Edge Level Register (SIEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 6.13.2.4 SIU Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 6.13.3 System Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 MPC555 / MPC555 USERS MANUAL TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA x

6.13.3.1 System Protection Control Register (SYPCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 6.13.3.2 Software Service Register (SWSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 6.13.3.3 Transfer Error Status Register (TESR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27 6.13.4 System Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 6.13.4.1 Decrementer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 6.13.4.2 Time Base SPRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-28 6.13.4.3 Time Base Reference Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 6.13.4.4 Time Base Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29 6.13.4.5 Real-Time Clock Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30 6.13.4.6 Real-Time Clock Register (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 6.13.4.7 Real-Time Clock Alarm Register (RTCAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-31 6.13.4.8 Periodic Interrupt Status and Control Register (PISCR). . . . . . . . . . . . . . . . . . . . 6-32 6.13.4.9 Periodic Interrupt Timer Count Register (PITC) . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32 6.13.4.10 Periodic Interrupt Timer Register (PITR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33 6.13.5 General-Purpose I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 6.13.5.1 SGPIO Data Register 1 (SGPIODT1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 6.13.5.2 SGPIO Data Register 2 (SGPIODT2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34 6.13.5.3 SGPIO Control Register (SGPIOCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
Section 7 RESET
7.1 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.1 Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.1.2 Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.1.3 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.1.4 Loss of Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.1.5 On-Chip Clock Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.1.6 Software Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.1.7 Checkstop Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.1.8 Debug Port Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.1.9 Debug Port Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.1.10 JTAG Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.2 Reset Actions Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 7.3 Data Coherency During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.4 Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.5 Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.5.1 Hard Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.5.2 Hard Reset Configuration Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.5.3 Soft Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
Section 8 CLOCKS AND POWER CONTROL

8.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 System Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 MPC555 / MPC555 USERS MANUAL TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xi

8.3 System PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.3.1 Frequency Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3.2 Skew Elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3.3 Pre-Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3.4 PLL Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4 8.3.5 PLL Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.4 System Clock During PLL Loss of Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.5 Low-Power Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 8.6 MPC555 / MPC556 Internal Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.6.1 General System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.6.2 CLKOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.6.3 Engineering Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.7 Clock Source Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8.8.1 Entering a Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 8.8.2 Power Mode Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 8.8.3 Exiting from Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 8.8.3.1 Exiting from Normal-Low Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 8.8.3.2 Exiting from Doze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 8.8.3.3 Exiting from Deep-Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 8.8.3.4 Exiting from Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 8.8.3.5 Low-Power Modes Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 8.9 Basic Power Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 8.9.1 Clock Unit Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 8.9.2 Chip Power Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 8.9.2.1 VDDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 8.9.2.2 VDDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 8.9.2.3 VDDSYN, VSSSYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.9.2.4 KAPWR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.9.2.5 VDDA, VSSA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.9.2.6 VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.9.2.7 VDDF, VSSF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.9.2.8 VDDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.9.2.9 VDDSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.9.2.10 VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-21 8.9.3 Keep Alive Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 8.9.3.1 Keep Alive Power Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 8.9.3.2 Keep Alive Power Registers Lock Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 8.10 VDDSRAM Supply Failure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25 8.11 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25 8.12 Clocks Unit Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-29 8.12.1 System Clock Control Register (SCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-30 8.12.2 PLL, Low-Power, and Reset-Control Register (PLPRCR) . . . . . . . . . . . . . . . . . . . . . . 8-33 MPC555 / MPC555 USERS MANUAL TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xii

8.12.3 Change of Lock Interrupt Register (COLIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35 8.12.4 VDDSRAM Control Register (VSRMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36
Section 9 EXTERNAL BUS INTERFACE

9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2 Bus Transfer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3 Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.4 Bus Interface Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3 9.5 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-7 9.5.1 Basic Transfer Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.5.2 Single Beat Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.5.2.1 Single Beat Read Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.5.2.2 Single Beat Write Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.5.2.3 Single Beat Flow with Small Port Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.5.3 Burst Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.5.4 Burst Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 9.5.5 Alignment and Packaging of Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-28 9.5.6 Arbitration Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-30 9.5.6.1 Bus Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31 9.5.6.2 Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32 9.5.6.3 Bus Busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-32 9.5.6.4 Internal Bus Arbiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33 9.5.7 Address Transfer Phase Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35 9.5.7.1 Transfer Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36 9.5.7.2 Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36 9.5.7.3 Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36 9.5.7.4 Burst Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-36 9.5.7.5 Transfer Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37 9.5.7.6 Address Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-37 9.5.7.7 Burst Data in Progress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-38 9.5.8 Termination Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-38 9.5.8.1 Transfer Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-38 9.5.8.2 Burst Inhibit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39 9.5.8.3 Transfer Error Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39 9.5.8.4 Termination Signals Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-39 9.5.9 Storage Reservation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-40 9.5.10 Bus Exception Control Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43 9.5.10.1 Retrying a Bus Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-43 9.5.10.2 Termination Signals Protocol Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-47 9.5.11 Bus Operation in External Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-47 9.5.12 Contention Resolution on External Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-52 9.5.13 Show Cycle Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-54
MOTOROLA xiii

Paragraph Number Section 10 MEMORY CONTROLLER
10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.2 Memory Controller Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.2.1 Associated Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.2.2 Port Size Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.2.3 Write-Protect Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.2.4 Address and Address Space Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.2.5 Burst Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 10.3 Chip-Select Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10.3.1 Memory Devices Interface Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Page Number
10.3.2 Peripheral Devices Interface Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 10.3.3 Relaxed Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-10 10.3.4 Extended Hold Time on Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14 10.3.5 Summary of GPCM Timing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-18 10.4 Global (Boot) Chip-Select Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-20 10.5 Write and Byte Enable Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10.6 Dual Mapping of the Internal Flash EEPROM Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21 10.7 Memory Controller External Master Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-24 10.8 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 10.8.1 General Memory Controller Programming Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-27 10.8.2 Memory Controller Status Registers (MSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 10.8.3 Memory Controller Base Registers (BR0 BR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-28 10.8.4 Memory Controller Option Registers (OR0 OR3) . . . . . . . . . . . . . . . . . . . . . . . . . . 10-30 10.8.5 Dual Mapping Base Register (DMBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-31 10.8.6 Dual-Mapping Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-32
Section 11 L-BUS TO U-BUS INTERFACE (L2U)

11.1 General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 DMPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.3 L2U Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.4 Modes Of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.4.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.4.2 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.4.3 Factory Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.4.4 Peripheral Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.5 Data Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.5.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4 11.5.2 Associated Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.5.3 L-bus Memory Access Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.6 Reservation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.6.1 The Reservation Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 MPC555 / MPC555 USERS MANUAL TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xiv

11.6.2 L2U Reservation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7 11.6.3 Reserved Location (Bus) and Possible Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 11.7 L-Bus Show Cycle Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.7.1 Programming Show Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.7.2 Performance Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 11.7.3 Show Cycle Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.7.4 L-Bus Write Show Cycle Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 11.7.5 L-Bus Read Show Cycle Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.7.6 Show Cycle Support Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-11 11.8 L2U Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12 11.8.1 U-bus Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.8.2 Transaction Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.8.3 L2U Module Configuration Register (L2U_MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-13 11.8.4 Region Base Address Registers (L2U_RBAx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-14 11.8.5 Region Attribute Registers (L2U_RAx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11.8.6 Global Region Attribute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15
Section 12 U-BUS TO IMB3 BUS INTERFACE (UIMB)

12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2 UIMB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.3 Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2 12.4 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.4.1 Interrupt Sources and Levels on IMB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.4.2 IMB Interrupt Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.4.3 ILBS Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.4.4 Interrupt Synchronizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.5 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.5.1 UIMB Module Configuration Register (UMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7 12.5.2 Test control register (UTSTCREG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8 12.5.3 Pending Interrupt Request Register (UIPEND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
Section 13 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64

13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.3 QADC64 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.3.1 Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.3.1.1 Port A Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.3.1.2 Port A Digital Input/Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.3.2 Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3.2.1 Port B Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3.2.2 Port B Digital Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3.3 External Trigger Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 MPC555 / MPC555 USERS MANUAL TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xv

13.3.4 Multiplexed Address Output Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.3.5 Multiplexed Analog Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.3.6 Voltage Reference Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.3.7 Dedicated Analog Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.3.8 External Digital Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.3.9 Digital Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 13.4 QADC64 Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.5 Module Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.5.1 Low-Power Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.5.2 Freeze Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.5.3 Supervisor/Unrestricted Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.6 General-Purpose I/O Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.6.1 Port Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.6.2 Port Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.7 External Multiplexing Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 13.8 Analog Input Channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 13.9 Analog Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11 13.9.1 Conversion Cycle Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 13.9.1.1 Amplifier Bypass Mode Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 13.9.2 Front-End Analog Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 13.9.3 Digital-to-Analog Converter Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 13.9.4 Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 13.9.5 Successive Approximation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 13.10 Digital Control Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 13.10.1 Queue Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 13.10.2 Queue Boundary Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-17 13.10.3 Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 13.10.3.1 Disabled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 13.10.3.2 Reserved Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 13.10.3.3 Single-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18 13.10.3.4 Continuous-Scan Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-21 13.10.4 QADC64 Clock (QCLK) Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-24 13.10.5 Periodic/Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29 13.11 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-29 13.11.1 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-30 13.11.2 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31 13.11.3 Interrupt Levels and Time Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31 13.12 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-31 13.12.1 QADC64 Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-33 13.12.2 QADC64 Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-33 13.12.3 QADC64 Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-33 13.12.4 Port A/B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-34 13.12.5 Port Data Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-35 MPC555 / MPC555 USERS MANUAL TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xvi

13.12.6 QADC64 Control Register 0 (QACR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-35 13.12.7 QADC64 Control Register 1 (QACR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-36 13.12.8 QADC64 Control Register 2 (QACR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-38 13.12.9 QADC64 Status Register 0 (QASR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-40 13.12.10 QADC64 Status Register 1 (QASR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-42 13.12.11 Conversion Command Word Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-43 13.12.12 Result Word Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-49
Section 14 QUEUED SERIAL MULTI-CHANNEL MODULE

14.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1
14.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2 14.5 QSMCM Global Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 14.5.1 Low-Power Stop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14.5.2 Freeze Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14.5.3 Access Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 14.5.4 QSMCM Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6 14.5.5 QSMCM Configuration Register (QSMCMMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7 14.5.6 QSMCM Test Register (QTEST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-8 14.5.7 QSMCM Interrupt Level Registers (QDSCI_IL, QSPI_IL) . . . . . . . . . . . . . . . . . . . . . . 14-8 14.6 QSMCM Pin Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9 14.6.1 Port QS Data Register (PORTQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-10 14.6.2 PORTQS Pin Assignment Register (PQSPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11 14.6.3 PORTQS Data Direction Register (DDRQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12 14.7 Queued Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-13 14.7.1 QSPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15 14.7.1.1 QSPI Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-16 14.7.1.2 QSPI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18 14.7.1.3 QSPI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18 14.7.1.4 QSPI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 14.7.1.5 QSPI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20 14.7.2 QSPI RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21 14.7.2.1 Receive RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.7.2.2 Transmit RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.7.2.3 Command RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.7.3 QSPI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23 14.7.4 QSPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24 14.7.4.1 Enabling, Disabling, and Halting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 14.7.4.2 QSPI Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26 14.7.4.3 QSPI Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26 14.7.5 Master Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-33
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14.7.5.1 Clock Phase and Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-34 14.7.5.2 Baud Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-34 14.7.5.3 Delay Before Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35 14.7.5.4 Delay After Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-35 14.7.5.5 Transfer Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36 14.7.5.6 Peripheral Chip Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-36 14.7.5.7 Master Wraparound Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-37 14.7.6 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-37 14.7.6.1 Description of Slave Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-39 14.7.7 Slave Wraparound Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-40 14.7.8 Mode Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-41 14.8 Serial Communication Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-41 14.8.1 SCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-44 14.8.2 SCI Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-45 14.8.3 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-45 14.8.4 SCI Status Register (SCxSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-47 14.8.5 SCI Data Register (SCxDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-49 14.8.6 SCI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-50 14.8.7 SCI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-50 14.8.7.1 Definition of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-50 14.8.7.2 Serial Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-51 14.8.7.3 Baud Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-51 14.8.7.4 Parity Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-52 14.8.7.5 Transmitter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-52 14.8.7.6 Receiver Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-54 14.8.7.7 Receiver Functional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-56 14.8.7.8 Idle-Line Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-57 14.8.7.9 Receiver Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-58 14.8.7.10 Internal Loop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-58 14.9 SCI Queue Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-58 14.9.1 Queue Operation of SCI1 for Transmit and Receive . . . . . . . . . . . . . . . . . . . . . . . . . 14-58 14.9.2 Queued SCI1 Status and Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-59 14.9.2.1 QSCI1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-59 14.9.2.2 QSCI1 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-61 14.9.3 QSCI1 Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-61 14.9.4 QSCI1 Additional Transmit Operation Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-62 14.9.5 QSCI1 Transmit Flow Chart Implementing the Queue . . . . . . . . . . . . . . . . . . . . . . . . 14-64 14.9.6 Example QSCI1 Transmit for 17 Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-66 14.9.7 Example SCI Transmit for 25 Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-67 14.9.8 QSCI1 Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-68 14.9.9 QSCI1 Additional Receive Operation Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-68 14.9.10 QSCI1 Receive Flow Chart Implementing The Queue . . . . . . . . . . . . . . . . . . . . . . . 14-71 14.9.11 QSCI1 Receive Queue Software Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-72 MPC555 / MPC555 USERS MANUAL TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xviii

Paragraph Number Page Number Section 15 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
15.1 MIOS1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.2 Submodule Numbering, Naming and Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.3 MIOS1 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 15.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.5 MIOS1 Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.5.1 Read/Write and Control Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.5.2 Request Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.5.3 Counter Bus Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.6 MIOS1 Programmers Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 15.7 MIOS1 I/O Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.8 MIOS Bus Interface Submodule (MBISM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.8.1 MIOS Bus Interface (MBISM) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.8.1.1 MIOS1 Test and Pin Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8 15.8.1.2 MIOS1 Vector Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.8.1.3 MIOS1 Module and Version Number Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.8.1.4 MIOS1 Module Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.8.2 MBISM Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 15.8.2.1 MIOS1 Interrupt Level Register 0 (MIOS1LVL0) . . . . . . . . . . . . . . . . . . . . . . . . 15-10 15.8.2.2 MIOS1 Interrupt Level Register 1 (MIOS1LVL1) . . . . . . . . . . . . . . . . . . . . . . . . 15-11 15.8.3 Interrupt Control Section (ICS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 15.9 MIOS Counter Prescaler Submodule (MCPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 15.9.1 MIOS Counter Prescaler Submodule (MCPSM) Registers . . . . . . . . . . . . . . . . . . . . 15-12 15.9.1.1 MCPSM Status/Control Register (MCPSMCSCR) . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.10 MIOS Modulus Counter Submodule (MMCSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.10.1 MIOS Modulus Counter Submodule (MMCSM) Registers . . . . . . . . . . . . . . . . . . . . 15-15 15.10.1.1 MMCSM Up-Counter Register (MMCSMCNT). . . . . . . . . . . . . . . . . . . . . . . . . 15-16 15.10.1.2 MMCSM Modulus Latch Register (MMCSMML) . . . . . . . . . . . . . . . . . . . . . . . 15-16 15.10.1.3 MMCSM Status/Control Register (Duplicated) . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 15.10.1.4 MMCSM Status/Control Register (MMCSMSCR) . . . . . . . . . . . . . . . . . . . . . . 15-17 15.11 MIOS Double Action Submodule (MDASM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.11.1 MIOS Double Action Submodule (MDASM) Registers . . . . . . . . . . . . . . . . . . . . . . . 15-19 15.11.1.1 MDASM Data A Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21 15.11.1.2 MDASM Data B Register (MDASMBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21 15.11.1.3 MDASM Status/Control Register (Duplicated) . . . . . . . . . . . . . . . . . . . . . . . . . 15-22 15.11.1.4 MDASM Status/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23 15.12 MIOS Pulse Width Modulation Submodule (MPWMSM) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-25 15.12.1 MIOS Pulse Width Modulation Submodule (MPWMSM) Registers . . . . . . . . . . . . . 15-26 15.12.1.1 MPWMSM Period Register (MPWMSMPERR) . . . . . . . . . . . . . . . . . . . . . . . . 15-27 15.12.1.2 MPWMSM Pulse Width Register (MPWMSMPULR) . . . . . . . . . . . . . . . . . . . . 15-27
14.9.12 Example QSCI1 Receive Operation of 17 Data Frames . . . . . . . . . . . . . . . . . . . . . 14-73
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15.12.1.3 MPWMSM Counter Register (MPWMSMCNTR) . . . . . . . . . . . . . . . . . . . . . . . 15-28 15.12.1.4 MPWMSM Status/Control Register(MPWMSMCR) . . . . . . . . . . . . . . . . . . . . . 15-28 15.13 MIOS 16-bit Parallel Port I/O Submodule (MPIOSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30 15.13.1 MIOS 16-bit Parallel Port I/O Submodule (MPIOSM) Registers. . . . . . . . . . . . . . . . 15-30 15.13.1.1 MPIOSM Data Register (MPIOSMDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-30 15.13.1.2 MPIOSM Data Direction Register (MPIOSMDDR) . . . . . . . . . . . . . . . . . . . . . . 15-31 15.14 MIOS1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-31 15.14.1 MIOS Interrupt Request Submodule (MIRSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-32 15.14.2 MIOS Interrupt Request Submodule 0 (MIRSM0) Registers . . . . . . . . . . . . . . . . . . 15-33 15.14.2.1 MIRSM0 Interrupt Status Register (MIOS1SR0) . . . . . . . . . . . . . . . . . . . . . . . 15-34 15.14.2.2 MIRSM0 Interrupt Enable Register (MIOS1ER0) . . . . . . . . . . . . . . . . . . . . . . . 15-35 15.14.2.3 MIRSM0 Request Pending Register (MIOS1RPR0) . . . . . . . . . . . . . . . . . . . . 15-35 15.14.3 MIOS Interrupt Request Submodule 1 (MIRSM1) Registers . . . . . . . . . . . . . . . . . . 15-36 15.14.3.1 MIRSM1 Interrupt Status Register (MIOS1SR1) . . . . . . . . . . . . . . . . . . . . . . . 15-36 15.14.3.2 MIRSM1 Interrupt Enable Register (MIOS1ER1) . . . . . . . . . . . . . . . . . . . . . . . 15-37 15.14.3.3 MIRSM1 Request Pending Register (MIOS1RPR1) . . . . . . . . . . . . . . . . . . . . 15-37 15.15 MIOS1 Function Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-38 15.15.1 MIOS1 Input Double Edge Pulse Width Measurement . . . . . . . . . . . . . . . . . . . . . . 15-38 15.15.2 MIOS1 Input Double Edge Period Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-40 15.15.3 MIOS1 Double Edge Single Output Pulse Generation . . . . . . . . . . . . . . . . . . . . . . . 15-41 15.15.4 MIOS1 Output Pulse Width Modulation With MDASM . . . . . . . . . . . . . . . . . . . . . . . 15-42 15.15.5 MIOS1 Input Pulse Accumulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-43 15.16 MIOS1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-43
Section 16 CAN 2.0B CONTROLLER MODULE

16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.2 External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.3 TouCAN Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.3.1 TX/RX Message Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 16.3.1.1 Common Fields for Extended and Standard Format Frames. . . . . . . . . . . . . . . . 16-4 16.3.1.2 Fields for Extended Format Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.3.1.3 Fields for Standard Format Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.3.1.4 Serial Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.3.1.5 Message Buffer Activation/Deactivation Mechanism . . . . . . . . . . . . . . . . . . . . . . 16-7 16.3.1.6 Message Buffer Lock/Release/Busy Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.3.2 Receive Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.3.3 Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 16.3.3.1 Configuring the TouCAN Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9 16.3.4 Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9 16.3.5 Time Stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 16.4 TouCAN Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.4.1 TouCAN Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
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16.4.2 TouCAN Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.4.3 Transmit Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.4.3.1 Transmit Message Buffer Deactivation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.4.3.2 Reception of Transmitted Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.4.4 Receive Process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.4.4.1 Receive Message Buffer Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.4.4.2 Locking and Releasing Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 16.4.5 Remote Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15 16.4.6 Overload Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16 16.5 Special Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16 16.5.1 Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16 16.5.2 Low-Power Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-17 16.5.3 Auto Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-18 16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-19 16.7 Programmers Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-20 16.7.1 TouCAN Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 16.7.2 TouCAN Test Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24 16.7.3 TouCAN Interrupt Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-24 16.7.4 Control Register 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-25 16.7.5 Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-26 16.7.6 Prescaler Divide Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-27 16.7.7 Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-28 16.7.8 Free Running Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29 16.7.9 Receive Global Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-29 16.7.10 Receive Buffer 14 Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30 16.7.11 Receive Buffer 15 Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30 16.7.12 Error and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-30 16.7.13 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-32 16.7.14 Interrupt Flag Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-33 16.7.15 Error Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-33
Section 17 TIME PROCESSOR UNIT 3

17.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.2 TPU3 Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2.1 Time Bases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2.2 Timer Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2.3 Scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2.4 Microengine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 17.2.5 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.2.6 Parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.3 TPU Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.3.1 Event Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3
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17.3.2 Channel Orthogonality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.3.3 Interchannel Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3.4 Programmable Channel Service Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3.5 Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3.6 Emulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3.7 TPU3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.3.8 Prescaler Control for TCR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.3.9 Prescaler Control for TCR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17.4 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-8 17.4.1 TPU Module Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 17.4.2 TPU3 Test Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 17.4.3 Development Support Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 17.4.4 Development Support Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 17.4.5 TPU3 Interrupt Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 17.4.6 Channel Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 17.4.7 Channel Function Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 17.4.8 Host Sequence Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 17.4.9 Host Service Request Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17 17.4.10 Channel Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 17.4.11 Channel Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 17.4.12 Link Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 17.4.13 Service Grant Latch Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 17.4.14 Decoded Channel Number Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 17.4.15 TPU3 Module Configuration Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20 17.4.16 TPU Module Configuration Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21 17.4.17 TPU3 Test Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22 17.4.18 TPU3 Parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22 17.5 Time Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23
Section 18 DUAL-PORT TPU RAM (DPTRAM)

18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.2 DPTRAM Configuration and Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.3 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.3.1 DPTRAM Module Configuration Register (DPTMCR) . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.3.2 DPTRAM Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.3.3 Ram Base Address Register (RAMBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.3.4 MISR High (MISRH) and MISR Low (MISRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.3.5 MISC Counter (MISCNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.4.1 Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.4.2 Standby Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 18.4.3 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7
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18.4.4 Stop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 18.4.5 Freeze Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 18.4.6 TPU3 Emulation Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8 18.5 Multiple Input Signature Calculator (MISC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8
Section 19 CDR MoneT FLASH EEPROM

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1.1 MPC555 / MPC556 CMF Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.1.2 Glossary of Terms for the CMF EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.2 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.2.1 CMF EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-4 19.2.1.1 CMF EEPROM Configuration Register (CMFMCR) . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.2.1.2 CMF EEPROM Test Register (CMFTST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 19.2.1.3 CMF EEPROM High Voltage Control Register (CMFCTL). . . . . . . . . . . . . . . . . . 19-9 19.2.2 CMF EEPROM Array Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-11 19.2.2.1 Read Page Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-12 19.2.2.2 Program Page Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 19.2.2.3 Array Configuration for CMF Module A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14 19.2.2.4 Array Configuration for CMF Module B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 19.3 Shadow Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 19.3.1 Address Range of Shadow Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16 19.3.2 Reset Configuration Word (CMFCFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16 19.4 Array Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-17 19.5 Programming the CMF Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18 19.5.1 Program Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18 19.5.2 Program Margin Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22 19.5.3 Over-Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23 19.6 Erasing CMF Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23 19.6.1 Erase Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23 19.6.2 Erase Margin Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26 19.6.3 Erasing Shadow Information Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26 19.7 Voltage Control for Programming and Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27 19.7.1 Pulse Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27 19.7.2 Pulse Width Timing Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27 19.7.3 System Clock Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28 19.7.4 Exponential Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-29 19.7.5 Linear Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-29 19.7.6 A Technique to Determine SCLKR, CLKPE, and CLKPM . . . . . . . . . . . . . . . . . . . . . 19-29 19.7.7 Starting and Ending a Program or Erase Sequence . . . . . . . . . . . . . . . . . . . . . . . . . 19-30 19.7.8 Controlling the Program/Erase Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31 19.8 Censored and Non-Censored Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31 19.8.1 Uncensored Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31
MOTOROLA xxiii

19.8.2 Censored Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31 19.8.3 Device Modes and Censorship Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-32 19.8.4 Setting and Clearing Censor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-33 19.8.5 Switching the CMF EEPROM Censorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-35 19.9 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-36 19.9.1 EPEE Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-36 19.9.2 FLASH Program/Erase Voltage Conditioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-37 19.10 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-39 19.10.1 Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-39 19.10.2 Soft Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-39 19.10.3 Emulation Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-40 19.11 Disabling the CMF Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-40
Section 20 STATIC RANDOM ACCESS MEMORY (SRAM)

20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.3 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.3.1 SRAM Module Configuration Register (SRAMMCR) . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.3.2 SRAM Test Register (SRAMTST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3
Section 21 DEVELOPMENT SUPPORT

21.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.2 Program Flow Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.2.1 Program Trace Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 21.2.1.1 Instruction Queue Status Pins VF [0:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.2.1.2 History Buffer Flushes Status Pins VFLS [0..1] . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.2.1.3 Queue Flush Information Special Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.2.2 Program Trace when in Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.2.3 Sequential Instructions Marked as Indirect Branch . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.2.4 The External Hardware. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.2.4.1 Synchronizing the Trace Window to the CPU Internal Events . . . . . . . . . . . . . . . 21-5 21.2.4.2 Detecting the Trace Window Start Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-6 21.2.4.3 Detecting the Assertion/Negation of VSYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 21.2.4.4 Detecting the Trace Window End Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 21.2.4.5 Compress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 21.2.5 Instruction Fetch Show Cycle Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.3 Watchpoints and Breakpoints Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.3.1 Internal Watchpoints and Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11 21.3.1.1 Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13 21.3.1.2 Byte and Half-Word Working Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-13 21.3.1.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-14 21.3.1.4 Context Dependent Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15 MPC555 / MPC555 USERS MANUAL TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xxiv

21.3.1.5 Ignore First Match. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15 21.3.1.6 Generating Six Compare Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16 21.3.2 Instruction Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-16 21.3.2.1 Load/Store Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17 21.3.3 Watchpoint Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21 21.3.3.1 Trap Enable Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21 21.4 Development System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21 21.4.1 Debug Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24 21.4.1.1 Debug Mode Enable vs. Debug Mode Disable. . . . . . . . . . . . . . . . . . . . . . . . . . 21-26 21.4.1.2 Entering Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26 21.4.1.3 The Check Stop State and Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-29 21.4.1.4 Saving Machine State upon Entering Debug Mode . . . . . . . . . . . . . . . . . . . . . . 21-29 21.4.1.5 Running in Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30 21.4.1.6 Exiting Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30 21.5 Development Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31 21.5.1 Development Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31 21.5.2 Development Serial Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31 21.5.3 Development Serial Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-31 21.5.4 Development Serial Data Out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32 21.5.5 Freeze Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32 21.5.5.1 SGPIO6/FRZ/PTR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32 21.5.5.2 IWP[0:1]/VFLS[0:1] Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32 21.5.5.3 VFLS[0:1]_MPIO32B[3:4] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32 21.5.6 Development Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32 21.5.6.1 Development Port Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33 21.5.6.2 Trap Enable Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33 21.5.6.3 Development Port Registers Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-33 21.5.6.4 Development Port Serial Communications Clock Mode Selection . . . . . . . . 21-34 21.5.6.5 Development Port Serial Communications Trap Enable Mode . . . . . . . . . . . 21-38 21.5.6.6 Serial Data into Development Port Trap Enable Mode . . . . . . . . . . . . . . . . . 21-38 21.5.6.7 Serial Data Out of Development Port Trap Enable Mode . . . . . . . . . . . . . . . 21-39 21.5.6.8 Development Port Serial Communications Debug Mode. . . . . . . . . . . . . . . . 21-39 21.5.6.9 Serial Data Into Development Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-40 21.5.6.10 Serial Data Out of Development Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-41 21.5.6.11 Fast Download Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-41 21.6 Software Monitor Debugger Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-43 21.6.1 Freeze Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-43 21.7 Development Support Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-43 21.7.1 Register Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-44 21.7.2 Comparator AD Value Registers (CMPACMPD) . . . . . . . . . . . . . . . . . . . . . . . . . . 21-45 21.7.3 Comparator EF Value Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46 21.7.4 Breakpoint Address Register (BAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46 21.7.5 Comparator GH Value Registers (CMPGCMPH) . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46 MPC555 / MPC555 USERS MANUAL TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xxv

21.7.6 I-Bus Support Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-47 21.7.7 L-Bus Support Control Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-49 21.7.8 L-Bus Support Control Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-50 21.7.9 Breakpoint Counter A Value and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-52 21.7.10 Breakpoint Counter B Value and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 21-53 21.7.11 Exception Cause Register (ECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-53 21.7.12 Debug Enable Register (DER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-55 21.7.13 Development Port Data Register (DPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-57
Section 22 IEEE 1149.1-COMPLIANT INTERFACE (JTAG)
22.1 JTAG Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.2 JTAG Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.3 Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.4 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.5 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-4 22.5.1 EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.5.2 SAMPLE/PRELOAD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.5.3 BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.5.4 CLAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.5.5 HI-Z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.6 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.7 Low-Power Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.8 Non-IEEE 1149.1-1990 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.9 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
Appendix A MPC555 / MPC556 INTERNAL MEMORY MAP Appendix B REGISTER GENERAL INDEX Appendix C REGISTER DIAGRAM INDEX Appendix D TPU ROM FUNCTIONS
D.1 D.2 D.3 D.4 D.5 D.6 D.7 D.8 D.9 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 Programmable Time Accumulator (PTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-4 Queued Output Match TPU Function (QOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-6 Table Stepper Motor (TSM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-8 Frequency Measurement (FQM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-11 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-13 New Input Capture/Transition Counter (NITC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-16 Multiphase Motor Commutation (COMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-18 Hall Effect Decode (HALLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-20 TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xxvi

D-22 D-29 D-32 D-34 D-36 D-38 D-40 D-43 D-45 D-47 D-48 D-50 D-50 D-50 D-50 D-50 D-50 D-51 D-51 D-52 D-52 D-52
D.10 Multichannel Pulse-Width Modulation (MCPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.11 Fast Quadrature Decode TPU Function (FQD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.12 Period/Pulse-Width Accumulator (PPWA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.13 Output Compare (OC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.14 Pulse-Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.15 Discrete Input/Output (DIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.16 Synchronized Pulse-Width Modulation (SPWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.17 Read / Write Timers and Pin TPU Function (RWTPIN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.18 ID TPU Function (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.19 Serial Input/Output Port (SIOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.19.1 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.19.1.1 CHAN_CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.19.1.2 BIT_D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.19.1.3 HALF_PERIOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.19.1.4 BIT_COUNT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.19.1.5 XFER_SIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.19.1.6 SIOP_DATA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.19.2 Host CPU Initialization of the SIOP Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.19.3 SIOP Function Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.19.3.1 XFER_SIZE Greater Than 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.19.3.2 Data Positioning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.19.3.3 Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix E CLOCK AND BOARD GUIDELINES

E.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.2 MPC555 / MPC556 Family Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.3 PLL and Crystal Oscillator External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.3.1 Crystal Oscillator External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.3.2 KAPWR Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.3.3 PLL External Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.3.4 PLL Off-Chip Capacitor CXFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.4 Clock Oscillator and PLL External Components Layout Requirements. . . . . . . . . . . . . . . . . . . E.4.1 Traces and Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E.4.2 Grounding/Guarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-1 E-2 E-4 E-4 E-5 E-6 E-7 E-7 E-7 E-8
Appendix F MEMORY ACCESS TIMING

F.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-1
Appendix G ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (VSS = 0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Target Failure Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G.4.1 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G.4.2 Definitions and Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G.4.3 Testing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G.5.1 Thermal References: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G.6 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPC555 / MPC555 USERS MANUAL TABLE OF CONTENTS Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com G.1 G.2 G.3 G.4 G-1 G-2 G-2 G-2 G-2 G-2 G-3 G-3 G-5 G-6
MOTOROLA xxvii

G.7 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-7 G.8 Oscillator and PLL Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-12 G.9 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-12 G.10 FLASH Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-13 G.10.1 Flash Module Life . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-14 G.10.2 Programming and Erase Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-15 G.11 Generic Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-16 G.12 Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-39 G.13 Debug Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-40 G.14 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-43 G.15 IEEE 1149.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-47 G.16 QADC64 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-52 G.17 QSMCM Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-53 G.18 GPIO Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-57 G.19 TPU3 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-57 G.20 TouCAN Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-58 G.21 MIOS Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-59 G.21.1 MPWMSM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-60 G.21.2 MMCSM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-62 G.21.3 MDASM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-65 G.21.4 MPIOSM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-68
Appendix H FLASH ELECTRICAL CHARACTERISTICS FOR ALL J76N MASK SETS AND 0K02A AND 1K02A ONLY
H.1 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-1 H.1.1 Flash Module Life. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-3 H.2 Programming and Erase Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-3
INDEX
Online publishing by JABIS, http://www.jabis.com
MOTOROLA xxviii
Figure Number
1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 3-1 3-2 3-3 3-4 4-1 4-2 4-3 4-4 4-5 4-6 4-7
LIST OF FIGURES
Page Number
MPC555 / MPC556 Block Diagram ................................................................ 1-2 MPC555 / MPC556 Memory Map ................................................................... 1-6 MPC555 / MPC556 Internal Memory Map ...................................................... 1-7 MPC555 / MPC556 Case Dimensions and Packaging ................................... 2-2 MPC555 / MPC556 Pinout Data ..................................................................... 2-3 Type A Interface ........................................................................................... 2-39 Type B Interface ........................................................................................... 2-39 Type C Interface ........................................................................................... 2-40 Type CH Interface ........................................................................................ 2-40 Type CNH Interface ...................................................................................... 2-41 Type D Interface ........................................................................................... 2-41 Type E Interface ........................................................................................... 2-42 3-V Type EOH Interface ............................................................................... 2-43 Type F Interface ........................................................................................... 2-44 Type G Interface ........................................................................................... 2-45 Type H Interface ........................................................................................... 2-46 Type I Interface ............................................................................................. 2-47 Type IH Interface .......................................................................................... 2-48 Type J Interface ............................................................................................ 2-49 Type JD Interface ......................................................................................... 2-50 EPEE Pad (Type K) ...................................................................................... 2-51 Type L Interface ............................................................................................ 2-52 Type M Interface ........................................................................................... 2-52 Type N Interface ........................................................................................... 2-53 Type O Interface ........................................................................................... 2-54 Type P Interface ........................................................................................... 2-55 Type Q Interface ........................................................................................... 2-56 Type R Interface ........................................................................................... 2-56 Type S Interface ........................................................................................... 2-57 RCPU Block Diagram ..................................................................................... 3-2 Sequencer Data Path ..................................................................................... 3-4 RCPU Programming Model ............................................................................ 3-8 Basic Instruction Pipeline ............................................................................. 3-37 Burst Buffer Block Diagram ............................................................................ 4-2 Example of Compressed Code ....................................................................... 4-5 Instruction Coding ........................................................................................... 4-5 Two Streams Memory Organization Before Compression ......................... 4-6 Two Streams Memory Organization After Compression ............................ 4-6 Examples of Compressed Symbols Layout .................................................... 4-7 Compressed Address Format ......................................................................... 4-8
LIST OF FIGURES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xxix

Figure Number
4-8 4-9 4-10 4-11 4-12 4-13 4-14 5-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 7-1 7-2 7-3 7-4 7-5 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 8-10 8-11 8-12 8-13 8-14
Page Number
Examples of Instruction Layout in Memory ..................................................... 4-9 Generating Compressed Code Address for PowerPC Direct Branches ................................................................... 4-10 Extracting Direct Branch Target Address in the Decompressor ................... 4-11 Code Compression Process (Phase A) ........................................................ 4-12 Bounded Huffman Code Tree ....................................................................... 4-13 Code Decompression Process ..................................................................... 4-14 Exception Table Entries Mapping ................................................................. 4-19 MPC555 / MPC556 USIU Block Diagram ....................................................... 5-2 System Configuration and Protection Logic ................................................... 6-2 MPC555 / MPC556 Memory Map ................................................................... 6-4 SGPIO Cell ..................................................................................................... 6-8 MPC555 / MPC556 Interrupt Structure ........................................................... 6-9 MPC555 / MPC556 Interrupt Configuration .................................................. 6-11 RTC Block Diagram ...................................................................................... 6-14 PIT Block Diagram ........................................................................................ 6-15 SWT Interrupts and Exceptions .................................................................... 6-16 SWT Block Diagram ..................................................................................... 6-17 Reset Configuration Basic Scheme ................................................................ 7-7 Reset Configuration Sampling Scheme For Short PORESET Assertion, Limp Mode Disabled .............................. 7-8 Reset Configuration Timing for Short PORESET Assertion, Limp Mode Enabled ..................................... 7-9 Reset Configuration Timing for Long PORESET Assertion, Limp Mode Disabled ..................................... 7-9 Reset Configuration Sampling Timing Requirements ................................... 7-10 Clock Unit Block Diagram ............................................................................... 8-2 Main System Oscillator (OSCM) ..................................................................... 8-3 System PLL Block Diagram ............................................................................ 8-5 MPC555 / MPC556 Clocks ............................................................................. 8-7 General System Clocks Select ..................................................................... 8-10 Divided System Clocks Timing Diagram ...................................................... 8-11 Clocks Timing For DFNH = 1 (or DFNL = 0) ................................................ 8-12 Clock Source Flow Chart .............................................................................. 8-14 MPC555 / MPC556 Low-Power Modes Flow Diagram ................................. 8-19 Basic Power Supply Configuration ............................................................... 8-22 External Power Supply Scheme ................................................................... 8-23 Keep Alive Register Key State Diagram ....................................................... 8-25 No Standby, No KAPWR, All System Power On/Off .................................... 8-27 Standby and KAPWR, Other Power On/Off ................................................. 8-28
LIST OF FIGURES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com
MOTOROLA xxx

Figure Number
9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 9-14 9-15 9-16 9-17 9-18 9-19 9-20 9-21 9-22 9-23 9-24 9-25 9-26 9-27 9-28 9-29 9-30 9-31 9-32 9-33 9-34 9-35 9-36 9-37 9-38 9-39 9-40 9-41
Page Number
Input Sample Window ..................................................................................... 9-2 MPC555 / MPC556 Bus Signals ..................................................................... 9-3 Basic Transfer Protocol .................................................................................. 9-8 Basic Flow Diagram of a Single Beat Read Cycle .......................................... 9-9 Single Beat Read CycleBasic TimingZero Wait States ............................ 9-10 Single Beat Read CycleBasic TimingOne Wait State ............................... 9-11 Basic Flow Diagram of a Single Beat Write Cycle ........................................ 9-12 Single Beat Basic Write Cycle Timing, Zero Wait States ............................. 9-13 Single Beat Basic Write Cycle Timing, One Wait State ................................ 9-14 Single Beat 32-Bit Data Write Cycle Timing, 16 Bit-Port Size ......................................................... 9-15 Basic Flow Diagram Of A Burst Read Cycle ................................................ 9-18 Burst-Read Cycle32-Bit Port SizeZero Wait State ................................... 9-19 Burst-Read Cycle32-Bit Port SizeOne Wait State .................................... 9-20 Burst-Read Cycle32-Bit Port SizeWait States Between Beats ................. 9-21 Burst-Read Cycle, 16-Bit Port Size .............................................................. 9-22 Basic Flow Diagram of a Burst Write Cycle .................................................. 9-23 Burst-Write Cycle, 32-Bit Port Size, Zero Wait States .................................. 9-24 Burst-Inhibit Cycle, 32-Bit Port Size (Emulated Burst) ................................. 9-25 Non-Wrap Burst with Three Beats ................................................................ 9-26 Non-Wrap Burst with One Data Beat ............................................................ 9-27 Internal Operand Representation ................................................................. 9-28 Interface To Different Port Size Devices ...................................................... 9-29 Bus Arbitration Flowchart ............................................................................. 9-31 Masters Signals Basic Connection ............................................................... 9-32 Bus Arbitration Timing Diagram .................................................................... 9-33 Internal Bus Arbitration State Machine ......................................................... 9-35 Termination Signals Protocol Basic Connection ........................................... 9-39 Termination Signals Protocol Timing Diagram ............................................. 9-40 Reservation On Local Bus ............................................................................ 9-41 Reservation On Multilevel Bus Hierarchy ..................................................... 9-42 Retry Transfer TimingInternal Arbiter ......................................................... 9-44 Retry Transfer TimingExternal Arbiter ........................................................ 9-45 Retry On Burst Cycle .................................................................................... 9-46 Basic Flow of an External Master Read Access ........................................... 9-48 Basic Flow of an External Master Write Access ........................................... 9-49 Peripheral Mode: External Master Reads from MPC555 / MPC556 Two Wait States ........................................... 9-50 Peripheral Mode: External Master Writes to MPC555 / MPC556; Two Wait States ........................................................................................ 9-51 Flow of Retry of External Master Read Access ............................................ 9-53 Retry of External Master Access (Internal Arbiter) ....................................... 9-54 Instruction Show Cycle Transaction ............................................................. 9-55 Data Show Cycle Transaction ...................................................................... 9-56
MOTOROLA xxxi

Figure Number
10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9
Page Number
10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 11-1 11-2 11-3 12-1 12-2 12-3 12-4 12-5 12-6 13-1 13-2 13-3 13-4 13-5 13-6
Memory Controller Function Within the USIU ............................................... 10-1 Memory Controller Block Diagram ................................................................ 10-2 MPC555 / MPC556 Simple System Configuration ....................................... 10-3 Bank Base Address and Match Structure ..................................................... 10-4 MPC555 / MPC556 GPCMMemory Devices Interface ............................... 10-7 Memory Devices Interface Basic Timing (ACS = 00,TRLX = 0) ................................................................................ 10-8 Peripheral Devices Interface ........................................................................ 10-9 Peripheral Devices Basic Timing (ACS = 11,TRLX = 0) ................................................................................ 10-9 Relaxed TimingRead Access (ACS = 11, SCY = 1, TRLX = 1) ............................................................. 10-11 Relaxed TimingWrite Access (ACS = 10, SCY = 0, CSNT = 0, TRLX = 1) ........................................... 10-12 Relaxed TimingWrite Access (ACS = 11, SCY = 0, CSNT = 1, TRLX = 1) ........................................... 10-13 Relaxed TimingWrite Access (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1 ............................................. 10-14 Consecutive Accesses (Write After Read, EHTR = 0) ................................ 10-15 Consecutive Accesses (Write After Read, EHTR = 1) ................................ 10-16 Consecutive Accesses (Read After Read From Different Banks, EHTR = 1) .............................. 10-17 Consecutive Accesses (Read After Read From Same Bank, EHTR = 1) .................................... 10-18 Aliasing Phenomena Illustration ................................................................. 10-23 Synchronous External Master Configuration For GPCMHandled Memory Devices ............................. 10-25 Synchronous External Master Basic Access (GPCM Controlled) .............. 10-26 L2U Bus Interface Block Diagram ................................................................ 11-2 DMP Basic Functional Diagram .................................................................... 11-4 Region Base Address Example .................................................................... 11-6 UIMB Interface Module Block Diagram ........................................................ 12-2 IMB Clock Full-Speed IMB Bus ................................................................. 12-3 IMB Clock Half-Speed IMB Bus ................................................................. 12-3 Interrupt Synchronizer Signal Flow ............................................................... 12-4 Time-Multiplexing Protocol for IRQ pins ....................................................... 12-5 Interrupt Synchronizer Block diagram .......................................................... 12-6 QADC64 Block Diagram ............................................................................... 13-1 QADC64 Input and Output Signals ............................................................... 13-3 Example of External Multiplexing ............................................................... 13-10 QADC64 Module Block Diagram ................................................................ 13-12 Conversion Timing ...................................................................................... 13-13 Bypass Mode Conversion Timing ............................................................... 13-13
LIST OF FIGURES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xxxii

Figure Number
13-7 13-8 13-9 13-10 13-11 13-12 14-1 14-2 14-3 14-4 14-5 14-6 14-7 14-8 14-9 14-10 14-11 14-12 14-13 14-14 14-15 14-16 14-17 14-18 14-19 14-20 14-21 14-22 14-23 15-1 15-2 15-3 15-4 15-5 15-6 15-7 15-8 15-9 15-10 15-11 15-12 16-1 16-2
Page Number
QADC64 Queue Operation with Pause ...................................................... 13-16 QADC64 Clock Subsystem Functions ........................................................ 13-26 QADC64 Clock Programmability Examples ............................................... 13-28 QADC64 Interrupt Flow Diagram ................................................................ 13-30 Interrupt Levels on IRQ with ILBS .............................................................. 13-31 QADC64 Conversion Queue Operation ..................................................... 13-44 QSMCM Block Diagram ............................................................................... 14-2 QSMCM Interrupt Levels .............................................................................. 14-6 QSPI Interrupt Generation ............................................................................ 14-7 QSPI Block Diagram ................................................................................... 14-14 QSPI RAM .................................................................................................. 14-22 Flowchart of QSPI Initialization Operation .................................................. 14-27 Flowchart of QSPI Master Operation (Part 1) ............................................. 14-28 Flowchart of QSPI Master Operation (Part 2) ............................................. 14-29 Flowchart of QSPI Master Operation (Part 3) ............................................. 14-30 Flowchart of QSPI Slave Operation (Part 1) ............................................... 14-31 Flowchart of QSPI Slave Operation (Part 2) ............................................... 14-32 SCI Transmitter Block Diagram .................................................................. 14-42 SCI Receiver Block Diagram ...................................................................... 14-43 Start Search Example ................................................................................. 14-56 Queue Transmitter Block Enhancements ................................................... 14-62 Queue Transmit Flow ................................................................................. 14-64 Queue Transmit Software Flow .................................................................. 14-65 Queue Transmit Example for 17 Data Bytes .............................................. 14-66 Queue Transmit Example for 25 Data Frames ........................................... 14-67 Queue Receiver Block Enhancements ....................................................... 14-68 Queue Receive Flow .................................................................................. 14-71 Queue Receive Software Flow ................................................................... 14-72 Queue Receive Example for 17 Data Bytes ............................................... 14-73 MIOS1 Block Diagram .................................................................................. 15-5 MIOS1 Memory Map .................................................................................... 15-7 MCPSM Block Diagram .............................................................................. 15-12 MMCSM Block Diagram ............................................................................. 15-15 MDASM Block Diagram .............................................................................. 15-19 MPWMSM Block Diagram .......................................................................... 15-25 MPIOSM One-Bit Block Diagram ............................................................... 15-30 MIOS Interrupt Structure ............................................................................ 15-32 MIOS1 Example: Double Capture Pulse Width Measurement ................... 15-39 MIOS1 Example: Double Capture Period Measurement ............................ 15-40 MIOS1 Example: Double Edge Output Compare ....................................... 15-41 MIOS1 Example: Pulse Width Modulation Output ...................................... 15-43 TouCAN Block Diagram ............................................................................... 16-1 Typical CAN Network ................................................................................... 16-3
LIST OF FIGURES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xxxiii

Figure Number
16-3 16-4 16-5 16-6 17-1 17-2 17-3 17-4 18-1 18-2
Page Number
Extended ID Message Buffer Structure ........................................................ 16-4 Standard ID Message Buffer Structure ......................................................... 16-4 Interrupt levels on IRQ with ILBS ............................................................... 16-20 TouCAN Message Buffer Memory Map ...................................................... 16-22 TPU3 Block Diagram .................................................................................... 17-1 TPU3 Interrupt Levels ................................................................................... 17-5 TCR1 Prescaler Control ............................................................................... 17-7 TCR2 Prescaler Control ............................................................................... 17-8 DPTRAM Configuration ................................................................................ 18-2 DPTRAM Memory Map ................................................................................ 18-3 CMF Array and Control Register Addressing ............................................... 19-4 Shadow Information .................................................................................... 19-16 Program State Diagram .............................................................................. 19-20 Erase State Diagram .................................................................................. 19-25 Pulse Status Timing .................................................................................... 19-27 Censorship States and Transitions ............................................................. 19-35 EPEE Digital Filter and Latch ..................................................................... 19-36 CMF_EPEE Timing Diagram ...................................................................... 19-37 VPP and VDDL Power Switching ............................................................... 19-38 VPP Conditioning Circuit ............................................................................ 19-39 SRAM Block Diagram ................................................................................... 20-1 SRAM Memory Map ..................................................................................... 20-2 Watchpoints and Breakpoint Support in the CPU ....................................... 21-10 Partially Supported Watchpoint/Breakpoint Example ................................. 21-15 Instruction Support General Structure ........................................................ 21-17 Load/Store Support General Structure ....................................................... 21-20 Functional Diagram of MPC555 / MPC556 Debug Mode Support ............. 21-23 Debug Mode Logic ..................................................................................... 21-25 Debug Mode Reset Configuration .............................................................. 21-27 Asynchronous Clock Serial Communications ............................................. 21-35 Synchronous Self Clock Serial Communication ......................................... 21-36 Enabling Clock Mode Following Reset ....................................................... 21-37 Download Procedure Code Example ......................................................... 21-42 Slow Download Procedure Loop ................................................................ 21-42 Fast Download Procedure Loop ................................................................. 21-42 JTAG Pins .................................................................................................... 22-1 Test Logic Block Diagram ............................................................................. 22-2 TAP Controller State Machine ...................................................................... 22-4 Bypass Register ........................................................................................... 22-6 Output Pin Cell (O.pin) ................................................................................. 22-8
LIST OF FIGURES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xxxiv
19-1 19-2 19-3 19-4 19-5 19-6 19-7 19-8 19-9 19-10 20-1 20-2 21-1 21-2 21-3 21-4 21-5 21-6 21-7 21-8 21-9 21-10 21-11 21-12 21-13 22-1 22-2 22-3 22-4 22-5

Figure Number
22-6 22-7 22-8 D-1 D-2 D-3 D-4 D-5 D-6 D-7 D-8 D-9 D-10 D-11 D-12 D-13 D-14 D-15 D-16 D-17 D-18 D-19 D-20 D-21 D-22 D-23 D-24 D-25 D-26 D-27 D-28 D-29 D-30 D-31 E-1 E-2 E-3 E-4 E-5 E-6
Page Number
Observe-Only Input Pin Cell (I.Obs) ............................................................. 22-8 Output Control Cell (IO.CTL) ........................................................................ 22-9 General Arrangement of Bidirectional Pin Cells ........................................... 22-9 TPU3 Memory Map ........................................................................................D-1 PTA Parameters .............................................................................................D-5 QOM Parameters ...........................................................................................D-7 TSM Parameters Master Mode ..................................................................D-9 TSM Parameters Slave Mode ..................................................................D-10 FQM Parameters ..........................................................................................D-12 UART Transmitter Parameters .....................................................................D-14 UART Receiver Parameters .........................................................................D-15 NITC Parameters .........................................................................................D-17 COMM Parameters (Part 1 of 2) ..................................................................D-19 COMM Parameters (Part 2 of 2) ..................................................................D-20 HALLD Parameters ......................................................................................D-21 MCPWM Parameters Master Mode .........................................................D-23 MCPWM Parameters Slave Edge-Aligned Mode ....................................D-24 MCPWM Parameters Slave Ch A Non-Inverted Center-Aligned Mode ...................................................................................D-25 MCPWM Parameters Slave Ch B Non-Inverted Center-Aligned Mode ...................................................................................D-26 MCPWM Parameters Slave Ch A Inverted Center-Aligned Mode ...................................................................................D-27 MCPWM Parameters Slave Ch B Non-Inverted Center-Aligned Mode ...................................................................................D-28 FQD Parameters Primary Channel ..........................................................D-30 FQD Parameters Secondary Channel .....................................................D-31 PPWA Parameters .......................................................................................D-33 OC Parameters ............................................................................................D-35 PWM Parameters .........................................................................................D-37 DIO Parameters ...........................................................................................D-39 SPWM Parameters, Part 1 of 2 ....................................................................D-41 SPWM Parameters, Part 2 of 2 ....................................................................D-42 RWTPIN Parameters ....................................................................................D-44 ID Parameters ..............................................................................................D-46 Two Possible SIOP Configurations ..............................................................D-47 SIOP Parameters .........................................................................................D-49 SIOP Function Data Transition Example ......................................................D-53 MPC555 / MPC556 Family Power Distribution Diagram 3 V ..................... E-2 MPC555 / MPC556 Family Power Distribution Diagram 5 V and Analog .. E-3 Crystal Oscillator Circuit ................................................................................. E-4 RC Filter Example .......................................................................................... E-5 Bypass Capacitors Example (Alternative) ...................................................... E-6 RC Filter Example .......................................................................................... E-6
LIST OF FIGURES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xxxv

Figure Number
E-7 E-8 G-1 G-2 G-3 G-4 G-5 G-6 G-7 G-8 G-9 G-10 G-11 G-12 G-13 G-14 G-15 G-16 G-17 G-18 G-19 G-20 G-21 G-22 G-23 G-24 G-25 G-26 G-27 G-28 G-29 G-30 G-31 G-32 G-33 G-34 G-35 G-36 G-37 G-38 G-39
Page Number
LC Filter Example (Alternative) ...................................................................... E-7 PLL Off-Chip Capacitor Example ................................................................... E-7 CLKOUT Timing .......................................................................................... G-16 External Clock Timing ................................................................................. G-23 Synchronous Output Signals Timing ........................................................... G-24 Synchronous Active Pull-Up and Open Drain Outputs Signals Timing ....... G-25 Synchronous Input Signals Timing .............................................................. G-26 Input Data Timing in Normal Case .............................................................. G-27 External Bus Read Timing (GPCM Controlled ACS = 00) .................... G-28 External Bus Read Timing (GPCM Controlled TRLX = 0 ACS = 10) .. G-29 External Bus Read Timing (GPCM Controlled TRLX = 0 ACS = 11) .. G-30 External Bus Read Timing (GPCM Controlled TRLX = 1, ACS = 10, ACS = 11) ......................... G-31 Address Show Cycle Bus Timing ................................................................ G-32 Address and Data Show Cycle Bus Timing ................................................. G-33 External Bus Write Timing (GPCM Controlled TRLX = 0, CSNT = 0) . G-34 External Bus Write Timing (GPCM Controlled TRLX = 0, CSNT = 1) . G-35 External Bus Write Timing (GPCM Controlled TRLX = 1, CSNT = 1) . G-36 External Master Read from Internal Registers Timing ................................ G-37 External Master Write to Internal Registers Timing ..................................... G-38 Interrupt Detection Timing for External Level Sensitive Lines ..................... G-39 Interrupt Detection Timing for External Edge Sensitive Lines ..................... G-40 Debug Port Clock Input Timing ................................................................... G-41 Debug Port Timings ..................................................................................... G-42 Reset Timing Configuration from Data Bus ............................................ G-44 Reset Timing Data Bus Weak Drive During Configuration ..................... G-45 Reset Timing Debug Port Configuration ................................................. G-46 JTAG Test Clock Input Timing .................................................................... G-48 JTAG Test Access Port Timing Diagram ................................................ G-49 JTAG TRST Timing Diagram .................................................................. G-50 Boundary Scan (JTAG) Timing Diagram ..................................................... G-51 QSPI Timing Master, CPHA = 0 ............................................................. G-55 QSPI Timing Master, CPHA = 1 ............................................................. G-55 QSPI Timing Slave, CPHA = 0 ............................................................... G-56 QSPI Timing Slave, CPHA = 1 ............................................................... G-56 TPU3 Timing ............................................................................................... G-58 MCPSM Enable to vs_pclk Pulse Timing Diagram ..................................... G-59 MPWMSM Minimum Output Pulse Example Timing Diagram .................... G-60 MCPSM Enable to MPWMO Output Pin Rising Edge Timing Diagram ....................................................................... G-61 MPWMSM Enable to MPWMO Output Pin Rising Edge Timing Diagram ....................................................................... G-61 MPWMSM Interrupt Flag to MPWMO Output Pin Falling Edge Timing Diagram ........................................................................................... G-62 MMCSM Minimum Input Pin (Either Load or Clock)
LIST OF FIGURES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xxxvi

Figure Number
G-40 G-41 G-42 G-43 G-44 G-45 G-46
Page Number
G-47 G-48 G-49 G-50
Timing Diagram ........................................................................................... G-63 MMCSM Clock Pin to Counter Bus Increment Timing Diagram ........................................................................................... G-63 MMCSM Load Pin to Counter Bus Reload Timing Diagram ....................... G-63 MMCSM Counter Bus Reload to Interrupt Flag Setting Timing Diagram ....................................................................... G-64 MMCSM Prescaler Clock Select to Counter Bus Increment Timing Diagram ........................................................................................... G-64 MDASM Minimum Input Pin Timing Diagram .............................................. G-65 MDASM Input Pin to Counter Bus Capture Timing Diagram ........................................................................................... G-66 MDASM Input Pin to MDASM Interrupt Flag Timing Diagram ........................................................................................... G-66 MDASM Minimum Output Pulse Width Timing Diagram ........................................................................................... G-66 Counter Bus to MDASM Output Pin Change Timing Diagram ........................................................................................... G-67 Counter Bus to MDASM Interrupt Flag Setting Timing Diagram ........................................................................................... G-67 MPIOSM Input Pin to MPIOSM_DR (Data Register) Timing Diagram ........................................................................................... G-68 Typical Program Time vs. VPP and Temperature (for CDR1 Target Process) ..........................................................................H-2
H-1
MOTOROLA xxxvii

Figure Number Page Number

MOTOROLA xxxviii
Table Number
2-1 2-2 2-3 2-4 2-5 2-6
LIST OF TABLES
Page Number
MPC555 / MPC556 Pin Functions for 272-Pin PBGA ........................................... 2-4 Pin Functionality Table .......................................................................................... 2-7 PDMCR Bit Descriptions..................................................................................... 2-29 Pin Reset State.................................................................................................... 2-32 Pad Groups Based on 3-V / 5-V Select ............................................................... 2-57 Pin Names and Abbreviations ............................................................................. 2-58
3-1 RCPU Execution Units........................................................................................... 3-5 3-2 Supervisor-Level SPRs.......................................................................................... 3-9 3-3 Development Support SPRs................................................................................ 3-11 3-4 FPSCR Bit Categories ......................................................................................... 3-13 3-5 FPSCR Bit Descriptions....................................................................................... 3-14 3-6 Floating-Point Result Flags in FPSCR................................................................. 3-15 3-7 Bit Descriptions for CR0 Field of CR ................................................................... 3-16 3-8 Bit Descriptions for CR1 Field of CR ................................................................... 3-17 3-9 CRn Field Bit Descriptions for Compare Instructions .......................................... 3-17 3-10 Integer Exception Register Bit Definitions ......................................................... 3-18 3-11 Time Base Field Definitions (Read Only)........................................................... 3-19 3-12 Machine State Register Bit Descriptions ........................................................... 3-21 3-13 Floating-Point Exception Mode Bits................................................................... 3-22 3-14 Time Base Field Definitions (Write Only)........................................................... 3-23 3-15 Uses of SPRG0SPRG3 ................................................................................... 3-25 3-16 Processor Version Register Bit Descriptions ..................................................... 3-26 3-17 EIE, EID, AND NRI Registers ............................................................................ 3-26 3-18 FPECR Bit Descriptions..................................................................................... 3-27 3-19 Instruction Set Summary ................................................................................... 3-29 3-20 MPC555 / MPC556 Exception Classes ............................................................. 3-34 3-21 Exception Vector Offset Table .......................................................................... 3-36 3-22 Instruction Latency and Blockage...................................................................... 3-38 3-23 Floating-Point Exception Mode Encoding.......................................................... 3-43 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 Exception Addresses Mapping by BBC ............................................................... 4-18 Region Base Address Registers RBA[0:1] .......................................................... 4-20 Region Attributes Registers ................................................................................. 4-20 BBC Module Configuration Register.................................................................... 4-20 MI_RBA[0:3] Bit Descriptions ............................................................................. 4-21 MI_RA[0:3] Registers Bits Description................................................................ 4-22 MI_GRA Bit Descriptions .................................................................................... 4-23 BBCMCR Bit Descriptions .................................................................................. 4-24
5-1 USIU Address Map ................................................................................................ 5-3 5-2 USIU Special-Purpose Registers........................................................................... 5-6 5-3 PowerPC Address Range...................................................................................... 5-6
MPC555 / MPC556 USERS MANUAL LIST OF TABLES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xxxix

Table Number Page Number
6-1 USIU Pins Multiplexing Control.............................................................................. 6-3 6-2 SGPIO Configuration ............................................................................................. 6-7 6-3 Priority of Interrupt Sources ................................................................................. 6-12 6-4 Decrementer Time-Out Periods........................................................................... 6-13 6-5 SIUMCR Bit Descriptions.................................................................................... 6-19 6-6 Debug Pins Configuration.................................................................................... 6-20 6-7 Debug Port Pins Configuration ............................................................................ 6-20 6-8 General Pins Configuration.................................................................................. 6-20 6-9 Single-Chip Select Field Pin Configuration.......................................................... 6-20 6-10 Multi-Level Reservation Control Pin Configuration ............................................ 6-21 6-11 IMMR Bit Descriptions ...................................................................................... 6-22 6-12 EMCR Bit Descriptions ..................................................................................... 6-23 6-13 SYPCR Bit Descriptions ................................................................................... 6-26 6-14 SWSR Bit Descriptions ..................................................................................... 6-27 6-15 TESR Bit Descriptions ...................................................................................... 6-28 6-16 TBSCR Bit Descriptions.................................................................................... 6-30 6-17 RTCSC Bit Descriptions ................................................................................... 6-31 6-18 PISCR Bit Descriptions..................................................................................... 6-32 6-19 PITC Bit Descriptions........................................................................................ 6-33 6-20 PIT Bit Descriptions .......................................................................................... 6-33 6-21 SGPIODT1 Bit Descriptions.............................................................................. 6-34 6-22 SGPIODT2 Bit Descriptions.............................................................................. 6-35 6-23 SGPIOCR Bit Descriptions ............................................................................... 6-35 6-24 Data Direction Control ....................................................................................... 6-36 7-1 7-2 7-3 7-4 7-5 Reset Action Taken For Each Reset Cause .......................................................... 7-4 Reset Configuration Word and Data Corruption/Coherency.................................. 7-4 Reset Status Register Bit Descriptions.................................................................. 7-5 Reset Configuration Options.................................................................................. 7-7 Hard Reset Configuration Word Bit Descriptions................................................ 7-11
8-1 Reset Clocks Source Configuration....................................................................... 8-9 8-2 TMBCLK Divisions................................................................................................. 8-9 8-3 Status of Clock Source ........................................................................................ 8-15 8-4 Power Mode Control Bit Descriptions ................................................................. 8-16 8-5 Power Mode Descriptions................................................................................... 8-16 8-6 Power Mode Wake-Up Operation....................................................................... 8-17 8-7 Clock Unit Power Supply ..................................................................................... 8-20 8-8 KAPWR Registers and Key Registers ................................................................. 8-24 8-9 SCCR Bit Descriptions........................................................................................ 8-30 8-10 PLPRCR Bit Descriptions ................................................................................. 8-34 8-11 COLIR Bit Descriptions..................................................................................... 8-36 8-12 VSRMCR Bit Descriptions ................................................................................ 8-36 9-1 MPC555 / MPC556 SIU Signals ............................................................................ 9-4 9-2 Data Bus Requirements For Read Cycles........................................................... 9-30
MPC555 / MPC556 USERS MANUAL LIST OF TABLES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xl

Table Number
9-3 9-4 9-5 9-6 9-7 9-8 9-9
Page Number
Data Bus Contents for Write Cycles .................................................................... 9-30 Priority Between Internal and External Masters over External Bus ..................... 9-34 Burst Length and Order ....................................................................................... 9-36 BURST/TSIZE Encoding ..................................................................................... 9-37 Address Type Pins............................................................................................... 9-37 Address Types Definition..................................................................................... 9-38 Termination Signals Protocol............................................................................... 9-47
10-1 Timing Attributes Summary ............................................................................... 10-6 10-2 Programming Rules for Strobes Timing........................................................... 10-19 10-3 Boot Bank Fields Values After Hard Reset...................................................... 10-20 10-4 Write Enable/Byte Enable Signals Function .................................................... 10-21 10-5 Memory Controller Address Map ..................................................................... 10-27 10-6 MSTAT Bit Descriptions.................................................................................. 10-28 10-7 BR0 BR3 Bit Descriptions............................................................................ 10-29 10-8 OR0 OR3 Bit Descriptions ........................................................................... 10-30 10-9 DMBR Bit Descriptions ................................................................................... 10-32 10-10 DMOR Bit Descriptions.................................................................................. 10-33 11-1 DMPU Registers ................................................................................................ 11-6 11-2 Reservation Snoop Support............................................................................... 11-9 11-3 L2U_MCR LSHOW Modes ................................................................................ 11-9 11-4 L2U Show Cycle Support Chart....................................................................... 11-12 11-5 L2U (PPC) Register Decode............................................................................ 11-12 11-6 Hex Address For SPR Cycles.......................................................................... 11-13 11-7 L2U_MCR Bit Descriptions ............................................................................. 11-14 11-8 L2U_RBAx Bit Descriptions ............................................................................ 11-14 11-9 L2U_RAx Bit Descriptions .............................................................................. 11-15 11-10 L2U_GRA Bit Descriptions ........................................................................... 11-16 12-1 12-2 12-3 12-4 12-5 12-6 12-7 13-1 13-2 13-3 13-4 13-5 13-6 13-7 13-8 STOP and HSPEED Bit Functionality................................................................ 12-2 Bus Cycles and System Clock Cycles ............................................................... 12-3 ILBS Signal functionality .................................................................................... 12-5 IRQMUX Functionality ....................................................................................... 12-5 UIMB Interface Register Map ............................................................................ 12-7 UMCR Bit Descriptions ..................................................................................... 12-8 UIPEND Bit Descriptions ................................................................................... 12-9 Multiplexed Analog Input Channels ................................................................... 13-5 Analog Input Channels .................................................................................... 13-11 Queue 1 Priority Assertion............................................................................... 13-15 QADC64 Clock Programmability ..................................................................... 13-28 QADC64 Status Flags and Interrupt Sources.................................................. 13-30 QADC64 Address Map .................................................................................... 13-32 QADC64MCR Bit Descriptions ....................................................................... 13-33 QADC64INT Bit Descriptions.......................................................................... 13-34
LIST OF TABLES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xli

13-9 PORTQA, PORTQB Bit Descriptions ............................................................. 13-34 13-10 DDRQA Bit Descriptions............................................................................... 13-35 13-11 QACR0 Bit Descriptions ............................................................................... 13-36 13-12 QACR1 Bit Descriptions ............................................................................... 13-37 13-13 Queue 1 Operating Modes ............................................................................ 13-38 13-14 QACR2 Bit Descriptions ............................................................................... 13-39 13-15 Queue 2 Operating Modes ............................................................................ 13-40 13-16 QASR0 Bit Descriptions................................................................................ 13-41 13-17 Queue Status................................................................................................. 13-42 13-18 QASR0 Bit Descriptions................................................................................ 13-43 13-19 CCW Bit Descriptions ................................................................................... 13-47 13-20 Non-Multiplexed Channel Assignments and Pin Designations...................... 13-48 13-21 Multiplexed Channel Assignments and Pin Designations.............................. 13-48 14-1 QSMCM Register Map....................................................................................... 14-3 14-2 QSMCM Global Registers ................................................................................. 14-5 14-3 Interrupt Levels .................................................................................................. 14-6 14-4 QSMCMMCR Bit Descriptions........................................................................... 14-8 14-5 QDSCI_IL Bit Descriptions ................................................................................ 14-8 14-6 QSPI_IL Bit Descriptions ................................................................................... 14-9 14-7 QSMCM Pin Control Registers .......................................................................... 14-9 14-8 Effect of DDRQS on QSPI Pin Function .......................................................... 14-10 14-9 QSMCM Pin Functions .................................................................................... 14-11 14-10 PQSPAR Bit Descriptions.............................................................................. 14-12 14-11 DDRQS Bit Descriptions................................................................................ 14-13 14-12 QSPI Register Map........................................................................................ 14-16 14-13 SPCR0 Bit Descriptions................................................................................ 14-17 14-14 Bits Per Transfer............................................................................................ 14-17 14-15 SPCR1 Bit Descriptions................................................................................ 14-18 14-16 SPCR2 Bit Descriptions................................................................................ 14-19 14-17 SPCR3 Bit Descriptions................................................................................ 14-20 14-18 SPSR Bit Descriptions .................................................................................. 14-21 14-19 Command RAM Bit Descriptions .................................................................. 14-23 14-20 QSPI Pin Functions ....................................................................................... 14-24 14-21 Example SCK Frequencies with a 40-MHz IMB Clock .................................. 14-35 14-22 SCI Registers................................................................................................. 14-44 14-23 SCCxR0 Bit Descriptions.............................................................................. 14-45 14-24 SCCxR1 Bit Descriptions.............................................................................. 14-46 14-25 SCxSR Bit Descriptions ................................................................................ 14-48 14-26 SCxSR Bit Descriptions ................................................................................ 14-50 14-27 SCI Pin Functions .......................................................................................... 14-50 14-28 Serial Frame Formats .................................................................................... 14-51 14-29 Examples of SCIx Baud Rates ...................................................................... 14-52 14-30 QSCI1CR Bit Descriptions............................................................................ 14-60 14-31 QSCI1SR Bit Descriptions ............................................................................ 14-61 15-1 MIOS1 I/O Ports ................................................................................................ 15-8
MPC555 / MPC556 USERS MANUAL LIST OF TABLES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xlii

15-2 MBISM Address Map......................................................................................... 15-8 15-3 MIOS1TPCR Bit Descriptions............................................................................ 15-9 15-4 MIOS1VNR Bit Descriptions .............................................................................. 15-9 15-5 MIOS1MCR Bit Descriptions ........................................................................... 15-10 15-6 MBISM Interrupt Registers Address Map ........................................................ 15-10 15-7 MIOS1LVL0 Bit Descriptions ........................................................................... 15-11 15-8 MIOS1LVL1 Bit Descriptions ........................................................................... 15-11 15-9 MCPSM Address Map ..................................................................................... 15-13 15-10 MCPSMSCR Bit Descriptions........................................................................ 15-13 15-11 MMCSM Address Map................................................................................... 15-15 15-12 MMCSMCNT Bit Descriptions ....................................................................... 15-16 15-13 MMCSMML Bit Descriptions.......................................................................... 15-16 15-14 MMCSMSCR Bit Descriptions ....................................................................... 15-17 15-15 MMCSMCR CP and MPWMSMSCR CP Values.......................................................................... 15-18 15-16 MDASM Address Map ................................................................................... 15-20 15-17 MDASMSCR Bit Descriptions........................................................................ 15-23 15-18 MDASM Mode Selects................................................................................... 15-24 15-19 MPWMSM Address Map ............................................................................... 15-26 15-20 MPWMSMPERR Bit Descriptions.................................................................. 15-27 15-21 MPWMSMPULR Bit Descriptions .................................................................. 15-27 15-22 MPWMSMCNTR Bit Descriptions.................................................................. 15-28 15-23 MPWMSMSCR Bit Descriptions .................................................................... 15-29 15-24 PWMSM Output Pin Polarity Selection.......................................................... 15-29 15-25 MPIOSM Address Map .................................................................................. 15-30 15-26 MPIOSMDR Bit Descriptions ......................................................................... 15-31 15-27 MPIOSMDDR Bit Descriptions ...................................................................... 15-31 15-28 MIRSM0 Address Map................................................................................... 15-34 15-29 MIOS1SR0 Bit Descriptions........................................................................... 15-34 15-30 MIOS1ER0 Bit Descriptions........................................................................... 15-35 15-31 MIOS1RPR0 Bit Descriptions ........................................................................ 15-36 15-32 MIRSM1 Address Map................................................................................... 15-36 15-33 MIOS1SR1 Bit Descriptions........................................................................... 15-37 15-34 MIOS1ER1 Bit Descriptions........................................................................... 15-37 15-35 MIOS1RPR1 Bit Descriptions ........................................................................ 15-38 15-36 MIOS1 Configuration ..................................................................................... 15-44 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 16-9 Common Extended/Standard Format Frames................................................... 16-5 Message Buffer Codes for Receive Buffers....................................................... 16-5 Message Buffer Codes for Transmit Buffers...................................................... 16-5 Extended Format Frames .................................................................................. 16-6 Standard Format Frames................................................................................... 16-6 Receive Mask Register Bit Values..................................................................... 16-8 Mask Examples for Normal/Extended Messages .............................................. 16-8 Example IMB Clock, CAN Bit Rate and S-Clock Frequencies........................... 16-9 Interrupt Levels ................................................................................................ 16-19
LIST OF TABLES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xliii

Table Number
16-10 16-11 16-12 16-13 16-14 16-15 16-16 16-17 16-18 16-19 16-20 16-21 16-22 16-23 16-24 16-25 16-26
Page Number
TouCAN Register Map................................................................................... 16-21 TCNMCR Bit Descriptions ............................................................................ 16-23 CANICR Bit Descriptions .............................................................................. 16-25 CANCTRL0 Bit Descriptions......................................................................... 16-25 RX MODE[1:0] Configuration......................................................................... 16-26 Transmit Pin Configuration ............................................................................ 16-26 CANCTRL1 Bit Descriptions.......................................................................... 16-27 PRESDIV Bit Descriptions ............................................................................ 16-28 CANCTRL2 Bit Descriptions......................................................................... 16-28 TIMER Bit Descriptions................................................................................. 16-29 RXGMSKHI, RXGMSKLO Bit Descriptions .................................................. 16-30 ESTAT Bit Descriptions ................................................................................ 16-31 Transmit Bit Error Status ............................................................................... 16-32 Fault Confinement State Encoding ................................................................ 16-32 IMASK Bit Descriptions................................................................................. 16-32 IFLAG Bit Descriptions ................................................................................. 16-33 RXECTR, TXECTR Bit Descriptions............................................................. 16-33
17-1 Enhanced TCR1 Prescaler Divide Values ........................................................ 17-6 17-2 TCR1 Prescaler Values ..................................................................................... 17-6 17-3 TCR2 Counter Clock Source ............................................................................. 17-7 17-4 TCR2 Prescaler Control..................................................................................... 17-8 17-5 TPU3 Register Map ........................................................................................... 17-9 17-6 TPUMCR Bit Descriptions .............................................................................. 17-11 17-7 DSCR Bit Descriptions.................................................................................... 17-13 17-8 DSSR Bit Descriptions.................................................................................... 17-14 17-9 TICR Bit Descriptions ..................................................................................... 17-15 17-10 CIER Bit Descriptions ................................................................................... 17-15 17-11 CFSRx Bit Descriptions ................................................................................ 17-16 17-12 HSQRx Bit Descriptions................................................................................ 17-17 17-13 HSSRx Bit Descriptions ................................................................................ 17-18 17-14 CPRx Bit Descriptions .................................................................................. 17-18 17-15 Channel Priorities .......................................................................................... 17-19 17-16 CISR Bit Descriptions ................................................................................... 17-19 17-17 TPUMCR2 Bit Descriptions .......................................................................... 17-20 17-18 Entry Table Bank Location............................................................................. 17-21 17-19 IMB Clock Frequency/Minimum Guaranteed Detected Pulse ....................... 17-21 17-20 TPUMCR3 Bit Descriptions .......................................................................... 17-21 17-21 Parameter RAM Address Offset Map ............................................................ 17-22 18-1 DPTRAM Register Map ..................................................................................... 18-3 18-2 DPTMCR Bit Descriptions ................................................................................ 18-4 18-3 RAMBAR Bit Descriptions ................................................................................ 18-5 19-1 CMF Register Programmers Model .................................................................. 19-5 19-2 CMFMCR Bit Descriptions................................................................................. 19-6
MPC555 / MPC556 USERS MANUAL LIST OF TABLES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xliv

19-3 CMFTST Bit Descriptions .................................................................................. 19-8 19-4 CMF Programming Algorithm (v6 and Later)..................................................... 19-8 19-5 CMF Erase Algorithm (v6) ................................................................................. 19-9 19-6 CMFCTL Bit Descriptions ................................................................................ 19-10 19-7 EEPROM Array Addressing............................................................................. 19-12 19-8 CMF EEPROM Array Address Fields .............................................................. 19-12 19-9 Program Interlock State Descriptions .............................................................. 19-21 19-10 Results of Programming Margin Read........................................................... 19-22 19-11 Erase Interlock State Descriptions................................................................. 19-26 19-12 System Clock Range ..................................................................................... 19-28 19-13 Clock Period Exponent and Pulse Width Range ........................................... 19-29 19-14 Censorship Control Bits ................................................................................. 19-31 19-15 Levels of Censorship ..................................................................................... 19-32 19-16 CMF EEPROM Devices Modes and Censorship Status ............................... 19-33 19-17 NVM Fuse States........................................................................................... 19-34 20-1 SRAMMCR Bit Descriptions ............................................................................. 20-3 21-1 VF Pins Instruction Encodings.......................................................................... 21-3 21-2 VF Pins Queue Flush Encodings....................................................................... 21-4 21-3 VFLS Pin Encodings.......................................................................................... 21-4 21-4 Detecting the Trace Buffer Start Point ............................................................... 21-7 21-5 Fetch Show Cycles Control ............................................................................... 21-8 21-6 Instruction Watchpoints Programming Options ............................................... 21-17 21-7 Load/Store Data Events................................................................................... 21-18 21-8 Load/Store Watchpoints Programming Options .............................................. 21-19 21-9 The Check Stop State and Debug Mode ......................................................... 21-29 21-10 Trap Enable Data Shifted into Development Port Shift Register ................... 21-38 21-11 Debug Port Command Shifted Into Development Port Shift Register ........... 21-38 21-12 Status / Data Shifted Out of Development Port Shift Register....................... 21-39 21-13 Debug Instructions / Data Shifted Into Development Port Shift Register....... 21-40 21-14 Development Support Programming Model................................................... 21-44 21-15 Development Support Registers Read Access Protection ............................ 21-45 21-16 Development Support Registers Write Access Protection............................. 21-45 21-17 CMPA-CMPD Bit Descriptions....................................................................... 21-45 21-18 CMPE-CMPF Bit Descriptions ....................................................................... 21-46 21-19 BAR Bit Descriptions ..................................................................................... 21-46 21-20 CMPG-CMPH Bit Descriptions ...................................................................... 21-46 21-21 ICTRL Bit Descriptions .................................................................................. 21-48 21-22 ISCT_SER Bit Descriptions ........................................................................... 21-49 21-23 LCTRL1 Bit Descriptions ............................................................................... 21-50 21-24 LCTRL2 Bit Descriptions ............................................................................... 21-51 21-25 Breakpoint Counter A Value and Control Register (COUNTA)...................... 21-52 21-26 Breakpoint Counter B Value and Control Register (COUNTB)..................... 21-53 21-27 ECR Bit Descriptions ..................................................................................... 21-54 21-28 DER Bit Descriptions ..................................................................................... 21-55
MPC555 / MPC556 USERS MANUAL LIST OF TABLES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xlv

22-1 JTAG Interface Pin Descriptions........................................................................ 22-3 22-2 Instruction Decoding .......................................................................................... 22-5 22-3 Boundary Scan Bit Definition ........................................................................... 22-10 A-1 SPR (Special Purpose Registers) ......................................................................... A-2 A-2 CMF (CDR MoneT Flash EEPROM) Flash Array ................................................. A-4 A-3 USIU (Unified System Interface Unit).................................................................... A-5 A-4 CMF (CDR MoneT Flash EEPROM)..................................................................... A-8 A-5 DPTRAM (Dual-Port TPU RAM) ...........................................................................A-9 A-6 DPTRAM Array...................................................................................................... A-9 A-7 TPU3 (Time Processor Unit) ............................................................................... A-10 A-8 QADC64 (Queued Analog-to-Digital Converter) ................................................. A-13 A-9 QSMCM (Queued Serial Multi-Channel Module) ................................................ A-15 A-10 MIOS1 (Modular Input/Output Subsystem) ....................................................... A-16 A-11 TouCAN (CAN 2.0B Controller).........................................................................A-22 A-12 UIMB (U-Bus to IMB3 Bus Interface) ................................................................A-25 A-13 SRAM (Static RAM Access Memory) ................................................................A-25 A-14 SRAM (Static RAM Access Memory) Array ...................................................... A-25 D-1 D-2 D-3 D-4 D-5 Bank 0 Functions ..................................................................................................D-2 Bank 1 Functions ..................................................................................................D-3 QOM Bit Encoding ................................................................................................D-6 SIOP Function Valid CHAN_Control Options......................................................D-50 SIOP State Timing ..............................................................................................D-52
E-1 External Components Value For Different Crystals (Q1) ......................................E-4 F-1 Memory Access Times Using Different Buses ...................................................... F-1 F-2 Timing Examples ................................................................................................... F-2 G-1 Absolute Maximum Ratings ................................................................................. G-1 G-2 Thermal Characteristics ....................................................................................... G-3 G-3 ESD Protection .................................................................................................... G-6 G-4 DC Electrical Characteristics ............................................................................... G-7 G-5 Oscillator and PLL.............................................................................................. G-12 G-6 Program and Erase Characteristics ................................................................... G-13 G-7 CMF AC and DC Power Supply Characteristics ................................................ G-14 G-8 Flash Module Life............................................................................................... G-14 G-9 CMF Programming Algorithm (v6 and Later) ..................................................... G-15 G-10 CMF Erase Algorithm (v6) ............................................................................... G-15 G-11 Bus Operation Timing ...................................................................................... G-17 G-12 Interrupt Timing................................................................................................ G-39 G-13 Debug Port timing ............................................................................................ G-40 G-14 RESET Timing ................................................................................................. G-43 G-15 JTAG Timing .................................................................................................... G-47 G-16 QADC64 Conversion Characteristics (Operating) ........................................... G-52
MPC555 / MPC556 USERS MANUAL LIST OF TABLES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xlvi

Table Number
G-17 G-18 G-19 G-20 G-21 G-22 G-23 G-24 G-25 H-1 H-2 H-3 H-4 H-5
Page Number
QSPI Timing..................................................................................................... G-53 GPIO Timing .................................................................................................... G-57 TPU3 Timing .................................................................................................... G-57 TouCAN Timing ............................................................................................... G-58 MCPSM Timing Characteristics ....................................................................... G-59 MPWMSM Timing Characteristics ................................................................... G-60 MMCSM Timing Characteristics ...................................................................... G-62 MDASM Timing Characteristics ....................................................................... G-65 MPIOSM Timing Characteristics...................................................................... G-68
Program and Erase Characteristics ......................................................................H-1 CMF AC and DC Power Supply Characteristics ...................................................H-2 Flash Module Life..................................................................................................H-3 CMF Programming Algorithm (v5) ........................................................................H-3 CMF Erase Algorithm (v5).....................................................................................H-3
LIST OF TABLES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com
MOTOROLA xlvii


LIST OF TABLES Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com
MOTOROLA xlviii
PREFACE
This manual defines the functionality of the MPC555 / MPC556 for use by software and hardware developers. The MPC555 / MPC556 is based on the PowerPC processor used in the Motorola MPC500 family of microcontrollers. For further information refer to the MPC500 Family RCPU Reference Manual, RCPURM/AD (Motorola order number). Boxed sections appear throughout this manual. These boxes designate optional features that are only available on the MPC556.
Audience This manual is intended for system software and hardware developers and applications programmers who want to develop products for the MPC555 / MPC556. It is assumed that the reader understands operating systems, microprocessor and microcontroller system design, and the basic principles of RISC processing. Additional Reading For additional reading that provides background to or supplements the information in this manual see: John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, Inc., San Mateo, CA PowerPC Microprocessor Family: the Programming Environments, MPCFPE/AD (Motorola order number) MPC500 Family RCPU Reference Manual, RCPURM/AD (Motorola order number) Conventions This document uses the following notational conventions: ACTIVE_HIGH Names for signals that are active high are shown in uppercase text without an overbar. Signals that are active high are referred to as asserted when they are high and negated when they are low. A bar over a signal name indicates that the signal is active low. Active-low signals are referred to as asserted (active) when they are low and negated when they are high. Hexadecimal numbers Binary numbers Abbreviations or acronyms for registers are shown in uppercase text. Specific bit fields or ranges are shown in brackets.
PREFACE Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com MOTOROLA xlix
ACTIVE_LOW
0x0F 0b0011 REG[FIELD]
In certain contexts, such as a signal encoding, this indicates a dont care. For example, if a field is binary encoded 0bx001, the state of the first bit is a dont care. NOTE: Throughout this manual references to 3 V refer to the nominal supply voltage of 3.3 volts.
Nomenclature Logic level one is the voltage that corresponds to Boolean true (1) state. Logic level zero is the voltage that corresponds to Boolean false (0) state.
To set a bit or bits means to establish logic level one on the bit or bits. To clear a bit or bits means to establish logic level zero on the bit or bits. A signal that is asserted is in its active logic state. An active low signal changes from logic level one to logic level zero when asserted, and an active high signal changes from logic level zero to logic level one. A signal that is negated is in its inactive logic state. An active low signal changes from logic level zero to logic level one when negated, and an active high signal changes from logic level one to logic level zero. LSB means least significant bit or bits. MSB means most significant bit or bits. References to low and high bytes are spelled out.
PREFACE Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com
MOTOROLA l
SECTION 1 OVERVIEW
The MPC555 / MPC556 is a member of Motorolas MPC500 PowerPCTM RISC Microcontroller family. The MPC555 / MPC556 offers the following features: PowerPC core with floating-point unit 26 Kbytes fast RAM and 6 Kbytes TPU microcode RAM 448 Kbytes flash EEPROM with 5-V programming 5-V I/O system Serial system: queued serial multi-channel module (QSMCM), dual CAN 2.0B controller modules (TouCANTM) 50-channel timer system: dual time processor units (TPU3), modular I/O system (MIOS1) 32 analog inputs: dual queued analog-to-digital converters (QADC64) Submicron HCMOS (CDR1) technology 272-pin plastic ball grid array (PBGA) packaging 40-MHz operation, -40 C to 125 C with dual supply (3.3 V, 5 V) MPC556 supports code compression to increase code density. NOTE Throughout this manual references to 3 V refer to the nominal supply voltage of 3.3 V.) 1.1 Block Diagram Figure 1-1 is a block diagram of the MPC555 / MPC556.
OVERVIEW
MOTOROLA 1-1
For MoreRev. 15 October 2000 Product, Information On This Go to: www.freescale.com
256 Kbytes Flash Burst Interface
192 Kbytes Flash
U-bus E-bus
RCPU 16 Kbytes SRAM
USIU 10 Kbytes SRAM
L2U
L-bus
QADC
QADC
QSMCM
TouCAN
UIMB
IMB3
TPU3
DPTRAM
TPU3
TouCAN
MIOS1
Figure 1-1 MPC555 / MPC556 Block Diagram 1.2 MPC555 / MPC556 Features Features of each module on the MPC555 / MPC556 are listed below. 1.2.1 RISC MCU Central Processing Unit (RCPU) 32-bit PowerPC architecture (compliant with PowerPC Architecture Book 1) Core performance measured at 52.7 Kmips (Dhrystone 2.1) @ 40 MHz. NOTE This assumes the RCPU core is running in normal mode and show cycles is turned off (ISCT_SER of the ICTRL register is set to 111). See Table 21-21. Fully static, low power operation Integrated floating-point unit Precise exception model Extensive system development support On-chip watchpoints and breakpoints Program flow tracking
MPC555
/ MPC556
OVERVIEW
MOTOROLA 1-2
USERS MANUAL

On-chip emulation (OnCETM) development interface 1.2.2 Four-Bank Memory Controller Works with SRAM, EPROM, flash EEPROM, and other peripherals Byte write enables 32-bit address decodes with bit masks Memory transfer start (MTS): This pin is the transfer start signal to access a slaves external memory by an external bus master 1.2.3 U-Bus System Interface Unit (USIU) Clock synthesizer Power management Reset controller PowerPC decrementer and time base Glueless interface to SRAMs and burstable FLASHs Real-time clock register Periodic interrupt timer Hardware bus monitor and software watchdog timer Interrupt controller that supports up to eight external and eight internal interrupts IEEE 1149.1 JTAG test access port External bus interface 24 address pins, 32 data pins Supports multiple master designs Four-beat transfer bursts, two-clock minimum bus transactions Tolerates 5-V inputs, provides 3.3-V outputs 1.2.4 Flexible Memory Protection Unit Four instruction regions and four data regions 4-Kbyte to 16-Mbyte region size support Default attributes available in one global entry Attribute support for speculative accesses 1.2.5 448 Kbytes of CDR MoneT Flash EEPROM Memory (CMF) One 256-Kbyte and one 192-Kbyte module Page read mode Block (32-Kbyte) erasable External 4.75-V to 5.25-V program and erase power supply 1.2.6 26 Kbytes of Static RAM One 16-Kbyte and one 10-Kbyte module Fast (one-clock) access Keep-alive power Soft defect detection (SDD)
MPC555
/ MPC556
OVERVIEW
MOTOROLA 1-3
USERS MANUAL

1.2.7 General-Purpose I/O Support Address (24) and data (32) pins can be used for general-purpose I/O in singlechip mode 9 general-purpose I/O pins in MIOS1 unit Many peripheral pins can be used for general-purpose I/O when not used for primary function 5-V outputs 1.2.8 Two Time Processor Units (TPU3) Each TPU3 module provides these features: A dedicated micro-engine operates independently of the RCPU 16 independent programmable channels and pins Each channel has an event register consisting of a 16-bit capture register, a 16-bit compare register and a 16-bit comparator Nine pre-programmed timer functions are available Any channel can perform any time function Each timer function can be assigned to more than one channel Two timer count registers with programmable prescalers Each channel can be synchronized to one or both counters Selectable channel priority levels 5-V outputs 6-Kbyte dual port TPU RAM (DPTRAM) is shared by the two TPU3 modules for TPU microcode 1.2.9 18-Channel Modular I/O System (MIOS1) Ten double action submodules (DASMs) Eight dedicated PWM sub-modules (PWMSMs) Two 16-bit modulus counter submodules (MCSMs) Two parallel port I/O submodules (PIOSM) 5-V outputs 1.2.10 Two Queued Analog-to-Digital Converter Modules (QADC) Each QADC provides: Up to 16 analog input channels, using internal multiplexing Up to 41 total input channels, using internal and external multiplexing 10-bit A/D converter with internal sample/hold Typical conversion time of 10 sec (100,000 samples per second) Two conversion command queues of variable length Automated queue modes initiated by: External edge trigger/level gate Software command 64 result registers Output data that is right- or left-justified, signed or unsigned
MPC555
/ MPC556
OVERVIEW
MOTOROLA 1-4
USERS MANUAL

1.2.11 Two CAN 2.0B Controller Modules (TouCANs) Each TouCAN provides these features: Full implementation of CAN protocol specification, version 2.0 A and B Each module has 16 receive/transmit message buffers of 0 to 8 bytes data length Global mask register for message buffers 0 to 13 Independent mask registers for message buffers 14 and 15 Programmable transmit-first scheme: lowest ID or lowest buffer number 16-bit free-running timer for message time-stamping Low power sleep mode with programmable wake-up on bus activity Programmable I/O modes Maskable interrupts Independent of the transmission medium (external transceiver is assumed) Open network architecture Multimaster concept High immunity to EMI Short latency time for high-priority messages Low power sleep mode with programmable wakeup on bus activity 1.2.12 Queued Serial Multi-Channel Module (QSMCM) Queued serial peripheral interface (QSPI) Provides full-duplex communication port for peripheral expansion or interprocessor communication Up to 32 preprogrammed transfers, reducing overhead Has 160-byte queue Programmable transfer length: from eight to 16 bits, inclusive Synchronous interface with baud rate of up to system clock / 4 Four programmable peripheral-select pins support up to 16 devices Wrap-around mode allows continuous sampling of a serial peripheral for efficient interfacing to serial A/D converters Two serial communications interfaces (SCI). Each SCI offers these features: UART mode provides NRZ format and half- or full-duplex interface 16 register receive buffer and 16 register transmit buffer (SCI1) Advanced error detection and optional parity generation and detection Word length programmable as eight or nine bits Separate transmitter and receiver enable bits and double buffering of data Wakeup functions allow the CPU to run uninterrupted until either a true idle line is detected or a new address byte is received External source clock for baud generation Multiplexing of transmit data pins with discrete outputs and receive data pins with discrete inputs 1.3 MPC555 / MPC556 Address Map The internal memory map is organized as a single 4-Mbyte block. The user can assign this block to one of eight locations by programming a register in the USIU. The eight possible locations are the first eight 4-Mbyte memory blocks starting with address / MPC556
MPC555
OVERVIEW
MOTOROLA 1-5
USERS MANUAL

0x0000 0000. (Refer to Figure 1-2). The programmability of the internal memory map location allows the user to implement a multiple-chip system.
0x0000 0000 0x003F FFFF 0x0040 0000 0x007F FFFF 0x0080 0000 0x00BF FFFF 0x00C0 0000 0x00FF FFFF 0x0100 0000 Internal 4-Mbyte Memory Block (Resides in one of eight locations)
0x013F FFFF 0x0140 0000 0x017F FFFF 0x0180 0000 0x01BF FFFF 0x01C0 0000 0x01FF FFFF
0xFFFF FFFF
Figure 1-2 MPC555 / MPC556 Memory Map The internal memory space is divided into the following sections: Flash memory (448 Kbytes) Static RAM memory (26 Kbytes) Control registers and IMB2 modules (64 Kbytes): USIU and flash control registers UIMB interface and IMB2 modules SRAM control registers
MPC555
/ MPC556
OVERVIEW
MOTOROLA 1-6
USERS MANUAL
0x00 0000 CMF Flash A 256 Kbytes 0x04 0000 0x06 FFFF
0x07 0000
Reserved 0x2F C000 USIU Control Registers 1 Kbyte FLASH Module A (64 bytes) 0x2F C800 FLASH Module B (64 bytes) Reserved for Flash (2.6 Mbytes - 16 Kbytes) Reserved for SIU 0x2F C840 0x2F C880
CMF Flash B 192 Kbytes
0x 2F BFFF 0x 2F C000 0x 2F FFFF 0x 30 0000
U SI U & F l ash Control 16 Kbytes IMB3 Address Space

UIMB Interface & IMB3 Modules (32 Kbytes) DPTRAM Control (12 bytes) Reserved (8180 bytes) DPTRAM (6 Kbytes) 0x30 2000 0x30 0000
0x 30 7 FFF 0x 30 8000 Reserved for IMB3 (480 Kbytes) 0x 37 FFFF 0x 38 0000 SR A M C on t r ol A ( 8 bytes) 0x 38 0008 SR A M C on t r ol B ( 8 bytes) Reserved (485.98 Kbytes) 0x 3F 9800 0x 3F C000 0x 3F FFFF
Reserved (2 Kbytes) TPU3_A (1 Kbyte) TPU3_B (1 Kbyte) QADC_A (1 Kbyte) QADC_B (1 Kbyte) QSMCM (4 Kbytes) 0x30 6000 MIOS1 (4 Kbytes) TouCAN_A (1 Kbyte) TouCAN_B (1 Kbyte) 0x30 7080 0x30 7480 0x30 7884 0x30 7F80 0x30 7FFF 0x30 4000 0x30 4400 0x30 4800 0x30 4C00 0x30 5000
0x 38 0010
SRAM A (10 Kbytes) SRAM B (16 Kbytes)
Reserved (1920 bytes) UIMB_Registers (128 bytes)
Figure 1-3 MPC555 / MPC556 Internal Memory Map
MPC555
/ MPC556
OVERVIEW
MOTOROLA 1-7
USERS MANUAL
MPC555
/ MPC556
OVERVIEW
MOTOROLA 1-8
USERS MANUAL
SECTION 2 SIGNAL DESCRIPTIONS

2.1 Packaging and Pinout Descriptions Figure 2-1 gives the case configuration and packaging information for the MPC555 / MPC556. Figure 2-2 gives the MPC555 / MPC556 pinout data. Table 2-1 gives an overview of the pins on the MPC555 / MPC556.

SIGNAL DESCRIPTIONS
MOTOROLA 2-1
PIN 1 INDEX
4X
0.2
A
272X
0.2 A
E2
0.35 A
D2 B TOP VIEW (D1)

19X
0.2
A B C
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER PARALLEL TO PRIMARY DATUM A. 4. PRIMARY DATUM A AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS.
MILLIMETERS MIN MAX 2.05 2.65 0.50 0.70 0.50 0.70 1.05 1.25 0.60 0.90 27.00 BSC 24.13 REF 23.30 24.70 27.00 BSC 24.13 REF 23.30 24.70 1.27 BSC
e
Y W V U T R P N M L K J H G F E D C B A
19X
DIM A A1 A2 A3 b D D1 D2 E E1 E2 e
(E1)
4X
A1 A3 A2 A SIDE VIEW
272X
e /2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
b 3
0.3
M M
BOTTOM VIEW
A B C A
0.15
CASE 1135A01 ISSUE B
Figure 2-1 MPC555 / MPC556 Case Dimensions and Packaging
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-2
USERS MANUAL
MPC555
1 2
A_TPUCH1 A_TPUCH4 A_TPUCH8 A_TPUCH12 A_TPUCH15 VRL AAN0_PQB0 AAN48_PQB4 AAN52_PQA0 AAN54_PQA2 BAN0_PQB0 BAN2_PQB2 BAN3_PQB3 BAN51_PQB7 VDDH MDA11 MDA12 MDA13
Ball Map
11 12 13 14 15 16 17 18 19 20
VDDH
10
MPC555
A
VDDH
B
B_T2CLK VDDH A_TPUCH6 A_TPUCH10 A_TPUCH11 A_TPUCH14 VRH AAN3_PQB3 AAN49_PQB5 AAN53_PQA1 AAN57_PQA5 BAN1_PQB1 BAN48_PQB4 BAN52_PQA0 BAN54_PQA2 ETRIG2 MDA14
MDA15
VDDH
MDA28
USERS MANUAL
C B_TPUCH15
A_T2CLK A_TPUCH3 A_TPUCH7 A_TPUCH9 A_TPUCH13 VDDA AAN2_PQB2 AAN51_PQB7 AAN56_PQA4 AAN59_PQA7 BAN49_PQB5 BAN53_PQA1 BAN56_PQA4 BAN57_PQA5 ETRIG1 MDA27 MDA29 MDA30 MDA31
/ MPC556
D B_TPUCH11 B_TPUCH13 A_TPUCH0
A_TPUCH2 A_TPUCH5 VDDI VSSA AAN1_PQB1 AAN50_PQB6 AAN55_PQA3 AAN58_PQA6 BAN50_PQB6 BAN55_PQA3 BAN58_PQA6 BAN59_PQA7 VDDI VDDL MPWM1
MPWM2
MPWM3
E
B_TPUCH7 B_TPUCH10 B_TPUCH14 VDDL
MPWM0
MPWM17
MPWM19
MPIO6
F
B_TPUCH5 B_TPUCH6 B_TPUCH8 B_TPUCH12
MPWM16
MPWM18
MPIO7
MPIO9
G
B_TPUCH2 B_TPUCH3 B_TPUCH4 B_TPUCH9
MPIO5
MPIO8
MPIO11
MPIO12
H
B_TPUCH1 B_TPUCH0 B_CNRX0 B_CNTX0
MPIO10
MPIO15
MPIO14
MPIO13
J TCK_ DSCK
TRST_B VDD SRAM VSS VSS VSS VSS
TDO_ DSDO
VF2 _MPIO2
VFLS0 _MPIO3
VF0 _MPIO0 VF1 _MPIO1
K
TMS TDI_DSDI SGP_FRZ VDDL VSS VSS VSS
VSS
VDDL
VFLS1 _MPIO4
A_CNTX0
A_CNRX0
L
VSS VSS
IWP1 _VFLS IWP0 _VFLS
IRQ3B _SGP
IRQ4B _SGP
VSS
VSS
PCS1 _QGP
PCS0 _QGP
MISO _QGP4 MOSI _QGP5
M IRQ0B _SGP
VSS VSS
IRQ1B _SGP
IRQ2B _SGP
SGP_ IRQOUTB
VSS
VSS
PCS3 _QGP
PCS2 _QGP
ECK
SCK_ QGP6
SIGNAL DESCRIPTIONS
N
WEB_ AT[0] BRB_IWP2 BGB_LWP1 BBB _IWP3
Note: The pinout is a top down view of the package.
RXD1_ QGPI
TXD1_ QGPO
RXD2_ QGPI
TXD2_ QGPO
P
WEB_ AT[1] WEB_ AT[2] WEB_ AT[3] CS0B
VPP
EPEE
VSSF
VDDH
Figure 2-2 MPC555 / MPC556 Pinout Data

R
RD_WRB CS3B CS2B CS1B

T
OEB TEAB TSIZ1 VDDL
VDDL
VDDF
XFC
VDDSYN
VDDI
KAPWR
VSSSYN
EXTAL
U
TSIZ0 TAB TSB BDIPB VDDI
Addr_ SGP31 Addr_ SGP30 Addr_ SGP28 Addr_ SGP29
VDDL
Data_ SGP29 Data_ SGP27 Data_ SGP25 Data_ SGP23
VDDL
Data_ SGP20 RCFB_TXP
EXTCLK
ECK_ BUCK
XTAL
V
BURSTB BIB_STSB
Addr_ SGP11 Addr_ SGP10 Addr_ SGP9 Addr_ SGP8 Addr_ SGP22 Addr_ SGP27 Data_ SGP31 Data_ SGP30 Data_ SGP28 Data_ SGP26 Data_ SGP24 Data_ SGP22 Data_ SGP21 Data_ SGP19 Data_ SGP18
CLKOUT
PORESETB
SRESETB
W Addr_ SGP12
VDDH
Addr_ SGP14 Addr_ SGP16 Addr_ SGP18 Addr_ SGP20 Addr_ SGP23 Addr_ SGP26 Data_ SGP1 Data_ SGP3 Data_ SGP5 Data_ SGP7 Data_ SGP9 Data_ SGP11 Data_ SGP13 Data_ SGP15 Data_ SGP17 IRQ5B _SGP
VDDH
HRESETB
Y
VDDH
Addr_ SGP13 Addr_ SGP15 Addr_ SGP17 Addr_ SGP19 Addr_ SGP21 Addr_ SGP24 Addr_ SGP25 Data_ SGP0 Data_ SGP2 Data_ SGP4 Data_ SGP6 Data_ SGP8 Data_ SGP10 Data_ SGP12 Data_ SGP14 Data_ SGP16 IRQ6B _mck2 IRQ7B _mck3
VDDH
VDDH Substrate 9/30/97a y Dees
=3 volt power (I/O)
VDDi
=3 volt power (internal)
VSS
=ground 21 November 1997
VDDH
=5 volt power
=Misc power Version 10.2
MOTOROLA
2-3

Table 2-1 MPC555 / MPC556 Pin Functions for 272-Pin PBGA
Functional Group 24 Address lines (16-Mbyte address space) 32-bit data bus Signals1 ADDR[8:31]/SGPIOA[8:31] DATA[0:31]/SGPIOD[0:31] IRQ[0]/SGPIOC[0] IRQ[1]/RSV/SGPIOC[1] IRQ[2]/CR/SGPIOC[2]/MTS External interrupts IRQ[3]/KR/RETRY/SGPIOC[3] IRQ[4]/AT[2]/SGPIOC[4] IRQ[5]/SGPIOC[5]/MODCK[1]3 IRQ[6:7]/MODCK[2:3]3 8 3-V / 5-V GPIO Pins 24 32 3 V / 5 V2 3-V / 5-V GPIO
TSIZ[0:1] RD/WR BURST BDIP TS Bus control TA TEA RSTCONF/TEXP3 OE BI/STS General purpose chip select machine (multiplexed with development and debug support) Power-on reset and reset configuration CS[0:3] WE[0:3]/BE[0:3]/AT[0:3] PORESET3 HRESET3 SRESET3 SGPIOC[6]/FRZ/PTR SGPIOC[7]/IRQOUT/LWP[0] Development and debug support BG/VF[0]/LWP[1] BR/VF[1]/IWP[2] BB/VF[2]/IWP[3] TMS TDI/DSDI JTAG and debug port TCK/DSCK TDO/DSDO TRST IWP[0:1]/VFLS[0:1] 7 3V 5 3-V / 5-V GPIO 3 3V 8 3V 11 3V
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-4
USERS MANUAL

Table 2-1 MPC555 / MPC556 Pin Functions for 272-Pin PBGA (Continued)
Functional Group Signals1 XTAL3 EXTAL3 Clocks and PLL CLKOUT EXTCLK3 XFC ENGCLK/BUCLK PCS0/ SS/QGPIO[0] PCS[1:3]/QGPIO[1:3] MISO/QGPIO[4] 1 5V 5 3V Pins 3 V / 5 V2
QSMCM
MOSI/QGPIO[5] SCK/QGPIO[6] TXD[1:2]/QGPO[1:2] RXD[1:2]/QGPI[1:2] ECK MDA[11], [13] MDA[12], [14] MDA[15], [27:31] MPWM[0:3], [16:19] VF[0:2]/MPIO32B[0:2]
12
5V
MIOS
18
5V
General-Purpose I/O from MIOS
VFLS[0:1]/MPIO32B[3:4] MPIO32B[5:15] A_TPUCH[0:15], B_TPUCH[0:15] A_T2CLK, B_T2CLK ETRIG[1:2] A_AN0/ANW/PQB0, B_AN0/ANW/PQB0 A_AN1/ANX/PQB1, B_AN1/ANX/PQB1 A_AN2/ANY/PQB2, B_AN2/ANY/PQB2 A_AN3/ANZ/PQB3, B_AN3/ANZ/PQB3 A_AN[48:51]/PQB[4:7], B_AN[48:51]/PQB[4:7] A_AN[52:54]/MA[0:2]/PQA[0:2], B_AN[52:54]/MA[0:2]/PQA[0:2] A_AN[55:56]/PQA[3:4], B_AN[55:56]/PQA[3:4] A_AN[57:59]/PQA[5:7], B_AN[57:59]/PQA[5:7]
5 11 34
3-V / 5-V GPIO 5V 5V
TPU
QADC
34
5V
TouCAN Flash EEPROM Ground Analog Ground Low Voltage Supply
A_CNTX0, B_CNTX0, A_CNRX0, B_CNRX0 EPEE Supplies VSS, VSSF, VSSSYN VSSA, VRL VDDI, VDDL, VDDSRAM, VDDSYN, KAPWR3, VDDF
4 1 18 2 16
5V 3V
3V
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-5
USERS MANUAL

Table 2-1 MPC555 / MPC556 Pin Functions for 272-Pin PBGA (Continued)
Functional Group High voltage Supply Programming Voltage Signals1 VDDH, VDDA, VRH VPP Pins 12 1 3 V / 5 V2 5V 3-V / 5-V
NOTES: 1. / implies that the corresponding functions are multiplexed on the pin 2. All inputs are 5 V friendly. All 5 V outputs are slow slew rate except for SCI transmit pins. 3. These pins are powered by KAPWR (Keep Alive Power Supply).
2.2 Pin Functionality The pad ring supports 234 functional pins (284 including all power and ground). Some pins serve multiple functions. The pad characteristics for each pin are described in Table 2-2. This table contains the following columns:
Pin List of functional (signal) names for each pin. (For actual pin names, see 2.7 Pin Names and Abbreviations. Function Name of function (signal). Each pin supports one or more functions, and each function (signal) name is a separate entry in the table. Driver Type Type of driver that is used to drive the pin (for output functionality). Types of output drivers are: Totem pole (TP). This driver type uses a push pull scheme to drive the pin. These pins can be driven high or low or can be three-stated. Care must be taken to ensure that there is no contention on this pin (for example, an external driver driving the pin high while an internal driver is driving it low). Open drain (OD). This driver type uses an open drain approach to drive the pins. Pins with an OD driver can be either driven low or three-stated. This driver scheme is typically used for pins that could potentially be asserted by multiple modules. Active negated (ANG). This driver type fully drives a low level. A high level is driven and then released. A pull-up resistor may be needed on this type of output. Receiver Type Type of receiver used for the pin. Some inputs need to have a synchronizer to prevent latching a metastable signal at the pins. Such requirements are indicated in this column with the abbreviation synch. Another possible entry is glitch filter. It is added to reset signals. Direction Direction of the pin for each function it supports. The possible directions are input (I), output (O) and bi-directional (I/O). Voltage Voltage requirement for each function of a pin. There are two supply voltages: 5 V and 3 V. Slew rate Timing needed from the 5-V drivers. The options are with slew rate (typically 200/50 ns with 50 pF load) or fast 5-V driver. Drive strength Drive strength for 3-V drivers of the output load. For all 3-V outputs, the drive strength is 25/50 pF. For two pads (clkout and engclk) the drive strength is 45/90 pF. Pad Type Functional pad structure used for a pin. For pad type descriptions, see 2.5 Pad Types.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-6
USERS MANUAL

Table 2-2 Pin Functionality Table
Type Pin Function Driver Receiver USIU ADDR[8:31]/ SGPIOA[8:31] DATA[0:31] SGPIOD[0:31] ADDR[8:31] SGPIOA[8:31] DATA[0:31] SGPIOD[0:31] IRQ[0] SGPIOC[0] IRQ[1] IRQ[1]/RSV/ SGPIOC[1] RSV SGPIOC[1] IRQ[2] IRQ[2]/CR/ SGPIOC[2]/ MTS CR SGPIOC[2] MTS IRQ[3] IRQ[3]/KR, RETRY/ SGPIOC[3] KR, RETRY SGPIOC[3] IRQ[4] IRQ[4]/AT[2]/ SGPIOC[4] AT[2] SGPIOC[4] IRQ[5] SGPIOC[5] MODCK[1] IRQ[6:7]/ MODCK[2:3]2 TSIZ[0:1] RD/WR BURST IRQ[6:7] MODCK[2:3] TSIZ[0:1] RD/WR BURST TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP TP Hysteresis, Synch Hysteresis, Synch Hysteresis, Synch Hysteresis, Synch Hysteresis, Synch Hysteresis, Synch Hysteresis, Synch Hysteresis, Synch Hysteresis, Synch Hysteresis, Synch Hysteresis, Synch Hysteresis, Synch Hysteresis, Synch Hysteresis, Synch Hysteresis, Synch I/O I/O I/O I/O I I/O I O I/O I I I/O O I I/O I/O I O I/O I I/O I I I I/O I/O I/O 3V 5V 3V 5V 3V 5V 3V 3V 5V 3V 3V 5V 3V 3V 3V 5V 3V 3V 5V 3V 5V 3V 3V 3V 3V 3V 3V 200 / fast 200 / fast 200 / fast 200 / fast 200 / fast 25 / 50 200 / fast 200 / fast 200 / fast 25 / 50 25 / 50 IH 25 / 50 25 / 50 IH IH IH JD J Direction1 Voltage Slew Rate ns / 50 pF Drive Strength (pF) Pad Type
IRQ[0]/ SGPIOC[0]
25 / 50 25 / 50 25 / 50 25 / 50 F F F CH IH IH
IRQ[5]/ SGPIOC[5]/ MODCK[1]2
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-7
USERS MANUAL

Table 2-2 Pin Functionality Table (Continued)
Type Pin BDIP TS3 TA3 TEA RSTCONF/ TEXP2 OE BI/STS Function BDIP TS TA TEA RSTCONF TEXP OE BI3 STS CS[0:3] CS[0:3] WE[0:3]/BE[0:3] WE[0:3]/ BE[0:3]/AT[0:3] AT[0:3] PORESET2 HRESET2 SRESET,2 PORESET HRESET SRESET SGPIOC[6] SGPIOC[6]/ FRZ/PTR FRZ PTR SGPIOC[7]/ IRQOUT/ LWP[0] SGPIOC[7] IRQOUT LWP[0] BG BG/VF[0]/ LWP[1] VF[0] LWP[1] BR BR/VF[1]/ IWP[2] VF[1] IWP[2] BB3 BB/VF[2]/ IWP[3] IWP[0:1]/ VFLS[0:1] TMS TDI/DSDI VF[2] IWP[3] IWP[0:1] VFLS[0:1] TMS TDI DSDI Driver TP ANG ANG OD TP TP ANG TP TP TP TP OD OD TP TP TP TP TP TP TP TP TP TP TP TP ANG TP TP TP TP Receiver Hysteresis Glitch filter Hysteresis Glitch filter Hysteresis Glitch filter Hysteresis, Synch Hysteresis, Synch Direction1 I/O I/O I/O I/O I O O I/O O O O O I I/O I/O I/O O O I/O O O I/O O O I/O O O I/O O O O O I I I Voltage 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 5V 3V 3V 5V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V Slew Rate ns / 50 pF 200 / fast 200 / fast Drive Strength (pF) 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 25 / 50 A C C G G G I I A F CNH EOH EOH Pad Type F E E E E A E
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-8
USERS MANUAL

Type Pin Function TCK DSCK TDO DSDO TRST XTAL EXTAL XFC CLKOUT EXTCLK ENGCLK BUCLK Driver TP TP TP TP TP TP Receiver QSMCM PCS0 PCS0/ SS/QGPIO[0] SS QGPIO[0] PCS[1:3]/ QGPIO[1:3] PCS[1:3] QGPIO[1:3] MISO MISO/QGPIO[4] QGPIO[4] MOSI MOSI/QGPIO[5] QGPIO[5] SCK SCK/QGPIO[6] QGPIO[6] TXD[1:2]/ QGPO[1:2] RXD[1:2]/ QGPI[1:2] ECK TXD[1:2] QGPO[1:2] RXD[1:2] QGPI[1:2] ECK TP/OD TP/OD TP/OD TP/OD TP/OD TP/OD TP/OD TP/OD TP/OD TP/OD TP/OD TP/OD TP/OD Synch/ No Synch Synch/ No Synch Synch/ No Synch Synch Synch Synch/ No Synch Synch/ No Synch Synch/ No Synch Synch/ No Synch Synch/ No Synch Synch/ No Synch MIOS MDA[11:15] MDA[27:31] MDA[11:15] MDA[27:31] TP TP Hysteresis, Synch Hysteresis, Synch I/O I/O 5V 5V 200 / fast 200 / fast P P I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I I I 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 50 / fast 50 / fast 50 / fast 50 / fast 50 / fast 50 / fast 50 / fast 50 / fast 50 / fast 50 / fast 50 / fast 200 / fast 200 / fast O O O Q R R O O Direction1 I I O O I O I I/O O I O O Voltage 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 5V 5V Slew Rate ns / 50 pF Drive Strength (pF) 25 / 50 25 / 50 30 / 904 25 / 505 Pad Type D A C B S
TCK/DSCK TDO/DSDO TRST XTAL2 EXTAL2 XFC
CLKOUT EXTCLK2 ENGCLK/ BUCLK
25 / 50
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-9
USERS MANUAL

Type Pin MPWM[0:3], [16:19] VF[0:2]/ MPIO32B[0:2] VFLS[0:1]/ MPIO32B[3:4] MPIO32B[5:15] Function MPWM[0:3], [16:19] VF[0:2] MPIO32B[0:2] VFLS[0:1] MPIO32B[3:4] MPIO32B[5:15] Driver TP TP TP TP TP TP Receiver Hysteresis, Synch Hysteresis, Synch Hysteresis, Synch Hysteresis, Synch TPU_A/TPU_B A_TPUCH[0:15] A_T2CLK B_TPUCH[0:15] B_T2CLK TPUCH[0:15] T2CLK TPUCH[0:15] T2CLK TP TP TP TP Hysteresis, Synch Hysteresis Synch Hysteresis, Synch Hysteresis, Synch Synch Analog Analog Hysteresis, Synch Analog Analog Hysteresis, Synch Analog Analog Hysteresis, Synch Analog Analog Hysteresis, Synch Analog Hysteresis, Synch Analog Hysteresis, Synch I/O I/O I/O I/O 5V 5V 5V 5V 200 / fast 200 / fast 200 / fast 200 / fast P P P P Direction1 I/O O I/O O I/O I/O Voltage 5V 3V 5V 3V 5V 5V Slew Rate ns / 50 pF 200 / fast 200 / fast 200 / fast 200 / fast Drive Strength (pF) 25 / 50 25 / 50 H H Pad Type P
QADC_A/QADC_B ETRIG[1:2] AN0/ ANW/ PQB0 ETRIG[1:2] AN0 ANW PQB0 AN1 AN1/ANX/PQB1 ANX PQB1 AN2 AN2/ANY/PQB2 ANY PQB2 AN3 AN3/ANZ/PQB3 ANZ PQB3 AN[48:51]/ PQB[4:7] AN[48:51] PQB[4:7] AN[52:54] AN[52:54]/ MA[0:2]/ PQA[0:2] MA[0:2] PQA[0:2] OD OD I I I I I I I I I I I I I I I I O I/O 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V L M M M M M N
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-10
USERS MANUAL

Type Pin Function AN[55:56] PQA[3:4] AN[57:59] PQA[5:7] AN0 AN0/ANW/ PQB0 ANW PQB0 Driver OD OD OD OD OD OD Receiver Analog Hysteresis, Synch Analog Hysteresis, Synch Analog Analog Hysteresis, Synch Analog Analog Hysteresis, Synch Analog Analog Hysteresis, Synch Analog Analog Hysteresis, Synch Analog Hysteresis, Synch Analog Hysteresis, Synch Analog Hysteresis, Synch Analog Hysteresis, Synch Synch / No Synch Synch / No Synch Direction1 I I/O I I/O I I I I I I I I I I I I I I I O I/O I I/O I I/O Voltage 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V Slew Rate ns / 50 pF Drive Strength (pF) L L L M M M M M L L Pad Type
AN[55:56]/ PQA[3:4] AN[57:59]/ PQA[5:7]
AN1 AN1/ANX/PQB1 ANX PQB1 AN2 AN2/ANY/PQB2 ANY PQB2 AN3 AN3/ANZ/PQB3 ANZ PQB3 AN[48:51]/ PQB[4:7] AN[48:51] PQB[4:7] AN[52:54] AN[52:54]/ MA[0:2]/ PQA[0:2] MA[0:2] PQA[0:2] AN[55:56] PQA[3:4] AN[57:59] PQA[5:7]
AN[55:56]/ PQA[3:4] AN[57:59]/ PQA[5:7]
TOUCAN_A/TOUCAN_B A_CNTX0 B_CNTX0 A_CNRX0 B_CNRX0 CNTX0_A CNTX0_B CNRX0_A CNRX0_B TP/OD TP/OD O O I I 5V 5V 5V 5V 50 / fast 50 / fast Q Q R R
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-11
USERS MANUAL

Type Pin Function Driver Receiver CMF EPEE VPP VDDA VDDF VDDL VDDH VDDI EPEE VPP VDDA VDDF VDDL VDDH VDDI VDDSYN VRH VRL VSSA VSSF VSSSYN KAPWR VDDSRAM VSS Sequencer I I I I I I I I I I I I I I I I 3V 5V 5V 3V 3V 5V 3V 3V 5V 3V 3V K Direction1 Voltage Slew Rate ns / 50 pF Drive Strength (pF) Pad Type
Global Power Supplies
VDDSYN VRH VRL VSSA VSSF VSSSYN KAPWR2 VDDSRAM VSS
NOTES: 1. All inputs are 5-V friendly. All 5-V outputs are slow slew rate. The QSMCM and TouCAN pins have some slew rate control, but are faster than the general/purpose I/O and timer pins. 2. These pins are powered by KAPWR (Keep Alive Power Supply). 3. This pin is an active negate signal and may need an external pull-up resister. 4. Drive strength was 45/90 in make sets prior to K62N. 5. Drive strength was 45/90 in make sets prior to K62N.
2.3 Signal Descriptions The pad ring supports 234 functional pins (284 including all power and ground). Each pin and the functionality it supports are described in this section. All references to timing in this document are numbers that are expected for a typical case process with a 50-pF load at 25oC. The supply voltages are assumed to be typical, as well: 5 V or 3.3 V. The 5-V supply is generally referred to as the 5-V supply, and the 3.3-V supply is referred to as the 3-V supply in this section. 2.3.1 USIU Pads 2.3.1.1 ADDR[8:31]/SGPIOA[8:31] Pin Name: addr_sgpioa[8:31] (24 pins) Address Bus Specifies the physical address of the bus transaction. The address is driven onto the bus and kept valid until a transfer acknowledge is received from the slave. ADDR8 is the most significant signal for this bus.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-12
USERS MANUAL

SGPIO This function allows the pins to be used as general purpose inputs/outputs. 2.3.1.2 DATA[0:31]/SGPIOD[0:31] Pin Name: data_sgpiod[0:31] (32 pins) Data Bus Provides the general purpose data path between the chip and all other devices. Although the data path is a maximum of 32 bits wide, it can be sized to support 8-, 16-, or 32-bit transfers. DATA[0] is the MSB of the data bus. SGPIO This function allows the pins to be used as general purpose inputs/outputs. 2.3.1.3 IRQ[0]/SGPIOC[0] Pin Name: irq0_b_sgpioc0
Interrupt Request One of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the RCPU. IRQ0 is a nonmaskable interrupt (NMI). SGPIO This function allows the pins to be used as general purpose inputs/outputs. 2.3.1.4 IRQ[1]/RSV/SGPIOC[1] Pin Name: irq1_b_rsv_b_sgpioc1 Interrupt Request One of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the RCPU. Reservation This line used together with the address bus to indicate that the internal core initiated a transfer as a result of a STWCX or a LWARX instruction. SGPIO This function allows the pins to be used as general purpose inputs/outputs. 2.3.1.5 IRQ[2]/CR/SGPIOC[2]/MTS Pin Name: irq2_b_cr_b_sgpioc2_mts Interrupt Request One of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the RCPU. Cancel Reservation Instructs the chip to clear its reservation, some other master has touched its reserved space. An external bus snooper would assert this signal. SGPIO This function allows the pins to be used as general purpose inputs/outputs. Memory Transfer Start This pin is the transfer start signal from the MPC555 / MPC556 memory controller to allow external memory access by an external bus master. 2.3.1.6 IRQ[3]/KR/RETRY/SGPIOC[3] Pin Name: irq3_b_kr_b_retry_b_sgpioc3
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-13
USERS MANUAL

Interrupt Request One of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the RCPU. Kill Reservation In case of a bus cycle initiated by a STWCX instruction issued by the CPU core to a non-local bus on which the storage reservation has been lost, this signal is used by the non-local bus interface to back-off the cycle. Retry Indicates to a master that the cycle is terminated but should be repeated. As an input, it is driven by the external slave to retry a cycle. SGPIO This function allows the pins to be used as general purpose inputs/outputs. 2.3.1.7 IRQ[4]/AT[2]/SGPIOC[4] Pin Name: irq4_b_at2_sgpioc4
Interrupt Request One of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the RCPU. Address Type A bit from the address type bus which indicates one of the 16 address types to which the address applies. The address type signals are valid at the rising edge of the clock in which the special transfer start (STS) is asserted. AT[2] identifies an access as either data or instrucion. SGPIO This function allows the pins to be used as general purpose inputs/outputs. 2.3.1.8 IRQ[5]/SGPIOC[5]/MODCK[1] Pin Name: irq5_b_sgpioc5_modck1 Interrupt Request One of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the RCPU. SGPIO This function allows the pins to be used as general purpose inputs/outputs. Mode Clock [1] Sampled at the negation of PORESET in order to configure the phase-locked loop (PLL)/clock mode of operation. 2.3.1.9 IRQ[6:7]/MODCK[2:3] Pin Name: irq6_b_modck2 - irq7_b_modck3 (2 pins) Interrupt Request One of the eight external lines that can request, by means of the internal interrupt controller, a service routine from the RCPU. Mode Clock [2:3] Sampled at the negation of PORESET in order to configure the PLL/clock mode of operation. 2.3.1.10 TSIZ[0:1] Pin Name: tsiz0 - tsiz1 (2 pins)
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-14
USERS MANUAL

Transfer size Indicates the size of the requested data transfer in the current bus cycle. 2.3.1.11 RD/WR Pin Name: rd_wr_b Read/Write Indicates the direction of the data transfer for a transaction. A logic one indicates a read from a slave device; a logic zero indicates a write to a slave device. 2.3.1.12 BURST Pin Name: burst_b
Burst Indicator Indicates whether the current transaction is a burst transaction or not. 2.3.1.13 BDIP Pin Name: bdip_b Burst data in progress Indicates to the slave that there is a data beat following the current data beat. 2.3.1.14 TS Pin Name: ts_b Transfer Start Indicates the start of a bus cycle that transfers data to/from a slave device. This signal is driven by the master only when it gained the ownership of the bus. Every master should negate this signal before the bus relinquish. Every master should negate this signal before the bus is relinquished. This pin is an active negate signal and may need an external pull-up resistor to ensure proper operation and signal timing specifications. 2.3.1.15 TA Pin Name: ta_b Transfer Acknowledge This line indicates that the slave device addressed in the current transaction has accepted the data transferred by the master (write) or has driven the data bus with valid data (read). The slave device negates the TA_B signal after the end of the transaction and immediately three-state it to avoid contentions on the line if a new transfer is initiated addressing other slave devices. This pin is an active negate signal and may need an external pull-up resistor to ensure proper operation and signal timing specifications. 2.3.1.16 TEA Pin Name: tea_b
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-15
USERS MANUAL

Transfer Error Acknowledge This signal indicates that a bus error occurred in the current transaction. The MCU asserts this signal when the bus monitor does not detect a bus cycle termination within a reasonable amount of time. The assertion of TEA causes the termination of the current bus cycle, regardless of the state of TEA. An external pull-up device is required to negate TEA quickly, before a second error is detected. That is, the pin must be pulled up within one clock cycle of the time it was threestated by the MPC555 / MPC556. 2.3.1.17 RSTCONF/TEXP Pin Name: rstconf_b_texp Reset Configuration Input. This input line is sampled by the chip during the assertion of the HRESET signal in order to sample the reset configuration. If the line is asserted, the configuration mode will be sampled from the external data bus. When this line is negated, the configuration mode adopted by the chip will be the default one. Timer Expired This output line reflects the status of the TEXPS bit in the PLPRCR register in the USIU. This indicates an expired timer value. 2.3.1.18 OE Pin Name: oe_b Output Enable This output line is asserted when a read access to an external slave controlled by the GPCM in the memory controller is initiated by the chip. 2.3.1.19 BI/STS Pin Name: bi_b_sts_b Burst Inhibit This bi-directional, active low, three-state line indicates that the slave device addressed in the current burst transaction is not able to support burst transfers. When the chip drives out the signal for a specific transaction, it asserts or negates BI during the transaction according to the value specified by the user in the appropriate control registers. Negation of the signal occurs after the end of the transaction followed by the immediate three-state. This pin is an active negate signal and may need an external pull-up resistor to ensure proper operation and signal timing specifications. Special Transfer Start This output signal is driven by the chip to indicate the start of a transaction on the external bus or signals the beginning of an internal transaction in showcycle mode. 2.3.1.20 CS[0:3] Pin Name: cs0_b - cs3_b (4 pins) Chip Select These output signals enable peripheral or memory devices at programmed addresses if defined appropriately in the memory controller. CS0 can be configured to be the global chip select for the boot device.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-16
USERS MANUAL

2.3.1.21 WE[0:3]/BE[0:3]/AT[0:3] Pin Name: we_b_at[0:3](4 pins) Write Enable[0:3]/Byte Enable[0:3] This output line is asserted when a write access to an external slave controlled by the GPCM in the memory controller is initiated by the chip. It can be optionally be asserted on all read and write accesses. See WEBS bit definition in Table 10-7. WE[0]/BE[0] is asserted if the data lane DATA[0:7] contains valid data to be stored by the slave device. WE[1]/BE[1] is asserted if the data lane DATA[8:15] contains valid data to be stored by the slave device. WE[2]/BE[2] is asserted if the data line DATA[16:23] contains valid data to be stored by the slave device. WE[3]/BE[3] is asserted if the data lane DATA[24:31] contains valid data to be stored by the slave device.
Address Type Indicates one of the 16 address types to which the address applies. The address type signals are valid at the rising edge of the clock in which the Special Transfer Start (STS) is asserted. 2.3.1.22 PORESET Pin Name: poreset_b Power on Reset This pin should be activated as a result of a voltage failure on the keep-alive power pins. The pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected. The internal PORESET signal is asserted only if PORESET is asserted for more than 100 ns. See SECTION 7 RESET for more details on timing. 2.3.1.23 HRESET Pin Name: hreset_b Hard Reset The chip can detect an external assertion of HRESET only if it occurs while the chip is not asserting reset. After negation of HRESET or SRESET is detected, a 16 cycles period is taken before testing the presence of an external reset. The internal HRESET signal is asserted only if HRESET is asserted for more than 100 ns. To meet external timing requirements, an external pull-up device is required to negate HRESET. See SECTION 7 RESET for more details on timing. 2.3.1.24 SRESET Pin Name: sreset_b Soft Reset The chip can detect an external assertion of SRESET only if it occurs while the chip is not asserting reset. After negation of HRESET or SRESET is detected, a 16-cycle period is taken before testing the presence of an external soft reset. To meet external timing requirements, an external pull-up device is required to negate SRESET. See SECTION 7 RESET for more details on timing. 2.3.1.25 SGPIOC[6]/FRZ/PTR Pin Name: sgpioc6_frz_ptr_b
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-17
USERS MANUAL

SGPIO This function allows the pins to be used as general purpose inputs/outputs. Freeze Indicates that the RCPU is in debug mode. Program Trace Indicates an instruction fetch is taking place in order to allow program flow tracking. 2.3.1.26 SGPIOC[7]/IRQOUT/LWP[0] Pin Name: sgpioc7_irqout_b_lwp0 SGPIO This function allows the pins to be used as general purpose inputs/outputs. Interrupt Out Indicates that an interrupt has been requested to all external devices.
Load/Store Watchpoint 0 This output line reports the detection of a data watchpoint in the program flow executed by the RCPU. See SECTION 21 DEVELOPMENT SUPPORT for more details. 2.3.1.27 BG/VF[0]/LWP[1] Pin Name: bg_b_vf0_lwp1 Bus Grant Indicates external data bus status. Is asserted low when the arbiter of the external bus grants to the specific master the ownership of the bus. Visible Instruction Queue Flush Status This output line together with VF1 and VF2 is output by the chip when a program instructions flow tracking is required by the user. VF report the number of instructions flushed from the instruction queue in the internal core. See SECTION 21 DEVELOPMENT SUPPORT for more details. Load/Store Watchpoint This output line reports the detection of a data watchpoint in the program flow executed by the RCPU. 2.3.1.28 BR/VF[1]/IWP[2] Pin Name: br_b_vf1_iwp2 Bus Request Indicates that the data bus has been requested for external cycle. Visible Instruction Queue Flush Status This output line together with VF1 and VF2 is output by the chip when a program instructions flow tracking is required by the user. VF report the number of instructions flushed from the instruction queue in the internal core. See SECTION 21 DEVELOPMENT SUPPORT for more details. Instruction Watchpoint 2 This output line reports the detection of an instruction watchpoint in the program flow executed by the RCPU. 2.3.1.29 BB/VF[2]/IWP[3] Pin Name: bb_b_vf2_iwp3
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-18
USERS MANUAL

Bus Busy Indicates that the master is using the bus. This pin is an active negate signal and may need an external pull-up resistor to ensure proper operation and signal timing specifications. Visible Instruction Queue Flush Status This output line together with VF0 and VF1 is output by the chip when a program instructions flow tracking is required by the user. VF report the number of instructions flushed from the instruction queue in the internal core. Instruction Watchpoint 3 This output line reports the detection of an instruction watchpoint in the program flow executed by the internal core. 2.3.1.30 IWP[0:1]/VFLS[0:1] Pin Name: iwp0_vfls0 - iwp1_vfls1 (2 pins) Instruction Watchpoint These output lines report the detection of an instruction watchpoint in the program flow executed by the RCPU. Visible History Buffer Flush Status These signals are output by the chip to enable program instruction flow tracking. They report the number of instructions flushed from the history buffer in the RCPU. See SECTION 21 DEVELOPMENT SUPPORT for details. 2.3.1.31 TMS Pin Name: tms Test Mode Select This input controls test mode operations for on-board test logic (JTAG). 2.3.1.32 TDI/DSDI Pin Name: tdi_dsdi Test Data In This input is used for serial test instructions and test data for on-board test logic (JTAG). Development Serial Data Input This input line is the data in for the debug port interface. See SECTION 21 DEVELOPMENT SUPPORT for details. 2.3.1.33 TCK/DSCK Pin Name: tck_dsck Test Clock This input provides a clock for on-board test logic (JTAG). Development Serial Clock This input line is the clock for the debug port interface. See SECTION 21 DEVELOPMENT SUPPORT for details. 2.3.1.34 TDO/DSDO Pin Name: tdo_dsdo
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-19
USERS MANUAL

Test Data Out This output is used for serial test instructions and test data for onboard test logic (JTAG). Development Serial Data Output This output line is the data-out line of the debug port interface. See SECTION 21 DEVELOPMENT SUPPORT for details. 2.3.1.35 TRST Pin Name: trst_b Test Reset This input provides asynchronous reset to the test logic (JTAG). For non-JTAG test applications, TRST should be connected to ground or PORESET via an external resistor.
2.3.1.36 XTAL Pin Name: xtal XTAL This output line is one of the connections to an external crystal for the internal oscillator circuitry. 2.3.1.37 EXTAL Pin Name: extal EXTAL This line is one of the connections to an external crystal for the internal oscillator circuitry. If this pin is unused, it must be grounded. 2.3.1.38 XFC Pin Name: xfc External Filter Capacitance This input line is the connection pin for an external capacitor filter for the PLL circuitry. 2.3.1.39 CLKOUT Pin Name: clkout Clock Out This output line is the clock system frequency. The CLKOUT drive strength can be configured to full strength, half strength, or disabled. The drive strength is configured using the COM[0:1] bits in the SCCR register in the USIU. 2.3.1.40 EXTCLK Pin Name: extclk EXTCLK Input. This is the external frequency source for the chip. If this is unused, the pin must be grounded. 2.3.1.41 VDDSYN Pin Name: vddsyn
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-20
USERS MANUAL

VDDSYN This is the power supply of the PLL circuitry. 2.3.1.42 VSSSYN Pin Name: vsssyn VSSSYN This is the power supply of the PLL circuitry. 2.3.1.43 ENGCLK/BUCLK Pin Name: engclk_buclk ENGCLK This is the engineering clock output. Drive strength can be configured to full strength, half strength or disabled. The drive strength is configured using the EECLK[0:1] bits in the SCCR register in the SIU.
BUCLK When the chip is in limp mode, it is operating from a less precise on-chip ring oscillator to allow the system to continue minimum functionality until the system clock is fixed. This backup clock can be seen externally based on the values of the EECLK[0:1] bits in the SCCR register in the USIU. 2.3.2 QSMCM PADS 2.3.2.1 PCS[0]/SS/QGPIO[0] Pin Name: pcs0_ss_b_qgpio0 PCS[0] This signal provides QSPI peripheral chip select 0. SS Assertion of this bi-directional signal places the QSPI in slave mode. QSPI GPIO[0] When this pin is not needed for a QSPI application it can be configured as a general purpose input/output. 2.3.2.2 PCS[1:3]/QGPIO[1:3] Pin Name: pcs1_qgpio1 - pcs3_qgpio3 (3 pins) PCS[1:3] These signals provide three QSPI peripheral chip selects. QGPIO[1:3] When these pins are not needed for QSPI applications they can be configured as a general purpose input/output. 2.3.2.3 MISO/QGPIO[4] Pin Name: miso_qgpio4 Master-In Slave-Out (MISO) This bi-directional signal furnishes serial data input to the QSPI in master mode, and serial data output from the QSPI in slave mode. QGPIO[4] When this pin is not needed for a QSPI application it can be configured as a general purpose input/output.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-21
USERS MANUAL

2.3.2.4 MOSI/QGPIO[5] Pin Name: mosi_qgpio5 Master-Out Slave-In (MOSI) This bi-directional signal furnishes serial data output from the QSPI in master mode and serial data input to the QSPI in slave mode. QGPIO[5] When this pin is not needed for a QSPI application it can be configured as a general purpose input/output. 2.3.2.5 SCK/QGPIO[6] Pin Name: sck_qgpio6 SCK This bi-directional signal furnishes the clock from the QSPI in master mode or furnishes the clock to the QSPI in slave mode. QGPIO[6] When this pin is not needed for a QSPI application, it can be configured as a general purpose input/output. When the QSPI is enabled for serial transmitting, the pin can not function as a GPIO. 2.3.2.6 TxD[1:2]/QGPO[1:2] Pin Name: txd1_qgpo1 - txd2_qgpo2 (2 pins) Transmit Data These output signals are the serial data outputs from the SCI1 and SCI2. QSCI GPO[1:2] When these pins are not needed for a SCI applications, they can be configured as general-purpose outputs. When the transmit enable bit in the SCI control register is set to a logic 1, these pins can not function as general purpose outputs 2.3.2.7 RxD[1:2]/QGPI[1:2] Pin Name: rxd1_qgpi1 - rxd2_qgpi2 (2 pins) Receive Data These input signals furnish serial data inputs to the SCI1 and SCI2. QSCI GPI[1:2] When these pins are not needed for SCI applications they can be configured as general purpose inputs. When the receive enable bit in the SCI control register is set to a logic 1, these pins can not function as general purpose inputs. 2.3.2.8 ECK Pin Name: eck External Baud Clock This signal provides an external baud clock used by SCI1 and SCI2.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-22
USERS MANUAL

2.3.3 MIOS PADS 2.3.3.1 MDA[11], [13] Pin Name: mda11, mda13 (2 pins) Double Action Each of these pins provide a path for two 16-bit input captures and two 16-bit output compares. Clock Input Each of these pins provide a clock input to the modulus counter submodule. MDA11 can be used as the clock input to the MMCSM6 modulus counter. MDA13 can be used as the clock input to the MMCSM22 modulus counter. 2.3.3.2 MDA[12], [14] Pin Name: mda12, mda14, (2 pins) Double Action Each of these pins provide a path for two 16-bit input captures and two 16-bit output compares. Load Input Each of these pins provide a load input to the modulus counter submodule. MDA12 can be used as the load input to the MMCSM6 modulus counter. MDA14 can be used as the load input to the MMCSM22 modulus counter. 2.3.3.3 MDA[15], [27:31] Pin Name: mda15, mda27 - mda31 (6 pins) Double Action Each of these pins provide a path for two 16-bit input captures and two 16-bit output compares. 2.3.3.4 MPWM[0:3], [16:19] Pin Name: mpwm0 - mpwm3, mpwm16 - mpwm19 (8 pins) Pulse Width Modulation These pins provide variable pulse width output signals at a wide range of frequencies. 2.3.3.5 VF[0:2]/MPIO32B[0:2] Pin Name: vf0_mpio32b0 - vf2_mpio32b2 (3 pins) Visible Instruction Queue Flush Status These lines output by the chip when Program instruction flow tracking is required by the user. VF reports the number of instructions flushed from the instruction queue in the internal core. MIOS GPIO This function allows the pins to be used as general-purpose inputs/outputs. 2.3.3.6 VFLS[0:1]/MPIO32B[3:4] Pin Name: vfls0_mpio32b3 - vfls1_mpio32b4 (2 pins)
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-23
USERS MANUAL

Visible History Buffer Flush Status These signals are output by the chip to allow program instruction flow tracking. They report the number of instructions flushed from the history buffer in the RCPU. See SECTION 21 DEVELOPMENT SUPPORT for details. MIOS GPIO This function allows the pins to be used as general purpose inputs/outputs. 2.3.3.7 MPIO32B[5:15] Pin Name: mpio32b5 - mpio32b15 (11 pins) MIOS GPIO This function allows the pins to be used as general purpose inputs/outputs.
2.3.4 TPU_A/TPU_B PADS 2.3.4.1 TPUCH[0:15]_[A:B] Pin Name: a_tpuch0 - a_tpuch15 (16 pins for first TPU), b_tpuch0 - b_tpuch15 (16 pins for second TPU) TPU Channels These signals provide each TPU with 16 input/output programmable timed events. 2.3.4.2 T2CLK Pin Name: a_t2clk (1 pin for first TPU), b_t2clk (1 pin for second TPU) T2CLK This signal is used to clock or gate the timer count register 2 (TCR2) within the TPU. This pin is an output-only in special test mode. 2.3.5 QADC_A/QADC_B PADS 2.3.5.1 ETRIG[1:2] Pin Name: etrig1 - etrig2 ETRIG These are the external trigger inputs to the QADC_A and QADC_B modules. ETRIG[1] can be configured to be used by both QADC_A and QADC_B. Likewise, ETRIG[2] can be used for both QADC_B and QADC_A. The trigger input pins are associated with the scan queues. 2.3.5.2 AN[0]/ANW/PQB[0]_[A:B] Pin Name: a_an0_anw_pqb0 (1 pin for first QADC), b_an0_anw_pqb0 (1 pin for second QADC) Analog Channel (AN0) Internally multiplexed input-only analog channels. Passed on as a separate signal to the QADC. Multiplexed Analog Input (ANW) Externally multiplexed analog input.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-24
USERS MANUAL

Port (PQB0) Input-only port. This is a 5-V input. This path is synchronized in the pad. The input is level-shifted before it is sent internally to the QADC. 2.3.5.3 AN[1]/ANX/PQB[1]_[A:B] Pin Name: a_an1_anx_pqb1 (1 pin for first QADC), b_an1_anx_pqb1 (1 pin for second QADC) Analog Channel (AN1) Internally multiplexed input-only analog channels. Passed on as a separate signal to the QADC. Multiplexed Analog Input (ANX) Externally multiplexed analog input. Port (PQB1) Input-only port. This is a 5-V input. This path is synchronized in the pad. The input is level-shifted before being sent internally to the QADC.
2.3.5.4 AN[2]/ANY/PQB[2]_[A:B] Pin Name: a_an2_any_pqb2 (1 pin for first QADC), b_an2_any_pqb2 (1 pin for second QADC) Analog Channel (AN2) Internally multiplexed input-only analog channel. The input is passed on as a separate signal to the QADC. Multiplexed Analog Input (ANY) Externally multiplexed analog input. Port (PQB2) Input-only port. This is a 5-V input. This path is synchronized in the pad. The input is level-shifted before it is sent internally to the QADC. 2.3.5.5 AN[3]/ANZ/PQB[3]_[A:B] Pin Name: a_an3_anz_pqb3 (1 pin for first QADC), b_an3_anz_pqb3 (1 pin for second QADC) Analog Input (AN3) Internally multiplexed input-only analog channel. The input is passed on as a separate signal to the QADC. Multiplexed Analog Input (ANZ) Externally multiplexed analog input. Port (PQB3) Input-only port. This is a 5-V input. This path is synchronized in the pad. The input is level-shifted before it is sent internally to the QADC. 2.3.5.6 AN[48:51]/PQB[4:7]_[A:B] Pin Name: a_an48_pqb4 a_an51_pqb7 (4 pins for first QADC), b_an48_pqb4 b_an51_pqb7 (4 pins for second QADC). Analog Input (AN[48:51]) Analog input channel. The input is passed on as a separate signal to the QADC. Port (PQB[4:7]) Input-only port. Has a synchronizer with an input enable and clock. The input is level-shifted before it is sent internally to the QADC.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-25
USERS MANUAL

2.3.5.7 AN[52:54]/MA[0:2]/PQA[0:2]_[A:B] Pin Name: a_an52_ma0_pqa0 a_an54_ma2_pqa2 (3 pins for first QADC), b_an52_ma0_pqa0 b_an54_ma2_pqa2 (3 pins for second QADC). Analog Input (AN[52:54]) Input-only. The input is passed on as a separate signal to the QADC. Multiplexed Address (MA[0:2]) Output. Provides a three-bit multiplexed address output to the external multiplexer chip to allow selection of one of the eight inputs. Port (PQA[0:2]) Bi-directional. 2.3.5.8 AN[55:59]/PQA[3:7]_[A:B] Pin Name: a_an55_pqa3 - a_an59_pqa7 (5 pins for first QADC), b_an55_pqa3 b_an59_pqa7 (5 pins for second QADC). Analog Input (AN[55:59]) Input-only. The input is passed on as a separate signal to the QADC. Port (PQA[3:7]) Bi-directional. 2.3.5.9 VRH Pin Name: vrh VRH Input pin for high reference voltage for the QADC_A and QADC_B modules. 2.3.5.10 VRL Pin Name: vrl VRL Input pin for low reference voltage for the QADC_A and QADC_B modules. 2.3.5.11 VDDA Pin Name: vdda VDDA Power supply input to analog subsystems of the QADC_A and QADC_B modules. 2.3.5.12 VSSA Pin Name: vssa VSSA Input. Ground level for analog subsystems of the QADC_A and QADC_B modules. 2.3.6 TOUCAN_A/TOUCAN_B PADS 2.3.6.1 CNTX0_[A:B] Pin Name: a_cntx0 (1 pin for first CAN), b_cntx0 (1 pin for second CAN)
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-26
USERS MANUAL

TouCAN Transmit Data 0 This signal is the serial data output. 2.3.6.2 CNRX0_[A:B] Pin Name: a_cnrx0 (1 pin for first CAN), b_cnrx0 (1 pin for second CAN) TouCAN Receive Data This signal furnishes serial input data. 2.3.7 CMF PADS 2.3.7.1 EPEE Pin Name: epee
EPEE Input. This control signal will externally control the program or erase operations. 2.3.7.2 VPP Pin Name: vpp VPP Input. Flash supply voltage (5-V supply) used during program and erase operations of the CMF. 2.3.7.3 VDDF Pin Name: vddf VDDF Flash core voltage input (3-V supply). This separate supply voltage is needed in order to reduce noise in the read path of CMF. 2.3.7.4 VSSF Pin Name: vssf VSSF Flash core zero supply input. This separate supply is needed in order to reduce noise in the read path of CMF. 2.3.8 GLOBAL POWER SUPPLIES 2.3.8.1 VDDL Pin Name: vddl VDDL 3-V voltage supply input. 2.3.8.2 VDDH Pin Name: vddh VDDH 5-V voltage supply input.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-27
USERS MANUAL

2.3.8.3 VDDI Pin Name: vddi VDDI 3-V voltage supply input for internal logic. 2.3.8.4 VSSI Pin Name: vssi VSSI Zero supply input for internal logic. In packaged devices, VSSI is not a separate input from VSS. 2.3.8.5 KAPWR Pin Name: kapwr
Keep-Alive Power 3-V voltage supply input for the oscillator and keep-alive registers. 2.3.8.6 VDDSRAM Pin Name: vddsram SRAM Keep-Alive Power 3-V voltage supply input for the SRAM. 2.3.8.7 VSS Pin Name: vss VSS Ground level reference input. 2.4 Reset State All input pins, with the exception of the power supply and clock related pins, are weakly pulled to a value during reset by a 130-microampere resistor based on certain conditions. In reset state all I/O pins become inputs, and all outputs except clkout, hreset_b, sreset_b, will be pulled only by the pull-up/pull-down. 2.4.1 Pin Functionality Out of Reset The functionality out of reset of some pins that support multiple functionality is defined in the SIUMCR through the reset configuration word. For details on which multiplexed pins are configured by the reset configuration word and how they are configured, refer to 7.5.2 Hard Reset Configuration Word. The 3-V related pins have selectable output buffer drive strengths which are controlled by the COM[0] bit in the USIUs system clock and reset control register (SCCR). The control is as follows:
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-28
USERS MANUAL

0 = 3-V bus pins full drive (50-pF load)* 1 = 3-V bus pins reduced drive (25-pF load)
* The bus pin drive selectability definition is inverted from the selectability of the pin control in the PDMCR register (for the TPU, QADC, USIU (SGPIO), QSPI, TouCAN, QSCI, and MIOS pins).
2.4.2 Pad Module Configuration Register (PDMCR) The slew rate and weak pull-up/pull-down characteristics of some pins are controlled by bits in the PDMCR. This register resides in the SIU memory map. The contents of the PDMCR are illustrated below. The PORESET signal resets all the PDMCR bits asynchronously.
.
PDMCR Pad Module Configuration Register
0x2F C03C
7 SPRD S 8 FTPU _PU1 9 10 11 12 Reserved 13 14 15
0 SLRC0
1 SLRC 1
6 PRDS
SLRC SLRC 2 3
Reserved
HARD RESET: 0 0 0 0 0 0 0 0
.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RESERVED HARD RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
NOTE: 1. FTPU_PU is only available on mask set K62N and later.
Table 2-3 PDMCR Bit Descriptions

Bit(s) 0 Name SLRC0 Description SLRC0 controls the slew rate of the following modules: TPU, QADC, USIU (SGPIO). 0 = Slow slew rate for pins. Controls slew rate pins of 200 ns. 1 = Normal slew rate for pins SLRC1 controls the slew rate of the QSPI and TouCAN modules. 0 = Slow slew rate for pins. Controls slew rate pins of 50 ns. 1 = Normal slew rate for pins SLRC2 controls the slew rate of the QSCI module. 0 = Slow slew rate for pins. Controls slew rate pins of 200 ns. 1 = Normal slew rate for pins SLRC3 controls the slew rate of the MIOS module. 0 = Slow slew rate for pins. Controls slew rate pins of 200 ns. 1 = Normal slew rate for pins Reserved The PRDS bit is used to enable or disable the weak pull-up/pull-down devices in the pads related to SGPIO and all pads related to IMB modules. Table 2-4 illustrates which pins are affected by PRDS. 0 = Enable pull-up/pull-down devices 1 = Disable pull-up/pull-down devices
SLRC1
SLRC2
3 4:5
SLRC3
PRDS
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-29
USERS MANUAL

Table 2-3 PDMCR Bit Descriptions (Continued)
Bit(s) Name Description The SPRDS bit is used to enable or disable the weak pull-up/pull-down devices in special 3-V only bus pads. Table 2-4 illustrates which pins are affected by SPRDS. For more details on how this bit affects the pins see 2.4.7 Special Pull Resistor Disable Control (SPRDS). 0 = Enable pull-up/pull-down devices 1 = Disable pull-up/pull-down devices
SPRDS
Follow TPU Pull-Up Controls the pull-up devices for all T2CLK pins. FTPU_PU is only available on mask set K62N and later. FTPU_PU 0 = Pull-ups are active when the pins are defined as inputs 1 = Pull-ups for the TPU T2CLK pins are enabled or disabled based on the state of PRDS Reserved
9:31
2.4.3 Pin State During Reset During reset, the functionality of some pins is undetermined. Their functionality is based on the bits in the SIUMCR. Since the SIUMCR bits are undetermined during reset, there is no way of predicting how the pins will function. However, the pins must not cause any spurious conditions or consume an excessive amount of power during reset. To prevent these conditions, the pins need to have a defined reset state. Table 24 describes the reset state of the pins based on pin functionality. All pins are initialized to a reset state during reset. This state remains active until reset is negated or until software disables the pull-up or pull-down device based on the pin functionality. Upon assertion of the corresponding bits in the pin control registers and negation of reset, the pin acquires the functionality that was programmed. 2.4.4 Power-On Reset and Hard Reset Power-on reset and hard reset affect the functionality of the pins out of reset. (During soft reset, the functionality of the pins is unaltered.) Upon assertion of the power-on reset signal (PORESET) the functionality of the pin is not yet known. The pull-up or pull-down resistors are enabled. The reset configuration word configures the system, and towards the end of reset the pin functionality is known. Based upon pin functionality, the pull-up or pull-down devices are either disabled immediately at the negation of reset or remain enabled. Hard reset can occur at any time, and there may be a bus cycle pending. For this reason, the bits in PDMCR that control the enabling and disabling of the pull-up or pulldown resistors in the pads are set or reset synchronously. (PORESET affects these bits asynchronously.) This causes the pull-up or pull-down resistors to be enabled at a time when they do not cause contention on the pins and are disabled before they can cause any contention on the pins. 2.4.5 Pull-Up and Pull-Down Enable and Disable for 5-V Only Pins For 5-V only pins, the enabling and disabling of the pull-up and pull-down devices is controlled by the PRDS bit in PDMCR. If the bit is negated, the devices are active. If the bit is asserted, the devices are inactive.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-30
USERS MANUAL

2.4.6 Pull-Up and Pull-Down Enable and Disable for 3-V / 5-V Multiplexed Pins Two signals are needed to enable or disable the pull-up/pull-down devices in the 3-V / 5-V multiplexed pads: The PRDS signal An encoded 3-V / 5-V select 2.4.6.1 PRDS Signal The PRDS signal is derived from the PRDS bit in the PDMCR. A single signal controls all affected pads (all pads related to SGPIO and all pads related to the UIMB modules). The bit is reset by default (pull-ups enabled) and must be explicitly set by software after reset. The bit is reset immediately following power-on reset and by hard reset after data coherency. This bit is not affected by soft reset.
2.4.6.2 Encoded 3-V / 5-V Select This signal selects between the 3-V functionality and the 5-V functionality of the pin. 5-V operation is selected until the function of the pin is determined (based on the reset configuration word) and PORESET is negated. At this point the 3-V / 5-V select signal assumes the intended state (high for 5 V and low for 3 V). Upon hard reset assertion, if the 3-V / 5-V select line is in 3-V select mode, it remains in this mode until any external bus access completes. After this the 3-V / 5-V select signal switches to 5-V mode to enable the pull-ups. This ensures that there is no contention on the bus due to the pull-up being enabled. This signal is not affected by soft reset. Each pad group has a 3-V / 5-V select signal. Internal to the pad, logic combines these signals to control the pull-up. 2.4.6.3 Examples The combination of this 3-V / 5-V select signal and the resistor disable signal enables or disables the pull-up.The logic to enable the pull-up is: pull_enable = PRDS & 3-V / 5-V select For example, if a pin is configured as a GPIO pin (5 V), the 3-V / 5-V select is high throughout reset. This causes the pull-up to be enabled. At the end of reset, the 3-V / 5-V select line remains high. The PRDS is high by default until cleared by software. This causes the pull-up to be enabled until software clears the PRDS bit in the PDMCR. If a pin is configured as a bus pin (3 V), the 3 V / 5 V remains high throughout reset. This causes the pull-up to be enabled. At the end of reset, the 3-V / 5-V select line goes low. This causes the pull-up to be disabled, preventing any power loss if the MCU starts fetching from external memory immediately out of reset.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-31
USERS MANUAL

2.4.7 Special Pull Resistor Disable Control (SPRDS) For the pins that support debug and opcode-tracking functionality, the pull-up and pulldown resistors are controlled by the SPRDS signal, which is somewhat like the encoded 3-V / 5-V select. During reset this signal is used synchronously to enable the pullup resistors in the pads. On negation of reset, based on which functionality is selected for the pins, this signal is set to disable the pull-up resistors or remains held in its reset state to indicate that the pull-ups are disabled only when the output driver is enabled. For example, if a pin is configured as a bus arbitration pin, The SPRDS signal remains low throughout reset. This causes the pull-up to be enabled. When reset is released, SPRDS remains low. The output enable for the driver is negated by default. When the output driver is enabled, the pull-up is disabled.
When a pin is configured as an opcode-tracking or debug pin, SPRDS remains low throughout reset. This causes the pull-up to be enabled. When reset is released, SPRDS is asserted. This disables the pull-up resistor immediately. The output driver drives the pin to the required state after reset. 2.4.8 Pin Reset States Table 2-4 summarizes the reset states of all the pins on the MPC555 / MPC556. Table 2-4 Pin Reset State
Pin
Function Port Voltage USIU ADDR[8:31]/ SGPIOA[8:31] DATA[0:31]/ SGPIOD[0:31] IRQ[0]/SGPIOC[0] ADDR[8:31] SGPIOA[8:31] DATA[0:31] SGPIOD[0:31] IRQ[0] SGPIOC[0] IRQ[1] IRQ[1]/ RSV/SGPIOC[1] RSV SGPIOC[1] IRQ[2] IRQ[2]/ CR/SGPIOC[2]/ MTS CR SGPIOC[2] MTS IRQ[3]/ KR, RETRY/ SGPIOC[3] IRQ[4]/ AT[2]/ SGPIOC[4] IRQ[3] KR, RETRY SGPIOC[3] IRQ[4] AT[2] SGPIOC[4] I/O IO I/O I/O I I/O I O I/O I I I/O O I I/O I/O I O I/O 3V 5V 3V 5V 3V 5V 3V 3V 5V 3V 3V 5V 3V 3V 3V 5V 3V 3V 5V PU5 until reset negates1 PU5 until PRDS is set PD until reset negates PD until PRDS is set PU5 until reset negates1 PU5 until PRDS is set PU5 until reset negates1 PU5 until reset negates1 PU5 until PRDS is set PU5 until reset negates1 PU5 until reset negates1 PU5 until PRDS is set PU5 until PRDS negates PU5 until reset negates1 PU5 when driver not enabled2 PU5 until PRDS is set PU5 until reset negates1 PU5 until reset negates1 PU5 until PRDS is set Reset State
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-32
USERS MANUAL

Table 2-4 Pin Reset State (Continued)
Pin
IRQ[5]/SGPIOC[5]/ MODCK[1]3 IRQ[6:7]/ MODCK[2:3]3 TSIZ[0:1] RD/WR BURST Function IRQ[5] SGPIOC[5] MODCK[1] IRQ[6:7] MODCK[2:3] TSIZ[0:1] RD/WR BURST BDIP TS TA Port I I/O I I I I/O I/O I/O I/O I/O I/O Voltage 3V 5V 3V 3V 3V 3V 3V 3V 3V 3V 3V Reset State PU5 until reset negates1 PU5 until PRDS is set PU5 until reset negates1 PU3 until SPRDS is set PU3 until reset negates PD when driver not enabled or until SPRDS is set PU3 when driver not enabled or until SPRDS is set PU3 when driver not enabled or until SPRDS is set PU3 when driver not enabled or until SPRDS is set PU3 when driver not enabled or until SPRDS is set PU3 when driver not enabled or until SPRDS is set PU3 when driver not enabled or until SPRDS is set An external pull-up is required in order to negate the pin in appropriate time PU3 when driver not enabled or until SPRDS is set PU3 until reset negates PU3 when driver not enabled or until SPRDS is set PU3 until reset negates PU3 when driver not enabled or until SPRDS is set PU3 when driver not enabled or until SPRDS is set An external pull-up is required in order to negate the pin in appropriate time PU3 when driver not enabled or until SPRDS is set An external pull-up is required in order to negate the pin in appropriate time PU5 until PRDS is set PU5 until reset negates1 PU5 until reset negates1
BDIP TS4 TA4
TEA
TEA
I/O
3V
RSTCONF/TEXP3 OE BI/STS CS[0:3] WE[0:3]/BE[0:3]/ AT[0:3] PORESET3
RSTCONF TEXP OE BI4 STS CS[0:3] WE[0:3]/BE[0:3] AT[0:3] PORESET
I O O I/O O O O O I
3V 3V 3V 3V 3V 3V 3V 3V 3V
HRESET3
HRESET
I/O
3V
SRESET3
SRESET
I/O
3V
SGPIOC[6]/ FRZ/ PTR
SGPIOC[6] FRZ PTR
I/O O O
5V 3V 3V
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-33
USERS MANUAL

Pin
SGPIOC[7/ IRQOUT/LWP[0] Function SGPIOC[7] IRQOUT LWP[0] BG/ VF[0]/ LWP[1] BR/ VF[1]/ IWP[2] BG VF[0] LWP[1] BR VF[1] IWP[2] BB4 VF[2] IWP[3] IWP[0:1] VFLS[0:1] TMS TDI DSDI TCK DSCK TDO DSDO TRST XTAL EXTAL XFC CLKOUT EXTCLK ENGCLK BUCLK
3
Port I/O O O I/O O O I/O O O I/O O O O O I I I I I O O I I I I O I O O
Voltage 5V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 5V 5V
Reset State PU5 until PRDS is set PU5 until reset negates1 PU5 until reset negates1 PU3 when driver not enabled or until SPRDS is set PU3 when driver not enabled or until SPRDS is set
BB/ VF[2]/ IWP[3] IWP[0:1]/ VFLS[0:1] TMS TDI/ DSDI TCK/ DSCK TDO/ DSDO TRST XTAL3 EXTAL XFC CLKOUT EXTCLK
3
PU3 when driver not enabled or until SPRDS is set
PU3 until reset negates PU3 until SPRDS is set PU3 until SPRDS is set PD until SPRDS is set PU3 until reset negates PU3 until SPRDS is set
ENGCLK/ BUCLK
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-34
USERS MANUAL

Pin
Function PCS0 SS QGPIO[0] PCS[1:3] QGPIO[1:3] MISO QGPIO[4] MOSI QGPIO[5] SCK QGPIO[6] TXD[1:2] QGPO[1:2] RXD[1:2] QGPI[1:2] ECK MDA[4:13] MPWM[0:3], [16:19] VF[0:2] MPIO32B[0:2] VFLS[0:1] MPIO32B[3:4] MPIO32B[5:15] TPUCH[0:15] T2CLK TPUCH[0:15] T2CLK Port I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I I I I/O I/O O I/O O I/O I/O I/O I/O I/O I/O Voltage 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V MIOS MDA[4:13] MPWM[0:3], [16:19] VF[0:2]/ MPIO32B[0:2] VFLS[0:1]/ MPIO32B[3:4] MPIO32B[5:15] A: TPUCH[0:15] A: T2CLK B: TPUCH[0:15] B: T2CLK 5V 5V 3V 5V 3V 5V 5V 5V 5V 5V 5V PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 when driver not enabled2 PU5 until PRDS is set PU5 when driver not enabled2 PD PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set Reset State QSMCM PCS0/ SS/ QGPIO[0] PCS[1:3]/ QGPIO[1:3] MISO/ QGPIO[4] MOSI/ QGPIO[5]
SCK/ QGPIO[6] TXD[1:2]/ QGPO[1:2] RXD[1:2]/QGPI[1:2] ECK
TPU_A/TPU_B
QADC_A/QADC_B ETRIG[1:2] A: AN0/ANW/PQB0 ETRIG[1:2] AN0 ANW PQB0 AN1 A: AN1/ANX/PQB1 ANX PQB1 AN2 A: AN2/ANY/PQB2 ANY PQB2 I I I I I I I I I I 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-35
USERS MANUAL

Pin
A: AN3/ANZ/PQB3 Function AN3 ANZ PQB3 A: AN[48:51]/ PQB[4:7] A: AN[52:54]/ MA[0:2]/PQA[0:2] A: AN[55:56]]/ PQA[3:4] AN[48:51] PQB[4:7] AN[52:54] MA[0:2] PQA[0:2] AN[55:56] PQA[3:4] AN[57:59] PQA[5:7] AN0 B: AN0/ANW/PQB0 ANW PQB0 AN1 B: AN1/ANX/PQB1 ANX PQB1 AN2 B: AN2/ANY/PQB2 ANY PQB2 AN3 B: AN3/ANZ/PQB3 ANZ PQB3 B: AN[48:51]/ PQB[4:7] B: AN[52:54]/ MA[0:2]/PQA[0:2] B: AN[55:56]/ PQA[3:4] B: AN[57:59]/ PQA[5:7] VRH VRL VDDA VSSA A: CNTX0 B: CNTX0 A: CNRX0 B: CNRX0 AN[48:51] PQB[4:7] AN[52:54] MA[0:2] PQA[0:2] AN[55:56] PQA[3:4] AN[57:59] PQA[5:7] VRH VRL VDDA VSSA A_CNTX0 B_CNTX0 A_CNRX0 B_CNRX0 Port I I I I I I I I/O I I/O I I/O I I I I I I I I I I I I I I I I I/O I I/O I I/O I I I I O O I I Voltage 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V Reset State PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set PU5 until PRDS is set
A: AN[57:59]/ PQA[5:7]
TouCAN_A/TouCAN_B
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-36
USERS MANUAL

Pin
EPEE VPP VDDF VSSF VDDL VDDH VDDI VSSI Function EPEE VPP VDDF VSSF VDDL VDDH VDDSI VSSI
3
Port I I I I I I I I I I I I I
Voltage CMF 3V 5V 3V 3V 3V 5V 3V 3V 3V 3V 3V 3V PD
Reset State
Global Power Supplies
KAPWR
KAPWR VDDSRAM VDDSYN VSS VSSSYN
VDDSRAM VDDSYN VSS VSSSYN
NOTES: 1. During reset, the output enable to the pad driver is negated and the PU3/PU5 is active. After reset is negated, the output enable is continuously enabled and the PU3 is disabled. The driver is responsible for driving a valid state on the pin. 2. Pull-up/pull-down is active when pin is defined as an input and/or during reset; therefore, output enable is negated. This also means that external pull-up/pull-down is not required unless specified. 3. These pins are powered by KAPWR (Keep-Alive Power Supply). 4. This pin is an active negate signal and may need an external pull-up resister.
2.5 Pad Types There are different pad types based on functional characteristics. Even pads with the same functionality may be different due to different electrical characteristics. All 5-V inputs have hysteresis. There is no synchronization in the pads; it is all in the modules. 2.5.1 Pad Interface Signals The pad interface consists of an internal interface and an external interface. The external interface is to the pin. The internal interface is the set of signals that interface the pad to the chips internal logic. The following internal interface signals are used: Data The line driven from an internal module of the chip to the pad. For bi-directional pins, the internal interface may be a single line for both input and output or two separate paths for input and output. The descriptions of individual pad types specify which. 3-V / 5-V select Selects a 3-V or 5-V driver, for pads that support both. This signal is driven from the USIU. Output enable (OE) Enables the output driver. For 3-V / 5-V pads, the appropriate driver is enabled based on the pin functionality selected. Input enable Enables the receiver. For 3-V / 5-V pads, the appropriate receiver is enabled based on the pin functionality selected.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-37
USERS MANUAL

Drive select Selects the drive strength of the pad. For example, data pin drivers can be configured to drive a 25-pF load or a 50-pF load. Synchronizer clock Some pins have synchronizer logic to handle metastable signals at the input of a pin. For pads that have synchronizers and support synchronized or normal data input, the corresponding interface signals to the internal logic are Normal Data In and Sync Data In. Slew rate control GPIO pins have slow slew rates, with edge rates in the range of 90 ns to 600 ns. The slew rate and weak pull-up/pull-down characteristics of these pins are controlled by bits in the PDMCR, see 2.4.2 Pad Module Configuration Register (PDMCR). For a description of PDMCR bits SLRC[0:3] that have controllable slew rates, see Table 2-3. Hysteresis input Slow pads contains hysteresis input buffers to reduce the sensitivity to noises. The input hyst_sel is used to configure the pad to provide hysteresis according to the pad configuration. Open drain enable For selected 3-V / 5-V pads, this signal determines the type of drive (open drain or totem pole) seen at the pin. Pull resistor disable select (PRDS) Reflects the state of the PRDS bit in the pad module configuration register (PDMCR). This signal controls the pull-up/pulldown resistor for the SGPIO pins and the pins for the modules on the UIMB. Special pull resistor disable select (SPRDS) Reflects the state of the SPRDS bit in the PDMCR. For pins that support bus arbitration functionality multiplexed with opcode-tracking and debug functionality, this signal controls the pull-up resistors. Analog Analog input signals to the QADC. The corresponding digital interface signals are referred to as Dig. In and Dig. Out. JTAG Joint Test Access Group related signals that are used for connectivity tests at the board level. These signals are not shown in the pad block diagrams in this section. In addition, the effect of the pull-up/pull-down resistors is not illustrated in the pad block diagrams. These interface signals are referred to in the following pad descriptions and shown in the pad diagrams. 2.5.2 Three-Volt Output Pad The output driver of a 3-V output-only pad can be configured to drive a 25-pF or 50-pF load. There are two subtypes: one with a pull-up device and the other with a pull-down device. The SPRDS and OE signals enable the pull-up and pull-down resistors. 2.5.2.1 Type A Interface This pad has a pull-up device to 3 V which can be conditionally turned off based on the value placed on OE. For a totem pole (push pull) pin with no three-state drive time, the OE can be connected to VDD, indicating a continuous drive. For a continuous drive, the pull-up can be disabled.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-38
USERS MANUAL

3V
Drive Sel Sprds Data Out OE Logic 3-V Driver Pin
Figure 2-3 Type A Interface 2.5.2.2 Type B Interface (Clock Pad) The pad has a capability to select the buffer for the appropriate load (45 or 90 pF). The OE input drives the totem pole output or three-states the output.
Drive Sel 3-V Driver Pin
Data Out OE
Logic
Figure 2-4 Type B Interface 2.5.3 Three-Volt Input Pad Four subtypes are defined for the 3-V input-only pad: one with a pull-up resistor, one with a pull-up resistor and with or without hysteresis in the receiver, one with hysteresis
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-39
USERS MANUAL

(no resistor), and one with a pull-down resistor. The SPRDS signal may disable the pull-up or pull-down resistor. 2.5.3.1 Type C Interface The type C interface has a 3-V input with a pull-up resistor. 3V
Data In Sprds 3-V Receiver Pin
Figure 2-5 Type C Interface 2.5.3.2 Type CH Interface Pad type CH has a 3-V input with hysteresis and a pull-up resistor. The hyst_sel signal selects the receiver with or without hysteresis. 3V
Data In Sprds
Receiver 3V Pin
hyst_sel
3V
Figure 2-6 Type CH Interface
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-40
USERS MANUAL

2.5.3.3 Type CNH Interface The CNH pad type has a 3-V input with hysteresis but no pull-up or pull-down device. 3V
Data In 3-V Receiver Pin
Figure 2-7 Type CNH Interface 2.5.3.4 Type D Interface This type of pad has a 3-V input and an internal pull-down resistor. 3V
Data In 3-V Receiver Sprds
Pin
Figure 2-8 Type D Interface 2.5.4 Three-Volt Input/Output Pad This is a 3-V bi-directional pad with a pull-up device. The drive strength for the output driver can be configured for either a 25-pF or a 50-pF load. The SPRDS and OE signals control the pull-up devices.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-41
USERS MANUAL

2.5.4.1 Type E Interface In this pad type the data interface to the internal logic has separate paths for input and output. This pad also has a open drain enable input. For totem pole driven outputs, the signal is connected to VSS to disable the open-drain drive. 3V OD Enable Drive Sel Sprds
Data Out OE Data In Logic
3-V Driver
Pin
3-V Receiver IE
Figure 2-9 Type E Interface 2.5.4.2 Type EOH Interface In this pad type the data interface to the internal logic has separate paths for input and output. The receiver has hysteresis. The pull-up is active when the driver is not enabled.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-42
USERS MANUAL

3V
Drive Sel Sprds Data Out Logic OE 3-V OD Driver Pin
Data In IE
3-V Receiver
Figure 2-10 3-V Type EOH Interface 2.5.4.3 Type F Interface In this pad type the data interface to the internal logic has the same path for both input and output. The pull-up is inactive when the driver is enabled.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-43
USERS MANUAL

3V Drive Sel Sprds Data IO Logic OE 3-V OD Driver
Pin
3-V Receiver IE
Figure 2-11 Type F Interface 2.5.4.4 Type G Interface In this pad type the data interface to the internal logic has the same path for both input and output. This pad type also has the SPRDS signal as an input to disable the resistor when the pad is a non-bus function.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-44
USERS MANUAL

3V Sprds Drive Sel
Data Out Logic OE
3-V Driver
Pin
Data In IE
3-V Receiver
Figure 2-12 Type G Interface 2.5.5 Five-Volt Input/Output Pad This pad type is for 5-V bi-directional pins. There is provision to pull the pin up to 5 V and logic to control when the pull-up is enabled. For a 5-V driver, the internal Fast Mode signal selects the slow or fast driver. All 5-V inputs have hyteresis. 2.5.5.1 Type H Interface This pad has logic for a 3-V output function as well as a 5-V input-output function. A 3-V / 5-V sel interface signal determines which driver gets selected. This pad type has two separate data output paths. These paths are multiplexed onto the output pin based on the 3-V / 5-V select signal. This pad also has a dedicated synchronous input path. If only one of the output paths is used on a device, the other can be connected to ground. In this case, the 3-V / 5-V select signal must be tied to the appropriate value to disable the other path.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-45
USERS MANUAL
5V 3-V / 5-V Sel PRDS Drive Sel 5 V Data Out 3 V Data Out Logic 5V Pin Driver 3V
OE SLRC Synch. Data In Synch. Clk
5-V Synch. Receiver
Figure 2-13 Type H Interface 2.5.5.2 Type I Interface This pad has logic for a 3-V input/output function as well as a 5-V input/output function. A 3-V / 5-V sel interface signal indicates which driver gets selected.The data interface to the internal logic has separate paths for input and output.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-46
USERS MANUAL
5V 3-V / 5-V Sel PRDS 5V Data Out OE Drive Sel SLRC Data In IE 5V Receiver 3V Logic Driver 3V Pin
Figure 2-14 Type I Interface 2.5.5.3 Type IH Interface This pad has logic for a 3-V input/output function as well as a 5-V input/output function. A 3-V / 5-V sel interface signal determines which driver gets selected. In this pad type the data interface to the internal logic has separate paths for input and output. The 3-V receiver has 2 possible paths: with or without hysteresis. The hyst_sel signal selects the appropriate path.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-47
USERS MANUAL
5V 3-V / 5-V Sel PRDS 5V Data Out OE Drive Sel SLRC Data In IE 5V Receiver 3V hyst_sel 3V Logic Driver 3V Pin
Figure 2-15 Type IH Interface 2.5.5.4 Type J Interface This pad has logic for a 3-V input/output function as well as a 5-V input/output function. A 3-V / 5-V sel interface signal indicates which driver gets selected. The data interface to the internal logic has the same path for both input and output.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-48
USERS MANUAL
5V 3-V / 5-V Sel PRDS 5V Data OE Drive Sel Logic Driver 3V Pin
SLRC 5V IE Receiver 3V
Figure 2-16 Type J Interface 2.5.5.5 Type JD Interface This pad has logic for a 3-V input/output function as well as a 5-V input/output function. A 3-V / 5-V sel interface signal indicates which driver gets selected. The data interface to the internal logic has the same path for both input and output. The pad has a pull-down resistor which is activated by reset and/or PRDS.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-49
USERS MANUAL
3-V / 5-V Sel PRDS 5V Pin Logic Driver 3V
Data OE Drive Sel SLRC
5V IE Receiver 3V
Figure 2-17 Type JD Interface 2.5.6 Type K Interface (EPEE Pad) This pad has a pull-down device that is enabled at all times. The module checks to see that a transition to a new state on the pin is maintained for at least two clocks before the information is passed on internally to the sequencer implemented in the flash. The synchronizer clock to this pad is GCLK2.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-50
USERS MANUAL
Data
1 1 0 1 0
1 1
0 Pin 1 0
Synch. Clk
Sequencer Figure 2-18 EPEE Pad (Type K) 2.5.7 Analog Pads The 5-V analog pads interface to the QADC modules internally. They have separate analog and digital paths in the pad in order to implement the functionality that is multiplexed on the pin. 2.5.7.1 Type L Interface (QADC Port A) This pad is used for interfacing to the port A of the QADC. The digital portion of the pad supports bi-directional operation. The receiver has a synchronizer. The digital input is level-shifted from 5 V to 3 V before it is sent internally to the QADC.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-51
USERS MANUAL

5V PRDS Analog In Dig. Out Data Direction Dig. In Input Enable Synch. Rx Digital Level Shifter OD Driver Pin Analog
Sync. Clk
Figure 2-19 Type L Interface 2.5.7.2 Type M Interface (QADC Port B) This pad is used for interfacing to port B of the QADC. This is an input-only pad. The receiver has a synchronizer. The digital input is level-shifted from 5 V to 3 V before it is sent internally to the QADC. 5V PRDS Analog In PRDS Pin Dig. In Input Enable Sync. Clk Digital Synch. Rx Level Shifter Analog
Figure 2-20 Type M Interface
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-52
USERS MANUAL

2.5.7.3 Type N Interface (ETRIG) This is the pad for the ETRIG function of the QADC. The input signal is level-shifted before being sent to the QADC module. The pad also serves as an output pad in test mode. 5V
Input Enable Dig. In Pin Synch. Rx Sync. Clk Digital
Figure 2-21 Type N Interface 2.5.8 Pads with Fast Mode The type O pads (for interfacing to the QSMCM) and type P pads (for interfacing to the TPU and MIOS) have a fast mode provision. 2.5.8.1 Type O Interface (QSMCM Pads) This pad is used for interfacing to the QSMCM. It is a 5-V, bi-directional pad and has provision for a fast mode in which the slow slew rate driver is bypassed and data is driven by a fast slew rate driver. When the pin is an input, the data can be driven either synchronously or asynchronously. A pull-up device is available which can be disabled using the PRDS signal.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-53
USERS MANUAL

5V SLRC OD Enable PRDS Data Out Logic OE Normal Data In 5-V Receiver 5-V Synch. Receiver 5-V Driver Slow 5-V Driver Fast Pin
Synch. Data In Synch. Clk
Figure 2-22 Type O Interface 2.5.8.2 Type P Interface (TPU and MIOS Pads) This is a 5-V, bi-directional pad that has a fast mode provision like the QSMCM pads. The input path is always synchronous. The receiver has hysteresis in order to minimize the effect of noise on the pins. In addition, the receiver has a digital filter (somewhat like the sequencer for the EPEE pad) to check for a state on the pin for a particular number of clocks. The pad also has a pull-up device. Depending on the reset state (see Table 2-4) the pull-up may be controlled by the PRDS signal.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-54
USERS MANUAL

5V SLRC 5-V Driver Slow Logic OE 5-V Driver Fast Pin
PRDS Data Out
5-V Synch. Data In Synch. Clk Synch. Hysteresis Receiver
Figure 2-23 Type P Interface 2.5.9 5V Input, 5V Output Pads These pads are 5-V only pads. 2.5.9.1 5V Output (Type Q) This pad is a 5-V output-only pad with slow and fast drive capability. The driver is configureable to be either push pull or open drain using the OD enable signal. This pad type has a pull-up device that can be controlled using the PRDS signal.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-55
USERS MANUAL

5V PRDS OD Enable 5-V Driver Slow Logic 5-V Driver Fast Pin
Data Out OE SLRC
Figure 2-24 Type Q Interface 2.5.9.2 Type R Interface This is a 5-V input-only pad with a synchronous and asynchronous receiver. Both synchronous and asynchronous data are driven in from the internal module that interfaces to this pad. A pull-up device can be controlled using the PRDS signal. 5V PRDS
Normal Data In Synch. Data In Synch. Clk
5-V Receiver 5-V Synch. Receiver
Pin
Figure 2-25 Type R Interface
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-56
USERS MANUAL

2.5.9.3 5V Output for Clock Pad This interface is used for a 5-V clock pad output. The drive select signal selects the buffer for a 45- or 90-pF load.
Drive Sel 5-V Data Out OE Logic Driver Pin
Figure 2-26 Type S Interface 2.6 Pad Groups A pad group is a set of pins that exhibits similar functional characteristics. Within a group the individual pads may be of different types. The functionality of some pins is defined based on the control bits that are set in the SIUMCR from the reset configuration word. Refer to the section on pin functionality out of reset in the reset section of the document. The following is a list of pad groups which were obtained based on the 3-V / 5-V selection from the information in the pin configuration out of reset tables. In other words, each group receives a different encoded 3-V / 5-V select signal. Table 2-5 Pad Groups Based on 3-V / 5-V Select
Group 1 2 3 4 5 DATA[0:31]/SGPIOD[0:31] ADDR[8:31]/SGPIOA[8:31] IRQ[0]/SGPIOC[0], IRQ[1]/SGPIOC[1], IRQ[4]/SGPIOC[4] IRQ[2]/SGPIOC[2], IRQ[3]/SGPIOC[3], IRQ[5]/SGPIOC[5] Pins FRZ/PTR/SGPIOC[6], SGPIO[7]/IRQOUT/LWP[0]
All pins that drive 3 V have the provision to choose between drive strengths for a 25pF load or a 50-pF load.
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-57
USERS MANUAL

2.7 Pin Names and Abbreviations The following table lists the recommended abbreviations for all the pins on the MPC555 / MPC556. The abbreviations can be used in applications for which the actual name is too long. For example, they can be used to on circuit boards to map the pin location on the boards. Table 2-6 Pin Names and Abbreviations
Pin List Pin Name addr_sgpioa[8] addr_sgpioa[9] addr_sgpioa[10] addr_sgpioa[11] addr_sgpioa[12] addr_sgpioa[13] addr_sgpioa[14] addr_sgpioa[15] addr_sgpioa[16] addr_sgpioa[17] addr_sgpioa[18] ADDR[8:31]/SGPIOA[8:31] addr_sgpioa[19] addr_sgpioa[20] addr_sgpioa[21] addr_sgpioa[22] addr_sgpioa[23] addr_sgpioa[24] addr_sgpioa[25] addr_sgpioa[26] addr_sgpioa[27] addr_sgpioa[28] addr_sgpioa[29] addr_sgpioa[30] addr_sgpioa[31] Abbreviation addr_sgp[8] addr_sgp[9] addr_sgp[10] addr_sgp[11] addr_sgp[12] addr_sgp[13] addr_sgp[14] addr_sgp[15] addr_sgp[16] addr_sgp[17] addr_sgp[18] addr_sgp[19] addr_sgp[20] addr_sgp[21] addr_sgp[22] addr_sgp[23] addr_sgp[24] addr_sgp[25] addr_sgp[26] addr_sgp[27] addr_sgp[28] addr_sgp[29] addr_sgp[30] addr_sgp[31] V6 V5 V4 V3 W1 Y2 W3 Y3 W4 Y4 W5 Y5 W6 Y6 V7 W7 Y7 Y8 W8 V8 U8 U9 U7 U6 Ball
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-58
USERS MANUAL

Table 2-6 Pin Names and Abbreviations (Continued)
Pin List Pin Name data_sgpiod[0] data_sgpiod[1] data_sgpiod[2] data_sgpiod[3] data_sgpiod[4] data_sgpiod[5] data_sgpiod[6] data_sgpiod[7] data_sgpiod[8] data_sgpiod[9] data_sgpiod[10] data_sgpiod[11] data_sgpiod[12] data_sgpiod[13] data_sgpiod[14] DATA[0:31]/SGPIOD[0:31] data_sgpiod[15] data_sgpiod[16] data_sgpiod[17] data_sgpiod[18] data_sgpiod[19] data_sgpiod[20] data_sgpiod[21] data_sgpiod[22] data_sgpiod[23] data_sgpiod[24] data_sgpiod[25] data_sgpiod[26] data_sgpiod[27] data_sgpiod[28] data_sgpiod[29] data_sgpiod[30] data_sgpiod[31] IRQ[0]/SGPIOC[0] IRQ[1]/RSV/SGPIOC[1] IRQ[2]/CR/SGPIOC[2]/MTS IRQ[3]/KR, RETRY/SGPIOC[3] IRQ[4]/AT[2]/SGPIOC[4] IRQ[5]/SGPIOC[5]/MODCK[1] IRQ[6:7]/MODCK[2:3] TSIZ[0:1] irq0_b_sgpioc0 irq1_b_rsv_b_sgpioc1 irq2_b_cr_b_sgpioc2_mts irq4_b_at2_sgpioc4 irq5_b_sgpioc5_modck1 irq6_b_modck2 irq7_b_modck3 tsiz0 tsiz1 Abbreviation data_sgp[0] data_sgp[1] data_sgp[2] data_sgp[3] data_sgp[4] data_sgp[5] data_sgp[6] data_sgp[7] data_sgp[8] data_sgp[9] data_sgp[10] data_sgp[11] data_sgp[12] data_sgp[13] data_sgp[14] data_sgp[15] data_sgp[16] data_sgp[17] data_sgp[18] data_sgp[19] data_sgp[20] data_sgp[21] data_sgp[22] data_sgp[23] data_sgp[24] data_sgp[25] data_sgp[26] data_sgp[27] data_sgp[28] data_sgp[29] data_sgp[30] data_sgp[31] irq0b_sgp irq1b_sgp irq2b_sgp irq4b_sgp irq5b_sgp irq6b_mck2 irq7b_mck3 tsiz0 tsiz1 Y9 W9 Y10 W10 Y11 W11 Y12 W12 Y13 W13 Y14 W14 Y15 W15 Y16 W16 Y17 W17 V17 V16 U16 V15 V14 U14 V13 U13 V12 U12 V11 U11 V10 V9 M1 M2 M3 L3 L4 W18 Y18 Y19 U1 T3 Ball
irq3_b_kr_b_retry_b_sgpioc3 irq3b_sgp
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-59
USERS MANUAL

Pin List RD/ WR BURST BDIP TS TA TEA RSTCONF/TEXP OE BI/STS rd_wr_b burst_b bdip_b ts_b ta_b tea_b rstconf_b_texp oe_b bi_b_sts_b cs0_b cs1_b cs2_b cs3_b we0_b_be0_b_at0 WE[0:3]/BE[0:3]/AT[0:3] we1_b_be1_b_at1 we2_b_be2_b_at2 we3_b_be3_b_at3 PORESET HRESET SRESET SGPIOC[6]/FRZ/PTR/ SGPIOC[7]/IRQOUT/LWP[0] BG/VF[0]/LWP[1] BR/VF[1]/IWP[2] BB/VF[2]/IWP[3] IWP[0:1]/VFLS[0:1] TMS TDI/DSDI TCK/DSCK TDO/DSDO TRST XTAL EXTAL XFC CLKOUT EXTCLK VDDSYN VSSSYN ENGCLK/BUCLK poreset_b hreset_b sreset_b sgpioc6_frz_ptr_b sgpioc7_irqout_b_lwp0 bg_b_vf0_lwp1 br_b_vf1_iwp2 bb_b_vf2_iwp3 iwp0_vfls0 iwp1_vfls1 tms tdi_dsdi tck_dsck tdo_dsdo trst_b xtal extal xfc clkout extclk vddsyn vsssyn engclk_buclk Pin Name Abbreviation rd_wrb burstb bdipb tsb tab teab rcfb_txp oeb bib_stsb cs0b cs1b cs2b cs3b web_at[0] web_at[1] web_at[2] web_at[3] poresetb hresetb sresetb sgp_frz sgp_irqoutb bgb_lwp1 brb_iwp2 bbb_iwp3 iwp0_vfls iwp1_vfls tms tdi_dsdi tck_dsck tdo_dsdo trst_b xtal extal xfc clkout extclk vddsyn vsssyn eck_buck R1 V1 U4 U3 U2 T2 U17 T1 V2 P4 R4 R3 R2 N1 P1 P2 P3 V19 W20 V20 K3 M4 N3 N2 N4 L2 L1 K1 K2 J1 J2 J3 U20 T20 R19 V18 U18 R20 T19 U19 Ball
CS[0:3]
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-60
USERS MANUAL

Pin List PCS0/SS/QGPIO[0] PCS[1:3]/QGPIO[1:3] MISO/QGPIO[4] MOSI/QGPIO[5] SCK/QGPIO[6] TXD[1:2]/QGPO[1:2] Pin Name QSMCM pcs0_ss_b_qgpio0 pcs1_qgpio1 pcs2_qgpio2 pcs3_qgpio3 miso_qgpio4 mosi_qgpio5 sck_qgpio6 txd1_qgpo1 txd2_qgpo2 rxd1_qgpi1 rxd2_qgpi2 eck MIOS mda11 mda12 MDA[11:15] mda13 mda14 mda15 mda27 mda28 MDA[27:31] mda29 mda30 mda31 mpwm0 mpwm1 mpwm2 MPWM[0:3], [16:19] mpwm3 mpwm16 mpwm17 mpwm18 mpwm19 vf0_mpio32b0 VF[0:2]/MPIO32B[0:2] vf1_mpio32b1 vf2_mpio32b2 VFLS[0:1]/MPIO32B[3:4] vfls0_mpio32b3 vfls1_mpio32b4 mda11 mda12 mda13 mda14 mda15 mda27 mda28 mda29 mda30 mda31 mpwm0 mpwm1 mpwm2 mpwm3 mpwm16 mpwm17 mpwm18 mpwm19 vf0_mpio0 vf1_mpio1 vf2_mpio2 vfls0_mpio3 vfls1_mpio4 A17 A18 A19 B17 B18 C17 B20 C18 C19 C20 E17 D18 D19 D20 F17 E18 F18 E19 J19 J20 J17 J18 K18 pcs0_qgp pcs1_qgp pcs2_qgp pcs3_qgp miso_qgp4 mosi_qgp5 sck_qgp6 txd1_qgpo txd2_qgpo rxd1_qgpi rxd2_qgpi eck L18 L17 M18 M17 L19 L20 M20 N18 N20 N17 N19 M19 Abbreviation Ball
RXD[1:2]/QGPI[1:2] ECK
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-61
USERS MANUAL

Pin List Pin Name mpio32b5 mpio32b6 mpio32b7 mpio32b8 mpio32b9 MPIO32B[5:15] mpio32b10 mpio32b11 mpio32b12 mpio32b13 mpio32b14 mpio32b15 TPU_A/TPU_B a_tpuch0 a_tpuch1 a_tpuch2 a_tpuch3 a_tpuch4 a_tpuch5 a_tpuch6 A: TPUCH[0:15] a_tpuch7 a_tpuch8 a_tpuch9 a_tpuch10 a_tpuch11 a_tpuch12 a_tpuch13 a_tpuch14 a_tpuch15 A: T2CLK a_t2clk a_tpuch0 a_tpuch1 a_tpuch2 a_tpuch3 a_tpuch4 a_tpuch5 a_tpuch6 a_tpuch7 a_tpuch8 a_tpuch9 a_tpuch10 a_tpuch11 a_tpuch12 a_tpuch13 a_tpuch14 a_tpuch15 a_t2clk D3 A2 D4 C3 A3 D5 B3 C4 A4 C5 B4 B5 A5 C6 B6 A6 C2 Abbreviation mpio5 mpio6 mpio7 mpio8 mpio9 mpio10 mpio11 mpio12 mpio13 mpio14 mpio15 G17 E20 F19 G18 F20 H17 G19 G20 H20 H19 H18 Ball
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-62
USERS MANUAL

Pin List b_tpuch0 b_tpuch1 b_tpuch2 b_tpuch3 b_tpuch4 b_tpuch5 b_tpuch6 B: TPUCH[0:15] b_tpuch7 b_tpuch8 b_tpuch9 b_tpuch10 b_tpuch11 b_tpuch12 b_tpuch13 b_tpuch14 b_tpuch15 B: T2CLK b_t2clk QADC_A/QADC_B ETRIG[1:2] A: AN0/ANW/PQB0 A: AN1/ANX/PQB1 A: AN2/ANY/PQB2 A: AN3/ANZ/PQB3 etrig1 etrig2 a_an0_anw_pqb0 a_an1_anx_pqb1 a_an2_any_pqb2 a_an3_anz_pqb3 a_an48_pqb4 A: AN[48:51]/PQB[4:7] a_an49_pqb5 a_an50_pqb6 a_an51_pqb7 a_an52_ma0_pqa0 A: AN[52:54]/MA[0:2]/PQA[0:2] a_an53_ma1_pqa1 a_an54_ma2_pqa2 A: AN[55:56]]/PQA[3:4] a_an55_pqa3 a_an56_pqa4 a_an57_pqa5 A: AN[57:59]/PQA[5:7] B: AN0/ANW/PQB0 B: AN1/ANX/PQB1 B: AN2/ANY/PQB2 B: AN3/ANZ/PQB3 a_an58_pqa6 a_an59_pqa7 b_an0_anw_pqb0 b_an1_anx_pqb1 b_an2_any_pqb2 b_an3_anz_pqb3 etrig1 etrig2 aan0_pqb0 aan1_pqb1 aan2_pqb2 aan3_pqb3 aan48_pqb4 aan49_pqb5 aan50_pqb6 aan51_pqb7 aan52_pqa0 aan53_pqa1 aan54_pqa2 aan55_pqa3 aan56_pqa4 aan57_pqa5 aan58_pqa6 aan59_pqa7 ban0_pqb0 ban1_pqb1 ban2_pqb2 ban3_pqb3 C16 B16 A8 D8 C8 B8 A9 B9 D9 C9 A10 B10 A11 D10 C10 B11 D11 C11 A12 B12 A13 A14 Pin Name Abbreviation b_tpuch0 b_tpuch1 b_tpuch2 b_tpuch3 b_tpuch4 b_tpuch5 b_tpuch6 b_tpuch7 b_tpuch8 b_tpuch9 b_tpuch10 b_tpuch11 b_tpuch12 b_tpuch13 b_tpuch14 b_tpuch15 b_t2clk H2 H1 G1 G2 G3 F1 F2 E1 F3 G4 E2 D1 F4 D2 E3 C1 B1 Ball
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-63
USERS MANUAL

Pin List Pin Name b_an48_pqb4 B: AN[48:51]/PQB[4:7] b_an49_pqb5 b_an50_pqb6 b_an51_pqb7 b_an52_ma0_pqa0 B: AN[52:54]/MA[0:2]/PQA[0:2] b_an53_ma1_pqa1 b_an54_ma2_pqa2 B: AN[55:56]/PQA[3:4] b_an55_pqa3 b_an56_pqa4 b_an57_pqa5 b_an58_pqa6 b_an59_pqa7 VRH VRL VDDA VSSA A: CNTX0 B: CNTX0 A: CNRX0 B: CNRX0 EPEE VPP VDDF VSSF vrh vrl vdda vssa TOUCAN_A/TOUCAN_B a_cntx0 b_cntx0 a_cnrx0 b_cnrx0 CMF epee vpp vddf vssf Global Power Supplies VDDL vddl vddl D17, E4, K4, K17, R17. T4, U10, U15 A1, A16, A20, B2, B19, P20, Y1, Y20, W2, W19 T17, U5, D6, D16 T18 J4 J9, J10, J11, J12, K9, K10, K11, K12, L9, L10, L11, L12, M9, M10, M11, M12 epee vpp vddf vssf P18 P17 R18 P19 a_cntx0 b_cntx0 a_cnrx0 b_cnrx0 K19 H4 K20 H3 Abbreviation ban48_pqb4 ban49_pqb5 ban50_pqb6 ban51_pqb7 ban52_pqa0 ban53_pqa1 ban54_pqa2 ban55_pqa3 ban56_pqa4 ban57_pqa5 ban58_pqa6 ban59_pqa7 vrh vrl vdda vssa B13 C12 D12 A15 B14 C13 B15 D13 C14 C15 D14 D15 B7 A7 C7 D7 Ball
B: AN[57:59]/PQA[5:7]
VDDH VDDI KAPWR VDDSRAM
vddh vddi kapwr vddsram
vddh vddi kapwr vddsram
VSS
vss
vss
MPC555
/ MPC556
SIGNAL DESCRIPTIONS
MOTOROLA 2-64
USERS MANUAL
SECTION 3 CENTRAL PROCESSING UNIT

The PowerPC-based RISC processor (RCPU) used in the MPC500 family of microcontrollers integrates five independent execution units: an integer unit (IU), a load/ store unit (LSU), and a branch processing unit (BPU), floating-point unit (FPU) and integer multiplier divider (IMD). The use of simple instructions with rapid execution times yields high efficiency and throughput for MPC555 / MPC556-based systems. Most integer instructions execute in one clock cycle. Instructions can complete out of order for increased performance; however, the processor makes execution appear sequential. This section provides an overview of the RCPU. For a detailed description of this processor, refer to the RCPU Reference Manual (RCPURM/AD). 3.1 RCPU Features Major features of the RCPU include the following: High-performance microprocessor Single clock-cycle execution for many instructions Five independent execution units and two register files Independent LSU for load and store operations BPU featuring static branch prediction A 32-bit IU Fully IEEE 754-compliant FPU for both single- and double-precision operations Thirty-two general-purpose registers (GPRs) for integer operands Thirty-two floating-point registers (FPRs) for single- or double-precision operands Facilities for enhanced system performance Programmable big- and little-endian byte ordering Atomic memory references In-system testability and debugging features High instruction and data throughput Condition register (CR) look-ahead operations performed by BPU Branch-folding capability during execution (zero-cycle branch execution time) Programmable static branch prediction on unresolved conditional branches A pre-fetch queue that can hold up to four instructions, providing look-ahead capability Interlocked pipelines with feed-forwarding that control data dependencies in hardware
CENTRAL PROCESSING UNIT
MOTOROLA 3-1

3.2 RCPU Block Diagram Figure 3-1 provides a block diagram of the RCPU.
RCPU
FPU
FPR HISTORY L-DATA
FPR (32 X 64)
LOAD/STORE FLOATING DATA
LOAD/ STORE INTEGER DATA L-ADDR LOAD/ STORE ADDRESS INSTRUCTION SEQUENCER CONTROL BUS
ALU/ BFU
INSTRUCTION PRE-FETCH QUEUE
IMUL/ IDIV
SO U RCE BU SES
I-DATA
BRANCH PROCESSOR UNIT
GPR (32 X 32) I-ADDR NEXT ADDRESS GENERATION CONTROL REGS

WRI TE BAC K B US 2 SL OT S/ CL OC K
Figure 3-1 RCPU Block Diagram
MPC555
/ MPC556
MOTOROLA 3-2
USERS MANUAL
(4 SLO TS /C LO CK )
GPR HISTORY

3.3 Instruction Sequencer The instruction sequencer provides centralized control over data flow between execution units and register files. The sequencer implements the basic instruction pipeline, fetches instructions from the memory system, issues them to available execution units, and maintains a state history so it can back the machine up in the event of an exception. The instruction sequencer fetches instructions from the burst buffer controller into the instruction pre-fetch queue. The BPU extracts branch instructions from the pre-fetch queue and uses static branch prediction on unresolved conditional branches to allow the instruction unit to fetch instructions from a predicted target instruction stream while a conditional branch is evaluated. The BPU folds out branch instructions for unconditional branches or conditional branches unaffected by instructions in the execution stage. Instructions issued beyond a predicted branch do not complete execution until the branch is resolved, preserving the programming model of sequential execution. If branch prediction is incorrect, the instruction unit flushes all predicted path instructions, and instructions are issued from the correct path.
MPC555
/ MPC556
MOTOROLA 3-3
USERS MANUAL
INSTRUCTION MEMORY SYSTEM

32
INSTRUCTION ADDRESS GENERATOR
INSTRUCTION BUFFER 32
BRANCH CONDITION EVALUATION READ WRITE BUSES CC UNIT INSTRUCTION PRE-FETCH QUEUE
32
EXECUTION UNITS AND REGISTERS FILES
Figure 3-2 Sequencer Data Path 3.4 Independent Execution Units The PowerPC architecture supports independent floating-point, integer, load/store, and branch processing execution units, making it possible to implement advanced features such as look-ahead operations. For example, since branch instructions do not depend on GPRs, branches can often be resolved early, eliminating stalls caused by taken branches. Table 3-1 summarizes the RCPU execution units.
MPC555
/ MPC556
MOTOROLA 3-4
USERS MANUAL

Table 3-1 RCPU Execution Units
Unit Branch processing unit (BPU) Load/store unit (LSU) Description Includes the implementation of all branch instructions Includes implementation of all load and store instructions, whether defined as part of the integer processor or the floating-point processor Includes implementation of all integer instructions except load/store instructions. This module includes the GPRs (including GPR history and scoreboard) and the following subunits: Integer unit (IU) The IMUL-IDIV includes the implementation of the integer multiply and divide instructions. The ALU-BFU includes implementation of all integer logic, add and subtract instructions, and bit field instructions.
Floating-point unit (FPU)
Includes the FPRs (including FPR history and scoreboard) and the implementation of all floating-point instructions except load and store floating-point instructions
The following sections describe the execution units in greater detail. 3.4.1 Branch Processing Unit (BPU) The BPU, located within the instruction sequencer, performs condition register lookahead operations on conditional branches. The BPU looks through the instruction queue for a conditional branch instruction and attempts to resolve it early, achieving the effect of a zero-cycle branch in many cases. The BPU uses a bit in the instruction encoding to predict the direction of the conditional branch. Therefore, when an unresolved conditional branch instruction is encountered, the processor pre-fetches instructions from the predicted target stream until the conditional branch is resolved. The BPU contains an calculation feature to compute branch target addresses and three special-purpose, user-accessible registers: the link register (LR), the count register (CTR), and the condition register (CR). The BPU calculates the return pointer for subroutine calls and saves it into the LR. The LR also contains the branch target address for the branch conditional to link register (bclrx) instruction. The CTR contains the branch target address for the branch conditional to count register (bcctrx) instruction. The contents of the LR and CTR can be copied to or from any GPR. Because the BPU uses dedicated registers rather than general-purpose or floating-point registers, execution of branch instructions is independent from execution of integer instructions. 3.4.2 Integer Unit (IU) The IU executes all integer processor instructions, except the integer storage access instructions, which are implemented by the load/store unit. The IU contains the following subunits: The IMULIDIV unit includes the implementation of the integer multiply and divide instructions. The ALUBFU unit includes the implementation of all integer logic, add and subtract, and bit field instructions.
MPC555
/ MPC556
MOTOROLA 3-5
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The IU also includes the integer exception register (XER) and the general-purpose register file. IMULIDIV and ALUBFU are implemented as separate execution units. The ALU BFU unit can execute one instruction per clock cycle. IMULIDIV instructions require multiple clock cycles to execute. IMULIDIV is pipelined for multiply instructions, so that consecutive multiply instructions can be issued on consecutive clock cycles. Divide instructions are not pipelined; an integer divide instruction preceded or followed by an integer divide or multiply instruction results in a stall in the processor pipeline. Note that since IMULIDIV and ALUBFU are implemented as separate execution units, an integer divide instruction preceded or followed by an ALUBFU instruction does not cause a delay in the pipeline.
3.4.3 Load/Store Unit (LSU) The load/store unit handles all data transfer between the general-purpose register file and the internal load/store bus (L-bus). The load/store unit is implemented as an independent execution unit so that stalls in the memory pipeline do not cause the master instruction pipeline to stall (unless there is a data dependency). The unit is fully pipelined so that memory instructions of any size may be issued on back-to-back cycles. There is a 32-bit wide data path between the load/store unit and the general-purpose register file. Single-word accesses can be achieved with an internal on-chip data RAM, resulting in two clocks latency. Double-word accesses require two clocks, resulting in three clocks latency. Since the L-bus is 32 bits wide, double-word transfers require two bus accesses. The load/store unit performs zero-fill for byte and half-word transfers and sign extension for half-word transfers. Addresses are formed by adding the source one register operand specified by the instruction (or zero) to either a source two register operand or to a 16-bit, immediate value embedded in the instruction. 3.4.4 Floating-Point Unit (FPU) The FPU contains a double-precision multiply array, the floating-point status and control register (FPSCR), and the FPRs. The multiply-add array allows the MPC555 / MPC556 to efficiently implement floating-point operations such as multiply, multiplyadd, and divide. The MPC555 / MPC556 depends on a software envelope to fully implement the IEEE floating-point specification. Overflows, underflows, NaNs, and denormalized numbers cause floating-point assist exceptions that invoke a software routine to deliver (with hardware assistance) the correct IEEE result. To accelerate time-critical operations and make them more deterministic, the MPC555 / MPC556 provides a mode of operation that avoids invoking the software envelope and attempts to deliver results in hardware that are adequate for most applications, if not in strict conformance with IEEE standards. In this mode, denormalized numbers, NaNs, and IEEE invalid operations are treated as legitimate, returning default results rather than causing floating-point assist exceptions.
MPC555
/ MPC556
MOTOROLA 3-6
USERS MANUAL

3.5 Levels of the PowerPC Architecture The PowerPC architecture consists of three layers. Adherence to the PowerPC architecture can be measured in terms of which of the following levels of the architecture are implemented: PowerPC user instruction set architecture (UISA) Defines the base user-level instruction set, user-level registers, data types, floating-point exception model, memory models for a uniprocessor environment, and programming model for a uniprocessor environment. PowerPC virtual environment architecture (VEA) Describes the memory model for a multiprocessor environment, and describes other aspects of virtual environments. Implementations that conform to the VEA also adhere to the UISA, but may not necessarily adhere to the OEA. PowerPC operating environment architecture (OEA) Defines the memory management model, supervisor-level registers, synchronization requirements, and the exception model. Implementations that conform to the OEA also adhere to the UISA and the VEA. 3.6 RCPU Programming Model The PowerPC architecture defines register-to-register operations for most computational instructions. Source operands for these instructions are accessed from the registers or are provided as immediate values embedded in the instruction opcode. The three-register instruction format allows specification of a target register distinct from the two source operands. Load and store instructions transfer data between memory and on-chip registers. PowerPC processors have two levels of privilege: supervisor mode of operation (typically used by the operating environment) and user mode of operation (used by the application software). The programming models incorporate 32 GPRs, special-purpose registers (SPRs), and several miscellaneous registers. Supervisor-level access is provided through the processors exception mechanism. That is, when an exception is taken (either due to an error or problem that needs to be serviced, or deliberately through the use of a trap instruction), the processor begins operating in supervisor mode. The level of access is indicated by the privilege-level (PR) bit in the machine state register (MSR). Figure 3-3 shows the user-level and supervisor-level RCPU programming models and also illustrates the three levels of the PowerPC architecture. The numbers to the left of the SPRs indicate the decimal number that is used in the syntax of the instruction operands to access the register. Note that registers such as the general-purpose registers (GPRs) are accessed through operands that are part of the instructions. Access to registers can be explicit (that is, through the use of specific instructions for that purpose such as move to special-purpose register (mtspr) and move from special-purpose register (mfspr) instructions) or implicitly as the part of the execution of an instruction. Some registers are accessed both explicitly and implicitly.
MPC555
/ MPC556
MOTOROLA 3-7
USERS MANUAL
USER MODEL UISA
SUPERVISOR MODEL OEA
FPR0 FPR1 0 FPR31 0 GPR0 GPR1

Condition Register
Machine State Register MSR 31 Supervisor-Level SPRs 63 See Table 3-2 for list of supervisor-level SPRs.
CR 0 GPR31 0 31
Floating-Point Status and Control Register
31 Development Support SPRs
FPSCR 0 31
See Table 3-3 for list of development-support SPRs.
User-Level SPRs
Integer Exception Register (XER) Link Register (LR) Count Register (CTR)
31
USER MODEL VEA
Time Base Facility (for Reading)
Time Base Lower Read (TBL) Time Base Upper Read (TBU)
Figure 3-3 RCPU Programming Model Table 3-2 lists the MPC555 / MPC556 supervisor-level registers.
MPC555
/ MPC556
MOTOROLA 3-8
USERS MANUAL

Table 3-2 Supervisor-Level SPRs
SPR Number (Decimal) 18 Special-Purpose Register DAE/Source Instruction Service Register (DSISR) See 3.9.2 DAE/Source Instruction Service Register (DSISR) for bit descriptions. Data Address Register (DAR) See 3.9.3 Data Address Register (DAR) for bit descriptions. Decrementer Register (DEC) See 3.9.5 Decrementer Register (DEC) for bit descriptions. Save and Restore Register 0 (SRR0) See 3.9.6 Machine Status Save/Restore Register 0 (SRR0) for bit descriptions. Save and Restore Register 1 (SRR1) See 3.9.7 Machine Status Save/Restore Register 1 (SRR1) for bit descriptions. External Interrupt Enable (EIE)1 See 3.9.10.1 EIE, EID, and NRI Special-Purpose Registers for bit descriptions. External Interrupt Disable (EID)1 See 3.9.10.1 EIE, EID, and NRI Special-Purpose Registers for bit descriptions. Non-Recoverable Interrupt (NRI)1 See 3.9.10.1 EIE, EID, and NRI Special-Purpose Registers for bit descriptions. SPR General 0 (SPRG0) See 3.9.8 General SPRs (SPRG0SPRG3) for bit descriptions. SPRGeneral 1 (SPRG1) See 3.9.8 General SPRs (SPRG0SPRG3) for bit descriptions. SPR General 2 (SPRG2) See 3.9.8 General SPRs (SPRG0SPRG3) for bit descriptions. SPR General 3 (SPRG3) See 3.9.8 General SPRs (SPRG0SPRG3) for bit descriptions. Time Base Lower Write (TBL) See Table 3-14 for bit descriptions. Time Base Upper Write (TBU) See Table 3-14 for bit descriptions. Processor Version Register (PVR) See Table 3-16 for bit descriptions. IMPU Global Region Attribute (MI_GRA)1 See Table 4-7 for bit descriptions. L2U Global Region Attribute (L2U_GRA)1 See Table 11-10 for bit descriptions. BBC Module Configuration Register (BBCMCR)1 See Table 4-8 for bit descriptions.
19
22
26
27
80
81
82
272
273
274
275
284 285 287 528 536 560
MPC555
/ MPC556
MOTOROLA 3-9
USERS MANUAL

Table 3-2 Supervisor-Level SPRs (Continued)
SPR Number (Decimal) 568 784 785 786 787 Special-Purpose Register L2U Module Configuration Register (L2U_MCR)1 See Table 11-7 for bit descriptions. IMPU Region Base Address 0 (MI_RBA0)1 See Table 4-5 for bit descriptions. IMPU Region Base Address 1 (MI_RBA1)1 See Table 4-5 for bit descriptions. IMPU Region Base Address 2 (MI_RBA2)1 See Table 4-5 for bit descriptions. IMPU Region Base Address 3 (MI_RBA3)1 See Table 4-5 for bit descriptions. L2U Region Base Address Register 0 (L2U_RBA0)1 See Table 11-8 for bit descriptions. L2U Region Base Address Register 1 (L2U_RBA1)1 See Table 11-8 for bit descriptions. L2U Region Base Address Register 2 (L2U_RBA2)1 See Table 11-8 for bit descriptions. L2U Region Base Address Register 3 (L2U_RBA3)1 See Table 11-8 for bit descriptions. IMPU Region Attribute Register 0 (MI_RA0)1 See Table 4-6 for bit descriptions. IMPU Region Attribute Register 1 (MI_RA1)1 See Table 4-6 for bit descriptions. IMPU Region Attribute Register 2 (MI_RA2)1 See Table 4-6 for bit descriptions. IMPU Region Attribute Register 3 (MI_RA3)1 See Table 4-6 for bit descriptions. L2U Region Attribute Register 0 (L2U_RA0)1 See Table 11-9 for bit descriptions. L2U Region Attribute Register 1 (L2U_RA1)1 See Table 11-9 for bit descriptions. L2U Region Attribute Register 2 (L2U_RA2)1 See Table 11-9 for bit descriptions. L2U Region Attribute Register 3 (L2U_RA3)1 See Table 11-9 for bit descriptions. Floating-Point Exception Cause Register (FPECR)1 See 3.9.10.2 Floating-Point Exception Cause Register (FPECR) for bit descriptions.
792 793 794 795 816 817 818 819 824 825 826 827
1022
NOTES: 1. Implementation-specific SPR.
Table 3-3 lists the MPC555 / MPC556 SPRs used for development support.
MPC555
/ MPC556
MOTOROLA 3-10
USERS MANUAL

Table 3-3 Development Support SPRs1
SPR Number (Decimal) 144 145 146 147 148 Special-Purpose Register Comparator A Value Register (CMPA) See Table 21-17 for bit descriptions. Comparator B Value Register (CMPB) See Table 21-17 for bit descriptions. Comparator C Value Register (CMPC) See Table 21-17 for bit descriptions. Comparator D Value Register (CMPD) See Table 21-17 for bit descriptions. Exception Cause Register (ECR) See Table 21-27 for bit descriptions. Debug Enable Register (DER) See Table 21-28 for bit descriptions. Breakpoint Counter A Value and Control (COUNTA) See Table 21-25 for bit descriptions. Breakpoint Counter B Value and Control (COUNTB) See Table 21-26 for bit descriptions. Comparator E Value Register (CMPE) See Table 21-18 for bit descriptions. Comparator F Value Register (CMPF) See Table 21-18 for bit descriptions. Comparator G Value Register (CMPG) See Table 21-20 for bit descriptions. Comparator H Value Register (CMPH) See Table 21-20 for bit descriptions. L-bus Support Comparators Control 1 (LCTRL1) See Table 21-23 for bit descriptions. L-bus Support Comparators Control 2 (LCTRL2) See Table 21-24 for bit descriptions. I-bus Support Control Register (ICTRL) See Table 21-21 for bit descriptions. Breakpoint Address Register (BAR) See Table 21-19 for bit descriptions. Development Port Data Register (DPDR) See 21.7.13 for bit descriptions.
149 150 151 152 153 154 155 156 157 158 159 630
NOTES: 1. All development-support SPRs are implementation-specific.
Where not otherwise noted, reserved fields in registers are ignored when written and return zero when read. An exception to this rule is XER[16:23]. These bits are set to the value written to them and return that value when read. 3.7 PowerPC UISA Register Set The PowerPC UISA registers can be accessed by either user- or supervisor-level instructions. The general-purpose registers are accessed through instruction operands.
MPC555
/ MPC556
MOTOROLA 3-11
USERS MANUAL

3.7.1 General-Purpose Registers (GPRs) Integer data is manipulated in the integer units thirty-two 32-bit GPRs, shown below. These registers are accessed as source and destination registers through operands in the instruction syntax. GPRs General-Purpose Registers
MSB 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 GPR0 GPR1 ... ... LSB 31
GPR31 RESET: UNCHANGED
3.7.2 Floating-Point Registers (FPRs) The PowerPC architecture provides thirty-two 64-bit FPRs. These registers are accessed as source and destination registers through operands in floating-point instructions. Each FPR supports the double-precision, floating-point format. Every instruction that interprets the contents of an FPR as a floating-point value uses the double-precision floating-point format for this interpretation. That is, all floating-point numbers are stored in double-precision format. All floating-point arithmetic instructions operate on data located in FPRs and, with the exception of the compare instructions (which update the CR), place the result into an FPR. Information about the status of floating-point operations is placed into the floating-point status and control register (FPSCR) and in some cases, into the CR, after the completion of the operations writeback stage. For information on how the CR is affected by floating-point operations, see 3.7.4 Condition Register (CR). FPRs Floating-Point Registers
MSB 0 FPR0 FPR1 ... ... FPR31 RESET: UNCHANGED LSB 63
3.7.3 Floating-Point Status and Control Register (FPSCR) The FPSCR controls the handling of floating-point exceptions and records status resulting from the floating-point operations. FPSCR[0:23] are status bits. FPSCR[24:31] are control bits.
MPC555
/ MPC556
MOTOROLA 3-12
USERS MANUAL

FPSCR[0:12] and FPSCR[21:23] are floating-point exception condition bits. These bits are sticky, except for the floating-point enabled exception summary (FEX) and floating-point invalid operation exception summary (VX). Once set, sticky bits remain set until they are cleared by an mcrfs, mtfsfi, mtfsf, or mtfsb0 instruction. Table 3-4 summarizes which bits in the FPSCR are sticky status bits, which are normal status bits, and which are control bits. Table 3-4 FPSCR Bit Categories
Bits [0], [3:12], [21:23] [1:2], [13:20] [24:31] Status, sticky Status, not sticky Control Type
FEX and VX are the logical ORs of other FPSCR bits. Therefore these two bits are not listed among the FPSCR bits directly affected by the various instructions. FPSCR Floating-Point Status and Control Register
MSB 0 FX 1 FEX 2 VX 3 OX 4 UX 5 ZX 6 XX 7 VXSNAN 8 VXISI 9 VXIDI 10 11 12 13 FR 14 FI 15 FPRF 0
VXZD VXIMZ VXVC Z
RESET: UNCHANGED
16
17
18
19
20 0
21
22
23
24 VE
25 OE
26 UE
27 ZE
28 XE
29 NI
30 RN
LSB 31
FPRF[1:4]
VXVXVXCVI SOFT SQRT
RESET: UNCHANGED
A listing of FPSCR bit descriptions is shown in Table 3-5.
MPC555
/ MPC556
MOTOROLA 3-13
USERS MANUAL

Table 3-5 FPSCR Bit Descriptions
Bit(s) Name Description Floating-point exception summary. Every floating-point instruction implicitly sets FPSCR[FX] if that instruction causes any of the floating-point exception bits in the FPSCR to change from 0 to 1. The mcrfs instruction implicitly clears FPSCR[FX] if the FPSCR field containing FPSCR[FX] is copied. The mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions can set or clear FPSCR[FX] explicitly. This is a sticky bit. Floating-point enabled exception summary. This bit signals the occurrence of any of the enabled exception conditions. It is the logical OR of all the floating-point exception bits masked with their respective enable bits. The mcrfs instruction implicitly clears FPSCR[FEX] if the result of the logical OR described above becomes zero. The mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions cannot set or clear FPSCR[FEX] explicitly. This is not a sticky bit. Floating-point invalid operation exception summary. This bit signals the occurrence of any invalid operation exception. It is the logical OR of all of the invalid operation exceptions. The mcrfs instruction implicitly clears FPSCR[VX] if the result of the logical OR described above becomes zero. The mtfsf, mtfsfi, mtfsb0, and mtfsb1 instructions cannot set or clear FPSCR[VX] explicitly. This is not a sticky bit. Floating-point overflow exception. This is a sticky bit. Floating-point underflow exception. This is a sticky bit. Floating-point zero divide exception. This is a sticky bit. Floating-point inexact exception. This is a sticky bit. Floating-point invalid operation exception for SNaN. This is a sticky bit. Floating-point invalid operation exception for -. This is a sticky bit. Floating-point invalid operation exception for /. This is a sticky bit. Floating-point invalid operation exception for 0/0. This is a sticky bit. Floating-point invalid operation exception for *0. This is a sticky bit. Floating-point invalid operation exception for invalid compare. This is a sticky bit. Floating-point fraction rounded. The last floating-point instruction that potentially rounded the intermediate result incremented the fraction. This bit is not sticky. Floating-point fraction inexact. The last floating-point instruction that potentially rounded the intermediate result produced an inexact fraction or a disabled exponent overflow. This bit is not sticky. Floating-point result flags. This field is based on the value placed into the target register even if that value is undefined. Refer to Table 3-6 for specific bit descriptions. 15 Floating-point result class descriptor (C). Floating-point instructions other than the compare instructions may set this bit with the FPCC bits, to indicate the class of the result. 1619 Floating-point condition code (FPCC). Floating-point compare instructions always set one of the FPCC bits to one and the other three FPCC bits to zero. Other floating-point instructions may set the FPCC bits with the C bit, to indicate the class of the result. Note that in this case the high-order three bits of the FPCC retain their relational significance indicating that the value is less than, greater than, or equal to zero. 16 Floating-point less than or negative (FL or <) 17 Floating-point greater than or positive (FG or >) 18 Floating-point equal or zero (FE or =) 19 Floating-point unordered or NaN (FU or ?) Reserved
FX
FEX
VX
3 4 5 6 7 8 9 10 11 12 13
OX UX ZX XX VXSNAN VXISI VXIDI VXZDZ VXIMZ VXVC FR
14
FI
[15:19]
FPRF
20
MPC555
/ MPC556
MOTOROLA 3-14
USERS MANUAL

Table 3-5 FPSCR Bit Descriptions (Continued)
Bit(s) Name Description Floating-point invalid operation exception for software request. This bit can be altered only by the mcrfs, mtfsfi, mtfsf, mtfsb0, or mtfsb1 instructions. The purpose of VXSOFT is to allow software to cause an invalid operation condition for a condition that is not necessarily associated with the execution of a floating-point instruction. For example, it might be set by a program that computes a square root if the source operand is negative. This is a sticky bit. Floating-point invalid operation exception for invalid square root. This is a sticky bit. This guarantees that software can simulate fsqrt and frsqrte, and to provide a consistent interface to handle exceptions caused by square-root operations. Floating-point invalid operation exception for invalid integer convert. This is a sticky bit. Floating-point invalid operation exception enable. Floating-point overflow exception enable. Floating-point underflow exception enable. This bit should not be used to determine whether denormalization should be performed on floating-point stores. Floating-point zero divide exception enable. Floating-point inexact exception enable. Non-IEEE mode bit. Floating-point rounding control. 00Round to nearest 01Round toward zero 10Round toward +infinity 11Round toward -infinity
21
VXSOFT
22 23 24 25
VXSQRT VXCVI VE OE UE ZE XE NI
26 27 28 29
3031
RN
Table 3-6 illustrates the floating-point result flags that correspond to FPSCR[15:19]. Table 3-6 Floating-Point Result Flags in FPSCR
Result Flags (Bits 1519) C<>=? 10001 01001 01000 11000 10010 00010 10100 00100 00101 Result value class Quiet NaN Infinity Normalized number Denormalized number Zero + Zero + Denormalized number + Normalized number + Infinity
3.7.4 Condition Register (CR) The condition register (CR) is a 32-bit register that reflects the result of certain operations and provides a mechanism for testing and branching. The bits in the CR are grouped into eight 4-bit fields, CR0 to CR7.
MPC555
/ MPC556
MOTOROLA 3-15
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CR Condition Register
MSB 1 0 CR0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CR3 CR4 CR5 CR6 CR7 LSB 31
CR1
CR2
RESET: UNCHANGED
The CR fields can be set in the following ways: Specified fields of the CR can be set by a move instruction (mtcrf) to the CR from a GPR. Specified fields of the CR can be moved from one CRx field to another with the mcrf instruction. A specified field of the CR can be set by a move instruction (mcrxr) to the CR from the XER. Condition register logical instructions can be used to perform logical operations on specified bits in the condition register. CR0 can be the implicit result of an integer operation. A specified CR field can be the explicit result of an integer compare instruction. Instructions are provided to test individual CR bits. 3.7.4.1 Condition Register CR0 Field Definition In most integer instructions, when the CR is set to reflect the result of the operation (that is, when Rc = 1), and for addic., andi., and andis., the first three bits of CR0 are set by an algebraic comparison of the result to zero; the fourth bit of CR0 is copied from XER[SO]. For integer instructions, CR[0:3] are set to reflect the result as a signed quantity. The result as an unsigned quantity or a bit string can be deduced from the EQ bit. The CR0 bits are interpreted as shown in Table 3-7. If any portion of the result (the 32bit value placed into the destination register) is undefined, the value placed in the first three bits of CR0 is undefined. Table 3-7 Bit Descriptions for CR0 Field of CR
CR0 Bit 0 1 2 3 Description Negative (LT) This bit is set when the result is negative. Positive (GT) This bit is set when the result is positive (and not zero). Zero (EQ) This bit is set when the result is zero. Summary overflow (SO) This is a copy of the final state of XER[SO] at the completion of the instruction.
3.7.4.2 Condition Register CR1 Field Definition In all floating-point instructions when the CR is set to reflect the result of the operation (that is, when Rc = 1), the CR1 field (bits 4 to 7 of the CR) is copied from FPSCR[0:3] to indicate the floating-point exception status. For more information about the FPSCR, see 3.7.3 Floating-Point Status and Control Register (FPSCR). The bit descriptions for the CR1 field are shown in Table 3-8.
MPC555
/ MPC556
MOTOROLA 3-16
USERS MANUAL

Table 3-8 Bit Descriptions for CR1 Field of CR
CR1 Bit 0 1 2 3 Description Floating-point exception (FX) This is a copy of the final state of FPSCR[FX] at the completion of the instruction. Floating-point enabled exception (FEX) This is a copy of the final state of FPSCR[FEX] at the completion of the instruction. Floating-point invalid exception (VX) This is a copy of the final state of FPSCR[VX] at the completion of the instruction. Floating-point overflow exception (OX) This is a copy of the final state of FPSCR[OX] at the completion of the instruction.
3.7.4.3 Condition Register CRn Field Compare Instruction When a specified CR field is set by a compare instruction, the bits of the specified field are interpreted as shown in Table 3-9. A condition register field can also be accessed by the mfcr, mcrf, and mtcrf instructions. Table 3-9 CRn Field Bit Descriptions for Compare Instructions
CRn Bit1 Less than, floating-point less than (LT, FL). 0 For integer compare instructions, (rA) < SIMM, UIMM, or (rB) (algebraic comparison) or (rA) SIMM, UIMM, or (rB) (logical comparison). For floating-point compare instructions, (frA) < (frB). Greater than, floating-point greater than (GT, FG). 1 For integer compare instructions, (rA) > SIMM, UIMM, or (rB) (algebraic comparison) or (rA) SIMM, UIMM, or (rB) (logical comparison). For floating-point compare instructions, (frA) > (frB). Equal, floating-point equal (EQ, FE). 2 For integer compare instructions, (rA) = SIMM, UIMM, or (rB). For floating-point compare instructions, (frA) = (frB). Summary overflow, floating-point unordered (SO, FU). 3 For integer compare instructions, this is a copy of the final state of XER[SO] at the completion of the instruction. For floating-point compare instructions, one or both of (frA) and (frB) is not a number (NaN). NOTES: 1. Here, the bit indicates the bit number in any one of the four-bit subfields, CR0CR7 Description
3.7.5 Integer Exception Register (XER) The integer exception register (XER) is a user-level, 32-bit register. XER Integer Exception Register
MSB 1 0 SO 2 3 4 5 6 7 8 9
SPR 1
LSB 31
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Reserved RESET: BYTES
OV
CA
MPC555
/ MPC556
MOTOROLA 3-17
USERS MANUAL

The bit definitions for XER, shown in Table 3-10, are based on the operation of an instruction considered as a whole, not on intermediate results. For example, the result of the Subtract from Carrying (subfcx) instruction is specified as the sum of three values. This instruction sets bits in the XER based on the entire operation, not on an intermediate sum. In most cases, reserved fields in registers are ignored when written to and return zero when read. However, XER[16:23] are set to the value written to them and return that value when read.
Table 3-10 Integer Exception Register Bit Definitions

Bit(s) Name SO Description Summary Overflow (SO) The summary overflow bit is set whenever an instruction sets the overflow bit (OV) to indicate overflow and remains set until software clears it. It is not altered by compare instructions or other instructions that cannot overflow. Overflow (OV) The overflow bit is set to indicate that an overflow has occurred during execution of an instruction. Integer and subtract instructions having OE=1 set OV if the carry out of bit 0 is not equal to the carry out of bit 1, and clear it otherwise. The OV bit is not altered by compare instructions or other instructions that cannot overflow. Carry (CA) In general, the carry bit is set to indicate that a carry out of bit 0 occurred during execution of an instruction. Add carrying, subtract from carrying, add extended, and subtract from extended instructions set CA to one if there is a carry out of bit 0, and clear it otherwise. The CA bit is not altered by compare instructions or other instructions that cannot carry, except that shift right algebraic instructions set the CA bit to indicate whether any 1 bits have been shifted out of a negative quantity. Reserved This field specifies the number of bytes to be transferred by a Load String Word Indexed (lswx) or Store String Word Indexed (stswx) instruction.
OV
CA
3:24 25:31
BYTES
3.7.6 Link Register (LR) The 32-bit link register supplies the branch target address for the Branch Conditional to Link Register (bclrx) instruction, and can be used to hold the logical address of the instruction that follows a branch and link instruction. Note that although the two least-significant bits can accept any values written to them, they are ignored when the LR is used as an address. Both conditional and unconditional branch instructions include the option of placing the effective address of the instruction following the branch instruction in the LR. This is done regardless of whether the branch is taken. LR Link Register
MSB 1 0 2 3 4 5 6 7 8 9
SPR 8
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Branch Address RESET: UNCHANGED LSB 31
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/ MPC556
MOTOROLA 3-18
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3.7.7 Count Register (CTR) The count register (CTR) is a 32-bit register for holding a loop count that can be decremented during execution of branch instructions that contain an appropriately coded BO field. If the value in CTR is 0 before being decremented, it is 1 afterward. The count register provides the branch target address for the Branch Conditional to Count Register (bcctrx) instruction. CTR Count Register
MSB 1 0 2 3 4 5 6 7 8 9
SPR 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Loop Count RESET: UNCHANGED LSB 31
3.8 PowerPC VEA Register Set Time Base The PowerPC virtual environment architecture (VEA) defines registers in addition to those in the UISA register set. The PowerPC VEA register set can be accessed by all software with either user- or supervisor-level privileges. The PowerPC VEA includes the time base facility (TB), a 64-bit structure that contains a 64-bit unsigned integer that is incremented periodically. The frequency at which the counter is updated is implementation-dependent. For details on the time base clock in the MPC555 / MPC556, refer to 6.7 MPC555 / MPC556 Time Base (TB), 8.6 MPC555 / MPC556 Internal Clock Signals, and 8.12.1 System Clock Control Register (SCCR). The TB consists of two 32-bit registers: time base upper (TBU) and time base lower (TBL). In the context of the VEA, user-level applications are permitted read-only access to the TB. The OEA defines supervisor-level access to the TB for writing values to the TB. Different SPR encodings are provided for reading and writing the time base. TB Time Base (Read Only)
0 TBU RESET: UNCHANGED 31 32 TBL
SPR 268, 269

63
Table 3-11 Time Base Field Definitions (Read Only)

Bits 0-31 32-63 Name TBU TBL Description Time Base (Upper) The high-order 32 bits of the time base Time Base (Lower) The low-order 32 bits of the time base
In 32-bit PowerPC implementations such as the RCPU, it is not possible to read the entire 64-bit time base in a single instruction. The mftb simplified mnemonic copies the lower half of the time base register (TBL) to a GPR, and the mftbu simplified mnemonic copies the upper half of the time base (TBU) to a GPR.
MPC555
/ MPC556
MOTOROLA 3-19
USERS MANUAL

3.9 PowerPC OEA Register Set The PowerPC operating environment architecture (OEA) includes a number of SPRs and other registers that are accessible only by supervisor-level instructions. Some SPRs are RCPU-specific; some RCPU SPRs may not be implemented in other PowerPC processors, or may not be implemented in the same way. 3.9.1 Machine State Register (MSR) The machine state register is a 32-bit register that defines the state of the processor. When an exception occurs, the current contents of the MSR are loaded into SRR1, and the MSR is updated to reflect the exception-processing machine state. The MSR can also be modified by the mtmsr, sc, and rfi instructions. It can be read by the mfmsr instruction.
MSR Machine State Register

MSB 0 1 2 3 4 5 6 RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 8 9 10 11 12 13 POW 14 0 15 ILE
16
17
18
19
20
21
22
23
24
25
26
27
28
29 DCMPEN
2
30
LSB 31 LE
EE
PR
FP
ME
FE0
SE
BE
FE1
IP
IR
DR
RESERVED
RI
RESET: 0 0 0 U 0 0 0 0 0 ID11 0 0 0 0 0 0
NOTES: 1. Reset value of this bit depends on the value of the internal data bus line during reset. 2. This bit is only available on the MPC556.
Table 3-12 shows the bit definitions for the MSR.
MPC555
/ MPC556
MOTOROLA 3-20
USERS MANUAL

Table 3-12 Machine State Register Bit Descriptions
Bit(s) 0:12 13 14 Name POW Reserved Power management enable 0 = Power management disabled (normal operation mode) 1 = Power management enabled (reduced power mode) Reserved Exception little-endian mode. When an exception occurs, this bit is copied into MSR[LE] to select the endian mode for the context established by the exception. 0 = Processor runs in big-endian mode during exception processing. 1 = Processor runs in little-endian mode during exception processing. External interrupt enable. Interrupts should only be negated while the EE bit is disabled (0). Software should disable interrupts in the CPU core prior to masking or disabling any interrupt which might be currently pending at the CPU core. For external interrupts, it is recommended that the edge triggered interrupt scheme be used. 0 = The processor delays recognition of external interrupts and decrementer exception conditions. 1 = The processor is enabled to take an external interrupt or the decrementer exception. Privilege level 0 = The processor can execute both user- and supervisor-level instructions. 1 = The processor can only execute user-level instructions. Floating-point available 0 = The processor prevents dispatch of floating-point instructions, including floating-point loads, stores and moves. Floating-point enabled program exceptions can still occur and the FPRs can still be accessed. 1 = The processor can execute floating-point instructions, and can take floating-point enabled exception type program exceptions. Machine check enable 0 = Machine check exceptions are disabled. 1 = Machine check exceptions are enabled. Floating-point exception mode 0 (See Table 3-13.) Single-step trace enable 0 = The processor executes instructions normally. 1 = The processor generates a single-step trace exception upon the successful execution of the next instruction. When this bit is set, the processor dispatches instructions in strict program order. Successful execution means the instruction caused no other exception. Single-step tracing may not be present on all implementations. Branch trace enable 0 = No trace exception occurs when a branch instruction is completed 1 = Trace exception occurs when a branch instruction is completed Floating-point exception mode 1 (See Table 3-13.) Reserved Exception prefix. The setting of this bit specifies the location of the exception vector table. 0 = Exception vector table starts at the physical address 0x0000 0000. 1 = Exception vector table starts at the physical address 0xFFF0 0000. Instruction relocation. 0 = Instruction address translation is off, the BBC IMPU does not check for address permission attributes. 1 = Instruction address translation is on, the BBC IMPU checks for address permission attributes. Data relocation 0 = Data address translation is off, the L2U DMPU does not check for address permission attributes. 1 = Data address translation is on, the L2U DMPU checks for address permission attributes. Description
15
ILE
16
EE
17
PR
18
FP
19 20
ME FE0
21
SE
22 23 24 25
BE FE1 IP
26
IR
27
DR
MPC555
/ MPC556
MOTOROLA 3-21
USERS MANUAL

Table 3-12 Machine State Register Bit Descriptions (Continued)
Bit(s) 28 29 Name DCMPEN1 RI Reserved Decompression On/Off 0 = RCPU Normal Operation 1 = RCPU is running in Compressed mode Recoverable exception (for machine check and non-maskable breakpoint exceptions) 0 = Machine state is not recoverable. 1 = Machine state is recoverable. Little-endian mode 0 = Processor operates in big-endian mode during normal processing. 1 = Processor operates in little-endian mode during normal processing. Description
30
31
LE
NOTES: 1. This bit is only available on the MPC556.
The floating-point exception mode bits are interpreted as shown in Table
3-13.
Table 3-13 Floating-Point Exception Mode Bits

FE[0:1] 00 Mode Ignore exceptions mode Floating-point exceptions do not cause the floating-point assist error handler to be invoked. Floating-point precise mode The system floating-point assist error handler is invoked precisely at the instruction that caused the enabled exception.
01, 10, 11
3.9.2 DAE/Source Instruction Service Register (DSISR) The 32-bit DSISR identifies the cause of data access and alignment exceptions. DSISR DAE/Source Instruction Service Register
MSB 1 0 2 3 4 5 6 7 8 9
SPR 18
LSB 31
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DSISR RESET: UNCHANGED
3.9.3 Data Address Register (DAR) After an alignment exception, the DAR is set to the effective address of a load or store element. DAR Data Address Register
MSB 1 0 2 3 4 5 6 7 8 9
SPR 19
LSB 31
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Data Address RESET: UNCHANGED
MPC555
/ MPC556
MOTOROLA 3-22
USERS MANUAL

3.9.4 Time Base Facility (TB) OEA As described in 3.8 PowerPC VEA Register Set Time Base, the time base (TB) provides a 64-bit incrementing counter. The VEA defines user-level, read-only access to the TB. Writing to the TB is reserved for supervisor-level applications such as operating systems and bootstrap routines. The OEA defines supervisor-level, write access to the TB. TB Time Base (Write Only)
0 TBU RESET: UNCHANGED 31 32 TBL
SPR 284, 285

63
Table 3-14 Time Base Field Definitions (Write Only)

Bits 0:31 32:63 Name TBU TBL Description Time Base (Upper) The high-order 32 bits of the time base Time Base (Lower) The low-order 32 bits of the time base
The TB can be written to at the supervisor privilege level only. The mttbl and mttbu simplified mnemonics write the lower and upper halves of the TB, respectively. The mtspr, mttbl, and mttbu instructions treat TBL and TBU as separate 32-bit registers; setting one leaves the other unchanged. It is not possible to write the entire 64-bit time base in a single instruction. For information about reading the time base, refer to 3.8 PowerPC VEA Register Set Time Base. 3.9.5 Decrementer Register (DEC) The decrementer (DEC, SPR 22) is a 32-bit decrementing counter defined by the MPC555 / MPC556 to provide a decrementer exception after a programmable delay. The DEC satisfies the following requirements: Loading a GPR from the DEC has no effect on the DEC. Storing a GPR to the DEC replaces the value in the DEC with the value in the GPR. Whenever bit 0 of the DEC changes from zero to one, a decrementer exception request (unless masked) is signaled. Multiple DEC exception requests may be received before the first exception occurs; however, any additional requests are canceled when the exception occurs for the first request. If the DEC is altered by software and the content of bit 0 is changed from zero to one, an exception request is signaled. PORESET resets and stops the decrementer, HRESET/SRESET do not. The decrementer frequency is based on a subdivision of the processor clock. A bit in the system clock control register (SCCR) in the SIU determines the clock source of both the decrementer and the time base. For details on the decrementer and time base
MPC555
/ MPC556
MOTOROLA 3-23
USERS MANUAL

clock in the MPC555 / MPC556, refer to 6.6 MPC555 / MPC556 Decrementer, 8.6 MPC555 / MPC556 Internal Clock Signals, and 8.12.1 System Clock Control Register (SCCR). The DEC does not run after power-up and must be enabled by setting the TBE bit in the TBSCR register, see Table 6-16. Power-on reset stops its counting and clears the register. A decrementer exception may be signaled to software prior to initialization. DEC Decrementer Register
MSB 1 0 2 3 4 5 6 7 8 9
SPR 22
LSB 31
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Decrementing Counter RESET: UNCHANGED
3.9.6 Machine Status Save/Restore Register 0 (SRR0) The machine status save/restore register 0 (SRR0) is a 32-bit register that identifies where instruction execution should resume when an rfi instruction is executed following an exception. It also holds the effective address of the instruction that follows the System Call (sc) instruction. When an exception occurs, SRR0 is set to point to an instruction such that all prior instructions have completed execution and no subsequent instruction has begun execution. The instruction addressed by SRR0 may not have completed execution, depending on the exception type. SRR0 addresses either the instruction causing the exception or the immediately following instruction. The instruction addressed can be determined from the exception type and status bits. SRR0 Machine Status Save/Restore Register 0
MSB 1 0 2 3 4 5 6 7 8 9
SPR 26
LSB 31
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SRR0 RESET: UNDEFINED
When an exception occurs, SRR0 is set to point to an instruction such that all prior instructions have completed execution and no subsequent instruction has begun execution. The instruction addressed by SRR0 may not have completed execution, depending on the exception type. SRR0 addresses either the instruction causing the exception or the immediately following instruction. The instruction addressed can be determined from the exception type and status bits. 3.9.7 Machine Status Save/Restore Register 1 (SRR1) SRR1 is a 32-bit register used to save machine status on exceptions and to restore machine status when an rfi instruction is executed.
MPC555
/ MPC556
MOTOROLA 3-24
USERS MANUAL

SRR1 Machine Status Save/Restore Register 1
MSB 1 0 2 3 4 5 6 7 8 9
SPR 27
LSB 31
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SRR1 RESET: UNDEFINED
In general, when an exception occurs, SRR1[0:15] are loaded with exception-specific information, and MSR[16:31] are placed into SRR1[16:31]. 3.9.8 General SPRs (SPRG0SPRG3) SPRG0SPRG3 are 32-bit registers provided for general operating system use, such as performing a fast-state save and for supporting multiprocessor implementations. SPRG0SPRG3 are shown below. SPRG0SPRG3 General Special-Purpose Registers 03
MSB 1 0 2 3 4 5 6 7 8 9
SPR 272 SPR 275

LSB 31
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SPRG0 SPRG1 SPRG2 SPRG3 RESET: UNCHANGED
Uses for SPRG0SPRG3 are shown in Table 3-15. Table 3-15 Uses of SPRG0SPRG3
Register SPRG0 SPRG1 SPRG2 SPRG3 Description Software may load a unique physical address in this register to identify an area of memory reserved for use by the exception handler. This area must be unique for each processor in the system. This register may be used as a scratch register by the exception handler to save the content of a GPR. That GPR then can be loaded from SPRG0 and used as a base register to save other GPRs to memory. This register may be used by the operating system as needed. This register may be used by the operating system as needed.
3.9.9 Processor Version Register (PVR) The PVR is a 32-bit, read-only register that identifies the version and revision level of the PowerPC processor. The contents of the PVR can be copied to a GPR by the mfspr instruction. Read access to the PVR is available in supervisor mode only; write access is not provided. PVR Processor Version Register
MSB 1 0 2 3 4 5 6 7 8 9
SPR 287
LSB 31
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 REVISION RESET: UNCHANGED
VERSION
MPC555
/ MPC556
MOTOROLA 3-25
USERS MANUAL

Table 3-16 Processor Version Register Bit Descriptions
Bit(s) 0:15 16:31 Name VERSION REVISION Description A 16-bit number that identifies the version of the processor and of the PowerPC architecture. MPC555 / MPC556 value is 0x0002. A 16-bit number that distinguishes between various releases of a particular version. The MPC555 / MPC556 value is 0x0020.
3.9.10 Implementation-Specific SPRs The MPC555 / MPC556 includes several implementation-specific SPRs that are not defined by the PowerPC architecture. These registers can be accessed by supervisorlevel instructions only. These registers are listed in Table 3-2 and Table 3-3.
3.9.10.1 EIE, EID, and NRI Special-Purpose Registers The RCPU includes three implementation-specific SPRs to facilitate the software manipulation of the MSR[RI] and MSR[EE] bits. Issuing the mtspr instruction with one of these registers as an operand causes the RI and EE bits to be set or cleared as shown in Table 3-17. A read (mfspr) of any of these locations is treated as an unimplemented instruction, resulting in a software emulation exception. Table 3-17 EIE, EID, AND NRI Registers
SPR Number (Decimal) 80 81 82 Mnemonic EIE EID NRI MSR[EE] 1 0 0 MSR[RI] 1 1 0
3.9.10.2 Floating-Point Exception Cause Register (FPECR) The FPECR is a 32-bit supervisor-level internal status and control register used by the floating-point assist firmware envelope. It contains four status bits indicating whether the result of the operation is tiny and whether any of three source operands are denormalized. In addition, it contains one control bit to enable or disable SIE mode. This register must not be accessed by user code.
MPC555
/ MPC556
MOTOROLA 3-26
USERS MANUAL

FPECR Floating-Point Exception Cause Register
MSB 0 SIE RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 RESERVED 9 10 11 12 13
SPR 1022
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28 DNC
29 DNB
30 DNA
LSB 31 TR
RESERVED RESET:
A listing of FPECR bit descriptions is shown in Table 3-18. Table 3-18 FPECR Bit Descriptions
Bit(s) 0 [1:27] 28 Name SIE DNC SIE mode control bit 0 = Disable SIE mode 1 = Enable SIE mode Reserved Source operand C denormalized status bit 0 = Source operand C is not denormalized 1 = Source operand C is denormalized Source operand B denormalized status bit 0 = Source operand B is not denormalized 1 = Source operand B is denormalized Source operand A denormalized status bit 0 = Source operand A is not denormalized 1 = Source operand A is denormalized Floating-point tiny result 0 = Floating-point result is not tiny 1 = Floating-point result is tiny Description
29
DNB
30
DNA
31
TR
NOTE Software must insert a sync instruction before reading the FPECR. 3.9.10.3 Additional Implementation-Specific Registers Refer to the following sections for details on additional implementation-specific registers in the MPC555 / MPC556: 4.6 Burst Buffer Programming Model 6.13.1.2 Internal Memory Map Register 11.8 L2U Programming Model SECTION 21 DEVELOPMENT SUPPORT
MPC555
/ MPC556
MOTOROLA 3-27
USERS MANUAL

3.10 Instruction Set All PowerPC instructions are encoded as single words (32 bits). Instruction formats are consistent among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. This fixed instruction length and consistent format greatly simplifies instruction pipelining. The PowerPC instructions are divided into the following categories: Integer instructions include computational and logical instructions. Integer arithmetic instructions Integer compare instructions Integer logical instructions Integer rotate and shift instructions Floating-point instructions include floating-point computational instructions, as well as instructions that affect the floating-point status and control register (FPSCR). Floating-point arithmetic instructions Floating-point multiply/add instructions Floating-point rounding and conversion instructions Floating-point compare instructions Floating-point status and control instructions Load/store instructions include integer and floating-point load and store instructions. Integer load and store instructions Integer load and store multiple instructions Floating-point load and store Primitives used to construct atomic memory operations (lwarx and stwcx. instructions) Flow control instructions include branching instructions, condition register logical instructions, trap instructions, and other instructions that affect the instruction flow. Branch and trap instructions Condition register logical instructions Processor control instructions are used for synchronizing memory accesses. Move to/from SPR instructions Move to/from MSR Synchronize Instruction synchronize Note that this grouping of the instructions does not indicate which execution unit executes a particular instruction or group of instructions. Integer instructions operate on byte, half-word, and word operands. Floating-point instructions operate on single-precision (one word) and double-precision (one double word) floating-point operands. The PowerPC architecture uses instructions that are four bytes long and word-aligned. It provides for byte, half-word, and word operand loads and stores between memory and a set of 32 GPRs.
MPC555
/ MPC556
MOTOROLA 3-28
USERS MANUAL

Computational instructions do not modify memory. To use a memory operand in a computation and then modify the same or another memory location, the memory contents must be loaded into a register, modified, and then written back to the target location with distinct instructions. PowerPC processors follow the program flow when they are in the normal execution state. However, the flow of instructions can be interrupted directly by the execution of an instruction or by an asynchronous event. Either kind of exception may cause one of several components of the system software to be invoked. 3.10.1 Instruction Set Summary Table 3-19 provides a summary of RCPU instructions. Refer to the RCPU Reference Manual (RCPURM/AD) for a detailed description of the instruction set.
Table 3-19 Instruction Set Summary

Mnemonic add (add. addo addo.) addc (addc. addco addco.) adde (adde. addeo addeo.) addi addic addic. addis addme (addme. addmeo addmeo.) addze (addze. addzeo addzeo.) and (and.) andc (andc.) andi. andis. b (ba bl bla) bc (bca bcl bcla) bcctr (bcctrl) bclr (bclrl) cmp cmpi cmpl cmpli cntlzw (cntlzw.) crand crandc creqv crnand crnor cror Operand Syntax rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,SIMM rD,rA,SIMM rD,rA,SIMM rD,rA,SIMM rD,rA rD,rA rA,rS,rB rA,rS,rB rA,rS,UIMM rA,rS,UIMM target_addr BO,BI,target_addr BO,BI BO,BI crfD,L,rA,rB crfD,L,rA,SIMM crfD,L,rA,rB crfD,L,rA,UIMM rA,rS crbD,crbA,crbB crbD,crbA, crbB crbD,crbA, crbB crbD,crbA,crbB crbD,crbA,crbB crbD,crbA,crbB Add Add Carrying Add Extended Add Immediate Add Immediate Carrying Add Immediate Carrying and Record Add Immediate Shifted Add to Minus One Extended Add to Zero Extended AND AND with Complement AND Immediate AND Immediate Shifted Branch Branch Conditional Branch Conditional to Count Register Branch Conditional to Link Register Compare Compare Immediate Compare Logical Compare Logical Immediate Count Leading Zeros Word Condition Register AND Condition Register AND with Complement Condition Register Equivalent Condition Register NAND Condition Register NOR Condition Register OR Name
MPC555
/ MPC556
MOTOROLA 3-29
USERS MANUAL

Table 3-19 Instruction Set Summary (Continued)
Mnemonic crorc crxor divw (divw. divwo divwo.) divwu divwu. divwuo divwuo. eieio eqv (eqv.) extsb (extsb.) extsh (extsh.) fabs (fabs.) fadd (fadd.) fadds (fadds.) fcmpo fcmpu fctiw (fctiw.) fctiwz (fctiwz.) fdiv (fdiv.) fdivs (fdivs.) fmadd (fmadd.) fmadds (fmadds.) fmr (fmr.) fmsub (fmsub.) fmsubs (fmsubs.) fmul (fmul.) fmuls (fmuls.) fnabs (fnabs.) fneg (fneg.) fnmadd (fnmadd.) fnmadds (fnmadds.) fnmsub (fnmsub.) fnmsubs (fnmsubs.) frsp (frsp.) fsub (fsub.) fsubs (fsubs.) isync lbz lbzu lbzux lbzx lfd lfdu rD,d(rA) rD,d(rA) rD,rA,rB rD,rA,rB frD,d(rA) frD,d(rA) rA,rS,rB rA,rS rA,rS frD,frB frD,frA,frB frD,frA,frB crfD,frA,frB crfD,frA,frB frD,frB frD,frB frD,frA,frB frD,frA,frB frD,frA,frC,frB frD,frA,frC,frB frD,frB frD,frA,frC,frB frD,frA,frC,frB frD,frA,frC frD,frA,frC frD,frB frD,frB frD,frA,frC,frB frD,frA,frC,frB frD,frA,frC,frB frD,frA,frC,frB frD,frB frD,frA,frB frD,frA,frB Operand Syntax crbD,crbA, crbB crbD,crbA,crbB rD,rA,rB rD,rA,rB Name Condition Register OR with Complement Condition Register XOR Divide Word Divide Word Unsigned Enforce In-Order Execution of I/O Equivalent Extend Sign Byte Extend Sign Half Word Floating Absolute Value Floating Add (Double-Precision) Floating Add Single Floating Compare Ordered Floating Compare Unordered Floating Convert to Integer Word Floating Convert to Integer Word with Round toward Zero Floating Divide (Double-Precision) Floating Divide Single Floating Multiply-Add (Double-Precision) Floating Multiply-Add Single Floating Move Register Floating Multiply-Subtract (Double-Precision) Floating Multiply-Subtract Single Floating Multiply (Double-Precision) Floating Multiply Single Floating Negative Absolute Value Floating Negate Floating Negative Multiply-Add (Double-Precision) Floating Negative Multiply-Add Single Floating Negative Multiply-Subtract (DoublePrecision) Floating Negative Multiply-Subtract Single Floating Round to Single Floating Subtract (Double-Precision) Floating Subtract Single Instruction Synchronize Load Byte and Zero Load Byte and Zero with Update Load Byte and Zero with Update Indexed Load Byte and Zero Indexed Load Floating-Point Double Load Floating-Point Double with Update
MPC555
/ MPC556
MOTOROLA 3-30
USERS MANUAL

Mnemonic lfdux lfdx lfs lfsu lfsux lfsx lha lhau lhaux lhax lhbrx lhz lhzu lhzux lhzx lmw lswi lswx lwarx lwbrx lwz lwzu lwzux lwzx mcrf mcrfs mcrxr mfcr mffs (mffs.) mfmsr mfspr mftb mtcrf mtfsb0 (mtfsb0.) mtfsb1 (mtfsb1.) mtfsf (mtfsf.) mtfsfi (mtfsfi.) mtmsr mtspr mulhw (mulhw.) mulhwu (mulhwu.) Operand Syntax frD,rA,rB frD,rA,rB frD,d(rA) frD,d(rA) frD,rA,rB frD,rA,rB rD,d(rA) rD,d(rA) rD,rA,rB rD,rA,rB rD,rA,rB rD,d(rA) rD,d(rA) rD,rA,rB rD,rA,rB rD,d(rA) rD,rA,NB rD,rA,rB rD,rA,rB rD,rA,rB rD,d(rA) rD,d(rA) rD,rA,rB rD,rA,rB crfD,crfS crfD,crfS crfD rD frD rD rD,SPR rD, TBR CRM,rS crbD crbD FM,frB crfD,IMM rS SPR,rS rD,rA,rB rD,rA,rB Name Load Floating-Point Double with Update Indexed Load Floating-Point Double Indexed Load Floating-Point Single Load Floating-Point Single with Update Load Floating-Point Single with Update Indexed Load Floating-Point Single Indexed Load Half-Word Algebraic Load Half-Word Algebraic with Update Load Half-Word Algebraic with Update Indexed Load Half-Word Algebraic Indexed Load Half-Word Byte-Reverse Indexed Load Half-Word and Zero Load Half-Word and Zero with Update Load Hal-Word and Zero with Update Indexed Load Half-Word and Zero Indexed Load Multiple Word Load String Word Immediate Load String Word Indexed Load Word and Reserve Indexed Load Word Byte-Reverse Indexed Load Word and Zero Load Word and Zero with Update Load Word and Zero with Update Indexed Load Word and Zero Indexed Move Condition Register Field Move to Condition Register from FPSCR Move to Condition Register from XER Move from Condition Register Move from FPSCR Move from Machine State Register Move from Special Purpose Register Move from Time Base Move to Condition Register Fields Move to FPSCR Bit 0 Move to FPSCR Bit 1 Move to FPSCR Fields Move to FPSCR Field Immediate Move to Machine State Register Move to Special Purpose Register Multiply High Word Multiply High Word Unsigned
MPC555
/ MPC556
MOTOROLA 3-31
USERS MANUAL

Mnemonic mulli mullw (mullw. mullwo mullwo.) nand (nand.) neg (neg. nego nego.) nor (nor.) or (or.) orc ori oris rfi rlwimi (rlwimi.) rlwinm (rlwinm.) rlwnm (rlwnm.) sc slw (slw.) sraw (sraw.) srawi (srawi.) srw (srw.) stb stbu stbux stbx stfd stfdu stfdux stfdx stfiwx stfs stfsu stfsux stfsx sth sthbrx sthu sthux sthx stmw stswi stswx stw rA,rS,rB rA,rS,rB rA,rS,SH rA,rS,rB rS,d(rA) rS,d(rA) rS,rA,rB rS,rA,rB frS,d(rA) frS,d(rA) frS,rB frS,rB frS,rB frS,d(rA) frS,d(rA) frS,rB frS,r B rS,d(rA) rS,rA,rB rS,d(rA) rS,rA,rB rS,rA,rB rS,d(rA) rS,rA,NB rS,rA,rB rS,d(rA) (orc.) Operand Syntax rD,rA,SIMM rD,rA,rB rA,rS,rB rD,rA rA,rS,rB rA,rS,rB rA,rS,rB rA,rS,UIMM rA,rS,UIMM rA,rS,SH,MB,ME rA,rS,SH,MB,ME rA,rS,rB,MB,ME Multiply Low NAND Negate NOR OR OR with Complement OR Immediate OR Immediate Shifted Return from Interrupt Rotate Left Word Immediate then Mask Insert Rotate Left Word Immediate then AND with Mask Rotate Left Word then AND with Mask System Call Shift Left Word Shift Right Algebraic Word Shift Right Algebraic Word Immediate Shift Right Word Store Byte Store Byte with Update Store Byte with Update Indexed Store Byte Indexed Store Floating-Point Double Store Floating-Point Double with Update Store Floating-Point Double with Update Indexed Store Floating-Point Double Indexed Store Floating-Point as Integer Word Indexed Store Floating-Point Single Store Floating-Point Single with Update Store Floating-Point Single with Update Indexed Store Floating-Point Single Indexed Store Half Word Store Half Word Byte-Reverse Indexed Store Half Word with Update Store Half Word with Update Indexed Store Half Word Indexed Store Multiple Word Store String Word Immediate Store String Word Indexed Store Word Name Multiply Low Immediate
MPC555
/ MPC556
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Mnemonic stwbrx stwcx. stwu stwux stwx subf (subf. subfo subfo.) subfc (subfc. subfco subfco.) subfe (subfe. subfeo subfeo.) subfic subfme (subfme. subfmeo subfmeo.) subfze (subfze. subfzeo subfzeo.) sync tw twi xor (xor.) xori xoris TO,rA,rB TO,rA,SIMM rA,rS,rB rA,rS,UIMM rA,rS,UIMM Operand Syntax rS,rA,rB rS,rA,rB rS,d(rA) rS,rA,rB rS,rA,rB rD,rA,rB rD,rA,rB rD,rA,rB rD,rA,SIMM rD,rA rD,rA Name Store Word Byte-Reverse Indexed Store Word Conditional Indexed Store Word with Update Store Word with Update Indexed Store Word Indexed Subtract From Subtract from Carrying Subtract from Extended Subtract from Immediate Carrying Subtract from Minus One Extended Subtract from Zero Extended Synchronize Trap Word Trap Word Immediate XOR XOR Immediate XOR Immediate Shifted
3.10.2 Recommended Simplified Mnemonics To simplify assembly language coding, a set of alternative mnemonics is provided for some frequently used operations (such as no-op, load immediate, load address, move register, and complement register). For a complete list of simplified mnemonics, see the RCPU Reference Manual (RCPURM/AD). Programs written to be portable across the various assemblers for the PowerPC architecture should not assume the existence of mnemonics not described in that manual. 3.10.3 Calculating Effective Addresses The effective address (EA) is the 32-bit address computed by the processor when executing a memory access or branch instruction or when fetching the next sequential instruction. The PowerPC architecture supports two simple memory addressing modes: EA = (rA|0) + 16-bit offset (including offset = 0) (register indirect with immediate index) EA = (rA|0) + rB (register indirect with index) These simple addressing modes allow efficient address generation for memory accesses. Calculation of the effective address for aligned transfers occurs in a single clock cycle.
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For a memory access instruction, if the sum of the effective address and the operand length exceeds the maximum effective address, the storage operand is considered to wrap around from the maximum effective address to effective address 0. Effective address computations for both data and instruction accesses use 32-bit unsigned binary arithmetic. A carry from bit 0 is ignored in 32-bit implementations. 3.11 Exception Model The PowerPC exception mechanism allows the processor to change to supervisor state as a result of external signals, errors, or unusual conditions arising in the execution of instructions. When exceptions occur, information about the state of the processor is saved to certain registers, and the processor begins execution at an address (exception vector) predetermined for each exception. Processing of exceptions occurs in supervisor mode. Although multiple exception conditions can map to a single exception vector, a more specific condition may be determined by examining a register associated with the exception for example, the DAE/source instruction service register (DSISR). Additionally, some exception conditions can be explicitly enabled or disabled by software. 3.11.1 Exception Classes The MPC555 / MPC556 exception classes are shown in Table 3-20.
Table 3-20 MPC555 / MPC556 Exception Classes

Class Asynchronous, unordered Asynchronous, ordered Synchronous (ordered, precise) Exception Type Machine check System reset External interrupt Decrementer Instruction-caused exceptions
3.11.2 Ordered Exceptions In the MPC555 / MPC556, all exceptions except for reset, debug port non-maskable interrupts, and machine check exceptions are ordered. Ordered exceptions satisfy the following criteria: Only one exception is reported at a time. If, for example, a single instruction encounters multiple exception conditions, those conditions are encountered sequentially. After the exception handler handles an exception, instruction execution continues until the next exception condition is encountered. When the exception is taken, no program state is lost. 3.11.3 Unordered Exceptions Unordered exceptions may be reported at any time and are not guaranteed to preserve program state information. The processor can never recover from a reset exception. It can recover from other unordered exceptions in most cases. However, if a
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debug port non-maskable interrupt or machine check exception occurs during the servicing of a previous exception, the machine state information in SRR0 and SRR1 (and, in some cases, the DAR and DSISR) may not be recoverable; the processor may be in the process of saving or restoring these registers. To determine whether the machine state is recoverable, the user can read the RI (recoverable exception) bit in SRR1. During exception processing, the RI bit in the MSR is copied to SRR1 and then cleared. The operating system should set the RI bit in the MSR at the end of each exception handlers prologue (after saving the program state) and clear the bit at the start of each exception handlers epilogue (before restoring the program state). Then, if an unordered exception occurs during the servicing of an exception handler, the RI bit in SRR1 will contain the correct value.
3.11.4 Precise Exceptions In the MPC555 / MPC556, all synchronous (instruction-caused) exceptions are precise. When a precise exception occurs, the processor backs the machine up to the instruction causing the exception. This ensures that the machine is in its correct architecturally-defined state. The following conditions exist at the point a precise exception occurs: 1. Architecturally, no instruction following the faulting instruction in the code stream has begun execution. 2. All instructions preceding the faulting instruction appear to have completed with respect to the executing processor. 3. SRR0 addresses either the instruction causing the exception or the immediately following instruction. Which instruction is addressed can be determined from the exception type and the status bits. 4. Depending on the type of exception, the instruction causing the exception may not have begun execution, may have partially completed, or may have completed execution. 3.11.5 Exception Vector Table The setting of the exception prefix (IP) bit in the MSR determines how exceptions are vectored. If the bit is cleared, the exception vector table begins at the physical address 0x0000 0000; if IP is set, the exception vector table begins at the physical address 0xFFF0 0000. Table 3-21 shows the exception vector offset of the first instruction of the exception handler routine for each exception type. NOTE In the MPC555 / MPC556, the exception table can additionally be relocated by the BBC module to internal memory and reduce the total size required by the exception table (see 4.5 Exception Table Relocation).
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Table 3-21 Exception Vector Offset Table
Vector Offset (Hexadecimal) 00000 00100 00200 00300 00400 00500 00600 00700 00800 Exception Type Reserved System reset, NMI interrupt Machine check Reserved Reserved External interrupt Alignment Program Floating-point unavailable Decrementer Reserved Reserved System call Trace Floating-point assist Implementation-dependent software emulation Reserved Reserved Implementation-dependent instruction protection error Implementation-dependent data protection error Reserved Implementation-dependent data breakpoint implementation-dependent instruction breakpoint Implementation-dependent maskable external breakpoint Implementation-dependent non-maskable external breakpoint
00900 00A00 00B00 00C00 00D00 00E00 01000 01100 01200 01300 01400 0150001BFF 01C00 01D00 01E00 01F00
3.12 Instruction Timing The MPC555 / MPC556 processor is pipelined. Because the processing of an instruction is broken into a series of stages, an instruction does not require the entire resources of the processor. The instruction pipeline in the MPC555 / MPC556 has four stages: 1. The dispatch stage is implemented using a distributed mechanism. The central dispatch unit broadcasts the instruction to all units. In addition, scoreboard information (regarding data dependencies) is broadcast to each execution unit. Each execution unit decodes the instruction. If the instruction is not implemented, a program exception is taken. If the instruction is legal and no data dependency is found, the instruction is accepted by the appropriate execution unit, and the data found in the destination register is copied to the history buffer. If a data dependency exists, the machine is stalled until the dependency is resolved.
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2. In the execute stage, each execution unit that has an executable instruction executes the instruction. (For some instructions, this occurs over multiple cycles.) 3. In the writeback stage, the execution unit writes the result to the destination register and reports to the history buffer that the instruction is completed. 4. In the retirement stage, the history buffer retires instructions in architectural order. An instruction retires from the machine if it completes execution with no exceptions and if all instructions preceding it in the instruction stream have finished execution with no exceptions. As many as six instructions can be retired in one clock. The history buffer maintains the correct architectural machine state. An exception is taken only when the instruction is ready to be retired from the machine (i.e., after all previously-issued instructions have already been retired from the machine). When an exception is taken, all instructions following the excepting instruction are canceled, i.e., the values of the affected destination registers are restored using the values saved in the history buffer during the dispatch stage. Figure 3-4 shows basic instruction pipeline timing.
FETCH
I1
I2
I3
DECODE READ AND EXECUTE WRITE BACK (TO DEST REG) L ADDRESS DRIVE L DATA LOAD WRITE BACK BRANCH DECODE BRANCH EXECUTE I1
I1 I1
I2 I2 I1 I1
STORE LOAD
I2
I1
I1
Figure 3-4 Basic Instruction Pipeline Table 3-22 indicates the latency and blockage for each type of instruction. Latency refers to the interval from the time an instruction begins execution until it produces a result that is available for use by a subsequent instruction. Blockage refers to the interval from the time an instruction begins execution until its execution unit is available for a subsequent instruction. Note that when the blockage equals the latency, it is not possible to issue another instruction to the same unit in the same cycle in which the first instruction is being written back.
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Table 3-22 Instruction Latency and Blockage
Instruction Type Floating-point multiply-add Floating-point add or subtract Floating-point multiply Floating-point divide Integer multiply Integer divide Precision Double Single Double Single Double Single Double Single Latency 7 6 4 4 5 4 17 10 2 2 to 111 See note1 Blockage 7 6 4 4 5 4 17 10 1 or 21 2 to 111 See note1
Integer load/store
NOTES: 1. Refer to Section 7 Instruction Manual (RCPURM/AD) for details.
Timing, in the RCPU Reference
3.13 PowerPC User Instruction Set Architecture (UISA) 3.13.1 Computation Modes The core of the MPC555 / MPC556 is a 32-bit implementation of the PowerPC architecture. Any reference in the PowerPC Architecture Books (UISA, VEA, OEA) regarding 64-bit implementations are not supported by the core. All registers except the floating-point registers are 32 bits wide. 3.13.2 Reserved Fields Reserved fields in instructions are described under the specific instruction definition sections. Unless otherwise stated in the specific instruction description, fields marked I, II and III in the instruction are discarded by the core decoding. Thus, this type of invalid form instructions yield results of the defined instructions with the appropriate field zero. In most cases, the reserved fields in registers are ignored on write and return zeros for them on read on any control register implemented by the MPC555 / MPC556. Exception to this rule are bits 16:23 of the fixed-point exception cause register (XER) and the reserved bits of the machine state register (MSR), which are set by the source value on write and return the value last set for it on read. 3.13.3 Classes of Instructions Non-optional instructions are implemented by the hardware. Optional instructions are executed by implementation-dependent code and any attempt to execute one of these commands causes the MPC555 / MPC556 to take the implementation-dependent software emulation interrupt (offset 0x01000 of the vector table). Illegal and reserved instruction class instructions are supported by implementationdependent code and, thus, the MPC555 / MPC556 hardware generates the implemenMPC555
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tation-dependent software emulation interrupt. Invalid and preferred instruction forms treatment by the MPC555 / MPC556 is described under the specific processor compliance sections. 3.13.4 Exceptions Invocation of the system software for any instruction-caused exception in the MPC555 / MPC556 is precise, regardless of the type and setting. 3.13.5 The Branch Processor 3.13.6 Instruction Fetching The core fetches a number of instructions into its internal buffer (the instruction prefetch queue) prior to execution. If a program modifies the instructions it intends to execute, it should call a system library program to ensure that the modifications have been made visible to the instruction fetching mechanism prior to execution of the modified instructions. 3.13.7 Branch Instructions The core implements all the instructions defined for the branch processor by the UISA in the hardware. For performance of various instructions, refer to Table 3-22 of this manual. 3.13.7.1 Invalid Branch Instruction Forms Bits marked with z in the BO encoding definition are discarded by the MPC555 / MPC556 decoding. Thus, these types of invalid form instructions yield result of the defined instructions with the z bit zero. If the decrement and test CTR option is specified for the bcctr or bcctrl instructions, the target address of the branch is the new value of the CTR. Condition is evaluated correctly, including the value of the counter after decrement. 3.13.7.2 Branch Prediction The core uses the y bit to predict path for pre-fetch. Prediction is only done for notready branch conditions. No prediction is done for branches to link or count register if the target address is not ready. Refer to RCPU Reference Manual (Conditional Branch Control) for more information. 3.13.8 The Fixed-Point Processor 3.13.8.1 Fixed-Point Instructions The core implements the following instructions: Fixed-point arithmetic instructions Fixed-point compare instructions Fixed-point trap instructions Fixed-point logical instructions
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Fixed-point rotate and shift instructions Move to/from system register instructions All instructions are defined for the fixed-point processor in the UISA in the hardware. For performance of the various instructions, refer to Table 3-22. Move To/From System Register Instructions. Move to/from invalid special registers in which spr0 = 1 yields invocation of the privilege instruction error interrupt handler if the processor is in problem state. For a list of all implemented special registers, refer to Table 3-2 Supervisor-Level SPRs, and Table 3-3 Development Support SPRs. Fixed-Point Arithmetic Instructions. If an attempt is made to perform any of the divisions in the divw[o][.] instruction: 0x80000000 -1 <anything> 0 Then, the contents of RT are 0x80000000 and if Rc =1, the contents of bits in CR field 0 are LT = 1, GT = 0, EQ = 0, and SO is set to the correct value. If an attempt is made to perform any of the divisions in the divw[o][.] instruction, <anything> 0. Then, the contents of RT are 0x80000000 and if Rc = 1, the contents of bits in CR field 0 are LT = 1, GT = 0, EQ = 0, and SO is set to the correct value. In cmpi, cmp, cmpli, and cmpl instructions, the L-bit is applicable for 64-bit implementations. In 32-bit implementations, if L = 1 the instruction form is invalid. The core ignores this bit and therefore, the behavior when L = 1 is identical to the valid form instruction with L = 0 3.13.9 Floating-Point Processor 3.13.9.1 General The MPC555 / MPC556 implements all floating-point features as defined in the UISA, including the non-IEEE working mode. Some features require software assistance. For more information refer to RCPU Reference Manual (Floating-point Load Instructions) for more information. 3.13.9.2 Optional instructions The only optional instruction implemented by MPC555 / MPC556 hardware is store floating point as integer word indexed (stfiwx). An attempt to execute any other optional instruction causes the implementation dependent software emulation interrupt to be taken. 3.13.10 Load/Store Processor The load/store processor supports all of the 32-bit implementation fixed-point PowerPC load/store instructions in the hardware.
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3.13.10.1 Fixed-Point Load With Update and Store With Update Instructions For load with update and store with update instructions, where RA = 0, the EA is written into R0. For load with update instructions, where RA = RT, RA is boundedly undefined. 3.13.10.2 Fixed-Point Load and Store Multiple Instructions For these types of instructions, EA must be a multiple of four. If it is not, the system alignment error handler is invoked. For a lmw instruction (if RA is in the range of registers to be loaded), the instruction completes normally. RA is then loaded from the memory location as follows: RA MEM(EA+(RA-RT)*4, 4)
3.13.10.3 Fixed-Point Load String Instructions Load string instructions behave the same as load multiple instructions, with respect to invalid format in which RA is in the range of registers to be loaded. In case RA is in the range, it is updated from memory. 3.13.10.4 Storage Synchronization Instructions For these type of instructions, EA must be a multiple of four. If it is not, the system alignment error handler is invoked. 3.13.10.5 Floating-Point Load and Store With Update Instructions For Load and Store with update instructions, if RT = 0 then the EA is written into R0. 3.13.10.6 Floating-Point Load Single Instructions In case the operand falls in the range of a single denormalized number the floatingpoint assist interrupt handler is invoked. Refer to RCPU Reference Manual (Floating-Point Assist for Denormalized Operands) for complete description of handling denormalized floating-point numbers. 3.13.10.7 Floating-Point Store Single Instructions In case the operand falls in the range of a single denormalized number, the floatingpoint assist interrupt handler is invoked. In case the operand is ZERO it is converted to the correct signed ZERO in single-precision format. In case the operand is between the range of single denormalized and double denormalized it is considered a programming error. The hardware will handle this case as if the operand was single denormalized. In case the operand falls in the range of double denormalized numbers it is considered a programming error. The hardware will handle this case as if the operand was ZERO.
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The following check is done on the stored operand in order to determine whether it is a denormalized single-precision operand and invoke the floating-point assist interrupt handler handler: (FRS1:11 0) AND (FRS1:11 896) Refer to RCPU Reference Manual (Floating-Point Assist for Denormalized Operands) for complete description of handling denormalized floating-point numbers. 3.13.10.8 Optional Instructions No optional instructions are supported.
3.13.10.9 Little-Endian Byte Ordering The load/store unit supports little-endian byte ordering as specified in the UISA. In little-endian mode, if an attempt is made to execute an individual scalar unaligned transfer, as well as a multiple or string instruction, an alignment interrupt is taken. 3.14 PowerPC Virtual Environment Architecture (VEA) 3.14.1 Atomic Update Primitives Both the lwarx and stwcx instructions are implemented according to the PowerPC architecture requirements. The MPC555 / MPC556 does not provide support for snooping an external bus activity outside the chip. The provision is made to cancel the reservation inside the MPC555 / MPC556 by using the CR_B and KR_B input pins. 3.14.2 Effect of Operand Placement on Performance The load/store unit hardware supports all of the PowerPC load/store instructions. An optimal performance is obtained for naturally aligned operands. These accesses result in optimal performance (one bus cycle) for up to 4 bytes size and good performance (two bus cycles) for double precision floating-point operands. Unaligned operands are supported in hardware and are broken into a series of aligned transfers. The effect of operand placement on performance is as stated in the VEA, except for the case of 8byte operands. In that case, since the MPC555 / MPC556 uses a 32-bit wide data bus, the performance is good rather than optimal. 3.14.3 Storage Control Instructions The MPC555 / MPC556 does not implement cache control instructions (icbi, isync, dcbt, dcbi, dcbf, dcbz, dcbst, and dcbtst) . 3.14.4 Instruction Synchronize (isync) Instruction The isync instruction causes a reflect which waits for all prior instructions to complete and then executes the next sequential instruction. Any instruction after an isync will see all effects of prior instructions. / MPC556
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3.14.4.1 Enforce In-Order Execution of I/O (eieio) Instruction When executing an eieio instruction, the load/store unit will wait until all previous accesses have terminated before issuing cycles associated with load/store instructions following the eieio instruction. 3.14.5 Timebase A description of the timebase register may be found in SECTION 6 SYSTEM CONFIGURATION AND PROTECTION and in SECTION 8 CLOCKS AND POWER CONTROL. 3.15 POWERPC Operating Environment Architecture (OEA) The MPC555 / MPC556 has an internal memory space that includes memory-mapped control registers and internal memory used by various modules on the chip. This memory is part of the main memory as seen by the MPC555 / MPC556 but cannot be accessed by any external system master. 3.15.1 Branch Processor Registers 3.15.1.1 Machine State Register (MSR) The floating-point exception mode encoding in the MPC555 / MPC556 core is as follows:
:
Table 3-23 Floating-Point Exception Mode Encoding

Mode Ignore exceptions Precise Precise Precise FE0 0 0 1 1 FE1 0 1 0 1
The SF bit is reserved set to zero The IP bit initial state after reset is set as programmed by the reset configuration as specified by the USIU specification. 3.15.1.2 Branch Processors Instructions The MPC555 / MPC556 implements all the instructions defined for the branch processor in the UISA in the hardware. 3.15.2 Fixed-Point Processor 3.15.2.1 Special Purpose Registers Unsupported Registers The following registers are not supported by the MPC555 / MPC556: SDR, EAR, IBAT0U, IBAT0L, IBAT1U, IBAT1L, IBAT2U, IBAT2L, IBAT3U, IBAT3L, DBAT0U, DBAT0L, DBAT1U, DBAT1L, DBAT2L,
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DBAT3U, DBAT3L Added Registers For a list of added special purpose registers, refer to Table 3-2, and Table 3-3. 3.15.3 Storage Control Instructions Storage Control Instructions mtsr, mtsrin, mfsr, mfsrin, dcbi, tlbie, tlbia, and tlbsync are not implemented by the MPC555 / MPC556. 3.15.4 Interrupts The core implements all storage-associated interrupts as precise interrupts. This means that a load/store instruction is not complete until all possible error indications have been sampled from the load/store bus. This also implies that a store, or a nonspeculative load instruction is not issued to the load/store bus until all previous instructions have completed. In case of a late error, a store cycle (or a nonspeculative load cycle) can be issued and then aborted. In each interrupt handler, when registers SRR0 and SRR1 are saved, MSRRI can be set to 1. The following paragraphs define the types of OEA interrupts The exception table vector defines the offset value by interrupt type. Refer to Table 3-21. 3.15.4.1 System Reset Interrupt A system reset interrupt occurs when the IRQ0 pin is asserted and the following registers are set.
Register Name Save/Restore Register 0 (SRR0)
Bits
Description Set to the effective address of the instruction that the processor attempts to execute next if no interrupt conditions are present
1:4 10:15 Save/Restore Register 1 (SRR1) Other IP ME Machine State Register (MSR) LE Other
Set to 0 Set to 0 Loaded from bits 16:31 of MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a zero value from MSRRI No change No change Bit is copied from ILE Set to 0
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3.15.4.2 Machine Check Interrupt A machine check interrupt indication is received from the U-bus as a possible response either to the address or data phase. It is usually caused by one of the following conditions: The accessed address does not exist A data error is detected As defined in the OEA, machine check interrupts are enabled when MSRME = 1. If MSRME = 0 and a machine check interrupt indication is received, the processor enters the checkstop state. The behavior of the MPC555 / MPC556 in checkstop state is dependent on the working mode as defined in 21.4.1.1 Debug Mode Enable vs. Debug Mode Disable. When the processor is in debug mode enable, it enters the debug mode instead of the checkstop state. When in debug mode disable, instruction processing is suspended and cannot be restarted without resetting the core. An indication is sent to the SIU which may generate an automatic reset in this condition. Refer to SECTION 7 RESET for more details. If the machine check interrupt is enabled, MSRME = 1, it is taken. If SRR1 Bit 30 = 1, the interrupt is recoverable and the following registers are set.
Bits
Description Set to the effective address of the instruction that caused the interrupt
1 2:4 Save/Restore Register 1 (SRR1) 10:15 Other IP ME Machine State Register (MSR) LE Other
Set to 1 for instruction fetch-related errors and 0 for load/ store-related errors Set to 0 Set to 0 Loaded from bits 16:31 of MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a zero value from MSRRI No change No change Bit is copied from ILE Set to 0
For load/store bus cases, these registers are also set: Execution resumes at offset 0x00200 from the base address indicated by MSRIP. 3.15.4.3 Data Storage Interrupt A data storage interrupt is never generated by the hardware. The software may branch to this location as a result of implementation-specific data storage protection error interrupt.
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Register Name Bits 0:14 15:16 Data/Storage Interrupt Status Register (DSISR) 17 18:21 22:31 Data Address Register (DAR) Set to 0 Set to bits 29:30 of the instruction if X-form and to 0b00 if Dform Set to Bit 25 of the instruction if X-form and to Bit 5 if D-form Set to bits 21:24 of the instruction if X-form and to bits 1:4 if D-form Set to bits 6:15 of the instruction Set to the effective address of the data access that caused the interrupt Description
3.15.4.4 Instruction Storage Interrupt An instruction storage interrupt is never generated by the hardware. The software may branch to this location as a result of an implementation-specific instruction storage protection error interrupt. 3.15.4.5 Alignment Interrupt An alignment exception occurs as a result of one of the following conditions: The operand of a floating-point load or store is not word aligned. The operand of load/store multiple is not word aligned. The operand of lwarx or stwcx is not word aligned. The operand of load/store individual scalar instruction is not naturally aligned when MSRLE = 1. An attempt to execute multiple/string instruction is made when MSRLE = 1. 3.15.4.6 Floating-Point Enabled Exception Type Program Interrupt A floating-point enabled exception type program interrupt is generated if ((MSRFE0 | MSRFE1) &FPSCRFEX) is set as a result of move to FPSCR instruction, move to MSR instruction or the execution of the rfi instruction. A floating-point enabled exception type program interrupt is not generated by floating-point arithmetic instructions. Instead if ((MSRFE0 | MSRFE1) &FPSCRFEX) is set, the floating-point assist interrupt is generated. 3.15.4.7 Illegal Instruction Type Program Interrupt An illegal instruction type program interrupt is not generated by the MPC555 / MPC556. An implementation dependent software emulation interrupt is generated instead. 3.15.4.8 Privileged Instruction Type Program interrupt A privileged instruction type program interrupt is generated for an on-core valid SPR field or any SPR encoded as an external to the core special register if SPR0 = 1 and MSRPR = 1, as well as an attempt to execute privileged instruction when MSRPR = 1. / MPC556
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3.15.4.9 Floating-Point Unavailable Interrupt The floating-point unavailable interrupt is generated by the MPC555 / MPC556 core as defined in the OEA. 3.15.4.10 Trace Interrupt A trace interrupt occurs if MSRSE = 1 and any instruction except rfi is successfully completed or MSRBE = 1 and a branch is completed. Notice that the trace interrupt does not occur after an instruction that caused an interrupt (for instance, sc). A monitor/debugger software must change the vectors of other possible interrupt addresses to single-step such instructions. If this is unacceptable, other debug features can be used. Refer to SECTION 21 DEVELOPMENT SUPPORT for more information. The following registers are set:
Bits
Description Set to the effective address of the instruction following the executed instruction
Execution resumes at offset 0x00D00 from the base address indicated by MSRIP. 3.15.4.11 Floating-Point Assist Interrupt A floating-point assist interrupt occurs in the following cases: When a floating-point exception condition is detected, the corresponding floatingpoint enable bit in the FPSCR (floating-point status and control register) is set (exception enabled) and ((MSRFE0 | MSRFE1) = 1). Note that when ((MSRFE0 | MSRFE1) and FPSCRFEX) is set as a result of move to FPSCR, move to MSR or rfi, the floating-point assist interrupt handler is not invoked. When an intermediate result is detected and the floating-point underflow exception is disabled (FPSCRUE = 0) In some cases when at least one of the source operands is denormalized. The following registers are set: Execution resumes at offset 0x00E00 from the base address indicated by MSRIP.
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Register Name Save/Restore Register 0 (SRR0) 1:4 Save/Restore Register 1 (SRR1) 10:15 Other IP ME Machine State Register (MSR) LE Other Bit is copied from ILE Set to 0 Bits Description Set to the effective address of the instruction that caused the interrupt Set to 0 Set to 0 Loaded from bits 16:31 of MSR1 No change No change
NOTES: 1. In the current implementation bit 30 of the SRR1 is never cleared other then by loading zero value from MSR RI.
3.15.4.12 Implementation-Dependent Software Emulation Interrupt An implementation-dependent software emulation interrupt occurs in the following instances: When executing any non-implemented instruction. This includes all illegal and unimplemented optional instructions and all floating-point instructions. When executing a mtspr or mfspr that specifies on-core non-implemented register, regardless of SPR0. When executing a mtspr or mfspr that specifies off-core non-implemented register and SPR0 = 0 or MSRPR = 0 (no program interrupt condition). Program interrupt is generated if ((MSRFE0 | MSRFE1) and FPSCRFEX) is set as a result of move to FPSCR instruction, move to MSR instruction, or the execution of the rfi instruction. Floating-point enabled exception type program interrupt is not generated by floating-point arithmetic instructions, instead if ((MSRFE0 | MSRFE1) &FPSCRFEX) is set, the floating-point assist interrupt is generated. In addition, the following registers are set:
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Bits
Execution resumes at offset 0x01000 from the base address indicated by MSRIP. 3.15.4.13 Implementation-Specific Instruction Storage Protection Error Interrupt The implementation-specific instruction storage protection error interrupt occurs in the following cases: The fetch access violates storage protection. The fetch access is to guarded storage and MSRIR = 1. The following registers are set:
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Bits
1 2 3 4 10
Set to 0 Set to 0 Set to 1 if the fetch access was to a guarded storage when MSRIR = 1, otherwise set to 0 Set to 1 if the storage access is not permitted by the protection mechanism; otherwise set to 0 Set to 0 Set to 0 Loaded from bits 16:31 of MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a zero value from MSRRI No change No change Bit is copied from ILE Set to 0
Save/Restore Register 1 (SRR1)
11:15 Other IP ME Machine State Register (MSR) LE Other
Execution resumes at offset 0x01300 from the base address indicated by MSRIP. 3.15.4.14 Implementation-Specific Data Storage Protection Error Interrupt The implementation-specific data storage protection error interrupt occurs in the following case: The access violates the storage protection. The following registers are set:
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Bits
1:4 10:15 Save/Restore Register 1 (SRR1) Other IP ME Machine State Register (MSR) LE Other 0 1 2:3 Data/Storage Interrupt Status Register (DSISR) 4 5 6 7:31 Data Address Register (DAR)
Set to 0 Set to 0 Loaded from bits 16:31 of MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a zero value from MSRRI No change No change Bit is copied from ILE Set to 0 Set to 0 Set to 0 Set to 0 Set to 1 if the storage access is not permitted by the protection mechanism. Otherwise set to 0 Set to 0 Set to 1 for a store operation and to 0 for a load operation Set to 0 Set to the effective address of the data access that caused the interrupt
Execution resumes at offset 0x01400 from the base address indicated by MSRIP. 3.15.4.15 Implementation-Specific Debug Interrupts Implementation-specific debug interrupts occur in the following cases: When there is an internal breakpoint match (for more details, refer to SECTION 21 DEVELOPMENT SUPPORT. When a peripheral breakpoint request is asserted to the MPC555 / MPC556 core. When the development port request is asserted to the MPC555 / MPC556 core. Refer to SECTION 21 DEVELOPMENT SUPPORT for details on how to generate the development port-interrupt request. The following registers are set:
MPC555
/ MPC556
MOTOROLA 3-51
USERS MANUAL
Register Name
Bits
Description For I-breakpoints, set to the effective address of the instruction that caused the interrupt. For L-breakpoint, set to the effective address of the instruction following the instruction that caused the interrupt. For development port maskable request or a peripheral breakpoint, set to the effective address of the instruction that the processor would have executed next if no interrupt conditions were present. If the development port request is asserted at reset, the value of SRR0 is undefined.
Save/Restore Register 0 (SRR0)
1:4 10:15
Set to 0 Set to 0 Loaded from bits 16:31 of MSR. In the current implementation, Bit 30 of the SRR1 is never cleared, except by loading a zero value from MSRRI. If the development port request is asserted at reset, the value of SRR1 is undefined. No change No change Bit is copied from ILE Set to 0
Save/Restore Register 1 (SRR1) Other
IP ME Machine State Register (MSR) LE Other
For L-bus breakpoint instances, these registers are set to:
Register Name BAR DAR and DSISR
Bits
Description Set to the effective address of the data access as computed by the instruction that caused the interrupt Do not change
Execution resumes at offset from the base address indicated by MSRIP as follows: 0x01D00 For instruction breakpoint match 0x01C00 For data breakpoint match 0x01E00 For development port maskable request or a peripheral breakpoint 0x01F00 For development port non-maskable request 3.15.4.16 Partially Executed Instructions In general, the architecture permits instructions to be partially executed when an alignment or data storage interrupt occurs. In the core, instructions are not executed at all if an alignment interrupt condition is detected and data storage interrupt is never generated by the hardware. In the MPC555 / MPC556, the instruction can be partially executed only in the case of the load/store instructions that cause multiple access to the memory subsystem. These instructions are:
MPC555
/ MPC556
MOTOROLA 3-52
USERS MANUAL

Multiple/string instructions Unaligned load/store instructions In the last case, the store instruction can be partially completed if one of the accesses (except the first one) causes the data storage protection error. The implementationspecific data storage protection interrupt is taken in this case. For the update forms, the update register (RA) is not altered. 3.15.5 Timer Facilities Descriptions of the timebase and decrementer registers can be found in SECTION 6 SYSTEM CONFIGURATION AND PROTECTION and in SECTION 8 CLOCKS AND POWER CONTROL.
3.15.6 Optional Facilities and Instructions Any other OEA optional facilities and instructions (except those that are discussed here) are not implemented by the MPC555 / MPC556 hardware. Attempting to execute any of these instructions causes an implementation dependent software emulation interrupt to be taken.
MPC555
/ MPC556
MOTOROLA 3-53
USERS MANUAL
MPC555
/ MPC556
MOTOROLA 3-54
USERS MANUAL
SECTION 4 BURST BUFFER

The burst buffer module consists of the burst buffer controller (BBC) and the instruction memory protection unit (IMPU). The BBC delivers the RCPU instruction fetch accesses from the instruction bus onto the U-bus. It utilizes the full U-bus pipeline and a special page access attribute in order to take full advantage of the U-bus bandwidth. It can handle both burstable and nonburstable external memories as well as non-burstable internal memories (flash EEPROM, SRAM). Code compression features are only available on the MPC556. The MPC556 utilizes a version of code compression / decompression which is called Phase A. Phase A code compression / decompression is described in this manual. Future parts may have a different type of code compression. The BBC also contains the functional module which is called the instruction code decompressor unit (ICDU). The ICDU is responsible for on-line (previously compressed) instruction code decompression in the Decompression-ON mode. In the Decompression-OFF mode, the ICDU is bypassed and the BBC is in normal function. The IMPU allows the memory to be divided into four regions with different attributes, as well as a default global region (for memory space that is not included in either of the two regions). Each of the two regions can be of size four Kbytes to four Gbytes. Overlap between regions is allowed. The IMPU includes registers that contain the following information: region base address, region size and the regions access permissions. For each access (from the processor to the memory), the IMPU finds which region matches the address. If more than one region matches, the region with the lowest index is chosen. If no region is matched, the global region is chosen. The IMPU compares the attributes of the access from the processor to the attributes of the appropriate region. If the access is allowed, the proper signals are sent to the BBC. If the access is not permitted, an interrupt is sent to the processor. The IMPU does not support address translation. The effective fetch address issued by the processor is the one that is transferred to the U-bus. 4.1 Burst Buffer Block Diagram Figure 4-1 is a block diagram of the burst buffer.
BURST BUFFER
MOTOROLA 4-1
IMPU
Protection-Abort to U-bus
RCPU InstructionAddress Bus
BBC
In-Page Access U-bus
ICDU--Decompressor
Figure 4-1 Burst Buffer Block Diagram 4.2 Burst Buffer Features The BBC offers the following features: Supports pipelined access to internal memory and burstable access to the external memory. Supports the de-coupled interface with the RCPU instruction unit. Serves as parked master on the U-bus, resulting in zero clocks delay for RCPU fetch access to cross to the U-bus. Full utilization of the U-bus pipeline for fetch accesses. Tightly interfaced with L2U interface module, taking advantage of full U-bus bandwidth and back-to-back accesses. Supports program trace and show cycle attributes. Supports special attribute for debug port fetch accesses. Is programmed using the MPC555 / MPC556 mtspr/mfspr instructions to/from implementation specific special-purpose registers. Designed for minimum power consumption. The ICDU offers the following features: Instruction code on-line decompression based on a fixed vocabulary (bounded Huffman) algorithm. No need for address translation between compressed and non-compressed address spaces ICDU provides next instruction address to the RCPU Instruction decompression takes one clock cycle. Code decompression is pipelined. No performance penalty during sequential program flow execution
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-2
USERS MANUAL

Minimal performance penalty due to change of program flow execution Two operation modes are available: Decompression ON and Decompression OFF. Switch between compressed and non-compressed user application software parts is possible. The IMPU has the following features: Four regions in which the base address and size can be programmed. Region sizes of four Kbytes up to four Gbytes (in powers of two) can be programmed. (A region must start on the specified region size boundary.) Overlap between regions is allowed. Each of the four regions supports the following attributes: Access protection (use r/ supervisor fetch or no access). Guarded attribute (causes an interrupt in case of fetch try). On / off option Compressed / non-compressed. Global region entry declares the default access protection and guarded attributes for all memory areas not covered by the four regions: Interrupt generated upon access violation or fetch from guarded region. MPC555 / MPC556 MSR[IR] bit controls MPU protection. Programming is done using MPC555 / MPC556 mtspr/mfspr instructions to/from implementation specific special purpose registers. Designed for minimum power consumption. Compressed/non-compressed region with enable/disable option. Special reset exception vector for Decompression ON mode. 4.3 Instruction VocabularyBased Compression Model Main Principles 4.3.1 Compression Model Features Implemented for PowerPC architecture Up to 30% code size reduction No need for address translation tables No changes in the CPU architecture Compression is done off line by a special compressor tool, using a fixed vocabulary instruction based algorithm, optimized for the PowerPC instruction set. Decompression is done at run-time with special hardware. Optimized for cache-less systems: Highly effective in system solutions for low cache-hit ratio environment and for systems with fast embedded program memory Deterministic program execution time No performance penalty during sequential program flow execution Minimal performance penalty due to change of program flow execution Switch between compressed and non-compressed user application sections is possible. (Compressed subroutine can call non-compressed one and be called from non-compressed portion of user application)
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-3
USERS MANUAL

Slight changes in the core and existing RISC development tools compilers, simulators, manually coded libraries. Compressed address space is up to four Megabytes (4 Mbytes). Branch displacement from its target: Conditional branch displacement is up to two Kbytes (2 Kbytes). Unconditional branch displacement is up to two Mbytes (2 Mbytes). NOTE Branch displacement is hardware limited. The compiler can enlarge the branch scope by creating branch chains. 4.3.2 Model Limitations No address arithmetic is allowed, because the address map changes during compression and no software tool can identify address arithmetic structures in the code. 4.3.3 Vocabulary Based Instruction Compression Algorithm The code compression algorithm is based on creating vocabularies of frequently appearing PowerPC RISC instructions or instruction halves and replacing these instructions with pointers to the vocabularies. Compressed and bypass field lengths may vary. An example of compressed code is shown in Figure 4-2. Compression of the instructions in a vocabulary may be in one of the following modes. 1. Compression of the whole instruction into four vocabulary byte pointers. The four compacted bytes may start on any bit location. Four of the decoded bits and another bit for starting from the left or right side of the address location determine the bit location for the byte start 2. Compression of a combination of the instructions bytes into vocabulary pointers and bypass of the other byte(s). Bypass is the placing of the fields uncompressed instruction information into the compressed code. 3. Bypass of the whole instruction. No compaction permitted.
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-4
USERS MANUAL
Original Code 0 1 2 3
0 4 8 8 c 10 14 18
Compressed
4
0 4 8 8 c 10 14 18
1 2
SAVED
Figure 4-2 Example of Compressed Code Each instruction is divided to four bytes, marked X1, X2, X3 and X4. For each such byte a separate (Huffman coding) vocabulary is generated, marked Tx1, Tx2, Tx3 and Tx4. Once compressed, each instruction yields four symbols (corresponding to the X1, X2, X3, and X4 input bytes). Therefore, in order to compress a given code, four vocabularies are required. This partitionong produced a better comression ratio.
7 8
15 16
23 24
31
X1
vocabulary1
X2
vocabulary2
X3
vocabulary3
X4
vocabulary4
Tx1
Tx2
Tx3
Tx4
Figure 4-3 Instruction Coding
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-5
USERS MANUAL

4.3.4 Memory Organization In order to enhance performance, the logic is built to decode two halves of an instruction in parallel. The memory is arranged to support this as two streams of compressed symbols: the left stream for the compressed symbols of X1 and X2 bytes, and the right stream for the compressed symbols of X3 and X4 bytes.
Left Stream
X1, X2
0 15 16
X3, X4
Right Stream
31
Figure 4-4 Two Streams Memory Organization Before Compression In Figure 4-4, each left and right stream line includes two original bytes of the instruction. Figure 4-5, shows the memory after compressed streams have been put into it.
Left Stream 0 Instruction Code Base Address 1112 1819
Right Stream Boundary Bit Field 30 31 1

01 0 1 0 1 0 1 0 1
Left Bit Pointer
Right Bit Pointer
Figure 4-5 Two Streams Memory Organization After Compression
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-6
USERS MANUAL

The compiler will set the left and right stream boundary at either bit 12 or bit 19. This will be determined by the most efficient placement of compressed instruction code. The boundary will be placed between bits 11 and 12 if bit 31 is equal to one. The boundary will be placed between bits 18 and 19 if bit 31 is equal to zero. The original right and left streams may span an adjacent base addresses before or after each other. This fact will also determine the placement of the boundary bit field. Each stream line may include a variable number of compressed symbols, depending on how well the bytes in the original stream were compressed. The decompressor has to maintain two bit pointers (left and right) in order to have access to the start location of any instructions half. The decompressor maintains tracking of the base address, to start fetching from the next address in the memory.
Uncompressed Code
0 n n+1 8 15
Compressed Code Stream

0 11
Boundary assumed to be 12 for both lines 0 n n+1 Xn,1 Xn,2 Xn+1,1 8 15 0 11
(n) and (n+1) are word addresses in the original uncompressed code
Figure 4-6 Examples of Compressed Symbols Layout
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-7
USERS MANUAL

4.3.5 Compressed Code Address Format The format of the compressed code in memory requires special addressing. The Decompressor module is responsible for generating compressed code addresses. The compressed instruction stream may start on any of the 32 bits. Thus, five bits are needed to locate such instruction inside a memory word. The instruction address in Decompression ON mode consists of a 20-bit word pointer for the base address, bits 20 and 21 to show the relation between the left and right streams, and two 5-bit instruction pointers. This is known as the two-pointer address form. See Figure 4-7.
:
Compressed Instruction Address
0 Word Pointer - Base Address
19
22 26 27 31 Left Right 1 1 Pointer Pointer
Left / Right Bit Same Line Bit x Base Address x+4 Right Pointer Start Bit x+8 x+c
Memory Layout - Compressed Instruction
Figure 4-7 Compressed Address Format The base address contains the lowest word address of physical memory where the instruction resides. The left / right bit, bit number 20, indicates which instruction stream side (left or right) resides in the memory word location being pointed to by the base address. A zero 0 for bit 20 will indicate that the left side is resident in the base address location. A one 1 for bit 20 will indicate that the right side is resident in the base address location. The instruction stream side not pointed to will reside in the following address location. The same line bit, bit 21, reflects the relative location of the two side streams for the instruction. If bit 21 is zero 0, both left and right streams are located at the base address location. In this case, bit 20 has no meaning and is a dont care value of X. If bit 21 is one 1, then the two parts of the instruction are located in different address word locations (one at x base address, the other at x+4). Figure 4-8 illustrates the three possible cases for bits 20 and 21.
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-8
USERS MANUAL

:
Base Address
x x+4 0 Word Pointer - Base Address 19 22 26 27 31 Left Right X 0 Pointer Pointer
Left/Right = X (dont care) ( Left and Right are at the base address), Same_Line = 0
Base Address
x x+4
0 Word Pointer - Base Address Left/Right = 1 (Right side is first at the base address), Same_Line = 1
19
22 26 27 31 Left Right 11 Pointer Pointer
Base Address
x x+4 0 Word Pointer - Base Address 19 22 26 27 31 Left Right 01 Pointer Pointer
Left/Right = 0 (Left side is first at the base address), Same_Line = 1
Compressed Instruction
Figure 4-8 Examples of Instruction Layout in Memory 4.3.6 Compressed Address Format Direct Branches The one pointer format is used for the conditional and unconditional direct branches. Figure 4-9 illustrates the one pointer format. The word pointer for the unconditional branch has nineteen bits (the lower two-byte bits are ignored). This will yield an unconditional branch displacement limit of two Mbytes. The word pointer for the conditional
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-9
USERS MANUAL

branch has nine bits. This will yield a conditional branch displacement limit of two Kbytes. When a change of flow occurs, the sequencer of the PPC core will issue the new address in compression mapped format. The address extractor unit of the BBC generates the direct branch address format to internal memory. Indirect branches use the regular two pointer format described in the previous section.
Word Pointer 0 6 30 31
Unconditional immediate branch instruction BEFORE compression mapping
Word Pointer 0 6
5-bit Pointer 25
30 31
Unconditional immediate branch instruction AFTER compression mapping (I-form)
Word Pointer 0 16 25 30 31
Conditional immediate branch instruction BEFORE compression mapping 5-biit Pointer 30 31
Word Pointer
25 16 0 Conditional immediate branch instruction AFTER compression mapping (B-form) Base Address of the Branch Instruction Word Pointer from the Immediate Field
Base Address Calculator
Word Pointer - Base Address 0 Direct (internal) branch address format (one pointer format)
5-bit Pointer 27 31
Figure 4-9 Generating Compressed Code Address for PowerPC Direct Branches
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-10
USERS MANUAL

An instruction in memory which will serve as the target of a branch will have a label attached. The label provides the needed pointer to the other half of the branch target instruction. The label token will be skipped in normal sequential operation. The label has three parts. First, the label prefix character (which is skipped by the decompressor). Second, a 5-bit pointer to the second half of the instruction. Third, a bit which indicates the location of the second instruction half on the same line or the next line.
Left Stream 0 11 12 1819
Right Stream Boundary Bit Field 30 31 1

01 0 1 0 1 0 1 0 1
Base Address
Instruction Code Label token
Label Format
Prefix Character 5-bit Pointer Same / Next Line bit
Figure 4-10 Extracting Direct Branch Target Address in the Decompressor 4.3.7 Compressed Address Format Indirect Branches Indirect branches use the regular two pointer format described above. The indirect branch destination address is copied without any change from one of the following registers: LR CTR SRR0 See the PowerPC RCPU Users Manual, RCPURM/AD, for more details. 4.3.8 Compression Process The compression process is implemented by the following steps (See Figure 4-11): User code compilation/linking User application code compression by software compression tool. The compiler will add a few simple hooks to the compiled code which will make compression possible. Compiled code will be generated in the elf format for code
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-11
USERS MANUAL

compression purposes. The resulting uncompressed elf code (with compression hooks) will load and run like any other elf code. The software compression tool compresses the elf code (x.elf) and produces a compressed elf code (x.elf.sqz). The system sees the compressed elf code as regular elf formatted code for purposes of loading into hardware (when programming the flash). However, the decompression module must now be used to run the compressed elf code. Figure 4-11 illustrates the several steps for generating compressed executable code. Once generated, this code can be loaded into flash or SRAM (internal or external) .
Program Executable Non-compressed
Program Executable Compressed
x.elf (with hooks)

Compiler/ Linker
Compressor Tool
x.elf.sqz
Vocabulary
Figure 4-11 Code Compression Process (Phase A) The compression tool replaces regular PowerPC instructions by their compressed representation which contain fewer data bits. The compressed data bit representation is contained in the vocabulary. The vocabulary is structured into a binary bounded Huffman code tree. This method has the result of the first instructions being represented by fewer bits. Further instructions require more bits for unique decoding. Therefore, the instructions that occur most in code should be represented earlier in the vocabulary structure. This would produce the most condensed code. A statistical study was made of typical application code. The existing vocabulary is fixed for Phase A
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-12
USERS MANUAL

code compression, and is a result of the statistical study. Figure 4-12 illustrates the binary decode tree for specific instructions.
a b BYPS_node h g e d c f
An a instruction half requires less bits than an h instruction half. A bypass instruction requires four bits. = another bit = Instruction location
Figure 4-12 Bounded Huffman Code Tree In Figure 4-12, instruction a would require two bits. The bypass node would require four bits. The bounded form of the Huffman code tree is limited in size for implementation into hardware. The largest compressed instruction is 36 bits four bits for the bypass mode plus the normal uncompressed 32-bit instruction. 4.3.9 Decompression The instruction code is stored in the memory in the compressed form The decode vocabulary is stored in the burst buffer controller (BBC). The decompression is done on-line by the dedicated decompressor unit in the BBC. Decompression flow: (See Figure 4-11) RCPU provides a bit aligned COF1 address to the BBC. ICDU: Converts COF address to word aligned physical address to access the memory Fetches the compressed instruction code data from the memory, decompresses it and delivers non-compressed instruction code together with the bit aligned next instruction address to the RCPU, that uses it for subroutine and exceptions handling. When instructions are running without a COF, the next instruction is prefetched and decoded in the current cycle. This eliminates any delays from code compression during regular sequential (non-COF) operation.
1. COF
= Change of Flow
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-13
USERS MANUAL
Compressed Instructions Memory
De compressor COF Word-Aligned Physical Address Vocabulary
Bit-Aligned COF Address
PowerPC Non-Compressed Instruction Code Embedded CPU
Compressed Instruction Code
Compressed Space Next Instruction Address
BBC
Figure 4-13 Code Decompression Process 4.3.10 Compression Environment Initialization At power on reset (POR) or with a hard reset, the default settings will be activated unless the configuration word inputs override these defaults. The compression mode configuration data to be programmed is supplied by the user software in the flash. The hard reset configuration word (described in SECTION 7 RESET) has two bits which control the code compression mode. Bit 21 enables code compression when equal to 1 and disables code compression when equal to 0. Bit 22 defines the exception table code as either compressed with a value of 1 or non-compressed with a value of 0. 4.4 Modes Of Operation The burst buffer module can operate in the following modes: Normal Slave Reset Debug Standby Burst The modes of operation are described in the following paragraphs.
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-14
USERS MANUAL

4.4.1 Normal Operation During normal operation, the burst buffer module transfers fetch accesses from the CPU to the U-bus. When a new access is issued by the CPU, it is transferred in parallel to both the IMPU and the BBC. The IMPU compares the address of the access to its region programming. The BBC determines whether the access can be immediately transferred to the U-bus. If not, it requests the U-bus for the next clock. Each new BBC U-bus access is accompanying by the burst request attribute. If burstable access is enabled, the BBC performs a burst access; otherwise, it performs a single access. If the IMPU detects an access violation, it does the following:
Cancels the request that was forwarded to the BBC Informs the RCPU core that the requested address generated an exception If the required address contains show cycle or program trace attributes, the BBC delivers the access to the U-bus even if the request is cancelled (due to the exception it caused). The BBC forwards show cycle, program trace and debug port access attributes accompanying the CPU access along with the U-bus access. 4.4.2 Slave Operation. The burst buffer module is operating as a U-bus slave module when the instruction memory protection unit (IMPU) registers are accessed by the user in order to be programmed. This programming is done using the mtspr /mfspr instructions. 4.4.3 Reset Operation On reset the BBC goes to an idle state, and all pending U-bus accesses are ignored. The IMPU goes to a disabled state in which all memory space is accessible to both user and supervisor. 4.4.4 Debug Mode Operation When the CPU is in debug mode, fetch accesses are attached with a special attribute. If this attribute is asserted, the BBC must initiate not-burstable accesses to the debug port. 4.4.5 Standby Mode Operation In this low-power mode the CPU stops issuing further accesses. The BBC clocks are turned off, and the BBC enters a power-save state. When the low-power mode is exited, clocks are activated and a new access from the CPU will activate the BBC. 4.4.6 Burst Operation The BBC can run burst accesses on the U-bus. Such burst cycles, if forwarded to external memory, are then exported to the EBI as burst cycles (if bursts are enabled by the USIU).
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-15
USERS MANUAL

The BE bit defined in 4.6.4 BBC Module Configuration Register (BBCMCR) determines whether the BBC operates burst cycles or not. Burst requests are enabled only when the BE bit is set. NOTE The negated state of the BE bit is useful mainly when the RCPU core runs in serialized mode. (Refer to 21.7.6 I-Bus Support Control Register for the ICTRL register.) 4.4.7 Error Detection If the IMPU detects access violation, the following actions must be taken: 1. Cancel the request that was forwarded to the burst buffer controller 2. Inform the RCPU core that the requested address generated an exception If the required address contains show cycle or program trace attributes, than the BBC delivers the access onto the U-bus even if the request is cancelled (due to the exception it caused). The way the IMPU notifies the RCPU core for an interrupt is by feeding error information into four bits (1, 3, 4 and 10) in the SRR1 register in the core. Only one bit is set at a time. The exception vector (address) that the core issues for this event is 0xnnn01300. The encoding of the status bits is as follows: SRR1 = 0 SRR3 = Guarded storage. SRR4 = Protected storage. SRR10 = 0 4.5 Exception Table Relocation The BBC has the ability to relocate the exception table. Exception table relocation is a feature to save memory space in the exception table. See 3.11.5 Exception Vector Table for normal operation of the exception vector table. This is done by mapping exceptions to be separated by eight bytes instead of 256 bytes (see Table 4-1). The relocation feature maps the exception table into the internal memory space of the MPC555 / MPC556 and requries MSR[IP] = 1. This feature is important in multiMPC555 / MPC556 systems, where more than one MCU can have internal exception tables with the same exception addresses issued by the RCPU. The relocation feature also saves the wasted space between exception table entries when each exception entry contains only a branch instruction to the exception routine, which is located elsewhere. If exception relocation is enabled (ETRE bit is set in the BBCMCR), all exception routines (except the reset exception routine) can be controlled to either remain in the lower addresses of the memory (base address + exception offset) BBCMCR[OERC] = 0 or to be relocated to memory (base address + 32 Kbytes) by setting BBCMCR[OERC] = 1. The reset exception routine location is fixed in memory (base address + the reset exception offset) and can not be relocated. See 4.6.4 BBC Module Configuration Register (BBCMCR) for programming details.
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-16
USERS MANUAL

4.5.1 Exception Table Relocation Operation When an exception is requested, the CPU initiates a fetch cycle that branches to the exception routine associated with the exception that caused the fetch. The exception addresses are fixed within the RCPU architecture and are 0x100 bytes apart from each other, starting at address 0x0000_0100 or 0xFFF0_0100, depending on the value of the MSR[IP] bit. If the relocation feature is disabled, the BBC transfers the exception fetch address to the internal bus of the MPC555 / MPC556 with no interference. In order to activate exception table relocation, the following steps are required: 1. Set the MSR[IP] bit. To set this bit out of reset, set the appropriate bit in the reset configuration word. 2. Set the ETRE bit in BBCMCR register. See 4.6.4 BBC Module Configuration Register (BBCMCR) for programming details. 3. Program absolute branch instructions at the locations indicated in Table 4-1 pointing to the desired exception handler routines. If the relocation feature is enabled, the BBC translates the starting address of the exception routine into the address located at the lowest portion of the internal memory. At that location, the user must insert a series (table) of consecutive branch instructions that point to the appropriate exception routines. NOTE These branch instructions must utilize absolute addressing modes of the RCPU (relative branches can not be used). Thus, the CPU branches twice to reach the appropriate exception routine. NOTE 1 The eight Kbytes allocated for the exception table can be almost fully utilized. This is possible if the MPC555 / MPC556s address space is not mapped to the exception address space that is, if addresses 0xFFF0_0000 to 0xFFF0_1FFF are not part of the MPC555 / MPC556 address space. In this case, these eight Kbytes can be fully utilized by the compiler, except for the lower 64 words (256 bytes), which are reserved for the exception pointers. NOTE 2 If the CPU issues any address that falls between two successive exception entries (e.g., 0xFFF0_0104), then an exception is generated to the CPU if exception relocation is enabled. See 4.6.4 BBC Module Configuration Register (BBCMCR).
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-17
USERS MANUAL

Table 4-1 Exception Addresses Mapping by BBC1
Name of Exception Address Issued by CPU (MSR[IP] = 1) 0xFFF0_0000 0xFFF0_0100 0xFFF0_0200 0xFFF0_0300 0xFFF0_0400 0xFFF0_0500 0xFFF0_0600 0xFFF0_0700 0xFFF0_0800 0xFFF0_0900 0xFFF0_0A00 0xFFF0_0B00 0xFFF0_0C00 0xFFF0_0D00 0xFFF0_0E00 0xFFF0_1000 0xFFF0_1300 0xFFF0_1C00 0xFFF0_1D00 0xFFF0_1E00 0xFFF0_1F00 Mapped Address by Exception Table Relocation Logic (BBCMCR[ETRE] = 1) BBCMCR[OERC] = 02 Reserved System Reset Machine Check Data Storage Instruction Storage External Interrupt Alignment 0x0000 0x0008 0x0010 0x0018 0x0020 0x0028 0x0030 0x0038 0x0040 0x0048 0x0050 0x0058 0x0060 0x0068 0x0070 0x0080 0x0098 0x00E0 0x00E8 0x00F0 0x00F8 BBCMCR[OERC] = 1 0x8000 0x00083 0x8010 0x8018 0x8020 0x8028 0x8030 0x8038 0x8040 0x8048 0x8050 0x8058 0x8060 0x8068 0x8070 0x8080 0x8098 0x80E0 0x80E8 0x80F0 0x80F8
.
Program Floating Point unavailable Decrementer Reserved Reserved System Call Trace Floating Point Assist Implementation Dependant Software Emulation Implementation Dependant Storage Error Implementation Dependant Data Breakpoint Implementation Dependant Instruction Breakpoint Implementation Dependant Maskable External Breakpoint Non-Maskable External Breakpoint
NOTES: 1. See Table 3-21 and 3.11.5 Exception Vector Table for Exception Relocation Table with ETRE = 0. 2. See 4.6.4 BBC Module Configuration Register (BBCMCR) 3. The reset exception is NOT affected by OERC.
MPC555
/ MPC556
BURST BUFFER
MOTOROLA 4-18
USERS MANUAL
Exception Pointer by RCPU 0
Internal Memory Structure

branch to... branch to... branch to...
100
branch to... branch to... branch to... branch to...
200
300
400
500
600
700
1F00
F8
branch to...
Main code can start here
Figure 4-14 Exception Table Entries Mapping

MPC555
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Exception Table

4.6 Burst Buffer Programming Model The BBC and IMPU module configuration registers are MPC555 / MPC556 specialpurpose registers (SPRs). They are programmed with the MPC555 / MPC556 mtspr/ mfspr instructions. All the registers can be accessed in supervisor mode only. The processor generates an exception internally if an attempt is made to access the registers from user mode. The following 32-bit registers contain the starting address and the size of the region. There is one register for each region. Table 4-2 Region Base Address Registers RBA[0:1]
Register Name
Address (Decimal) 784 785 786 787
ub_addr[18:27] (hex) 0x2180 0x2380 0x2580 0x2780
MI_RBA[0] MI_RBA[1] MI_RBA[2] MI_RBA[3]
The following registers hold the attributes of the corresponding regions and of the default region. Each of the four MI_RAx registers contains access permission attributes. The MI_GRA (global region attribute) register contains two additional bits to enable each of the MI_RBAx registers. Table 4-3 Region Attributes Registers
Register Name MI_RA[0] MI_RA[1] MI_RA[2] MI_RA[3] MI_GRA Address (Decimal) 816 817 818 818 528 ub_addr [18:27] (Hex) 0x2190 0x2390 0x2590 0x2790 0x2100
The BBC holds only one register, the BBC module configuration register (BBCMCR). Table 4-4 BBC Module Configuration Register
Register name BBCMCR Addr (Decimal) 560 ub_addr [0:31] (Hex) 0x2110
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4.6.1 Region Base Address Registers MI_RBA[0:3] Region Base Address Register
MSB 0 1 2 3 4 5 6 7 RA RESET: Unaffected by Reset 8 9 10 11 12
SPR 784 787

13 14 15
16
17 RA
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
Reserved
RESET:
Unaffected by Reset
Table 4-5 MI_RBA[0:3] Bit Descriptions

Bit(s) 0:19 20:31 Name RA Reserved Description Region address. This field defines the base address (most significant 20 bits) for the region.
4.6.2 Region Attribute Registers MI_RA[0:3] Description MI_RA[0:3] Region Attribute Register
MSB 0 1 2 3 4 5 6 7 RS HRESET U U U U U U U U U U U U U U U U
,
SPR 816 819

8 9 10 11 12 13 14 15
16
17 RS
18
19
20 PP
21
22
23 RESERVED
24
25 G
26
27
28
29
30
LSB 31
CMPR1
RESERVED
HRESET U U U U U U 0 0 0 U U U U 0 0 0
NOTES: 1. Available only on the MPC556.
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Table 4-6 MI_RA[0:3] Registers Bits Description
Bit(s) Name Description Region size. The region size is a power of two, determined as follows: 0000_0000_0000_0000_0000 4 Kbytes 0000_0000_0000_0000_0001 8 Kbytes 0000_0000_0000_0000_0011 16 Kbytes 0000_0000_0000_0000_0111 32 Kbytes 0000_0000_0000_0000_1111 64 Kbytes 0000_0000_0000_0001_1111 128 Kbytes 0000_0000_0000_0011_1111 256 Kbytes 0000_0000_0000_0111_1111 512 Kbytes 0000_0000_0000_1111_1111 1 Mbyte 0000_0000_0001_1111_1111 2 Mbytes 0000_0000_0011_1111_1111 4 Mbytes 0000_0000_0111_1111_1111 8 Mbytes 0000_0000_1111_1111_1111 16 Mbytes 0000_0001_1111_1111_1111 32 Mbytes 0000_0011_1111_1111_1111 64 Mbytes 0000_0111_1111_1111_1111 128 Mbytes 0000_1111_1111_1111_1111 256 Mbytes 0001_1111_1111_1111_1111 512 Mbytes 0011_1111_1111_1111_1111 1 Gbyte 0111_1111_1111_1111_1111 2 Gbytes 1111_1111_1111_1111_1111 4 Gbytes Protection bits: 00: Supervisor No Access, User No Access. 01: Supervisor Fetch, User No Access. 1x: Supervisor Fetch, User Fetch. Reserved Guard attribute for region 0 = Speculative fetch is not prohibited from region. Region is not guarded. 1 = Speculative fetch is prohibited from guarded region. An exception will occur under such attempt. Compressed Region. x0 = The region in not restricted. 01 = Region is considered a non-compressed code region. Access to the region is allowed only in Decompression Off mode. 11 = Region is considered a compressed code region. Access to the region is allowed only in Decompression On mode. Reserved
0:19
RS
20:31 22:24 25
PP1 G
26:27
CMPR2
28:30
NOTES: 1. G and PP attributes perform similar protection activities on a region. The more protective attribute will be implied on the region if the attributes programming oppose each other. 2. This bit is available only on the MPC556.
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4.6.3 Global Region Attribute Register Description (MI_GRA) MI_GRA Global Region Attribute Register
MSB 0 ENR0 RESET: 0 0 0 0 0 0 0
0
SPR 528
8 9 10 11 12 13 14 15
1 ENR1
ENR2 ENR3
RESERVED
16
17
18
19
20 PP
21
22
23 RESERVED
24
25 G
26
27
28
29
30
LSB 31
RESERVED
CMPR1
RESERVED
RESET: 0 0 0 0 0 0 0
0
Table 4-7 MI_GRA Bit Descriptions

Bit(s) 0 Name ENR0 Enable region 0 of IMPU 0 = Region 0 is off 1 = Region 0 is on Enable region 1 of IMPU 0 = Region 1 is off 1 = Region 1 is on Enable region 2 of IMPU 0 = Region 2 is off 1 = Region 2 is on Enable region 3 of IMPU 0 = Region 3 is off 1 = Region 3 is on Reserved Protection bits 00 = No supervisor access, no user access 01 = Supervisor fetch access, no user access 10 = Supervisor fetch access, user fetch access 11 = Supervisor fetch access, user fetch access Reserved Guarded attribute for region 0 = Fetch is allowed from guarded region. 1 = Fetch is prohibited from guarded region. An attempted fetch will generate an exception. Compressed region x0 = The region in not restricted 01 = Region is considered a non-compressed code region. Access to the region is allowed only in "Decompression Off" mode 11 = Region is considered a compressed code region. Access to the region is allowed only in "De-compression On" mode Reserved Description
ENR1
ENR2
3 4:19
ENR3
20:21
PP
22:24 25
26:27
CMPR1
28:31
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4.6.4 BBC Module Configuration Register (BBCMCR) BBCMCR BBC Module Configuration Register
MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13
SPR 560
14 15
RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18 BE
19 ETRE
20 OERC
21 EN_ COMP2
22
23
24
25
26
27
28
29
30
LSB 31
RESERVED
EXC_ DECOMP 2 COMP2 _SC_EN
RESERVED
RESET: 0 0 0 ID[19]1 0 0 0 0 0 0 0 0 0 0 0 0
NOTES: 1. Reset value is taken from the indicated bit of the reset configuration word. 2. Available only on the MPC556.
Table 4-8 BBCMCR Bit Descriptions

Bit(s) 16:17 18 Name BE Reserved Burst enable 0 = BBC does not request burst accesses 1 = BBC requests burst accesses Exception table relocation enable 0 = Exception table relocation is off the BBC does not map exception addresses 1 = Exception table relocation is on the BBC maps exception addresses to a branch instruction table. Refer to 4.5 Exception Table Relocation. Other exceptions relocation control. 0 = All exceptions except reset are mapped to the internal memory base address. 1 = All exceptions except reset are mapped to the internal memory base address + 32 Kbytes. Description
19
ETRE
20
OERC
21
Enable COMPression This bit enables the operation of the MPC556 in "Compression ON" mode. The default state is disabled. This bit is read only. 0 = "Decompression ON" mode is disabled. The MPC556 operates only in "Decompression OFF" mode. EN_COMP 1 = "Decompression ON" mode is enabled. The MPC556 may operates with both "Decompression ON" and "Decompression OFF" modes. The bit value is determined by reset configuration word, bit #21. Exception Compression This bit determines the operation of the MPC556 with exceptions. If this bit is set, the MPC556 assumes that the all exception routines code is compressed; otherwise it is assumed that all exception routines code is not compressed. The reset value is determined by reset configuration word bit #22. 0 = The MPC556 assumes that exception routines are non-compressed 1 = The MPC556 assumes that ALL exception routines are compressed. This bit effects only when EN_COMP bit is set.
22
EXC_ COMP
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Table 4-8 BBCMCR Bit Descriptions (Continued)
Bit(s) Name Description DECOMPression Show Cycle ENable - This bit determines the way the MPC556 executes instruction show-cycle. The reset value is determined by configuration word bit #21. For further deDECOMP_ tails regarding show cycles execution in "Decompression ON" mode see 4.3.9 Decompression. SC_EN 0 = Decompression Show Cycle does not include the bit pointer. 1 = Decompression Show Cycles includes the bit pointer information on the data bus. Reserved
23
24:31
NOTE An ISYNC instruction is required immediately following any write to the BBCMCR.
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SECTION 5 UNIFIED SYSTEM INTERFACE UNIT

The unified system interface unit (USIU) of the MPC555 / MPC556 controls system start-up, system initialization and operation, system protection, and the external system bus. The MPC555 / MPC556 USIU functions include the following: System configuration and protection Interrupt controller System reset monitoring and generation Clock synthesizer Power management External bus interface (EBI) control Memory controller Debug support 5.1 Module Overview The system configuration and protection function controls the overall system configuration and provides various monitors and timers, including the bus monitor, software watchdog timer, periodic interrupt timer, PowerPC decrementer, time base, and real time clock. The interrupt controller and USIU are also included in the system configuration and protection function. Refer to SECTION 6 SYSTEM CONFIGURATION AND PROTECTION for details. The reset controller receives input from a number of reset sources and takes appropriate actions, depending on the source. The reset status register (RSR) reflects the most recent source to cause a reset. Refer to SECTION 7 RESET for details. The clock synthesizer generates the clock signals used by the SIU as well as the other modules and external devices. This circuitry can generate the system clock from a 4MHz or 20-MHz crystal. The SIU supports various low-power modes. Each supplies a different range of power consumption, functionality and wake-up time. Clock generation and low-power modes are described in SECTION 8 CLOCKS AND POWER CONTROL. The external bus interface (EBI) handles the transfer of information between the internal busses and the memory or peripherals in the external address space. The MPC555 / MPC556 is designed to allow external bus masters to request and obtain mastership of the system bus, and if required access the on-chip memory and registers. SECTION 9 EXTERNAL BUS INTERFACE describes the bus operation. The memory controller module provides a glueless interface to many types of memory devices and peripherals. It supports up to four memory banks, each with its own device
UNIFIED SYSTEM INTERFACE UNIT
MOTOROLA 5-1

and timing attributes. See SECTION 10 MEMORY CONTROLLER for more information. 5.2 SIU Architecture Figure 5-1 is a block diagram of the MPC555 / MPC556 USIU.
Clocks & RESET
Memory Controller Memory Control Lines
U-bus -
U-Bus I/F
Address Data E-bus Interface E-Bus
Slave I/F
SW watch Dog Bus monitor Periodic interrupt PowerPC timer & decrementer Real-time clock Debug Pin multiplexing Interrupt controller
SGPIO
Figure 5-1 MPC555 / MPC556 USIU Block Diagram 5.3 USIU Address Map Table 5-1 is an address map of the SIU registers. Where not otherwise noted, registers are 32 bits wide. The address shown for each register is relative to the base address of the MPC555 / MPC556 internal memory map. The internal memory block can reside in one of eight possible 4-Mbyte memory spaces. See Figure 1-3 in SECTION 1 OVERVIEW for details.
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Table 5-1 USIU Address Map
Address 0x2F C000 0x2F C004 0x2F C008 0x2F C00E1 0x2F C010 Register SIU Module Configuration Register (SIUMCR) See Table 6-5 for bit descriptions. System Protection Control Register (SYPCR) See Table 6-13 for bit descriptions. Reserved Software Service Register (SWSR) See Table 6-14 for bit descriptions. Interrupt Pending Register (SIPEND) See 6.13.2.1 SIPEND Register for bit descriptions. Interrupt Mask Register (SIMASK) See 6.13.2.2 SIU Interrupt Mask Register (SIMASK) for bit descriptions. Interrupt Edge Level Mask (SIEL) See 6.13.2.3 SIU Interrupt Edge Level Register (SIEL) for bit descriptions. Interrupt Vector (SIVEC) See 6.13.2.4 SIU Interrupt Vector Register for bit descriptions. Transfer Error Status Register(TESR) See Table 6-15 for bit descriptions. USIU General-Purpose I/O Data Register (SGPIODT1) See Table 6-21 for bit descriptions. USIU General-Purpose I/O Data Register 2 (SGPIODT2) See Table 6-22 for bit descriptions. USIU General-Purpose I/O Control Register (SGPIOCR) See Table 6-23 for bit descriptions. External Master Mode Control Register (EMCR) See Table 6-12 for bit descriptions. Pads Module Configuration Register (PDMCR) See Table 2-3 for bit descriptions. Reserved Memory Controller Registers 0x2F C100 0x2F C104 0x2F C108 0x2F C10C 0x2F C110 0x2F C114 0x2F C118 0x2F C11C Base Register 0 (BR0) See Table 10-7 for bit descriptions. Option Register 0 (OR0) See Table 10-8 for bit descriptions. Base Register 1 (BR1) See Table 10-7 for bit descriptions. Option Register 1 (OR1) See Table 10-8 for bit descriptions. Base Register 2 (BR2) See Table 10-7 for bit descriptions. Option Register 2 (OR2) See Table 10-8 for bit descriptions. Base Register 3 (BR3) See Table 10-7 for bit descriptions. Option Register 3 (OR3) See Table 10-8 for bit descriptions.
0x2F C014
0x2F C018
0x2F C01C 0x2F C020 0x2F C024 0x2F C028 0x2F C02C 0x2F C030 0x2F C03C1 0x2F C040 0x2F C0FC
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Table 5-1 USIU Address Map (Continued)
Address 0x2F C120 0x2F C13C 0x2F C140 0x2F C144 0x2F C148 0x2F C174 0x2F C1781 0x2F C17A 0x2F C1FFC Reserved Dual-Mapping Base Register (DMBR) See Table 10-9 for bit descriptions. Dual-Mapping Option Register (DMOR) See Table 10-10 for bit descriptions. Reserved Memory Status (MSTAT) See Table 10-6 for bit descriptions. Reserved System Integration Timers 0x2F C200 0x2F C204 0x2F C208 0x2F C20C 0x2F C21C 0x2F C220 0x2F C224 0x2F C228 0x2F C22C 0x2F C230 0x2F C23C 0x2F C240 0x2F C244 0x2F C248 0x2F C24C 0x2F C27C Time Base Status and Control (TBSCR) See Table 6-16 for bit descriptions. Time Base Reference 0 (TBREF0) See 6.13.4.3 Time Base Reference Registers for bit descriptions. Time Base Reference 1 (TBREF1) See 6.13.4.3 Time Base Reference Registers for bit descriptions. Reserved Real-Time Clock Status and Control (RTCSC) See Table 6-17 for bit descriptions. Real-Time Clock (RTC) See 6.13.4.6 Real-Time Clock Register (RTC) for bit descriptions. Real-Time Alarm Seconds (RTSEC) Reserved Real-Time Alarm (RTCAL) See 6.13.4.7 Real-Time Clock Alarm Register (RTCAL) for bit descriptions. Reserved PIT Status and Control (PISCR) See Table 6-18 for bit descriptions. PIT Count (PITC) See Table 6-19 for bit descriptions. PIT Register (PITR) See Table 6-20 for bit descriptions. Reserved Clocks and Reset 0x2F C280 0x2F C284 0x2F C2881 0x2F C28C1 System Clock Control Register (SCCR) See Table 8-9 for bit descriptions. PLL Low-Power and Reset Control Register (PLPRCR) See Table 8-10 for bit descriptions. Reset Status Register (RSR) See Table 7-3 for bit descriptions. Change of Lock Interrupt Register (COLIR) See Table 8-11 for bit descriptions. Register
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Table 5-1 USIU Address Map (Continued)
Address 0x2F C2901 0x2F C294 0x2F C2FC Register VDDSRM Control Register (VSRMCR) See Table 8-12 for bit descriptions. Reserved System Integration Timer Keys 0x2F C300 0x2F C304 0x2F C308 Time Base Status and Control Key (TBSCRK) See Table 8-8 for bit descriptions. Time Base Reference 0 Key (TBREF0K) See Table 8-8 for bit descriptions. Time Base Reference 1 Key (TBREF1K) See Table 8-8 for bit descriptions. Time Base and Decrementer Key (TBK) See Table 8-8 for bit descriptions. Reserved Real-Time Clock Status and Control Key (RTCSCK) See Table 8-8 for bit descriptions. Real-Time Clock Key (RTCK) See Table 8-8 for bit descriptions. Real-Time Alarm Seconds Key (RTSECK) See Table 8-8 for bit descriptions. Real-Time Alarm Key (RTCALK) See Table 8-8 for bit descriptions. Reserved PIT Status and Control Key (PISCRIK) See Table 8-8 for bit descriptions. PIT Count Key (PITCK) See Table 8-8 for bit descriptions. Reserved Clocks and Reset Keys 0x2F C380 0x2F C384 0x2F C388 0x2F C38C 0x2F C3FC System Clock Control Key (SCCRK) See Table 8-8 for bit descriptions. PLL Low-Power and Reset Control Register Key (PLPRCRK) See Table 8-8 for bit descriptions. Reset Status Register Key (RSRK) See Table 8-8 for bit descriptions. Reserved
0x2F C30C 0x2F C310 0x2F C31C 0x2F C320 0x2F C324 0x2F C328 0x2F C32C 0x2F C330 0x2F C33C 0x2F C340 0x2F C344 0x2F C348 0x2F C37C
NOTES: 1. 16-bit register.
5.4 USIU PowerPC Memory Map Table 5-2 lists the USIU PowerPC special-purpose registers (SPR). These registers can be accessed with the PowerPC mtspr and mfspr instructions, or from an external master (refer to 6.2 External Master Modes for details). All registers are 32 bits wide.
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Table 5-2 USIU Special-Purpose Registers
Internal Address[0:31] 0x2C00 0x1880 0x1A80 0x3880 0x3A80 0x3B30 Register Decrementer (DEC) Time Base Read (TB) Time Base Upper Read (TBU) Time Base Write (TB) Time Base Upper Write (TBU) Internal Memory Mapping Register (IMMR) Decimal Address spr[5:9]:spr[0:4]1 22 268 269 284 285 638
NOTES: 1. Bits [0:17] and [28:31] are all 0.
Table 5-3 shows the PowerPC special address range. For an external master accessing a PowerPC SPR, address bits [0:17] and [28:31] are compared to zeros to confirm that an SPR access is valid. Table 5-3 PowerPC Address Range
0:17 0...0 18:27 spr[0:9] 28:31 0000
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SECTION 6 SYSTEM CONFIGURATION AND PROTECTION

The MPC555 / MPC556 incorporates many system functions that normally must be provided in external circuits. In addition, it is designed to provide maximum system safeguards again hardware and/or software faults. The system configuration and protection sub-module provides the following features: System Configuration The USIU allows the user to configure the system according to the particular requirements. The functions include control of show cycle operation, pin multiplexing, and internal memory map location. System configuration also includes a register containing part and mask number constants to identify the part in software. Interrupt Configuration The interrupt controller receives interrupt requests from a number of internal and external sources and directs them on a single interrupt-request line to the RCPU. General-Purpose I/O The USIU provides 64 pins for general-purpose I/O. The SGPIO pins are multiplexed with the address and data pins. External Master Modes Support External master modes are special modes of operation that allow an alternate master on the external bus to access the internal modules for debugging and backup purposes. Bus Monitor The SIU provides a bus monitor to watch internal to external accesses. It monitors the transfer acknowledge (TA) response time for internal to external transfers. A transfer error acknowledge (TEA) is asserted if the TA response limit is exceeded. This function can be disabled. Software Watchdog Timer (SWT) The SWT asserts a reset or non-maskable interrupt (as selected by the system protection control register) if the software fails to service the SWT for a designated period of time (e.g, because the software is trapped in a loop or lost). After a system reset, this function is enabled with a maximum time-out period and asserts a system reset if the time-out is reached. The SWT can be disabled or its time-out period can be changed in the SYPCR. Once the SYPCR is written, it cannot be written again until a system reset. Periodic Interrupt Timer (PIT) The SIU provides a timer to generate periodic interrupts for use with a real-time operating system or the application software. The PIT provides a period from 1 s to 4 seconds with a 4-Mhz crystal or 200 ns to 0.8 ms with a 20-Mhz crystal. The PIT function can be disabled. Power-PC Time Base Counter (TB) The TB is a 64-bit counter defined by the MPC555 / MPC556 architecture to provide a time base reference for the operating system or application software. The TB has four independent reference registers which can generate a maskable interrupt when the time-base counter reaches the value programmed in one of the four reference registers. The associated bit in the TB status register will be set for the reference register which generated the interrupt. Power-PC Decrementer (DEC) The DEC is a 32-bit decrementing counter deMPC555 / MPC556 USERS MANUAL SYSTEM CONFIGURATION AND PROTECTION MOTOROLA 6-1

fined by the MPC555 / MPC556 architecture to provide a decrementer interrupt. This binary counter is clocked by the same frequency as the time base (also defined by the MPC555 / MPC556 architecture). The period for the DEC when driven by a 4-Mhz oscillator is 4295 seconds, which is approximately 71.6 minutes. Real-Time Clock (RTC) The RTC is used to provide time-of-day information to the operating system or application software. It is composed of a 45-bit counter and an alarm register. A maskable interrupt is generated when the counter reaches the value programmed in the alarm register. The RTC is clocked by the same clock as the PIT. Freeze Support The SIU allows control of whether the SWT, PIT, TB, DEC and RTC should continue to run during the freeze mode. Figure 6-1 shows a block diagram of the system configuration and protection logic.
Module Configuration
Interrupt Controller
Bus Monitor
TEA Signal
Periodic Interrupt Timer
Interrupt
Software Watchdog Timer
Interrupt or System Reset
Clock
MPC555 Decrementer
Decrementer Exception
MPC555 Time Base Counter
Interrupt
Real-Time Clock
Interrupt
Figure 6-1 System Configuration and Protection Logic
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6.1 System Configuration The SIU allows the user to configure the system according to the particular requirements. The functions include control of show cycle operation, pin multiplexing, and internal memory map location. System configuration also includes a register containing part and mask number constants to identify the part in software. System configuration registers include the system configuration register (SIUMCR), the internal memory mapping register (IMMR). Refer to 6.13 System Configuration and Protection Registers for register diagrams and bit descriptions. 6.1.1 USIU Pins Multiplexing Some of the functions defined in the various sections of the SIU (external bus interface, memory controller, and general-purpose I/O) share pins. Table 6-1 summarizes how the pin functions of these multiplexed pins are assigned.
.
Table 6-1 USIU Pins Multiplexing Control

Pin Name IRQ0/SGPIOC0 IRQ1/RSV/SGPIOC1 IRQ2/CR/SGPIOC2/MTS IRQ3/KR/RETRY/SGPIOC3 IRQ4/AT2/SGPIOC4 IRQ5/SGPIOC5/MODCK1 IRQ6/MODCK2 IRQ7/MODCK3 SGPIOC6/FRZ/PTR SGPIOC7/IRQ_OUT/LWP0 BG/VF0/LWP1 BR/VF1/IWP2 BB/VF2/IWP3 IWP[0:1]/VFLS[0:1] BI/STS WE(0:3)/BE(0:3)/AT(0:3) TDI/DSDI TCK/DSCK TDO/DSDO DATA[0:31]/SGPIOD[0:31] ADDR[8:31]/SGPIOA[8:31] Multiplexing Controlled By:
At Power-on reset: MODCK[1:3] Otherwise: programmed in SIUMCR (See 6.13.1.1 SIU Module Configuration Register.)
Programmed in the SIUMCR and via the hard reset configuration. (See 6.13.1.1 SIU Module Configuration Register and 7.5.2 Hard Reset Configuration Word.)
Programmed in SIUMCR and hard reset configuration. (See 6.13.1.1 SIU Module Configuration Register and 7.5.2 Hard Reset Configuration Word.) At Power-on reset: RSTCONF Otherwise: programmed in SIUMCR. (See 6.13.1.1 SIU Module Configuration Register.)
RSTCONF/TEXP
6.1.2 Memory Mapping The MPC555 / MPC556 internal memory space can be assigned to one of eight locations. The internal memory map is organized as a single 4-Mbyte block. The user can assign this block to one of eight locations by programming the ISB field in the internal memory
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mapping register (IMMR). The eight possible locations are the first eight 4-Mbyte memory blocks starting with address 0x0000 0000. (Refer to Figure 6-2.)
0x0000 0000 0x003F FFFF 0x0040 0000 0X007F FFFF 0X0080 0000 0x00BF FFFF 0x00C0 0000 0x00FF FFFF 0x0100 0000 Internal 4-Mbyte Memory Block (Resides in one of eight locations)
0x013F FFFF 0x0140 0000 0x017F FFFF 0x0180 0000 0x01BF FFFF 0x01C0 0000 0x01FF FFFF
0xFFFF FFFF
Figure 6-2 MPC555 / MPC556 Memory Map 6.1.3 Arbitration Support Two bits in the SIUMCR control USIU bus arbitration. The external arbitration (EARB) bit determines whether arbitration is performed internally or externally. If EARB is cleared (internal arbitration), the external arbitration request priority (EARP) bit determines the priority of an external masters arbitration request. The operation of the internal arbiter is described in 9.5.6.4 Internal Bus Arbiter.
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/ MPC556
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6.2 External Master Modes External master modes are special modes of operation that allow an alternate master on the external bus to access the internal modules for debugging and backup purposes. They provide access to the internal buses (U-bus and L-bus) and to the intermodule bus (IMB3). There are two external master modes. Peripheral mode (enabled by setting PRPM in the EMCR) is a special slave mechanism in which the RCPU is shut down and an alternate master on the external bus can perform accesses to any internal bus slave. Slave mode (enabled by setting SLVM and clearing PRPM in the EMCR) enables an external master to access any internal bus slave while the RCPU is fully operational. Both modes can be enabled and disabled by software. In addition, peripheral mode can be selected from reset.
The internal bus is not capable of providing fair priority between internal RCPU accesses and external master accesses. If the bandwidth of external master accesses is large, it is recommended that the system forces gaps between external master accesses in order to avoid suspension of internal RCPU activity. The MPC555 / MPC556 does not support burst accesses from an external master; only single accesses of 8, 16, or 32 bits can be performed. The MPC555 / MPC556 asserts burst inhibit (BI) on any attempt to initiate a burst access to internal memory. The MPC555 / MPC556 provides memory controller services for external master accesses (single and burst) to external memories. See SECTION 10 MEMORY CONTROLLER for details. 6.2.1 Operation of External Master Modes The external master modes are controlled by the EMCR register, which contains the internal bus attributes. The default attributes in the EMCR enable the external master to configure EMCR with the required attributes, and then access the internal registers. The external master must be granted external bus ownership in order to initiate the external master access. The SIU compares the address on the external bus to the allocated internal address space. If the address is within the internal space, the access is performed with the internal bus. The internal address space is determined according to ISB (see 6.13.1.2 Internal Memory Map Register for details). The external master access is terminated by the TA, TEA or RETRY signal on the external bus. A deadlock situation might occur if an internal-to-external access is attempted on the internal bus while an external master access is initiated on the external bus. In this case, the SIU will assert the RETRY on the external bus in order to relinquish and retry the external access until the internal access is completed. The internal bus will deny other internal accesses for the next eight clocks in order to complete the pending accesses and prevent additional internal accesses from being initiated on the internal bus. The SIU will also mask internal accesses to support consecutive external accesses if the delay between the external accesses is less than 4 clocks. The external master access and retry timings are described in 9.5.11 Bus Operation in External Master Modes.
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/ MPC556
MOTOROLA 6-5
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The external master may access the internal MPC555 / MPC556 special registers that are located outside the RCPU. In order to access one of these MPC555 / MPC556 registers, program the EMCR to MPC555 / MPC556 special register access (CONT = 1 and SUPU = 0 in EMCR). Next, access the register by providing the address according to the MPC555 / MPC556 address map. Only the first external master access that follows EMCR setting will be assigned to the special register map; the next accesses will be directed to the normal address map. This is done in order to enable the user to access the EMCR again after the required MPC555 / MPC556 special register access. Peripheral mode does not require external bus arbitration between the external master and the internal RCPU, since the internal RCPU is disabled. The BR and BB signals should be connected to ground, and the internal bus arbitration should be selected in order to prevent the slave MPC555 / MPC556 from occupying the external bus. Internal bus arbitration is selected by clearing the EARB bit in the SIUMCR (see 6.13.1.1 SIU Module Configuration Register). 6.2.2 Address Decoding for External Accesses During an external master access, the USIU compares the external address with the internal address block to determine if MPC555 / MPC556 operation is required. Since only 24 of the 32 internal address bits are available on the external bus, the USIU assigns zeros to the most significant address bits (ADDR[0:7]). The address compare sequence can be summarized as follows: Normal external access. If the CONT bit in EMCR is cleared, the address is compared to the internal address map. MPC555 / MPC556 special register external access. If the CONT bit in EMCR is set by the previous external master access, the address is compared to the MPC555 / MPC556 special address range. See 5.4 USIU PowerPC Memory Map for a list of the SPRs in the USIU. Memory controller external access. If the first two comparisons do not match, the internal memory controller determines whether the address matches an address assigned to one of the regions. If it finds a match, the memory controller generates the appropriate chip select and attribute accordingly When trying to fetch an MPC555 / MPC556 special register from an external master, the address might be aliased to one of the external devices on the external bus. If this device is selected by the MPC555 / MPC556 internal memory controller, this aliasing does not occur since the chip select is disabled. If the device has its own address decoding or is being selected by external logic, this case should be resolved. 6.3 USIU General-Purpose I/O The USIU provides 64 general-purpose I/O (SGPIO) pins. The SGPIO pins are multiplexed with the address and data pins. In single-chip mode, where communicating with external devices is not required, the user can use all 64 SGPIO pins. In multiple-chip mode, only eight SGPIO pins are available. Another configuration allows the use of the address bus for instruction show cycles while the data bus is dedicated to SGPIO func-
MPC555
/ MPC556
MOTOROLA 6-6
USERS MANUAL

tionality. The functionality of these pins is assigned by the single-chip (SC) bit in the SIUMCR. (See 6.13.1.1 SIU Module Configuration Register.) SGPIO pins are grouped as follows: Six groups of eight pins each, whose direction is set uniformly for the whole group 16 single pins whose direction is set separately for each pin Table 6-2 describes the SGPIO signals, and all available configurations. The SGPIO registers are described in 6.13.5 General-Purpose I/O Registers. Table 6-2 SGPIO Configuration
SGPIO Group Name SGPIOD[0:7] SGPIOD[8:15] SGPIOD[16:23] SGPIOD[24:31] SGPIOC[0:7]1 SGPIOA[8:15] SGPIOA[16:23] SGPIOA[24:31] X X Individual Pin Control Direction Control GDDR0 GDDR1 GDDR2 SDDRD[23:31] SDDRC[0:7] GDDR3 GDDR4 GDDR5 X X X X X Available Available Available Available When SC = 10 When SC = 00 When SC = 01 When SC = 11 (Single-Chip (32-bit Port (16-bit Port (Single-Chip Mode with Size Mode) Size Mode) Mode) Trace) X X X X X X X X
NOTES: 1. SGPIOC[0:7] is selected according to GPC and MLRC fields in SIUMCR. See 6.13.1.1 SIU Module Configuration Register.
Figure 6-3 illustrates the functionality of the SGPIO.
MPC555
/ MPC556
MOTOROLA 6-7
USERS MANUAL
Read
Internal Bus
Write
OE
Clk
SGPIO Pad
Figure 6-3 SGPIO Cell 6.4 Interrupt Controller The USIU receives interrupts from internal sources (such as the PIT and RTC), from the IMB3 module (which has its own interrupt controller), and from external pins IRQ[0:7]. An overview of the MPC555 / MPC556 interrupt structure is shown in Figure 6-4.
MPC555
/ MPC556
MOTOROLA 6-8
USERS MANUAL
IRQ[0:7]
Edge Detect Selector SWT NMI Generate IRQ0
NMI DEC Level 7 DEC 8 TB Level 6 8 PIT IMB3 Interrupt Levels 32 I6 Level 5 I5 8 RTC Level 4 I4 Change of Lock 8 Level 3 I3 Level 2 8
UIMB
I7
RCPU Interrupt Controller
IREQ
I2 Level 1 I1 Level 0 I0
IMB3 Interrupts: IRQ[0:6]Level 0:6 IRQ[7:31]Level 7 Debug
Debug
SIU
IRQOUT
Figure 6-4 MPC555 / MPC556 Interrupt Structure If programmed to generate interrupts, the SWT and external pin IRQ[0] always generate a non-maskable interrupt (NMI) to the RCPU. Notice that the RCPU takes the system reset interrupt when an NMI is asserted and the external interrupt for any other interrupt asserted by the interrupt controller. Each one of the external pins IRQ[1:7] has its own dedicated assigned priority level. IRQ[0] is also mapped but should be used only as a status bit indicating that IRQ[0] was asserted and generated an NMI interrupt. There are eight additional interrupt priMPC555
/ MPC556
MOTOROLA 6-9
USERS MANUAL

ority levels. Each one of the SIU internal interrupt sources, as well as the interrupt requests generated by the IMB3 modules, can be assigned by the software to any one of those eight interrupt priority levels. The same interrupt request signal that is generated within the RCPU is optionally driven on the IRQ_OUT pin. This pin may be used in peripheral mode, in which the internal processor is shut off and the internal modules are accessed externally. The IMB3 interrupts are controlled by the UIMB. The IMB3 provides 32 interrupt levels. Any interrupt source can be configured to any IMB3 interrupt level. The 32-bit UIPEND register in the UIMB holds the pending IMB3 interrupt requests. IMB3 interrupt request levels zero to six are mapped to USIU interrupt levels zero to six, respectively. IMB3 interrupt request levels seven to 31 are mapped to USIU request level seven. The user must read the UIPEND register to determine the actual source of the interrupt. Refer to 12.4 Interrupt Operation for more information. NOTE If the same interrupt level is assigned to more than one source, software must read the appropriate status bits in the appropriate UIMB3 registers to determine which interrupt was asserted. Figure 6-5 illustrates the operation of the interrupt controller.
MPC555
/ MPC556
MOTOROLA 6-10
USERS MANUAL

.
IRQ[0:7] IRQ[0] Interrupt Level (0-7) NMI to RCPU
8 Interrupt Vector
Highest Priority Interrupt Detector (1 from 16)
S I V E C
(Enables Branch to the Highest Priority Interrupt Routine)
SIPEND SIMASK
Interrupt Request (to RCPU and Pads) latch
Figure 6-5 MPC555 / MPC556 Interrupt Configuration 6.4.1 SIU Interrupt Sources Priority The SIU has 15 interrupt sources that assert just one interrupt request to the RCPU. There are eight external IRQ pins (IRQ[0] should be masked since it generates a NMI) and eight interrupt levels. The priority between all interrupt sources is shown in Table 6-3.
MPC555
/ MPC556
MOTOROLA 6-11
USERS MANUAL

Table 6-3 Priority of Interrupt Sources
Priority 0 (Highest) 1 2 3 4 5 6 7 8 9 Interrupt Source IRQ0 Level 0 IRQ1 Level 1 IRQ2 Level 2 IRQ3 Level 3 IRQ4 Level 4 IRQ5 Level 5 IRQ6 Level 6 IRQ7 Level 7 Reserved Interrupt Code 00000000 00000100 00001000 00001100 00010000 00010100 00011000 00011100 00100000 00100100 00101000 00101100 00110000 00110100 00111000 00111100
10 11 12 13 14 15 (Lowest) 16-31
6.5 Hardware Bus Monitor The bus monitor ensures that each bus cycle is terminated within a reasonable period of time. The USIU provides a bus monitor option to monitor internal to external bus accesses on the external bus. The monitor counts from transfer start to transfer acknowledge and from transfer acknowledge to transfer acknowledge within bursts. If the monitor times out, transfer error acknowledge (TEA) is asserted internally. The bus monitor timing bit in the system protection control register (SYPCR) defines the bus monitor time-out period. The programmability of the time-out allows for variation in system peripheral response time. The timing mechanism is clocked by the system clock divided by eight. The maximum value is 2040 system clock cycles. The bus monitor enable (BME) bit in the SYPCR enables or disables the bus monitor. The bus monitor is always enabled, however, when freeze is asserted or when a debug mode request is pending, regardless of the state of this bit. 6.6 MPC555 / MPC556 Decrementer The decrementer (DEC) is a 32-bit decrementing counter defined by the MPC555 / MPC556 architecture to provide a decrementer interrupt. This binary counter is clocked by the same frequency as the time base (also defined by the MPC555 / MPC556 architecture). The operation of the time base and decrementer are therefore coherent. In the MPC555 / MPC556, the DEC is clocked by the TMBCLK clock. The decrementer period is computed as follows:
MPC555
/ MPC556
MOTOROLA 6-12
USERS MANUAL

2 32 T dec = ----------------Ftmbclk The state of the DEC is not affected by any resets and should be initialized by software. The DEC runs continuously after power-up once the time base is enabled by setting the TBE bit of the TBSCR (see Table 6-16) (unless the clock module is programmed to turn off the clock). The decrementer continues counting while reset is asserted. Loading from the decrementer has no effect on the counter value. Storing to the decrementer replaces the value in the decrementer with the value in the GPR.
Whenever bit zero (the MSB) of the decrementer changes from zero to one, a decrementer exception occurs. If software alters the decrementer such that the content of bit 0 is changed to a value of 1, a decrementer exception occurs. A decrementer exception causes a decrementer interrupt request to be pending in the RCPU. When the decrementer exception is taken, the decrementer interrupt request is automatically cleared. Table 6-4 illustrates some of the periods available for the decrementer, assuming a 4MHz or 20-MHz crystal, and TBS = 0 which selects tbclk division to FOUR. NOTE Time base must be enabled to use the decrementer. See 6.13.4.4 Time Base Control and Status Register for more information. Table 6-4 Decrementer Time-Out Periods
Count Value 0 9 99 999 9999 999999 9999999 99999999 999999999 (hex) FFFFFFFF Time-Out @ 4 MHz 1.0 s 10 s 100 s 1.0 ms 10.0 ms 1.0 s 10.0 s 100.0 s 1000. s 4295 s Time-Out @ 20 MHz 0.2 s 2.0 s 20 s 200 s 2 ms 200 ms 2.0 s 20 s 200 s 859 s
Refer to 3.9.5 Decrementer Register (DEC) for more information. 6.7 MPC555 / MPC556 Time Base (TB) The time base (TB) is a 64-bit free-running binary counter defined by the MPC555 / MPC556 architecture. The TB has two independent reference registers which can / MPC556
MPC555
MOTOROLA 6-13
USERS MANUAL

generate a maskable interrupt when the time base counter reaches the value programmed in one of the two reference registers. The period of the TB depends on the driving frequency. In the MPC555 / MPC556, the TB is clocked by the TMBCLK clock. The period for the TB is:
2 64 = ---------------------TB F tmbclk
The state of the time base is not affected by any resets and should be initialized by software. Reads and writes of the TB are restricted to special instructions. Separate special-purpose registers are defined in the MPC555 / MPC556 architecture for reading and writing the time base. For the MPC555 / MPC556 implementation, it is not possible to read or write the entire TB in a single instruction. Therefore, the mttb and mftb instructions are used to move the lower half of the time base (TBL) while the mttbu and mftbu instructions are used to move the upper half (TBU). Two reference registers are associated with the time base: TBREF0 and TBREF1. A maskable interrupt is generated when the TB count reaches to the value programmed in one of the two reference registers. Two status bits in the time base control and status register (TBSCR) indicate which one of the two reference registers generated the interrupt. Refer to 6.13.4 System Timer Registers for diagrams and bit descriptions of time base registers. Refer to 3.9.4 Time Base Facility (TB) OEA and to RCPU Reference Manual (RCPURM/AD) for additional information regarding the MPC555 / MPC556 time base. 6.8 Real-Time Clock (RTC) The RTC is a 32-bit counter and pre-divider used to provide a time-of-day indication to the operating system and application software. It is clocked by the pitrtclk clock.The counter is not affected by reset and operates in all low-power modes. It is initialized by software. The RTC can be programmed to generate a maskable interrupt when the time value matches the value programmed in its associated alarm register. It can also be programmed to generate an interrupt once a second. A control and status register is used to enable or disable the different functions and to report the interrupt source.
MPC555
/ MPC556
MOTOROLA 6-14
USERS MANUAL

FREEZE RTSEC pitrtclk Clock Clock Disable Divide By 15625 MUX Divide By 78125 Sec Interrupt
32-bit Counter (RTC)
Alarm Interrupt
4-MHz / 20-MHz crystal 32-bit Register (RTCAL)
Figure 6-6 RTC Block Diagram 6.9 Periodic Interrupt Timer (PIT) The periodic interrupt timer consists of a 16-bit counter clocked by the PITRCLK clock supplied by the clock module. The 16-bit counter counts down to zero when loaded with a value from the PITC. After the timer reaches zero, the PS bit is set and an interrupt is generated if the PIE bit is is a logic one. The software service routine should read the PS bit and then write it to zero to terminate the interrupt request. At the next input clock edge, the value in the PITC is loaded into the counter, and the process starts over again. When a new value is loaded into the PITC, the periodic timer is updated, the divider is reset, and the counter begins counting. If the PS bit is not cleared, an interrupt request is generated. The request remains pending until PS is cleared. If the PS bit is set again prior to being cleared, the interrupt remains pending until PS is cleared. Any write to the PITC stops the current countdown, and the count resumes with the new value in PITC. If the PTE bit is not set, the PIT is unable to count and retains the old count value. Reads of the PIT have no effect on the counter value.
MPC555
/ MPC556
MOTOROLA 6-15
USERS MANUAL
PTE (PISCR)
PITC (PISCR)
pitrtclk Clock
Clock Disable
16-bit Modulus Counter
PS (PISCR) PIT Interrupt PIE (PISCR)
PITF (PISCR)
Figure 6-7 PIT Block Diagram
The timeout period is calculated as:

PIT period PITC + 1 PITC + 1 = ----------------------- = ---------------------------------------------F ExternalClock pitrtclk ---------------------------- 4or256
Solving this equation using a 4-MHz external clock and a pre-divider of 256 gives:
PITC + 1 PITperiod = ----------------------15625
This gives a range from 64 microseconds, with a PITC of 0x0000, to 4.19 seconds, with a PITC of 0xFFFF. When a 20-MHz crystal is used with a pre-divider of 256, the range is between 12.8 microseconds to 0.84 seconds. 6.10 Software Watchdog Timer (SWT) The software watchdog timer (SWT) prevents system lockout in case the software becomes trapped in loops with no controlled exit. The SWT is enabled after system reset to cause a system reset if it times out. it. The SWT requires a special service sequence to be executed on a periodic basis. If this periodic servicing action does not occur, the SWT times out and issues a reset or a non-maskable interrupt (NMI), depending on the value of the SWRI bit in the SYPCR. The SWT can be disabled by clearing the SWE bit in the SYPCR. Once the SYPCR is written by software, the state of the SWE bit cannot be changed. The SWT service sequence consists of the following two steps: 1. Write 0x556C to the Software Service Register (SWSR) 2. Write 0xAA39 to the SWSR The service sequence clears the watchdog timer and the timing process begins again. If any value other than 0x556C or 0xAA39 is written to the SWSR, the entire sequence must start over.
MPC555
/ MPC556
MOTOROLA 6-16
USERS MANUAL

Although the writes must occur in the correct order prior to time-out, any number of instructions may be executed between the writes. This allows interrupts and exceptions to occur, if necessary, between the two writes.
Not 0x556C / Dont Reload 0x556C / Dont Reload
Reset
State 0 Waiting for 0x556C
State 1 Waiting for 0xAA39
0xAA39 / Reload Not 0x556C / Dont Reload Not 0xAA39 / Dont Reload
Figure 6-8 SWT Interrupts and Exceptions Although most software disciplines support the watchdog concept, different systems require different time-out periods. For this reason, the software watchdog provides a selectable range for the time-out period. In Figure 6-9, the range is determined by the value SWTC field. The value held in the SWTC field is then loaded into a 16-bit decrementer clocked by the system clock. An additional divide by 2048 prescaler is used if necessary. The decrementer begins counting when loaded with a value from the software watchdog timing count field (SWTC). After the timer reaches 0x0, a software watchdog expiration request is issued to the reset or NMI control logic. Upon reset, the value in the SWTC is set to the maximum value and is again loaded into the software watchdog register (SWR), starting the process over. When a new value is loaded into the SWTC, the software watchdog timer is not updated until the servicing sequence is written to the SWSR. If the SWE is loaded with the value zero, the modulus counter does not count.
MPC555
/ MPC556
MOTOROLA 6-17
USERS MANUAL
SWSR
SWE (SYPCR)
Service Logic
SWTC
System Clock
Clock Disable
Divide By 2048 MUX
Reload
16-bit SWR / Decrementer Rollover = 0
Reset or NMI
FREEZE Time-out SWP (SYPCR)
Figure 6-9 SWT Block Diagram 6.11 Freeze Operation When the FREEZE line is asserted, the clocks to the software watchdog, the periodic interrupt timer, the real-time clock, the time base counter, and the decrementer can be disabled. This is controlled by the associated bits in the control register of each timer. If programmed to stop during FREEZE assertion, the counters maintain their values while FREEZE is asserted, unless changed by the software. The bus monitor, however, remains enabled regardless of this signal. 6.12 Low Power Stop Operation When the processor is set in a low-power mode (doze, sleep, or deep sleep), the software watchdog timer is frozen. It remains frozen and maintain its count value until the processor exits this state and resumes executing instructions. The periodic interrupt timer, decrementer, and time base are not affected by these lowpower modes. They continue to run at their respective frequencies. These timers are capable of generating an interrupt to bring the MCU out of these low-power modes. 6.13 System Configuration and Protection Registers This section provides diagrams and bit descriptions of the system configuration and protection registers.
MPC555
/ MPC556
MOTOROLA 6-18
USERS MANUAL

6.13.1 System Configuration Registers System configuration registers include the SIUMCR, the EMCR, and the IMMR. 6.13.1.1 SIU Module Configuration Register The SIU module configuration register (SIUMCR) configures various aspects of SIU operation. SIUMCR SIU Module Configuration Register
MSB 0 EARB RESET: 1 2 EARP 3 4 5 6 7 8 DSHW 9 10 DBGC 11 12 13 GPC
0x2F C000
14 15 DLK
RESERVED
DBPC ATWC
ID0*
ID[9:10]*
ID11*
ID12*
16 RESERVE D
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
SC
RCTX
MLRC
RESERVED
MTSC
RESERVED
RESET: 0 ID[17:18]* 0 0 0 0 0 0 0 0 0 0 0 0 0
* The reset value is a reset configuration word value, extracted from the indicated internal data bus lines.
WARNING Software must not change any SIUMCR fields controlled by the reset configuration word while the functions that these fields control are active.
MPC555
/ MPC556
MOTOROLA 6-19
USERS MANUAL

Table 6-5 SIUMCR Bit Descriptions
Bit(s) 0 Name EARB External arbitration 0 = Internal arbitration is performed 1 = External arbitration is assumed External arbitration request priority. This field defines the priority of an external masters arbitration request. This field is valid when EARB is cleared. Refer to 9.5.6.4 Internal Bus Arbiter for details. Reserved Data show cycles. This bit selects the show cycle mode to be applied to U-bus data cycles (data cycles to IMB modules and flash EEPROM). This field is locked by the DLK bit. Note that instruction show cycles are programmed in the ICTRL and L-bus data show cycles (to SRAM) are programmed in the L2UMCR. 0 = Disable show cycles for all internal data cycles 1 = Show address and data of all internal data cycles Debug pins configuration. Refer to Table 6-6. Debug port pins configuration. Refer to Table 6-7. Address write type enable configuration. This bit configures the pins to function as byte write enables or address types for debugging purposes. 0 = WE[0:3]/BE[0:3]/AT[0:3] functions as WE[0:3]/BE[0:3]1 1 = WE[0:3]/BE[0:3]/AT[0:3] functions as AT[0:3] This bit configures the pins as shown in Table 6-8. Debug register lock 0 = Normal operation 1 = SIUMCR is locked and can be written only in test mode or when the internal freeze signal is asserted. Reserved Single-chip select. This field configures the functionality of the address and data buses. Changing the SC field while external accesses are performed is not supported. Refer to Table 6-9. Reset configuration/timer expired. During reset the RSTCONF/TEXP pin functions as RSTCONF. After reset the pin can be configured to function as TEXP, the timer expired signal that supports the low-power modes. 0 = RSTCONF/TEXP functions as RSTCONF 1 = RSTCONF/TEXP functions as TEXP Multi-level reservation control. This field selects between the functionality of the reservation logic and IRQ pins, refer to Table 6-10. Reserved Memory transfer start control. 0 = IRQ[2]/CR/SGPIOC[2]/MTS functions according to the MLRC bits setting 1 = IRQ[2]/CR/SGPIOC[2]/MTS functions as MTS Reserved Description
1:3 4:7
EARP
DSHW
9:10 11
DBGC DBPC
12
ATWC
13:14 15 16 17:18
GPC DLK SC
19
RCTX
20:21 22:23 24 25:31
MLRC MTSC
NOTES: 1. WE/BE is selected per memory region by WEBS in the approprite BR register in the memory controller.
MPC555
/ MPC556
MOTOROLA 6-20
USERS MANUAL

Table 6-6 Debug Pins Configuration
DBGC 00 01 10 11 Pin Function IWP[0:1]/VFLS[0:1] VFLS[0:1] IWP[0:1] VFLS[0:1] IWP[0:1] BI/STS BI STS STS STS BG/VF0/LWP1 BG BG VF0 LWP1 BR/VF1/IWP2 BR BR VF1 IWP2 BB/VF2/IWP3 BB BB VF2 IWP3
Table 6-7 Debug Port Pins Configuration

DBPC Pin Function TCK/DSCK DSCK TCK TDI/DSDI DSDI TDI TDO/DSDO DSDO TDO
0 1
Table 6-8 General Pins Configuration

GPC 00 01 10 11 Pin Function FRZ/PTR/SGPIOC6 PTR SGPIOC6 FRZ FRZ IRQOUT/LWP0/SGPIOC7 LWP0 SGPIOC7 LWP0 IRQOUT
Table 6-9 Single-Chip Select Field Pin Configuration

Pin Function SC 00 (multiple chip, 32-bit port size) 01 (multiple chip, 16-bit port size 10 (single-chip with address show cycles for debugging) 11 (single-chip) DATA[0:15]/ SGPIOD[0:15] DATA[0:15] DATA[0:15] SPGIOD[0:15] SPGIOD[0:15] DATA[16:31] SGPIOD[16:31] DATA[16:31] SPGIOD[16:31] SPGIOD[16:31] SPGIOD[16:31] ADDR[8:31]/ SGPIOA[8:31] ADDR[8:31] ADDR[8:31] ADDR[8:31] SPGIOA[8:31]
MPC555
/ MPC556
MOTOROLA 6-21
USERS MANUAL

Table 6-10 Multi-Level Reservation Control Pin Configuration
Pin Function MLRC IRQ[0]/ SGPIOC[0] IRQ[0] IRQ[0] SGPIOC[0] IRQ[0] IRQ[1]/RSV/ SGPIOC[1] IRQ[1] RSV SGPIOC[1] IRQ[1] IRQ[2]/CR/ SGPIOC[2]/ MTS IRQ[2]2 CR2 SGPIOC[2]2 SGPIOC[2]2 IRQ[3]/KR/ RETRY / SGPIOC[3] IRQ[3] KR/RETRY SGPIOC[3] KR/RETRY IRQ[4]/AT[2]/ SGPIOC[4] IRQ[4] AT[2] SGPIOC[4] AT[2] IRQ[5]/SGPIOC[5]/ MODCK[1]1 IRQ[5] / MODCK[1] IRQ[5] / MODCK[1] SGPIOC[5]/ MODCK[1] SGPIOC[5]/ MODCK[1]
00 01 10 11
NOTES: 1. Operates as MODCK[1] during reset. 2. This holds if MTSC bit is reset to 0. Otherwise IRQ[2]/CR/SGPIOC[2]/MTS will function as MTS.
6.13.1.2 Internal Memory Map Register The internal memory map register (IMMR) is a special register located within the MPC555 / MPC556 special register space. The IMMR contains identification of a specific device as well as the base for the internal memory map. Based on the value read from this register, software can deduce availability and location of any on-chip system resources. This register can be read by the mfspr instruction. The ISB field can be written by the mtspr instruction. The PARTNUM and MASKNUM fields are mask programmed and cannot be changed. IMMR Internal Memory Mapping Register
MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13
SPR 638
14 15
PARTNUM RESET: Read-Only Fixed Value
MASKNUM
Read-Only Fixed Value
16
17
18
19
20 FLEN
21
22
23 CLES
24
25
26
27
28
29 ISB
30
LSB 31 0
RESERVED RESET: 0 0 0 0
RESERVED
RESERVED
ID20*
ID23*
ID[28:30]*
* The reset value is a reset configuration word value extracted from the indicated bits of the internal data bus. Refer to 7.5.2 Hard Reset Configuration Word.
MPC555
/ MPC556
MOTOROLA 6-22
USERS MANUAL

Table 6-11 IMMR Bit Descriptions
Bit(s) Name Description This read-only field is mask programmed with a code corresponding to the part number of the part on which the SIU is located. It is intended to help factory test and user code which is sensitive to part changes. This changes when the part number changes. For example, it would change if any new module is added, if the size of any memory module is changed. It would not change if the part is changed to fix a bug in an existing module. The MPC555 / MPC556 chip has an ID of 0x30. This read-only field is mask programmed with a code corresponding to the mask number of the part. It is intended to help factory test and user code which is sensitive to part changes. Reserved Flash enable is a read-write bit. The default state of FLEN is negated, meaning that the boot is performed from external memory. This bit can be set at reset by the reset configuration word. 0 = On-chip flash memory is disabled, and all internal cycles to the allocated flash address space are mapped to external memory 1 = On-chip flash memory is enabled Reserved Core little-endian swap 0 = Little-endian swap logic in the EBI is not activated for RCPU accesses after reset 1 = Little-endian swap logic in the EBI is activated for RCPU accesses after reset Reserved This read-write field defines the base address of the internal memory space. The initial value of this field can be configured at reset to one of eight addresses, and then can be changed to any value by software. Internal base addresses are as follows: 000 = 0x0000 0000 001 = 0x0040 0000 010 = 0x0080 0000 011 = 0x00C0 0000 100 = 0x0100 0000 101 = 0x0140 0000 110 = 0x0180 0000 111 = 0x01C0 0000 Reserved
0:7
PARTNUM
8:15 16:19
MASKNUM
20
FLEN
21:22 23 24:27
CLES
28:30
ISB
31
6.13.1.3 External Master Control Register (EMCR) The external master control register selects the external master modes and determines the internal bus attributes for external-to-internal accesses. EMCR External Master Control Register
MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13
0x2F C030
14 15
RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MPC555
/ MPC556
MOTOROLA 6-23
USERS MANUAL

LSB 31
16
17
18 0
19 SIZE
20
21 SUPU
22 INST
23
24
25
26
27 0
28
29
30
PRPM SLVM RESET: ID16* 0
RESERVED
RESV CONT
TRAC SIZEN
RESERVED
* The reset value is a reset configuration word value, extracted from the indicated internal data bus line. Refer to 7.5.2 Hard Reset Configuration Word.
Table 6-12 EMCR Bit Descriptions

Bit(s) 0:15 Name Reserved Peripheral mode. In this mode, the internal RCPU core is shut off and an alternative master on the external bus can access any internal slave module. The reset value of this bit is determined by the reset configuration word bit 16. The bit can also be written by software. 0 = Normal operation 1 = Peripheral mode operation Slave mode (valid only if PRPM = 0). In this mode, an alternative master on the external bus can access any internal slave module while the internal RCPU core is fully operational. If PRPM is set, the value of SLVN is a dont care. 0 = Normal operation 1 = Slave mode Reserved Size attribute. If SIZEN = 1, the SIZE bits controls the internal bus attributes as follows: 00 = Double word (8 bytes) 01 = Word (4 bytes) 10 = Half word (2 bytes) 11 = Byte Supervisor/user attribute. SUPU controls the supervisor/user attribute as follows: 0 = Supervisor mode access permitted to all registers 1 = User access permitted to registers designated user access Instruction attribute. INST controls the internal bus instruction attribute as follows: 0 = Instruction fetch 1 = Operand or non-CPU access Reserved Reservation attribute. RESV controls the internal bus reservation attribute as follows: 0 = Storage reservation cycle 1 = Not a reservation Control attribute. CONT drives the internal bus control bit attribute as follows: 0 = Access to MPC555 / MPC556 control register, or control cycle access 1 = Access to global address map Reserved Trace attribute. TRAC controls the internal bus program trace attribute as follows: 0 = Program trace 1 = Not program trace External size enable control bit. SIZEN determines how the internal bus size attribute is driven: 0 = Drive size from external bus signals TSIZE[0:1] 1 = Drive size from SIZE0, SIZE1 in EMCR Reserved Description
16
PRPM
17
SLVM
18
19:20
SIZE
21
SUPU
22 23:24 25
INST RESV
26 27 28
CONT TRAC
29 30:31
SIZEN
MPC555
/ MPC556
MOTOROLA 6-24
USERS MANUAL

6.13.2 SIU Interrupt Registers The SIU interrupt controller contains the SIPEND, SIMASK, SIEL, and SIVEC registers. 6.13.2.1 SIPEND Register Each of the 32 bits in the SIPEND register corresponds to an interrupt request. The bits associated with internal exceptions indicate, if set, that an interrupt service is requested (if not masked by the corresponding bit in the SIMASK register). Each bit reflects the status of the internal requestor device and is cleared when the appropriate actions are initiated by the software in the device itself. Writing to these bits while they are not set has no effect.
The bits associated with the IRQ pins have a different behavior depending on the sensitivity defined for them in the SIEL register. When the IRQ is defined as a level interrupt the corresponding bit behaves similar to the bits associated with internal interrupt sources. When the IRQ is defined as an edge interrupt and if the corresponding bit is set, it indicates that a falling edge was detected on the line and the bit can be reset by software by writing a 1 to it. SIPEND SIU Interrupt Pending Register
MSB 0 IRQ0 1 LVL0 2 IRQ1 3 LVL1 4 IRQ2 5 LVL2 6 IRQ3 7 LVL3 8 IRQ4 9 LVL4 10 IRQ5 11 LVL5 12 IRQ6 13 LVL6
0x2F C010
14 IRQ7 15 LVL7
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.13.2.2 SIU Interrupt Mask Register (SIMASK) The SIMASK is a 32-bit read/write register. Each bit corresponds to an interrupt request bit in the SIPEND register. Setting a bit in this register allows the interrupt request to reach the RCPU. SIMASK is updated by the software and cleared upon reset. It is the responsibility of the software to determine which of the interrupt sources are enabled at a given time. SIMASK SIU Interrupt Mask Register
MSB 0 1 2 IRM1 3 LVM1 4 IRM2 5 LVM2 6 IRM3 7 LVM3 8 IRM4 9 LVM4 10 IRM5 11 LVM5 12 IRM6 13 LVM6
0x2F C014
14 IRM7 15 LVM7
IRM0* LVM0 RESET: 0 0
MPC555
/ MPC556
MOTOROLA 6-25
USERS MANUAL

LSB 31
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
*IRQ0 of the SIPEND register is not affected by the setting or clearing of the IRM0 bit of the SIMASK register. IRQ0 is a non-maskable interrupt.
6.13.2.3 SIU Interrupt Edge Level Register (SIEL) The SIEL is a 32-bit read/write register. Each pair of bits corresponds to an external interrupt request. The EDx bit, if set, specifies that a falling edge in the corresponding IRQ line will be detected as an interrupt request. When the EDx bit is 0, a low logical level in the IRQ line will be detected as an interrupt request. The WMx (wake-up mask) bit, if set, indicates that an interrupt request detection in the corresponding line causes the MPC555 / MPC556 to exit low-power mode. SIEL SIU Interrupt Edge Level Register
MSB 0 ED0 1 WM0 2 ED1 3 WM1 4 ED2 5 WM2 6 ED3 7 WM3 8 ED4 9 WM4 10 ED5 11 WM5 12 ED6 13 WM6
0x2F C018
14 ED7 15 WM7
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.13.2.4 SIU Interrupt Vector Register The SIVEC is a 32-bit read-only register that contains an 8-bit code representing the unmasked interrupt source of the highest priority level. The SIVEC can be read as either a byte, half word, or word. When read as a byte, a branch table can be used in which each entry contains one instruction (branch). When read as a half-word, each entry can contain a full routine of up to 256 instructions. The interrupt code is defined such that its two least significant bits are 0, thus allowing indexing into the table. SIVEC SIU Interrupt Vector
MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13
0x2F C01C
14 15
INTERRUPT CODE RESET: 0 0 1 1 1 1 0 0 0 0 0
RESERVED
MPC555
/ MPC556
MOTOROLA 6-26
USERS MANUAL

LSB 31
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
6.13.3 System Protection Registers 6.13.3.1 System Protection Control Register (SYPCR) The system protection control register (SYPCR) controls the system monitors, the software watchdog period, and the bus monitor timing. This register can be read at any time, but can be written only once after system reset.
SYPCR System Protection Control Register

MSB 0 1 2 3 4 5 6 7 SWTC RESET: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 9 10 11 12 13
0x2F C004
14 15
16
17
18
19 BMT
20
21
22
23
24 BME
25
26 RESERVED
27
28 SWF
29 SWE
30 SWRI
LSB 31 SWP
RESET: 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1
Table 6-13 SYPCR Bit Descriptions

Bit(s) 0:15 16:23 Name SWTC BMT Description Software watchdog timer count. This field contains the count value of the software watchdog timer. Bus monitor timing. This field specifies the time-out period, in eight-system-clock resolution, of the bus monitor. Bus monitor enable 0 = Disable bus monitor 1 = Enable bus monitor Reserved Software watchdog freeze 0 = Software watchdog continues to run while FREEZE is asserted 1 = Software watchdog stops while FREEZE is asserted Software watchdog enable. Software should clear this bit after a system reset to disable the SWT. 0 = Watchdog is disabled 1 = Watchdog is enabled
24 25:27 28
BME SWF
29
SWE
MPC555
/ MPC556
MOTOROLA 6-27
USERS MANUAL

Table 6-13 SYPCR Bit Descriptions (Continued)
Bit(s) 30 Name SWRI Description Software watchdog reset/interrupt select 0 = Software watchdog time-out causes a non-maskable interrupt to the RCPU 1 = Software watchdog time-out causes a system reset Software watchdog prescale 0 = Software watchdog timer is not pre-scaled 1 = Software watchdog timer is prescaled by 2048
31
SWP
6.13.3.2 Software Service Register (SWSR) The SWSR is the location to which the SWT servicing sequence is written. To prevent SWT time-out, the user should write a 0x556C followed by 0xAA39 to this register. The SWSR can be written at any time but returns all zeros when read.
MPC555
/ MPC556
MOTOROLA 6-28
USERS MANUAL

SWSR Software Service Register
MSB 0 1 2 3 4 5 6 7 SWSR RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 9 10 11 12 13
0x2F C00E
14 LSB 15
Table 6-14 SWSR Bit Descriptions

Bit(s) 0:15 Name SWSR Description SWT servicing sequence is written to this register. To prevent SWT time-out, the user should write a 0x556C followed by 0xAA39 to this register. The SWSR can be written at any time but returns all zeros when read.
6.13.3.3 Transfer Error Status Register (TESR) The transfer error status register contains a bit for each exception source generated by a transfer error. A bit set to logic 1 indicates what type of transfer error exception occurred since the last time the bits were cleared by reset or by the normal software status bit-clearing mechanism. Note that these bits may be set due to canceled speculative accesses which do not cause an interrupt. The register has two identical sets of bit fields; one is associated with instruction transfers and the other with data transfers. TESR Transfer Error Status Register
MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13
0x2F C020
14 15
RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18 IEXT
19 IBMT
20
21
22
23
24
25
26 DEXT
27 DBM
28
29
30
LSB 31
RESERVED RESET: 0 0
RESERVED
RESERVED
MPC555
/ MPC556
MOTOROLA 6-29
USERS MANUAL

Table 6-15 TESR Bit Descriptions
Bit(s) 0:17 18 19 20:25 26 27 28:31 Name IEXT IBMT DEXT DBM Reserved Instruction external transfer error acknowledge. This bit is set if the cycle was terminated by an externally generated TEA signal when an instruction fetch was initiated. Instruction transfer monitor time out. This bit is set if the cycle was terminated by a bus monitor time-out when an instruction fetch was initiated. Reserved Data external transfer error acknowledge. This bit is set if the cycle was terminated by an externally generated TEA signal when a data load or store is requested by an internal master. Data transfer monitor time out. This bit is set if the cycle was terminated by a bus monitor timeout when a data load or store is requested by an internal master. Reserved Description
6.13.4 System Timer Registers The following sections describe registers associated with the system timers. These facilities are powered by the KAPWR and can preserve their value when the main power supply is off. Refer to 8.3.3 Pre-Divider for details on the required actions needed in order to guarantee this data retention. 6.13.4.1 Decrementer Register The 32-bit decrementer register is defined by the MPC555 / MPC556 architecture. The values stored in this register are used by a down counter to cause decrementer exceptions. The decrementer causes an exception whenever bit zero changes from a logic zero to a logic one. A read of this register always returns the current count value from the down counter. Contents of this register can be read or written to by the mfspr or the mtspr instruction. The decrementer register is reset by PORESET. HRESET and SRESET do not affect this register. The decrementer is powered by standby power and can continue to count when standby power is applied. DEC Decrementer Register
MSB 0 Decrementing Counter PORESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPR 22
LSB 31
HRESET/SRESET: UNCHANGED
Refer to 3.9.5 Decrementer Register (DEC) for more information on this register. 6.13.4.2 Time Base SPRs The TB is a 64-bit register containing a 64-bit integer that is incremented periodically. There is no automatic initialization of the TB; the system software must perform this
MPC555
/ MPC556
MOTOROLA 6-30
USERS MANUAL

initialization. The contents of the register may be written by the mttbl or the mttbu instructions, see 3.9.4 Time Base Facility (TB) OEA. Refer to 3.8 PowerPC VEA Register Set Time Base and 3.9.4 Time Base Facility (TB) OEA for more information on reading and writing the TBU and TBL registers. TB Time Base (Reading)
MSB 0 TBU RESET: UNCHANGED 31 32 TBL
SPR 268, 269

LSB 63
TB Time Base (Writing)
SPR 284, 285

31 32 LSB 63 TBL RESET: UNCHANGED
MSB 0 TBU
6.13.4.3 Time Base Reference Registers Two reference registers (TBREF0 and TBREF1) are associated with the lower part of the time base (TBL). Each is a 32-bit read/write register. Upon a match between the contents of TBL and the reference register, a maskable interrupt is generated. TBREF0 Time Base Reference Register 0
MSB 0 TBREF0 RESET:
0x2F C204
LSB 31
TBREF1 Time Base Reference Register 1

MSB 0 TBREF1 RESET:
0x2F C208
LSB 31
6.13.4.4 Time Base Control and Status Register The TBSCR is 16-bit read/write register. It controls the TB, decrementer count enable, and interrupt generation and is used for reporting the source of the interrupts. The register can be read anytime. A status bit is cleared by writing a one to it. (Writing a zero has no effect.) More than one bit can be cleared at a time.
MPC555
/ MPC556
MOTOROLA 6-31
USERS MANUAL

TBSCR Time Base Control and Status Register
MSB 0 1 2 3 TBIRQ PORESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 5 6 7 8 9 10 11 12 13
0x2F C200
14 TBF LSB 15 TBE
REFA REFB
RESERVED
REFAE REFBE
Table 6-16 TBSCR Bit Descriptions

Bit(s) 0:7 Name TBIRQ Description Time base interrupt request. These bits determine the interrupt priority level of the time base. Refer to 6.4 Interrupt Controller for interrupt level encodings. Reference A (TBREF0) interrupt status. 0 = No match detected 1 = TBREF0 value matches value in TBL Reference B (TBREF1) interupt status. 0 = No match detected 1 = TBREF1 value matches value in TBL Reserved Reference A (TBREF0) interrupt enable. If this bit is set, the time base generates an interrupt when the REFA bit is set. Reference B (TBREF1) interrupt enable. If this bit is set, the time base generates an interrupt when the REFB bit is set. Time base freeze. If this bit is set, the time base and decrementer stop while FREEZE is asserted. Time base enable 0 = Time base and decrementer are disabled 1 = Time base and decrementer are enabled
REFA
9 10:11 12 13 14
REFB REFAE REFBE TBF
15
TBE
6.13.4.5 Real-Time Clock Status and Control Register The RTCSC is used to enable the different RTC functions and to report the source of the interrupts. The register can be read anytime. A status bit is cleared by writing it to a one. (Writing a zero does not affect a status bits value.) More than one status bit can be cleared at a time. This register is locked after RESET. Unlocking is accomplished by writing 0x55CCAA33 to its associated key register. See 8.9.3.2 Keep Alive Power Registers Lock Mechanism. RTCSC Real-Time Clock Status and Control Register
MSB 0 1 2 3 4 5 6 7 8 SEC 9 ALR 10 Reserved 11 4M 12 SIE 13 ALE
0x2F C220
14 RTF LSB 15 RTE
RTCIRQ RESET: 0 0 0 0 0 0 0 0
MPC555
/ MPC556
MOTOROLA 6-32
USERS MANUAL

Table 6-17 RTCSC Bit Descriptions
Bit(s) 0:7 8 9 10 11 12 Name RTCIRQ SEC ALR 4M SIE ALE RTF RTE Description Real-time clock interrupt request. Thee bits determine the interrupt priority level of the RTC. Refer to 6.4 Interrupt Controller for interrupt level encodings. Once per second interrupt. This status bit is set every second. It should be cleared by the software. Alarm interrupt. This status bit is set when the value of the RTC equals the value programmed in the alarm register. Reserved Real-time clock source 0 = RTC assumes that it is driven by 20 MHz to generate the seconds pulse. 1 = RTC assumes that it is driven by 4 MHz Second interrupt enable. If this bit is set, the RTC generates an interrupt when the SEC bit is set. Alarm interrupt enable. If this bit is set, the RTC generates an interrupt when the ALR bit is set. Real-time clock freeze. If this bit is set, the RTC stops while FREEZE is asserted. Real-time clock enable 0 = RTC is disabled 1 = RTC is enabled
13 14 15
6.13.4.6 Real-Time Clock Register (RTC) The real-time clock register is a 32-bit read write register. It contains the current value of the real-time clock. A write to the RTC resets the seconds timer to zero. This register is locked after RESET. Unlocking is accomplished by writing 0x55CCAA33 to its associated key register. See 8.9.3.2 Keep Alive Power Registers Lock Mechanism. RTC Real-Time Clock Register
MSB 0 RTC RESET: UNCHANGED
0x2F C224
LSB 31
6.13.4.7 Real-Time Clock Alarm Register (RTCAL) The RTCAL is a 32-bit read/write register. When the value of the RTC is equal to the value programmed in the alarm register, a maskable interrupt is generated. The alarm interrupt will be generated as soon as there is a match between the ALARM field and the corresponding bits in the RTC. The resolution of the alarm is 1 sec. This register is locked after RESET. Unlocking is accomplished by writing 0x55CCAA33 to its associated key register. See 8.9.3.2 Keep Alive Power Registers Lock Mechanism. RTCAL Real-Time Clock Alarm Register
MSB 0 ALARM RESET: UNCHANGED
0x2F C22C
LSB 31
MPC555
/ MPC556
MOTOROLA 6-33
USERS MANUAL

6.13.4.8 Periodic Interrupt Status and Control Register (PISCR) The PISCR contains the interrupt request level and the interrupt status bit. It also contains the controls for the 16 bits to be loaded into a modulus counter. This register can be read or written at any time. PISCR Periodic Interrupt Status and Control Register
MSB 0 1 2 3 PIRQ HARD RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 5 6 7 8 PS 9 10 11 12 13 PIE
0x2F C240
14 PITF LSB 15 PTE
RESERVED
Table 6-18 PISCR Bit Descriptions

Bit(s) 0:7 Name PIRQ Description Periodic interrupt request. These bits determine the interrupt priority level of the PIT. Refer to 6.4 Interrupt Controller for interrupt level encodings. Periodic interrupt status. This bit is set if the PIT issues an interrupt. The PIT issues an interrupt after the modulus counter counts to zero. PS can be negated by writing a one to it. A write of zero has no affect. Reserved Periodic interrupt enable. If this bit is set, the time base generates an interrupt when the PS bit is set. PIT freeze. If this bit is set, the PIT stops while FREEZE is asserted. Periodic timer enable 0 = PIT stops counting and maintains current value 1 = PIT continues to decrement
8 9:12 13 14 15
PS PIE PITF PTE
6.13.4.9 Periodic Interrupt Timer Count Register (PITC) The PITC register contains the 16 bits to be loaded in a modulus counter. This register is readable and writable at any time. PITC Periodic Interrupt Timer Count
MSB 0 1 2 3 4 5 6 7 PITC RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 9 10 11 12 13
0x2F C244
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MPC555
/ MPC556
MOTOROLA 6-34
USERS MANUAL

Table 6-19 PITC Bit Descriptions
Bit(s) 0:15 16:31 Name PITC Description Periodic interrupt timing count. This field contains the 16-bit value to be loaded into the modulus counter that is loaded into the periodic timer. This register is readable and writeable at any time. Reserved
6.13.4.10 Periodic Interrupt Timer Register (PITR) The periodic interrupt register is a read-only register that shows the current value in the periodic interrupt down counter. Read or writing this register does not affect the register. PITR Periodic Interrupt Timer Register 0x2F C248
8 PIT RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 10 11 12 13 14 15
MSB 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 6-20 PIT Bit Descriptions

Bit(s) 0:15 16:31 Name PIT Description Periodic interrupt timing count This field contains the current count remaining for the periodic timer. Writes have no effect on this field. Reserved
MPC555
/ MPC556
MOTOROLA 6-35
USERS MANUAL

6.13.5 General-Purpose I/O Registers 6.13.5.1 SGPIO Data Register 1 (SGPIODT1) SGPIODT1 SGPIO Data Register 1
MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13
0x2F C024
14 15
SGPIOD[0:7] RESET: 0 0 0 0 0 0 0 0 0 0 0
SGPIOD[8:15]
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
SGPIOD[16:23] RESET: 0 0 0 0 0 0 0 0 0 0 0
SGPIOD[24:31]
Table 6-21 SGPIODT1 Bit Descriptions

Bit(s) 0:7 Name SGPIOD[0:7] Description SIU general-purpose I/O Group D[0:7]. This 8-bit register controls the data of general-purpose I/O pins SGPIOD[0:7]. The direction (input or output) of this group of pins is controlled by the GDDR0 bit in the SGPIO control register.
8:15
SIU general-purpose I/O Group D[8:15]. This 8-bit register controls the data of general-purSGPIOD[8:15] pose I/O pins SGPIOD[8:15]. The direction (input or output) of this group of pins is controlled by the GDDR1 bit in the SGPIO control register. SGPIOD[16:23] SIU general-purpose I/O Group D[16:23]. This 8-bit register controls the data of the general-purpose I/O pins SGPIOD[16:23]. The direction (input or output) of this group of pins is controlled by the GDDR2 bit in the SGPIO control register SIU general-purpose I/O Group D[24:31]. This 8-bit register controls the data of the general-purpose I/O pins SGPIOD[24:31]. The direction of SGPIOD[24:31] is controlled by eight dedicated direction control signals SDDRD[24:31]. Each pin in this group can be configured separately as general-purpose input or output.
16:23
24:31
SGPIOD[24:31]
6.13.5.2 SGPIO Data Register 2 (SGPIODT2) SGPIODT2 SGPIO Data Register 2

MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13
0x2F C028
14 15
SGPIOC[0:7] RESET: 0 0 0 0 0 0 0 0 0 0 0
SGPIOA[8:15]
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
SGPIOA[16:23] RESET: 0 0 0 0 0 0 0 0 0 0 0
SGPIOA[24:31]
MPC555
/ MPC556
MOTOROLA 6-36
USERS MANUAL

Table 6-22 SGPIODT2 Bit Descriptions
Bit(s) Name Description SIU general-purpose I/O Group C[0:7]. This 8-bit register controls the data of the generalpurpose I/O pins SGPIOC[0:7]. The direction of SGPIOC[0:7] is controlled by 8 dedicated direction control signals SDDRC[0:7] in the SGPIO control register. Each pin in this group can be configured separately as general-purpose input or output. NOTE: Bit 0 controls SGPIOC0, bit 1 controls SGPIOC1, etc. 8:15 SIU general-purpose I/O Group A[8:15]. This 8-bit register controls the data of the generalSGPIOA[8:15] purpose I/O pins SGPIOA[8:15]. The GDDR3 bit in the SGPIO control register configures these pins as a group as general-purpose input or output. SGPIOA [16:23] SGPIOA [24:31] SIU general-purpose I/O Group A[16:23]. This 8-bit register controls the data of the general-purpose I/O pins SGPIOA[16:23]. The GDDR4 bit in the SGPIO control register configures these pins as a group as general-purpose input or output. SIU general-purpose I/O Group A[24:31]. This 8-bit register controls the data of the general-purpose I/O pins SGPIOA[24:31]. The GDDR5 bit in the SGPIO control register configures these pins as a group as general-purpose input or output.
0:7
SGPIOC[0:7]
16:23
24:31
6.13.5.3 SGPIO Control Register (SGPIOCR) SGPIOCR SGPIO Control Register

MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13
0x2F C02C
14 15
SDDRC[0:7] RESET: 0 0 0 0 0 0 0 0 0 0 0
RESERVED
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
GDDR GDDR GDDR GDDR GDDR GDDR 0 1 2 3 4 5 RESET: 0 0 0 0 0 0
RESERVED
SDDRD[24:31]
Table 6-23 SGPIOCR Bit Descriptions

Bit(s) 0:7 8:15 16 17 18 19 20 21 22:23 24:31 Name SDDRC[0:7] GDDR0 GDDR1 GDDR2 GDDR3 GDDR4 GDDR5 SDDRD [24:31] Description SGPIO data direction for SGPIOC[0:7]. Each SDDR bit zero to seven controls the direction of the corresponding SGPIOC pin zero to seven Reserved Group data direction for SGPIOD[0:7] Group data direction for SGPIOD[8:15] Group data direction for SGPIOD[16:23] Group data direction for SGPIOA[8:15] Group data direction for SGPIOA[16:23] Group data direction for SGPIOA[24:31] Reserved SGPIO data direction for SGPIOD[24:31]. Each SDDRD bit 24:31 controls the direction of the corresponding SGPIOD pin [24:31].
MPC555
/ MPC556
MOTOROLA 6-37
USERS MANUAL

Table 6-24 describes the bit values for data direction control. Table 6-24 Data Direction Control
SDDR/GDDR 0 1 Operation SGPIO configured as input SGPIO configured as output
MPC555
/ MPC556
MOTOROLA 6-38
USERS MANUAL
SECTION 7 RESET
This section describes the MPC555 / MPC556 reset sources, operation, control, and status. 7.1 Reset Operation The MPC555 / MPC556 has several inputs to the reset logic which include the following:
Power on reset External hard reset pin (HRESET) External soft reset pin (SRESET) Loss of lock On-chip clock switch Software watchdog reset Checkstop reset Debug port hard reset Debug port soft reset JTAG reset All of these reset sources are fed into the reset controller. The control logic determines the cause of the reset, synchronizes it if necessary, and resets the appropriate logic modules, depending on the source of the reset. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only on hard reset. External soft reset initializes internal logic while maintaining system configuration. The reset status register (RSR) reflects the most recent source to cause a reset. 7.1.1 Power On Reset The power-on reset pin, PORESET, is an active low input. In a system with powerdown low-power mode, this pin should be activated only as a result of a voltage failure in the KAPWR pin. After detecting the assertion of PORESET, the MPC555 / MPC556 enters the power-on reset state. During this state the MODCK[1:3] signals determine the oscillator frequency, PLL multiplication factor, and the PITRCLK and TMBCLK clock sources. In addition, the MPC555 / MPC556 asserts the SRESET and HRESET pins. The PORESET pin should be asserted for a minimum time of 100,000 cycles of clock oscillator after a valid level has been reached on the KAPWR supply. After detecting the assertion of PORESET, the MPC555 / MPC556 remains in the power-on reset state until the last of the following two events occurs: The Internal PLL enters the lock state and the system clock is active. The PORESET pin is negated.
MPC555 / MPC556 USERS MANUAL RESET MOTOROLA 7-1

If the MPC555 / MPC556 is in single-chip mode and limp mode is enabled, the internal PLL is not required to be locked before the chip exits power-on reset. After exiting the power-on reset state, the MCU continues to drive the HRESET and SRESET pins for 512 system clock cycles. When the timer expires (after 512 cycles), the configuration is sampled from data bus pins, if required (see 7.5.1 Hard Reset Configuration) and the MCU stops driving the HRESET and SRESET pins. In addition, the internal MODCK[1:3] values are sampled. The PORESET pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected. The internal PORESET signal asserts only if the PORESET pin asserts for more than 100 ns. 7.1.2 Hard Reset HRESET (hard reset) is an active low, bi-directional I/O pin. The MPC555 / MPC556 can detect an external assertion of HRESET only if it occurs while the MCU is not asserting reset. When the MPC555 / MPC556 detects assertion of the external HRESET pin or a cause to assert the internal HRESET line, is detected the chip starts to drive the HRESET and SRESET for 512 cycles. When the timer expires (after 512 cycles) the configuration is sampled from data pins (refer to 7.5.1 Hard Reset Configuration) and the chip stops driving the HRESET and SRESET pins. An external pull-up resistor should drive the HRESET and SRESET pins high. After detecting the negation of HRESET or SRESET, the MCU waits 16 clock cycles before testing the presence of an external hard or soft reset. The HRESET pin has a glitch detector to ensure that low spikes of less than 20 ns are rejected. The internal HRESET will be asserted only if HRESET is asserted for more than 100 ns. The HRESET is an open collector type pin. 7.1.3 Soft Reset SRESET (soft reset) is an active low, bi-directional I/O pin. The MPC555 / MPC556 can only detect an external assertion of SRESET if it occurs while the MPC555 / MPC556 is not asserting reset. When the MPC555 / MPC556 detects the assertion of external SRESET or a cause to assert the internal SRESET line, the chip starts to drive the SRESET for 512 cycles. When the timer expires (after 512 cycles) the debug port configuration is sampled from the DSDI and DSCK pins and the chip stops driving the SRESET pin. An external pullup resistor should drive the SRESET pin high. After the MPC555 / MPC556 detects the negation of SRESET, it waits 16 clock cycles before testing the presence of an external soft reset.
MPC555
/ MPC556
RESET
MOTOROLA 7-2
USERS MANUAL

7.1.4 Loss of Lock If the PLL detects a loss of lock, erroneous external bus operation will occur if synchronous external devices use the MPC555 / MPC556 input clock. Erroneous operation could also occur if devices with a PLL use the MPC555 / MPC556 CLKOUT signal. This source of reset can be optionally asserted if the LOLRE bit in the PLL, low-power, and reset control register (PLPRCR) is set. The enabled PLL loss of lock event generates an internal hard reset sequence. Refer to SECTION 8 CLOCKS AND POWER CONTROL for more information on loss of lock. 7.1.5 On-Chip Clock Switch If the system clocked is switched to the backup clock or switched from backup clock to another clock source an internal hard reset sequence is generated. Refer to SECTION 8 CLOCKS AND POWER CONTROL. 7.1.6 Software Watchdog Reset When the MPC555 / MPC556 software watchdog counts to zero, a software watchdog reset is asserted. The enabled software watchdog event generates an internal hard reset sequence. 7.1.7 Checkstop Reset When the RCPU enters a checkstop state, and the checkstop reset is enabled (the CSR bit in the PLPRCR is set), a checkstop reset is asserted. The enabled checkstop event generates an internal hard reset sequence. Refer to the RCPU Reference Manual (RCPURM/AD) for more information. 7.1.8 Debug Port Hard Reset When the development port receives a hard reset request from the development tool, an internal hard reset sequence is generated, see SECTION 8 CLOCKS AND POWER CONTROL. In this case the development tool must reconfigure the debug port. Refer to SECTION 21 DEVELOPMENT SUPPORT for more information. 7.1.9 Debug Port Soft Reset When the development port receives a soft reset request from the development tool, an internal soft reset sequence is generated, see SECTION 8 CLOCKS AND POWER CONTROL. In this case the development tool must reconfigure the debug port. Refer to SECTION 21 DEVELOPMENT SUPPORT for more information. 7.1.10 JTAG Reset When the JTAG logic asserts the JTAG soft reset signal, an internal soft reset sequence is generated, see SECTION 8 CLOCKS AND POWER CONTROL. Refer to SECTION 22 IEEE 1149.1-COMPLIANT INTERFACE (JTAG) for more information. 7.2 Reset Actions Summary Table 7-1 summarizes the action taken for each reset.
MPC555
/ MPC556
RESET
MOTOROLA 7-3
USERS MANUAL

Table 7-1 Reset Action Taken For Each Reset Cause
Reset Logic and System PLL ConfiguraStates tion Reset Reset Yes Yes Clock Module Reset Yes Debug HRESET Port Pin Driven Configuration Yes Yes Other Internal Logic Reset Yes SRESET Pin Driven Yes
Reset Source
Power On Reset Hard Reset Sources External Hard Reset Loss of Lock On-Chip Clock Switch Illegal Low-Power Mode Software Watchdog Checkstop Debug Port Hard Reset
No
Yes
Yes
Yes
Yes
Yes
Yes
Soft Reset Sources External Soft Reset Debug Port Soft Reset JTAG Reset
No
No
No
No
Yes
Yes
Yes
7.3 Data Coherency During Reset The MPC555 / MPC556 supports data coherency and avoids data corruption while reset. If a cycle is to be executed when detecting any SRESET or HRESET source, then the cycle will either complete or will not start before generating the corresponding reset control signal. There are reset sources, however, when the MPC555 / MPC556 generates an internal reset due to special internal situation where this protection is not supported. See 7.4 Reset Status Register. In the case of large operand size (32 or 16 bits) transaction to a smaller port size, the cycle is split into two 16-bit or four 8-bit cycles. In this case, data coherency is assured and data will not be corrupted. In the case where the core executes an unaligned load/store cycle which is broken down into multiple cycles, data coherency is NOT assured between these cycles (i.e., data could be corrupted). A contention on the data pins may occur while asserting external reset (EXT_RESET) if the data coherency mechanism is required, and thus enables a cycle to complete, while external hardware drives the data for the configuration word. See Table 7-2 for a description of the required EXT_RESET line source in a system. Table 7-2 Reset Configuration Word and Data Corruption/Coherency
Reset Driven HRESET SRESET HRESET & SRESET Reset to Use for Data Coherency (EXT_RESET) SRESET HRESET HRESET || SRESET Provided only one of them is driven into the MPC555 / MPC556 at a time Comments
MPC555
/ MPC556
RESET
MOTOROLA 7-4
USERS MANUAL

7.4 Reset Status Register All of the reset sources are fed into the reset controller. The 16-bit reset status register (RSR) reflects the most recent source, or sources, of reset. (Simultaneous reset requests can cause more than one bit to be set at the same time.) This register contains one bit for each reset source. A bit set to logic one indicates the type of reset that occurred. Once set, individual bits in the RSR remain set until software clears them. Can be cleared by writing a one to the bit. A write of zero has no effect on the bit. The register can be read at all times. The reset status register receives its default reset values during power-on reset. The RSR is powered by the KAPWR pin. RSR Reset Status Register 0x2F C288
6 DBSRS 7 8 9 ILBC 10 GPOR 11 GHRST 12 GSRS T 13 14 RESERVED 15
MSB 0 1 2 3 4 5 DBHRS
EHRS ESRS RESET: 0 0
LLRS SWRS CSRS
JTRS OCCS
Table 7-3 Reset Status Register Bit Descriptions

Bit(s) 0 Name EHRS1 External hard reset status 0 = No external hard reset has occurred 1 = An external hard reset has occurred External soft reset status 0 = No external soft reset has occurred 1 = An external soft reset has occurred Loss of lock reset status 0 = No enabled loss-of-lock reset has occurred 1 = An enabled loss-of-lock reset has occurred Software watchdog reset status 0 = No software watchdog reset has occurred 1 = A software watchdog reset has occurred Checkstop reset status 0 = No enabled checkstop reset has occurred 1 = An enabled checkstop reset has occurred Debug port hard reset status 0 = No debug port hard reset request has occurred 1 = A debug port hard reset request has occurred Debug port soft reset status 0 = No debug port soft reset request has occurred 1 = A debug port soft reset request has occurred JTAG reset status 0 = No JTAG reset has occurred 1 = A JTAG reset has occurred On-chip clock switch 0 = No on-chip clock switch reset has occurred 1 = An on-chip clock switch reset has occurred Description
ESRS1
LLRS
SWRS
CSRS
DBHRS
DBSRS
JTRS
OCCS
MPC555
/ MPC556
RESET
MOTOROLA 7-5
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Table 7-3 Reset Status Register Bit Descriptions (Continued)
Bit(s) Name Description Illegal bit change. This bit is set when the MPC555 / MPC556 changes any of the following bits when they are locked: LPM[0:1], locked by the LPML bit MF[0:11], locked by the MFPDL bit DIVF[0:4], locked by the MFPDL bit Glitch detected on PORESET pin. This bit is set when the PORESET pin is asserted for more than TBD ns 0 = No glitch was detected on the PORESET pin 1 = A glitch was detected on the PORESET pin Glitch detected on HRESET pin. This bit is set when the HRESET pin is asserted for more than TBD ns 0 = No glitch was detected on the HRESET pin 1 = A glitch was detected on the HRESET pin Glitch detected on SRESET pin. If the SRESET pin is asserted for more than TBD ns the GHRST bit will be set. If an internal or external SRESET is generated the SRESET pin is asserted and the GSRST bit will be set. The GSRST bit remains set until software clears it. The GSRST bit can be negated by writing a one to GSRST. A write of zero has no effect on this bit. 0 = No glitch was detected on SRESET pin 1 = A glitch was detected on SRESET pin. Reserved
ILBC
10
GPOR
11
GHRST
12
GSRST
13:15
NOTES: 1. In the USIU RSR, if both EHRS and ESRS are set, the reset source is internal. The EHRS and ESRS bits in RSR register are set for any internal reset source in addition to external HRESET and external SRESET events. If both internal and external indicator bits are set, then the reset source is internal.
7.5 Reset Configuration 7.5.1 Hard Reset Configuration When a hard reset event occurs, the MPC555 / MPC556 reconfigures its hardware system as well as the development port configuration The logical value of the bits that determine its initial mode of operation, are sampled from the following: The external data bus pins DATA[0:31] An internal default constant (0x0000 0000) An internal NVM register value (CMFCFIG) If at the sampling time (at HRESET negation) RSTCONF is asserted, then the configuration is sampled from the data bus. If RSTCONF is negated and a valid NVM value exists (CMFCFIG bit HC=0), then the configuration is sampled from the NVM register in the CMF module. If RSTCONF is negated and no valid NVM value exists (CMFCFIG bit HC=1), then the configuration word is sampled from the internal default. HC will be 1 if the internal flash is erased. Table 7-4 summarizes the reset configuration options. NOTE If the CMFCFIG reset config word is being used, then the flash is automatically enabled.
MPC555
/ MPC556
RESET
MOTOROLA 7-6
USERS MANUAL

Table 7-4 Reset Configuration Options
RSTCONF 0 1 1 Has Configuration (HC) x 0 1 Internal Configuration Word DATA[0:31] pins NVM flash EEPROM register (CMFCFIG) Internal data word default (0x0000 0000)
If the PRDS control bit in the PDMCR register is set and HRESET and RSTCONF are asserted, the MPC555 / MPC556 pulls the data bus low with a weak resistor. The user can overwrite this default by driving the appropriate bit high. See Figure 7-1 for the basic reset configuration scheme.
Has Configuration HC
Config. Word MUX
32 32 32 OE
CMF
Dx (Data line)
Data Coherency INT_RESET
EXT_RESET (See Table 7-2) HRESET/SRESET RSTCONF
MPC555
Figure 7-1 Reset Configuration Basic Scheme During the assertion of the PORESET input signal, the chip assumes the default reset configuration. This assumed configuration changes if the input signal RSTCONF is asserted when the PORESET is negated or the CLKOUT starts to oscillate. To ensure
MPC555
/ MPC556
RESET
MOTOROLA 7-7
USERS MANUAL

that stable data is sampled, the hardware configuration is sampled every eight clock cycles on the rising edge of CLKOUT with a double buffer. The setup time required for the data bus is approximately 15 cycles, and the maximum rise time of HRESET should be less than 6 clock cycles. In systems where an external reset configuration word and the TEXP output function are both required, RSTCONF should be asserted until SRESET is negated. Figure 7-2 to Figure 7-5 provide sample reset configuration timings.
CLKOUT
PORESET
Internal PORESET
HRESET
RSTCONF
Tsup
Internal DATA[0:31]
Default
RSTCONF Controlled
Figure 7-2 Reset Configuration Sampling Scheme For Short PORESET Assertion, Limp Mode Disabled
MPC555
/ MPC556
RESET
MOTOROLA 7-8
USERS MANUAL
CLKOUT (Backup Clock) PORESET
Internal PORESET
HRESET SRESET
RSTCONF Internal DATA(0:31)
Tsup
Default
RSTCONF Controlled
Figure 7-3 Reset Configuration Timing for Short PORESET Assertion, Limp Mode Enabled
CLKOUT
PORESET
PLL lock
Internal PORESET
HRESET
RSTCONF
Tsup
Internal DATA[0:31]
Default
RSTCONF Controlled
Figure 7-4 Reset Configuration Timing for

MPC555
/ MPC556
RESET
MOTOROLA 7-9
USERS MANUAL

Long PORESET Assertion, Limp Mode Disabled
MPC555
/ MPC556
RESET
MOTOROLA 7-10
USERS MANUAL
MPC555
USERS MANUAL
/ MPC556 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RESET CONFIGURATION WORD Tsup = Minimum Setup time of reset recognition = 15 clocks Sample Data Configuration
15
16
CLKOUT
HRESET
RSTCONF
Maximum time of reset recognition (maximum rise time - up to 6 clocks)
Data
RESET
Figure 7-5 Reset Configuration Sampling Timing Requirements
Internal reset
Sample Data Configuration
MOTOROLA
7-11

7.5.2 Hard Reset Configuration Word The hard reset configuration word, which is sampled from the internal data bus on the negation of HRESET, is shown below. The reset configuration word is not a register in the memory map. Most of the bits in the configuration are located in registers in the USIU. The user should refer to the appropriate register definition for a detailed description of each control bit. Hard Reset Configuration Word
MSB 0 EARB 1 IP 2 BDRV 3 BDIS 4 BPS 5 6 7 Reserved 8 9 10 DBGC 11 12 13 14 15 Reserved
DBPC ATWC
EBDF
DEFAULT: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LSB 16 PRPM DEFAULT: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 SC 18 19 ETRE 20 FLEN 21

EN_ COMP
22
23
24
25
26
27
28
29 ISB
30
31 DME
EXC_ RECOMP SERVED
Reserved
Table 7-5 Hard Reset Configuration Word Bit Descriptions

Bit(s) Name Description External arbitration. Refer to 6.13.1.1 SIU Module Configuration Register for a detailed bit definition. 0 = Internal arbitration is performed 1 = External arbitration is assumed Initial interrupt prefix. This bit defines the initial value of the MSR[IP] bit immediately after reset. MSR[IP] defines the interrupt table location. 0 = MSR[IP] = 0 after reset 1 = MSR[IP] = 1 after reset Bus pins drive strength. This bit determines the driving capability of the bus pins (address, data, and control) and the CLKOUT pin. For details, refer to description of the COM bits in 8.12.1 System Clock Control Register (SCCR). The default value is full drive strength for the bus pins and CLKOUT. 0 = Full drive 1 = Reduced drive External boot disable. If a write to the OR0 register occurs after reset, this bit definition is ignored. 0 = Memory controller bank 0 is active and matches all addresses immediately after reset 1 = Memory controller is not activated after reset. Boot port size. If a write to the OR0 register occurs after reset, this field definition is ignored. 00 = 32-bit port (default) 01 = 8-bit port 10 = 16-bit port 11 = Reserved Reserved Debug pins configuration. See 6.13.1.1 SIU Module Configuration Register for this field definition. The default value is for these pins to function as VFLS[0:1], BI, BR, BG, and BB.
EARB
IP
BDRV
BDIS
4:5
BPS
6:8 9:10
DBGC
MPC555
/ MPC556
RESET
MOTOROLA 7-12
USERS MANUAL

Table 7-5 Hard Reset Configuration Word Bit Descriptions (Continued)
Bit(s) 11 12 Name DBPC ATWC Description Debug port pins configuration. See 6.13.1.1 SIU Module Configuration Register for this field definition. The default value is for these pins to function as development support pins. Address type write-enable configuration. Refer to 6.13.1.1 SIU Module Configuration Register for this field definition. The default value is for these pins to function as write-enable pins. External bus division factor. This field defines the initial value of the external bus frequency. Refer to 8.12.1 System Clock Control Register (SCCR) for details. The default value is that CLKOUT frequency is equal to that of the internal clock (divide by one). Reserved Peripheral mode enable. This bit determines whether the chip is in peripheral mode. Refer to 6.13.1.3 External Master Control Register (EMCR) for details. The default value is that peripheral mode is not enabled. Single chip select. Refer to 6.13.1.1 SIU Module Configuration Register for details. 00 = Extended chip, 32 bits data 01 = Extended chip, 16 bits data 10 = Single chip and show cycles (address) 11 = Single chip Exception table relocation enable. This field defines whether the exception table relocation feature in the BBC is enabled or disabled. The default state is disabled. Refer to SECTION 4 BURST BUFFER for details. Flash Enable This field determines whether the on-chip flash memory is enabled or disabled out of reset. The default state is disabled, which means that by default, the boot is from external memory. 0 = Flash disabled boot is from external memory 1 = Flash enabled Enable Compression This bit enables the operation of the MPC555 / MPC556 with compressed code. The default state is disabled. See Table 4-8. Exception Compression This bit determines the operation of the MPC555 with exceptions. If this bit is set, than the MPC555 assumes that ALL the exception routines are in compressed code. The default indicates the exceptions are all non-compressed. See Table 4-8. This bit should not be high in the reset configuration word. Reserved Initial internal space base select. This field defines the initial value of the ISB field in the IMMR register. Refer to 6.13.1.2 Internal Memory Map Register for details. The default state is that the internal memory map is mapped to start at address 0x0000 0000. Dual mapping enable. This bit determines whether dual mapping of the flash EEPROM module is enabled. Refer to 10.8.5 Dual Mapping Base Register (DMBR) for details.The default value is for dual mapping to be disabled. 0 = Dual mapping disabled 1 = Dual mapping enabled
13:14 15 16
EBDF PRPM
17:18
SC
19
ETRE
20
FLEN
21
EN_ COMP1 EXC_ COMP1 ISB
22 23 24:27 28:30
31
DME
NOTES: 1. This bit is available only on the MPC555 / MPC556.
7.5.3 Soft Reset Configuration When a soft reset event occurs, the MPC555 / MPC556 reconfigures the development port. Refer to SECTION 21 DEVELOPMENT SUPPORT for details.
MPC555
/ MPC556
RESET
MOTOROLA 7-13
USERS MANUAL
MPC555
/ MPC556
RESET
MOTOROLA 7-14
USERS MANUAL
SECTION 8 CLOCKS AND POWER CONTROL

8.1 Overview The main timing reference for the MPC555 / MPC556 can monitor any of the following: A crystal with a frequency of four MHz or 20 MHz An external frequency source with a frequency of 4 MHz An external frequency source at the system frequency The system operating frequency is generated through a programmable phase-locked loop, the system PLL (SPLL). The SPLL is programmable in integer multiples of the input oscillator frequency to generate the internal (VCO/2) operating frequency. A predivider before the SPLL enables the user to divide the high frequency crystal oscillator. The SPLL VCO is twice the system frequency. The internal operating SPLL frequency should be at least 30 MHz. It can be divided by a power-of-two divider to generate the system operating frequencies. In addition to the system clock, the clocks submodule provides the following: TMBCLK to the time base (TB) and decrementer (DEC) PITRTCLK to the periodic interrupt timer (PIT) and real-time clock (RTC) The oscillator, TB, DEC, RTC, and the PIT are powered from the keep alive power supply (KAPWR) pin. This allows the counters to continue to count (increment/decrement) at the oscillator frequency even when the main power to the MCU is off. While the power is off, the PIT may be used to signal to the power supply IC to enable power to the system at specific intervals. This is the power-down wake-up feature. When the chip is not in power-down low-power mode, the KAPWR is powered to the same voltage value as the voltage of the I/O buffers and logic. The MPC555 / MPC556 clock module consists of the main crystal oscillator (OSCM), the SPLL, the low-power divider, the clock generator, the system low-power control block, and the limp mode control block. The clock module receives control bits from the system clock control register (SCCR), change of lock interrupt register (COLIR), the low-power and reset-control register (PLPRCR), and the PLL. All of the MPC555 peripherals on the IMB bus derive its clock timing from the UIMB module. The UIMB runs on the main system clock, but can divide the system frequency in half. See 12.3 Clock Module. Figure 8-1 illustrates the functional block diagram of the clock unit.
CLOCKS AND POWER CONTROL
MOTOROLA 8-1
MODCK[1:3]
VDDSYN
EXTCLK
2:1 MUX VCOOUT 2:1 MUX SPLL
VSSSYN Lock
XFC
TBCLK
GCLK2
3:1 MUX (/4 or /16)
Low Power Dividers (1/2N) Clock Drivers
GCLK1 / GCLK2 SYSTEM CLOCK GCLK1C / GCLK2C SYSTEM CLOCK TO RCPU AND BBC
Back_Up Clock Oscillator Loss Detector
System Low-Power Control
CLKOUT Drivers ENGCLK
TMBclk Driver 3:1 MUX RTC / PIT Clock and DRIVER Main Clock Oscillator EXTAL /4 or /256
TMBCLK
PITRTCLK
XTAL
Figure 8-1 Clock Unit Block Diagram
MPC555
/ MPC556
MOTOROLA 8-2
USERS MANUAL

8.2 System Clock Sources The system clock can be provided by the main system oscillator (OSCM), an external clock input, or the backup clock (BUCLK) on-chip ring oscillator, see Figure 8-2. The OSCM uses either a 4-MHz or 20-MHz crystal to generate the PLL reference clock. When the main system oscillator output is the timing reference to the system PLL, skew elimination between the XTAL/EXTAL pins and CLKOUT is not guaranteed. The external clock input receives a clock signal from an external source. The clock frequency must be either in the range of 3 MHz 5 MHz or at the system frequency of at least 15 MHz (1:1 mode). When the external clock input is the timing reference to the system PLL skew elimination between the EXTCLK pin and the CLKOUT is less than 1 ns. The backup clock on-chip ring oscillator enables the MCU to function with a less precise clock. When operating from the backup clock, the MCU is in limp mode. This enables the system to continue minimum functionality until the system is fixed. The BUCLK frequency is approximately 7 MHz (see APPENDIX G ELECTRICAL CHARACTERISTICS for the complete frequency range). For normal operation, at least one clock source (EXTCLK or OSCM) must be active. A configuration with both clock sources active is possible as well. At this configuration EXTCLK provides the OSCCLK and OSCM provides the PITRTCLK. The input of an unused timing reference (EXTCLK or EXTAL) must be grounded.
XTAL EXTAL
1 M*
CL
CL
*Resistor is not currently required on the board but space should be available for its addition in the future.
Figure 8-2 Main System Oscillator (OSCM) 8.3 System PLL The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock input, a feature which offers two benefits. Lower frequency clock input reduces the overall electromagnetic interference generated by the system, and the ability to oscillate at different frequencies reduces cost by eliminating the need to add an additional oscillator to a system. The PLL can perform the following functions: Frequency multiplication
MPC555
/ MPC556
MOTOROLA 8-3
USERS MANUAL

Skew elimination Frequency division 8.3.1 Frequency Multiplication The PLL can multiply the input frequency by any integer between one and 4096. The multiplication factor depends on the value of the MF[0:11] bits in the PLPRCR register. While any integer value from one to 4096 can be programmed, the resulting VCO output frequency must be at least 15 MHz. The multiplication factor is set to a predetermined value during power-on reset as defined in Table 8-1. 8.3.2 Skew Elimination The PLL is capable of eliminating the skew between the external clock entering the chip (EXTCLK) and both the internal clock phases and the CLKOUT pin, making it useful for tight synchronous timings. Skew elimination is active only when the PLL is enabled and programmed with a multiplication factor of one or two (MF = 0 or 1). The timing reference to the system PLL is the external clock input. 8.3.3 Pre-Divider A pre-divider before the phase comparator enables additional system clock resolution when the crystal oscillator frequency is 20 MHz. The division factor is determined by the DIVF[0:4] bits in the PLPRCR. 8.3.4 PLL Block Diagram As shown in Figure 8-3, the reference signal, OSCCLK, goes to the phase comparator. The phase comparator controls the direction (up or down) that the charge pump drives the voltage across the external filter capacitor (XFC). The direction depends on whether the feedback signal phase lags or leads the reference signal. The output of the charge pump drives the VCO. The output frequency of the VCO is divided down and fed back to the phase comparator for comparison with the reference signal, OSCCLK. The MF values, zero to 4095, are mapped to multiplication factors of one to 4096. Note that when the PLL is operating in 1:1 mode (refer to Table 8-1), the multiplication factor is one (MF = 0). The PLL output frequency is twice the maximum system frequency. This double frequency is needed to generate GCLK1 and GCLK2 clocks. On power-up, with a four MHz or 20 MHz crystal and the default MF settings, System Frequency (FREQSYS) will be 40 MHz and the system clock will be 20 MHz. The equation for system frequency (FREQSYS) is shown below: System Frequency (FREQSYS) = OSCCLK DIVF + 1 x (MF + 1) x 2 / 2
NOTE When operating with the backup clock, the system clock (and CLKOUT) is one-half of the ring oscillator frequency. (i.e., the system clock is a nominal seven MHz). The time base and PIT clocks will be twice the system clock frequency.
MPC555
/ MPC556
MOTOROLA 8-4
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The PLL maximum lock time is determined by the input clock to the phase detector. The PLL locks within 500 input clock cycles. NOTE Upon initial system power up and after KAPWR is lost, an external circuit must assert power on reset (PORESET). If limp mode will be enabled during power-on reset, PORESET must be asserted for at least 100,000 cycles of input PLL clock after a valid level has been reached on the KAPWR supply. If limp mode will be disabled, PORESET should be asserted for approximately 3 s after a valid level has been reached on the KAPWR supply. Whenever power-on reset is asserted, the MF bits are set according to Table 8-1, and the DFNH and DFNL bits in SCCR are set to the value of 0 (1 and 2), respectively.
XFC
OSCCLK
Division Factor DIVF[0:4] Feedback
Phase Comparator
Up Down
Charge Pump
System Frequency (FREQSYS) VCO
2 2
VDDSYN / VSSSYN
Clock Delay
Multiplication Factor MF[0:11]
Figure 8-3 System PLL Block Diagram 8.3.5 PLL Pins The following pins are dedicated to the PLL operation: VDDSYN Drain voltage. This is the VDD dedicated to the analog PLL circuits. The voltage should be well-regulated and the pin should be provided with an extremely low impedance path to the VDD power rail. VDDSYN should be bypassed to VSSSYN by a 0.1 F capacitor located as close as possible to the chip package. VSSSYN Source voltage. This is the VSS dedicated to the analog PLL circuits. The pin should be provided with an extremely low impedance path to ground. VSSSYN should be bypassed to VDDSYN by a 0.1 F capacitor located as close as possible to the chip package. XFC External filter capacitor. XFC connects to the off-chip capacitor for the PLL filter. One terminal of the capacitor is connected to XFC, and the other terminal is connected to VDDSYN. The off-chip capacitor must have the following values:
MPC555
/ MPC556
MOTOROLA 8-5
USERS MANUAL

0 < MF + 1 < 4 MF + 1 4 (680 x (MF + 1) 120) pF 1100 x (MF + 1) pF
Where MF = the value stored on MF[0:11]. This is one less than the desired frequency multiplication factor.
8.4 System Clock During PLL Loss of Lock At reset, until the SPLL is locked, the SPLL output clock is disabled. During normal operation (once the PLL has locked), either the oscillator or an external clock source is generating the system clock. In this case, if loss of lock is detected and the LOLRE (loss of lock reset enable) bit in the PLPRCR is cleared, the system clock source continues to function as the PLLs output clock. The USIU timers can operate with the input clock to the PLL, so that these timers are not affected by the PLL loss of lock. Software can use these timers to measure the loss-of-lock period. If the timer reaches the user-preset software criterion, the MCU can switch to the backup clock by setting the switch to backup clock (STBUC) bit in the SCCR, provided the limp mode enable (LME) bit in the SCCR is set. If loss of lock is detected during normal operation, assertion of HRESET (for example, if LOLRE is set) disables the PLL output clock until the lock condition is met. During hard reset, the STBUC bit is set as long as the PLL lock condition is not met and clears when the PLL is locked. If STBUC and LME are both set, the system clock switches to the backup clock, and the chip operates in limp mode until STBUC is cleared. Every change in the lock status of the PLL can generate a maskable interrupt. NOTE When the VCO is the system clock source, chip operation is unpredictable while the PLL is unlocked. Note further that a switch to the backup clock is possible only if the LME bit in the SCCR is set. 8.5 Low-Power Divider The output of the PLL is sent to a low-power divider block. (In limp mode the BUCLK is sent to a low-power divider block.) This block generates all other clocks in normal operation, but has the ability to divide the output frequency of the VCO before it generates the general system clocks sent to the rest of the MPC555 / MPC556. The PLL System Frequency (FREQSYS) is always divided by at least 2. The purpose of the low-power divider block is to allow the user to reduce and restore the operating frequencies of different sections of the MPC555 / MPC556 without losing the PLL lock. Using the low-power divider block, the user can still obtain full chip operation, but at a lower frequency. This is called gear mode. The selection and speed of gear mode can be changed at any time, with changes occurring immediately. The low-power divider block is controlled in the system clock control register (SCCR). The default state of the low-power divider is to divide all clocks by one. Thus, for a 40MHz system, the general system clocks are each 40 MHz.
MPC555
/ MPC556
MOTOROLA 8-6
USERS MANUAL

8.6 MPC555 / MPC556 Internal Clock Signals The internal clocks generated by the clocks module are shown in Figure 8-4. The clocks module also generates the CLKOUT and ENGCLK external clock signals. The PLL synchronizes these signals to each other. The PITRTCLK frequency and source are specified by the RTDIV and RTSEL bits in the SCCR. When the backup clock is functioning as the system clock, the backup clock is automatically selected as the time base clock source and is twice the MPC555 / MPC556 system clock.
GCLK1 System Clock GCLK2
GCLK1_50 (EBDF = 00) GCLK2_50 (EBDF = 00) CLKOUT (EBDF = 00) GCLK1_50 (EBDF = 01) GCLK2_50 (EBDF = 01) CLKOUT (EBDF = 01) T1
T2
T3
T4
Figure 8-4 MPC555 / MPC556 Clocks Note that GCLK1_50, GCLK2_50, and CLKOUT can have a lower frequency than GCLK1 and GCLK2. This is to enable the external bus operation at lower frequencies (controlled by EBDF in the SCCR). GCLK2_50 always rises simultaneously with
MPC555
/ MPC556
MOTOROLA 8-7
USERS MANUAL

GCLK2. When DFNH = 0, GCLK2_50 has a 50% duty cycle. With other values of DFNH or DFNL, the duty cycle is less than 50%. Refer to Figure 8-7. GCLK1_50 rises simultaneously with GCLK1. When the MPC555 / MPC556 is not in gear mode, the falling edge of GCLK1_50 occurs in the middle of the high phase of GCLK2_50. EBDF determines the division factor between GCLK1/GCLK2 and GCLK1_50/GCLK2_50. During power-on reset, the MOCCK1, MODCK2, and MODCK3 pins determine the clock source for the PLL and the clock drivers. These pins are latched on the positive edge of PORESET. Their values must be stable as long as this line is asserted. The configuration modes are shown in Table 8-1. MODCK1 specifies the input source to the SPLL (OSCM or EXTCLK). MODCK1, MODCK2, and MODCK3 together determine the multiplication factor at reset and the functionality of limp mode.
If the configuration of PITRTCLK and TMBCLK and the SPLL multiplication factor is to remain unchanged in power-down low-power mode, the MODCK signals should not be sampled at wake-up from this mode. In this case the PORESET pin should remain negated and HRESET should be asserted during the power supply wake-up stage. When MODCK1 is cleared, the output of the main oscillator (OSCM) is selected as the input to the SPLL. When MODCK1 is asserted, the external clock input (EXTCLK) is selected as the input to the SPLL. In all cases, the system clock frequency (freqgclk2) can be reduced by the DFNH[0:2] bits in the SCCR. Note that freqgclk2(max) occurs when the DFNH bits are cleared. The TBS bit in the SCCR selects the time base clock to be either the SPLL input clock or GCLK2. When the backup clock is functioning as the system clock, the backup clock is automatically selected as the time base clock source. The PITRTCLK frequency and source are specified by the RTDIV and RTSEL bits in the SCCR. When the backup clock is functioning as the system clock, the backup clock is automatically selected as the time base clock source. When the PORESET pin is negated (driven to a high value), the MODCK1, MODCK2, and MODCK3 values are not affected. They remain the same as they were defined during the most recent power-on reset. Table 8-1 shows the clock configuration modes during power-on reset (PORESET asserted). NOTE The MODCK[1:3] are shared functions with IRQ[5:7]. If IRQ[5:7] are used as interrupts, the interrupt source should be removed during PORESET to insure the MODCK pins are in the correct state on the rising edge of PORESET.
MPC555
/ MPC556
MOTOROLA 8-8
USERS MANUAL

Table 8-1 Reset Clocks Source Configuration
Default Values @ PORESET MODCK[1:3] 000 001
1
LME 0 0
MF + 1 513 1
PITCLK Division 4 256
TMBCLK Division 4 16
SPLL Options Used for testing purposes. Normal operation, PLL enabled. Main timing reference is freq(OSCM) = 20 MHz. Limp mode disabled. Normal operation, PLL enabled. Main timing reference is freq(OSCM) = 4 MHz. Limp mode enabled. Normal operation, PLL enabled. Main timing reference is freq(OSCM) = 20 MHz. Limp mode enabled. Normal operation, PLL enabled. 1:1 Mode freqclkout(max) = freq(EXTCLK) Limp mode disabled. Normal operation, PLL enabled. Main timing reference is freq(EXTCLK) = 3-5 MHz. Limp mode disabled. Normal operation, PLL enabled. 1:1 Mode freqclkout(max) = freq(EXTCLK) Limp mode enabled.
010
256
011
256
16
100 101
256
16
110
256
111
256
16
NOTES: 1. For other implementations in the MPC500 family, MODCK2 could be inverted.
NOTE The reset value of the PLL pre-divider is 1. The values of the PITRTCLK clock division and TMBCLK clock division can be changed by software. The RTDIV bit value in the SCCR register defines the division of PITRTCLK. All possible combinations of the TMBCLK divisions are listed in Table 8-2. Table 8-2 TMBCLK Divisions
SCCR[TBS] 1 0 0 MF + 1 1, 2 >2 TMBCLK Division 16 16 4
8.6.1 General System Clocks The general system clocks (GCLK1C, GCLK2C, GCLK1, GCLK2, GCLK1_50, and GCLK2_50) are the basic clock supplied to all modules and sub-modules on the MPC555 / MPC556. GCLK1C and GCLK2C are supplied to the RCPU and to the BBC. GCLK1C and GCLK2C are stopped when the chip enters the doze-low power mode. GCLK1 and GCLK2 are supplied to the SIU and the clock module. The external bus clock GCLK2_50 is the same as CLKOUT. The general system clock defaults to VCO/
MPC555
/ MPC556
MOTOROLA 8-9
USERS MANUAL

2 = 20 MHz (assuming a 20-MHz system frequency) with default power-on reset MF values. The general system clock frequency can be switched between different values. The highest operational frequency can be achieved when the system clock frequency is determined by DFNH (CSRC bit in the PLPRCR is cleared) and DFNH = 0 (division by one). The general system clock can be operated at a low frequency (gear mode) or a high frequency. The DFNL bits in SCCR define the low frequency. The DFNH bits in SCCR define the high frequency. The frequency of the general system clock can be changed dynamically with the system clock control register (SCCR), as shown in Figure 8-5.
VCO/2 (e.g., 40 MHz) Normal
DFNH Divider
DFNH
O O General System Clock
DFNL Divider
DFNL
O
Low Power
Figure 8-5 General System Clocks Select The frequency of the general system clock can be changed on the fly by software. The user may simply cause the general system clock to switch to its low frequency. However, in some applications, there is a need for a high frequency during certain periods. Interrupt routines, for example, may require more performance than the low frequency operation provides, but must consume less power than in maximum frequency operation. The MPC555 / MPC556 provides a method to automatically switch between low and high frequency operation whenever one of the following conditions exists: There is a pending interrupt from the interrupt controller. This option is maskable by the PRQEN bit in the SCCR. The (POW) bit in the MSR is clear in normal operation. This option is maskable by the PRQEN bit in the SCCR. When neither of these conditions exists and the CSRC bit in PLPRCR is set, the general system clock switches automatically back to the low frequency. Abrupt changes in the divide ratio can cause linear changes in the operating currents of the MPC555 / MPC556. Insure that the proper power supply filtering is available to handle this change instantaneously. When the general system clock is divided, its duty cycle is changed. One phase remains the same (e.g., 12.5 ns @ 40 MHZ) while the other become longer. Note that CLKOUT does not have a 50% duty cycle when the general system clock is divided. The CLKOUT waveform is the same as that of GCLK2_50.
MPC555
/ MPC556
MOTOROLA 8-10
USERS MANUAL

GCLK1 Divide by 1 GCLK2 Divide by 1 GCLK1 Divide by 2 GCLK2 Divide by 2 GCLK1 Divide by 4 GCLK2 Divide by 4
Figure 8-6 Divided System Clocks Timing Diagram The system clocks GCLK1 and GCLK2 frequency is:
FREQsysmax FREQ sys = ------------------------------------------------------DFNH DFNL + 1 (2 )or ( 2 )

where FREQsysmax = System Frequency (FREQSYS)/2
Therefore, the complete equation for determining the system clock frequency is: OSCCLK DIVF + 1 (MF + 1) (2DFNH or 2DFNL + 1) 2 2
System Frequency (FREQSYS) =
The clocks GCLK1_50 and GCLK2_50 frequency is: FREQsysmax 1 FREQ50 = ------------------------------------------------------- -------------------------DFNH DFNL + 1 EBDF + 1 (2 )or ( 2 ) Figure 8-7 shows the timing of USIU clocks when DFNH = 1 or DFNL = 0.
MPC555
/ MPC556
MOTOROLA 8-11
USERS MANUAL
GCLK1
GCLK2
GCLK1_50 (EBDF = 00) GCLK2_50 (EBDF = 00) CLKOUT (EBDF = 00)
GCLK1_50 (EBDF = 01) GCLK2_50 (EBDF = 01) CLKOUT (EBDF = 01)
Figure 8-7 Clocks Timing For DFNH = 1 (or DFNL = 0) 8.6.2 CLKOUT CLKOUT has the same frequency as the general system clock (GCLK2_50). Unlike the main system clock GCLK1/GCLK2 however, CLKOUT (and GCLK2_50) represents the external bus clock, and thus will be one-half of the main system clock if the external bus is running at half speed (EBDF = 0b01). The CLKOUT frequency defaults to VCO/2. CLKOUT can drive full- or half-strength or be disabled. The drive strength is controlled in the system clock and reset-control register (SCCR). Disabling or decreasing the strength of CLKOUT can reduce power consumption, noise, and electromagnetic interference on the printed circuit board. When the PLL is acquiring lock, the CLKOUT signal is disabled and remains in the low state (provided that BUCS = 0). 8.6.3 Engineering Clock ENGCLK is an output clock with a 50% duty cycle. Its frequency defaults to VCO/1281, which is one-sixtyfourth of the main system frequency. ENGCLK frequency can be programmed to the main system frequency divided by a factor from one to 64, as controlled by the ENGDIV[0:5] bits in the SCCR. ENGCLK can drive full- or half-strength or be disabled (remaining in the high state). The drive strength is controlled by the EECLK[0:1] bits in the SCCR. Disabling ENGCLK can reduce power consumption, noise, and electromagnetic interference on the printed circuit board.
1. Mask
sets prior to K62N default to VCO/4.
MPC555
/ MPC556
MOTOROLA 8-12
USERS MANUAL

When the PLL is acquiring lock, the ENGCLK signal is disabled and remains in the low state (provided that BUCS = 0). NOTE Skew elimination between CLKOUT and ENGCLK is not guaranteed. 8.7 Clock Source Switching For limp mode support, clock source switching is supported. If for any reason the clock source for the chip is not functioning, the user has the option to switch the system clock to the backup clock ring oscillator, BUCLK. This circuit consists of a loss-of-clock detector, which sets the LOCS status bit and LOCSS sticky bit in the PLPRCR. If the LME bit in the SCCR is set, whenever LOCS is asserted the clock logic switches the system clock automatically to BUCLK and asserts hard reset to the chip. Switching the system clock to BUCLK is also possible by software setting the STBUC bit in SCCR. Switching from limp mode to normal system operation is accomplished by clearing STBUC and LOCSS bits. This operation also asserts hard reset to the chip. At HRESET assertion, if the PLL output clock is not valid, the BUCLK will be selected until software clears LOCSS bit in SCCR. At HRESET assertion, if the PLL output clock is valid, the system will switch to oscillator/external clock. If during HRESET the PLL loses lock or the clock frequency becomes slower than the required value, the system will switch to the BUCLK. After HRESET negation, the PLL lock condition does not effect the system clock source selection. If the LME bit is clear, the switch to the backup clock is disabled and assertion of STBUC bit is ignored. If the chip is in limp mode, clearing the LME bit switches the system to normal operation and asserts hard reset to the chip. Figure 8-8 describes the clock switching control logic. Table 8-3 summarizes the status and control for each state.
MPC555
/ MPC556
MOTOROLA 8-13
USERS MANUAL
1,BUCLK
poreset_b = 1 LME = 1
poreset_b = 0 else
LME = 1 poreset_b = 0
buclk_enable = 1 & hreset_b = 0

bu c hr lk_ es en et ab _b le
LME = 0
=
else
3,BUCLK
bu cl hr k _e es n et ab _b le = =0 1 buclk_enable=0 & hreset_b=0 4,osc

2,BUCLK
hreset_b = 0 LOCS
hreset_b = 1
bu cl k as _ e se na rt ble hr es = 1 et _b
hresert_b = 0
hreset_b = 1
buclk_enable = 0 & hreset_b = 0
6,BULCK
buclk-enable = 1 & hreset_b = 0
5, osc
else
Figure 8-8 Clock Source Flow Chart NOTES BUCLK_ENABLE = (STBUC | LOC) & LME lock indicates loss of lock status bit (LOCS) for all cases and loss of clock sticky bit (LOCSS) when state 3 is active. When BUCLK_ENABLE is changed, the chip asserts HRESET to switch the system clock to BUCLK or PLL. At PORESET negation, if the PLL is not locked, the loss-of-clock sticky bit (LOCSS) is asserted, and the chip should operate with BUCLK.
MPC555
/ MPC556
MOTOROLA 8-14
USERS MANUAL

The switching from state three to state four is accomplished by clearing the STBUC and LOCSS bits. If the switching is done when the PLL is not locked, the system clock will not oscillate until lock condition is met. Table 8-3 Status of Clock Source
STATE 1 2 3
1
PORESET 0 1 1 1 1 1
HRESET 0 0 1 0 1 0
LME 1 1 1 0/1 0/1 1
LOCS (status) 0 0/1 x2 0 0 0/1
LOCSS (sticky) 0 0 0/1 x2 x2 1
STBUC 0 0 0/1 0 0 0/1
BUCS 1 1 1 0 0 1
Chip Clock Source BUCLK BUCLK BUCLK Oscillator Oscillator BUCLK
5 6
NOTES: 1. At least one of the two bits, LOCSS or BUCS, must be asserted (one) in this state. 2. X = dont care.
The default value of the LME bit is determined by MODCK[1:3] during assertion of the PORESET line. The configuration modes are shown in Table 8-1. 8.8 Low-Power Modes The LPM and other bits in the PLPRCR are encoded to provide one normal operating mode and four low-power modes. In normal and doze modes the system can be in high state with frequency defined by the DFNH bits, or in the low state with frequency defined by the DFNL bits. The normal-high operating mode is the state out of reset. This is also the state of the bits after the low-power mode exit signal arrives. There are four low-power modes: Doze mode Sleep mode Deep-sleep mode Power-down mode 8.8.1 Entering a Low-Power Mode Low-power modes are enabled by setting the POW bit in the MSR and clearing the LPML (low-power mode lock) bit in the PLPRCR. Once enabled, a low-power mode is entered by setting the LPM bits to the appropriate value. This can be done only in one of the normal modes. The user cannot change the LPM or CSRC bits when the MCU is in doze mode. Table 8-6 summarizes the control bit descriptions for the different clock power modes.
MPC555
/ MPC556
MOTOROLA 8-15
USERS MANUAL

Table 8-4 Power Mode Control Bit Descriptions
Power Mode Normal-high Normal-low (gear) Doze-high Doze-low Sleep Deep-sleep Power-down LPM[0:1] 00 00 01 01 10 11 11 CSRC 0 1 0 1 X X X TEXPS X X X X X 1 0
8.8.2 Power Mode Descriptions Table 8-5 describes the power consumption, clock frequency, and chip functionality for each power mode. Table 8-5 Power Mode Descriptions
Operation Mode Normal-high Normal-low (gear) Doze-high SPLL Active Active Active Clocks Full frequency 2DFNH Full frequency 2DFNL+1 Full frequency 2DFNH Full frequency 2DFNL+1 Not active Not active Not active Not active SRAMs data retention Enabled: RTC, PIT, TB and DEC Functionality Full functions not in use are shut off Enabled: RTC, PIT, TB and DEC, memory controller Disabled: extended core (RCPU, BBC, FPU)
Doze-low Sleep Deep-sleep Power-down VDDSRAM
Active Active Not active Not active Not active
8.8.3 Exiting from Low-Power Modes Exiting from low-power modes occurs through an asynchronous interrupt or a synchronous interrupt generated by the memory controller. Any enabled asynchronous interrupt clears the LPM bits but does not change the PLPRCR[CSRC] bit. The exit from normal-low, doze-high, and low modes and sleep mode to normal-high mode is accomplished with the asynchronous interrupt. The sources of the asynchronous interrupt are: Asynchronous wake-up interrupt from the interrupt controller RTC, PIT, or time base interrupts (if enabled) Decrementer exception The system response to asynchronous interrupts is fast. The wake-up time from normal-low, doze-high, doze-low, and sleep mode due to an asynchronous interrupt or
MPC555
/ MPC556
MOTOROLA 8-16
USERS MANUAL

decrementer exception is only three to four clock cycles of maximum system frequency. In 40-MHz systems, this wake-up requires 75 to 100 ns. The asynchronous wakeup interrupt from the interrupt controller is level sensitive one. It will therefore be negated only after the reset of interrupt cause in the interrupt controller. The timers (RTC, PIT, time base, or decrementer) interrupts indication set status bits in the PLPRCR (TMIST). The clock module considers this interrupt to be pending asynchronous interrupt as long as the TMIST is set. The TMIST status bit should be cleared before entering any low-power mode. Table 8-7 summarizes wake-up operation for each of the low-power modes. Table 8-6 Power Mode Wake-Up Operation
Operation Mode
Wake-up Method Software or Interrupt Interrupt Interrupt Interrupt Interrupt
Return Time from Wake-up Event to Normal-High Asynchronous interrupts: 3-4 maximum system cycles Synchronous interrupts: 3-4 actual system cycles 3-4 maximum system clocks < 500 Oscillator Cycles 125 sec 4 MHz 25 sec 20 MHz < 500 oscillator cycles + power supply wake-up Power-on sequence
Normal-low (gear) Doze-high Doze-low Sleep Deep-sleep
Power-down VDDSRAM
Interrupt External
8.8.3.1 Exiting from Normal-Low Mode In normal mode (as well as doze mode), if the PLPRCR[CSRC] bit is set, the system toggles between low frequency (defined by PLPRCR[DFNL]) and high frequency (defined by PLPRCR[DFNH]. The system switches from normal-low mode to normal-high mode if either of the following conditions is met: An interrupt is pending from the interrupt controller; or The MSR[POW] bit is cleared (power management is disabled). When neither of these conditions are met, the PLPRCR[CSRC] bit is set, and the asynchronous interrupt status bits are reset, the system returns to normal-low mode. 8.8.3.2 Exiting from Doze Mode The system changes from doze mode to normal-high mode whenever an interrupt is pending from the interrupt controller. 8.8.3.3 Exiting from Deep-Sleep Mode The system switches from deep-sleep mode to normal-high mode if any of the following conditions is met:
MPC555
/ MPC556
MOTOROLA 8-17
USERS MANUAL

An interrupt is pending from the interrupt controller An interrupt is requested by the RTC, PIT, or time base A decrementer exception In deep-sleep mode the PLL is disabled. The wake-up time from this mode is up to 500 PLL input frequency clocks. In one-to-one mode the wake-up time may be up to 100 PLL input frequency clocks. For a PLL input frequency of 4 MHz, the wake-up time is less than 125 s. 8.8.3.4 Exiting from Power-Down Mode Exit from power-down mode is accomplished through hard reset. External logic should assert HRESET in response to the TEXPS bit being set and TEXP pin being asserted. The TEXPS bit is set by an enabled RTC, PIT, time base, or decrementer interrupt. The hard reset should be asserted for no longer than the time it takes for the power supply to wake-up in addition to the PLL lock time. When the TEXPS bit is cleared (and the TEXP signal is negated), assertion of hard reset sets the bit, causes the pin to be asserted, and causes an exit from power-down low-power mode. Refer to 8.9.3 Keep Alive Power for more information. 8.8.3.5 Low-Power Modes Flow Figure 8-9 shows the flow among the different power modes.
MPC555
/ MPC556
MOTOROLA 8-18
USERS MANUAL
(MSRPOW+Interrupt)+CSRC Software *
Normal-Low LPM = 00, CSRC = 1
((MSRPOW+Interrupt))*CSRC***
Software *
Doze-Low LPM = 01, CSRC = 1
Interrupt
Wake-up: 3 - 4 SysFreq Clocks Asynchronous Interrupts Wake-up: 3 - 4 SysFreqmax Clocks
Software *
Doze-High LPM = 01, CSRC = 0/1
Normal High Mode LPM = 00 CSRC = 0/1
Software *
Sleep Mode LPM = 10, CSRC = 0

Async. Wake-up or RTC/PIT/TB/DEC Interrupt Wake-up: 500 Input Frequency Clocks
Software *
Deep-Sleep Mode LPM = 11, CSRC = 0, TEXPS = 1 Power-Down Mode LPM = 11, CSRC = 0, TEXPS = 0**
Software *
RTC/PIT/TB/DEC Interrupt followed by External Hard Reset or External Hard Reset Software * Hard Reset
* Software is active only in normal-high/low modes ** TEXPS receives the zero value by writing one. Writing of zero has no effect on TEXPS. *** The switch from normal-high to normal-low is enable only if the conditions to asynchronous interrupt are cleared
Figure 8-9 MPC555 / MPC556 Low-Power Modes Flow Diagram
MPC555
/ MPC556
MOTOROLA 8-19
USERS MANUAL

8.9 Basic Power Structure 8.9.1 Clock Unit Power Supply KAPWR and VSS power the following clock unit modules: oscillator, PITRTCLK and TMBCLK generation logic, timebase, decrementer, RTC, PIT, system clock control register (SCCR), low-power and reset-control register (PLPRCR), and reset status register (RSR). All other circuits are powered by the normal supply pins, VDDI, VDDL, VDDH and VSS. The power supply for each block is listed in Table 8-7. Table 8-7 Clock Unit Power Supply
Circuit CLKOUT SPLL (digital), System low-power control Internal logic Clock drivers SPLL (analog) Main oscillator Reset machine Limp mode mechanism Register control SCCR, PLLRCR and RSR RTC, PIT, TB, and DEC SRAM, VDDSRAM detector, VSRMCR Power Supply
VDDL/VDDI
VDDSYN
KAPWR
VDDSRAM
The following are the relations between different power supplies: VDDL = VDDI = VDDSYN = VDDF = 3.3 V 10% KAPWR VDDL 0.2 V (during normal operation) VDDSRAM VDDL 0.3 V (during normal operation) VDDSRAM 1.4 V (during standby operation) VPP VDDL 0.3 V, but VPP VDDL < 4.0 volts 8.9.2 Chip Power Structure The MPC555 / MPC556 provides a wide range of possibilities for power supply connections. Figure 8-10 illustrates the different power supply sources for each of the basic units on the chip. 8.9.2.1 VDDL The I/O buffers and logic are fed by a 3.3-V power supply. 8.9.2.2 VDDI VDDI powers the internal logic of the MPC555 / MPC556, nominally 3.3 V.
MPC555
/ MPC556
MOTOROLA 8-20
USERS MANUAL

8.9.2.3 VDDSYN, VSSSYN The charge pump and the VCO of the SPLL are fed by a separate 3.3-V power supply (VDDSYN) in order to improve noise immunity and achieve a high stability in its output frequency. VSSSYN provides an isolated ground reference for the PLL. 8.9.2.4 KAPWR The oscillator, time base counter, decrementer, periodic interrupt timer and the realtime clock are fed by the KAPWR rail. This allows the external power supply unit to disconnect all other sub-units of the MCU in low-power deep-sleep mode. The TEXP pin (fed by the same rail) can be used by the external power supply unit to switch between sources. The IRQ[6:7]/MODCK[2:3], IRQ[5]/MODCK1, XTAL, EXTAL, EXTCLK, PORESET, HRESET, SRESET, and RSTCONF/TEXP input pins are powered by KAPWR. Circuits, including pull-up resisters, driving these inputs should be powered by KAPWR. 8.9.2.5 VDDA, VSSA VDDA supplies power to the analog subsystems of the QADC_A and QADC_B modules; it is nominally 5.0 V. VDDA is the ground reference for the analog subsystems. 8.9.2.6 VPP VPP supplies the programming and erase voltage for the CMF flash modules. It is nominally 5.0 V for program or erase operations and can be lowered to a nominal 3.3 V for read operations. 8.9.2.7 VDDF, VSSF VDDF provides internal power to the CMF flash module; it should be a nominal 3.3 V. VSSF provides an isolated ground for the CMF flash module. 8.9.2.8 VDDH VDDH provides power for the 5-V I/O operations. It is a nominal 5.0 V. 8.9.2.9 VDDSRAM VDDSRAM supplies power to the 26-Kbyte SRAM module and the DPTRAM. It can be used to keep the contents on the SRAM stable while the rest of the MPC555 / MPC556 is powered down for standby operation. 8.9.2.10 VSS VSS provides the ground reference for the MPC555 / MPC556.
MPC555
/ MPC556
MOTOROLA 8-21
USERS MANUAL
VPP
VDDF I/O VDDH
SRAM
FLASH Oscillator, PIT, RTC, TB, and DEC TEXP KAPWR
Internal Logic
PLL
Clock Control
VDDI VDDL
VDDI VDDSRAM
VDDSYN
Figure 8-10 Basic Power Supply Configuration 8.9.3 Keep Alive Power 8.9.3.1 Keep Alive Power Configuration Figure 8-11 illustrates an example of a switching scheme for an optimized low-power system. SW1 and SW2 can be unified in only one switch if VDDSYN and VDDI/VDDL are supplied by the same source.
MPC555
/ MPC556
MOTOROLA 8-22
USERS MANUAL

SW1
O
VDDSYN
O O
SW2
Main Power Supply 3.3 V
VDD
MPC555
TEXP
Switch Logic VDDSRAM Power Supply 3.3 V
VDDSRAM
KAPWR
3 V - 3.3 V Backup Power Supply
Figure 8-11 External Power Supply Scheme The MPC555 / MPC556 asserts the TEXP signal, if enabled, when the RTC or TB time value matches the value programmed in the associated alarm register or when the PIT or DEC value reaches zero. The TEXP signal is negated when the TEXPS status bit is written to one. The KAPWR power supply feeds the main crystal oscillator (OSCM). The condition for the main crystal oscillator stability is that the power supply value changes slowly. The maximum slope must be less than 5 mV per oscillation cycle ( > 200-300/freqoscm). 8.9.3.2 Keep Alive Power Registers Lock Mechanism The USIU timer, clocks, reset, power, decrementer, and time base registers are powered by the KAPWR supply. When the main power supply is disconnected after powerdown mode is entered, the value stored in any of these registers is preserved. If power-down mode is not entered before power disconnect, there is a chance of data loss in these registers. To minimize the possibility of data loss, the MPC555 / MPC556 includes a key mechanism that ensures data retention as long as a register is locked. While a register is locked, writes to this register are ignored. Each of the registers in the KAPWR region have a key that can be in one of two states: open or locked. At power-on reset the following keys are locked: RTC, RTSEC, RT-
MPC555
/ MPC556
MOTOROLA 8-23
USERS MANUAL

CAL, and RTCSC. All other registers are unlocked. Each key has an address associated with it in the internal memory map. A write of 0x55CCAA33 to the associated key register changes the key to the open state. A write of any other data to this location changes the key to the locked state. NOTE A read of a key register may be interpreted as a write of a lock value and may lock the associated KAPWR register. The key registers are write-only. A read of the key register has undefined side effects and may be interpreted as a write that locks the associated register. Table 8-8 lists the registers powered by KAPWR and the associated key registers.
Table 8-8 KAPWR Registers and Key Registers

KAPWR Register Address or SPR Number 0x2F C200 Register Time Base Status and Control (TBSCR) See Table 6-16 for bit descriptions. Address 0x2F C300 Associated Key Register Register Time Base Status and Control Key (TBSCRK) Time Base Reference 0 Key (TBREF0K)
0x2F C204
Time Base Reference 0 (TBREF0) See 6.13.4.3 Time Base Reference Reg- 0x2F C304 isters for bit descriptions. Time Base Reference 1 (TBREF1) See 6.13.4.3 Time Base Reference Reg- 0x2F C308 isters for bit descriptions. Real Time Clock Status and Control (RTCSC) See Table 6-17 for bit descriptions. Real Time Clock (RTC) See 6.13.4.6 Real-Time Clock Register (RTC) for bit descriptions. Real Time Alarm Seconds (RTSEC) Reserved Real Time Alarm (RTCAL) See 6.13.4.7 Real-Time Clock Alarm Register (RTCAL) for bit descriptions. PIT Status and Control (PISCR) See Table 6-18 for bit descriptions. PIT Count (PITC) See Table 6-19 for bit descriptions. System Clock Control Register (SCCR) See Table 8-9 for bit descriptions. PLL Low-Power and Reset-Control Register (PLPRCR) See Table 8-10 for bit descriptions. Reset Status Register (RSR) See Table 7-3 for bit descriptions. 0x2F C320
0x2F C208
Time Base Reference 1 Key (TBREF1K)
0x2F C220
Real Time Clock Status and Control Key (RTCSCK)
0x2F C224
0x2F C324
Real Time Clock Key (RTCK)
0x2F C228
0x2F C328
Real Time Alarm Seconds Key (RTSECK)
0x2F C22C
0x2F C32C
Real Time Alarm Key (RTCALK)
0x2F C240 0x2F C244 0x2F C280
0x2F C340 0x2F C344 0x2F C380
PIT Status and Control Key (PISCRK) PIT Count Key (PITCK) System Clock Control Key (SCCRK) PLL Low-Power and Reset-Control Register Key (PLPRCRK) Reset Status Register Key (RSRK)
0x2F C284
0x2F C384
0x2F C288
0x2F C388
MPC555
/ MPC556
MOTOROLA 8-24
USERS MANUAL

Table 8-8 KAPWR Registers and Key Registers (Continued)
KAPWR Register Address or SPR Number SPR 22 Register Decrementer See 3.9.5 Decrementer Register (DEC) for bit descriptions. Time Base See Table 3-11 and Table 3-14 for bit descriptions. Address Associated Key Register Register
0x2F C30C
Time Base and Decrementer Key (TBK)
SPR 268, 269, 284, 285,
Figure 8-12 illustrates the process of locking or unlocking a register powered by KAPWR.
Power On Reset (Valid for other registers) Open
Write to the key other value
Write to the Key 0x55CCAA33 Power On Reset (Valid for RTC, RTSEC, RTCAL and RTCSC)
Locked
Figure 8-12 Keep Alive Register Key State Diagram 8.10 VDDSRAM Supply Failure Detection A special circuit for VDDSRAM supply failure detection is provided. In the case of supply failure detection, the dedicated sticky bits LVSRS in the VSRMCR register are asserted. Software can read or clear these bits. The user should enable the detector and then clear these bits. If the user reads any of the LVSR bits as one, then a power failure of VDDSRAM has occurred. The circuit is capable of detecting supply failure below 2.6 V. Also, enable/disable control bit for the VDDSRAM detector may be used to disconnect the circuit and save the detector power consumption. 8.11 Power Up/Down Sequencing Figure 8-13 and Figure 8-14 detail the power-up sequencing for MPC555 / MPC556 during normal operation. Note that for each of the conditions detailing the voltage relationships the absolute bounds of the minimum and maximum voltage supply cannot be violated, i.e. the value of VDDL cannot fall below 3.0 V or exceed 3.6 V and the value of VDDH cannot fall below 4.5 V or exceed 5.5 V for normal operation. Further information detailing the functionality of the VPP signal for flash program and erase is outlined in 19.9.2 FLASH Program/Erase Voltage Conditioning. Power consumption during power up sequencing can not be specified prior to evaluation and charac-
MPC555
/ MPC556
MOTOROLA 8-25
USERS MANUAL

terization of production silicon. The goal is to keep the power consumption during power up sequencing below the operating power consumption. During the power down sequence the user needs to assert PORESET while VDDI and VDDL are at a voltage equal or greater to 3 V. Below this voltage the power supply chip can be turned off. If the turn off voltage of the power supply chip is greater than 0.74 V for the 3-V supply and greater than 0.8 V for the 5-V supply, then the circuitry inside the MPC555 / MPC556 will act as a load to the respective supply and will discharge the supply line down to these values. Since the 3-V logic represents a larger load to the supply chip, the 3-V supply line will decay faster than the 5-V supply line.
Power On
Operating See Note 1.
Power Off
See Note 2.
VDDH VDD, NVVL, QVDDL KAPRR VDDSRAM VDDA, VRH VDDSYN
VFLASH (5 V) PORESET HRESET
Figure 8-13 No Standby, No KAPWR, All System Power On/Off
MPC555
/ MPC556
MOTOROLA 8-26
USERS MANUAL
No Battery
Connect Battery
Power On
Operating
Power Off
No Battery
VDDH VDD, NVVL, QVDDL KAPRR VDDSRAM VDDA, VRH VDDSYN
VFLASH (5 V) PORESET HRESET
Figure 8-14 Standby and KAPWR, Other Power-On/Off NOTE The following notes apply to Figure 8-13 and Figure 8-14 above: 1. VDDH VDDL - 0.35 V (0.5 V max. at temperature extremes) VPP VDDH + 0.5 V AND VPP VDDL - 0.35 V (The delta VPP - VDDL must be 3.6 V during power on or off) VDDA can lag VDDH, and VDDSYN can lag VDDL, but both must be at a valid level before resets are negated. 2. If keep alive functions are NOT used, then when system power is on: KAPWR = VDDSRAM = VDDL 0.35 V 3. If keep alive functions ARE used, then KAPWR = VDDSRAM = VDDL = 3.3 V 0.35 V when system power is on VDDSRAM 1.8 V and optionally KAPWR = 3.3 V 0.3 V when system power is off Normal system power is defined as VDDL = VDDI = VDDF = VDDSYN = VPP = VDDSRAM = KAPWR = 3.3 0.3 V and VDDA = VDDH = 5.0 0.5 V
MPC555
/ MPC556
MOTOROLA 8-27
USERS MANUAL
Flash programming requirements are the same as normal system power, except VPP = 5.0 0.25 V 4. Do not hold the 3-V supplies at ground while VDDH/VDDA is ramping to 5 V. 5. If 5 V is applied before the 3-V supply, all 5-V outputs will be in indeterminate states until the 3-V supply reaches a level that allows reset to be distributed throughout the device 8.12 Clocks Unit Programming Model 8.12.1 System Clock Control Register (SCCR) The SPLL has a 32-bit control register, SCCR, which is powered by keep-alive power.
SCCR System Clock Control Register

MSB 0
DBCT
0x2F C280
8 9 10 11 12
BUCS
1
COM
3
DCSLR
4
MFPDL
5
LPML
6
TBS
13
EBDF
14
15
LME
RERTDIV2 STBUC SERVED PRQEN RTSEL
POWER-ON RESET: 1 0 ID21 0 0 0 0 12 0 0 1 EQ23 ID[13:14]1 EQ34
HARD RESET: U 0 ID21 U 0 0 U U U 0 1 U U ID[13:14]1 U
16
17
18
19
20
21
22
23
24
25
26 DFNL
27
28
29
30 DFNH
LSB 31
EECLK POWER-ON RESET: 0 0 1 1
ENGDIV5
HARD RESET: U U U U U U U U 0 0 0 0 0 0 0
NOTES: 1. The hard reset value is a reset configuration word value, extracted from the indicated internal data bus lines. Refer to 7.5.2 Hard Reset Configuration Word. U = Unaffected by reset 2. RTDIV will be 0 if MODCK[1:3] = 0b000 3. EQ2 = MODCK1 4. EQ3 = (MODCK1 & MODCK2 & MODCK3) | (MODCK1 & MODCK2 & MODCK3) | (MODCK1 & MODCK2 & MODCK3). See Table 8-1. 5. On mask sets prior to K62N, ENGDIV defaults to 0b000001.
MPC555
/ MPC556
MOTOROLA 8-28
USERS MANUAL

Table 8-9 SCCR Bit Descriptions
Bit(s) Name Description Disable backup clock for timers. The DBCT bit controls the timers clock source while the chip is in limp mode. If DBCT is set, the timers clock (tbclk, rtclk) source will not be the backup clock, even if the system clock source is the backup clock ring oscillator. The real-time clock source will be EXTAL or EXTCLK according to RTSEL bit (see description in bit 11 below), and the time base clocks source will be determined according to TBS bit and MODCK1. 0 = If the chip is in limp mode, the timer clock source is the backup (limp) clock 1 = The timer clock source is either the external clock or the crystal (depending on the current clock mode selected) Clock output mode. These bits control the output buffer strength of the CLKOUT and external bus pins. These bits can be dynamically changed without generating spikes on the CLKOUT and external bus pins. If CKLOUT is not connected to external circuits, set both bits (disabling CLKOUT) to minimize noise and power dissipation. COM1 is determined by the hard reset configuration word. 00 = Clock output enabled full-strength output buffer, bus pins full drive 01 = Clock output enabled half-strength output buffer, bus pins reduced drive 10 = Clock output disabled, bus pins full drive 11 = Clock output disabled, bus pins reduced drive Disable clock switching at loss of lock during reset. When DCSLR is clear and limp mode is enabled, the chip will switch automaticaly to the backup clock if the PLL losses lock during HRESET. When DCSLR is asserted, a PLL loss-of-lock event does not cause clock switching. If HRESET is asserted and DCSLR is set, the chip will not negate HRESET until the PLL aquires lock. 0 = Enable clock switching if the PLL loses lock during reset 1 = Disable clock switching if the PLL loses lock during reset MF and pre-divider lock. Setting this control bit disables writes to the MF and DIVF bits. This helps prevent runaway software from changing the VCO frequency and causing the SPLL to lose lock. In addition, to protect against hardware interference, a hardware reset will be asserted if these fields are changed while LPML is asserted. This bit is writable once after power-on reset. 0 = MF and DIVF fields are writable 1 = MF and DIVF fields are locked LPM lock. Setting this control bit disables writes to the LPM and CSRC control bits. In addition, for added protection, a hardware reset is asserted if any mode is entered other than normal-high mode. This protects against runaway software causing the MCU to enter low-power modes. (The MSR[POW] bit provides additional protection). LPML is writable once after power-on reset. 0 = LPM and CSRC bits are writable 1 = LPM and CSRC bits are locked and hard reset will occur if the MCU is not in normal-high mode Time base source. Note that when the chip is operating in limp mode (BUCS = 1), TBS is ignored, and the backup clock is the time base clock source. 0 = Source is OSCCLK divided by either four or 16 1 = Source is system clock divided by 16 RTC (and PIT) clock divider. At power-on reset this bit is cleared if MODCK[1:3] are all low; otherwise the bit is set. 0 = RTC and PIT clock divided by four 1 = RTC and PIT clock divided by 256 Switch to backup clock control. When software sets this bit, the system clock is switched to the on-chip backup clock ring oscillator, and the chip undergoes a hard reset. The STBUC bit is ignored if LME is cleared. 0 = Do not switch to the backup clock ring oscillator 1 = Switch to backup clock ring oscillator Reserved
DBCT
1:2
COM
DCSLR
MFPDL
LPML
TBS
RTDIV
STBUC
MPC555
/ MPC556
MOTOROLA 8-29
USERS MANUAL

Table 8-9 SCCR Bit Descriptions (Continued)
Bit(s) Name Description Power management request enable 0 = Remains in the lower frequency (defined by DFNL) even if the power management bit in the MSR is reset (normal operational mode) or if there is a pending interrupt from the interrupt controller 1 = Switches to high frequency (defined by DFNH) when the power management bit in the MSR is reset (normal operational mode) or there is a pending interrupt from the interrupt controller RTC circuit input source select. At power-on reset RTSEL receives the value of the MODCK1 bit. Note that if the chip is operating in limp mode (BUCS = 0), the RTSEL bit is ignored, and the backup clock is the clock source for the RT and PIT clocks 0 = OSCM clock is selected as input to RTC and PIT 1 = EXTCLK clock is selected as the RTC and PIT clock source Backup clock status. This status bit indicates the current system clock source. When loss of clock is detected and the LME bit is set, the clock source is the backup clock and this bit is set. When the user sets the STBUC bit and LME bit is set, the system switches to the backup clock and BUCS is set. 0 = System clock is not the backup clock 1 = System clock is the backup clock External bus division factor. These bits define the frequency division factor between (GCLK1 and GCLK2) and (GCLK1_50 and GCLK2_50). CLKOUT is similar to GCLK2_50. The GCLK2_50 and GCKL1_50 are used by the external bus interface and memory controller in order to interface to the external system. The EBDF bits are initialized during hard reset using the hard reset configuration mechanism. 00 = CLKOUT is GCKL2 divided by 1 01 = CLKOUT is GCKL2 divided by 2 1x = Reserved Limp mode enable. When LME is set, the loss-of-clock monitor is enabled and any detection of loss of clock will switch the system clock automatically to backup clock. It is also possible to switch to the backup clock by setting the STBUC bit. If LME is cleared, the option of using limp mode is disabled. The loss of clock detector is not active, and any write to STBUC is ignored. The LME bit is writable once, by software, after power-on reset, when the system clock is not backup clock (BUCS = 0). During power-on reset, the value of LME is determined by the MODCK[1:3] bits. (Refer to Table 8-1.) 0 = Limp mode disabled 1 = Limp mode enabled Enable engineering clock. This field controls the output buffer strength of the ENGCLK pin. When both bits are set the ENGCLK pin is held in the high state. These bits can be dynamically changed without generating spikes on the ENGCLK pin. If ENGCLK is not connected to external circuits, set both bits (disabling ENGCLK) to minimize noise and power dissipation. For measurement purposes the backup clock (BUCLK) can be driven externally on the ENGCLK pin. 00 = Engineering clock enabled, full-strength output buffer 01 = Engineering clock enabled, half-strength output buffer 10 = BUCLK is the output on the ENGCLK full-strength output buffer 11 = Engineering clock disabled Engineering clock division factor. These bits define the frequency division factor between VCO/2 and ENGCLK. The divider ratio is ENGDIV+1. Division factor can be from 1 (ENGDIV = 0b000000) to 64 (ENGDIV = 0b111111). These bits can be read and written at any time. They are not affected by hard reset but are cleared during power-on reset. 18:23 ENGDIV NOTE: If the engineering clock division factor is not a power of two, synchronization between the system and ENGCLK is not guaranteed. NOTE: The default (Power On Reset) value of ENGDIV will be 0b111111 on all mask sets after K62N. The default for previous mask sets (J76N, K02A, and K83H) is 0b000001.
10
PRQEN
11
RTSEL
12
BUCS
13:14
EBDF
15
LME
16:17
EECLK
MPC555
/ MPC556
MOTOROLA 8-30
USERS MANUAL

Table 8-9 SCCR Bit Descriptions (Continued)
Bit(s) 24 Name Reserved Division factor low frequency. The user can load these bits with the desired divide value and the CSRC bit to change the frequency. Changing the value of these bits does not result in a loss of lock condition. These bits are cleared by power-on or hard reset. Refer to 8.6.1 General System Clocks and Figure 8-5 for details on using these bits. 000 = Divide by 2 001 = Divide by 4 010 = Divide by 8 011 = Divide by 16 100 = Divide by 32 101 = Divide by 64 110 = Reserved 111 = Divide by 256 Reserved Division factor high frequency. These bits determine the general system clock frequency during normal mode. Changing the value of these bits does not result in a loss of lock condition. These bits are cleared by power-on or hard reset. The user can load these bits at any time to change the general system clock rate. Note that the GCLKs generated by this division factor are not 50% duty cycle (i.e. CLKOUT). 000 = Divide by 1 001 = Divide by 2 010 = Divide by 4 011 = Divide by 8 100 = Divide by 16 101 = Divide by 32 110 = Divide by 64 111 = Reserved Description
25:27
DFNL
28
29:31
DFNH
8.12.2 PLL, Low-Power, and Reset-Control Register (PLPRCR) The PLL, low-power, and reset-control register (PLPRCR) is a 32-bit register powered by the keep alive power supply.
MPC555
/ MPC556
MOTOROLA 8-31
USERS MANUAL

PLPRCR PLL, Low-Power, and Reset-Control Register
MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13
0x2F C284
14 LOCSS 15
MF POWER-ON RESET: 0 OR 4 HARD RESET: U U U U U U U U U U U U
RESERVE LOCS D
SPLS
16
17
18
19
20
21
22
23
24
25 LOLRE
26 RESERVE D
27
28
29
30
LSB 31
SPLS S
RERETEXP SERVE TMIST SERVE CSRC S D D
LPM
CSR
DIVF
POWER-ON RESET: 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HARD RESET: U 1 U 0 U 0 0 0 U U U U U U U
U = Unaffected by reset
Table 8-10 PLPRCR Bit Descriptions

Bit(s) Name Description Multiplication factor bits. The output of the VCO is divided to generate the feedback signal to the phase comparator. The MF bits control the value of the divider in the SPLL feedback loop. The phase comparator determines the phase shift between the feedback signal and the reference clock. This difference results in either an increase or decrease in the VCO output frequency. 0:11 MF The MF bits can be read and written at any time. However, this field can be write-protected by setting the MF and pre-divider lock (MFPDL) bit in the SCCR. Changing the MF bits causes the SPLL to lose lock. Also, the MF field should not be modified when entering or exiting from low power mode (LPM change), or when back-up clock is active. The normal reset value for the DFNH bits is zero (divide by one). When the PLL is operating in one-to-one mode, the multiplication factor is set to x1 (MF = 0). 12 Reserved Loss of clock status. When the oscillator or external clock source is not at the minimum frequency, the loss-of-clock circuit asserts the LOCS bit. This bit is cleared when the oscillator or external clock source is functioning normally. This bit is reset only on power-on reset. Writes to this bit have no effect. 0 = No loss of oscillator is currently detected 1 = Loss of oscillator is currently detected Loss of clock sticky. If, after negation of PORESET, the loss-of-clock circuit detects that the oscillator or external clock source is not at a minimum frequency, the LOCSS bit is set. LOCSS remains set until software clears it by writing a one to it. A write of zero has no effect on this bit. The reset value is determined during hard reset. The STBUC bit will be set provided the PLL lock condition is not met when HRESET is asserted, and cleared if the PLL is locked when HRESET is asserted. 0 = No loss of oscillator has been detected 1 = Loss of oscillator has been detected
13
LOCS
14
LOCSS
MPC555
/ MPC556
MOTOROLA 8-32
USERS MANUAL

Table 8-10 PLPRCR Bit Descriptions (Continued)
Bit(s) 15 Name SPLS System PLL lock status bit 0 = SPLL is currently not locked 1 = SPLL is currently locked SPLL lock status sticky bit. An out-of-lock sets the SPLSS bit. The bit remains set until software clears it by writing a one to it. A write of zero has no effect on this bit. The bit is cleared at power-on reset. This bit is not affected due to a software initiated loss-of-lock (MF change and entering deep-sleep or power-down mode). The SPLSS bit is not affected by hard reset. 0 = SPLL has remained in lock 1 = SPLL has gone out of lock at least once (not due to software-initiated loss of lock) Timer expired status bit. This bit controls whether the chip negates the TEXP pin in deepsleep mode, thus enabling external circuitry to switch off the VDD (power-down mode). When LPM = 11, CSRC = 0, and TEXPS is high, the TEXP pin remains asserted. When LPM = 11, CSRC = 0, and TEXPS is low, the TEXPS pin is negated. Description
16
SPLSS
17
TEXPS
To enable automatic wake-up TEXPS is asserted when one of the following occurs: The PIT is expired The real-time clock alarm is set The time base clock alarm is set The decrementer exception occurs The bit remains set until software clears it by writing a one to it. A write of zero has no effect on this bit. TEXPS is set by power-on or hard reset. 0 = TEXP is negated in deep-sleep mode 1 = TEXP pin remains asserted always
18
Reserved Timers interrupt status.TMIST is set when an interrupt from the RTC, PIT, TB or DEC occurs. The TMIST bit is cleared by writing a one to it. Writing a zero has no effect on this bit. The system clock frequency remains at its high frequency value (defined by DFNH) if the TMIST bit is set, even if the CSRC bit in the PLPRCR is set (DFNL enabled) and conditions to switch to normal-low mode do not exist. This bit is cleared during power-on or hard reset. 0 = No timer expired event was detected 1 = A timer expire event was detected Reserved Clock source. This bit is cleared at hard reset. 0 = General system clock is determined by the DFNH value 1 = General system clock is determined by the DFNL value Low-power mode select. These bits are encoded to provide one normal operating mode and four low-power modes. In normal and doze modes, the system can be in high state (frequency determined by the DFNH bits) or low state (frequency defined by the DFNL bits). The LPM field can be write-protected by setting the LPM and CSRC lock (LPML) bit in the PLPRCR Refer to Table 8-4 and Table 8-5. Checkstop reset enable. If this bit is set, then an automatic reset is generated when the RCPU signals that it has entered checkstop mode, unless debug mode was enabled at reset. If the bit is clear and debug mode is not enabled, then the USIU will not do anything upon receiving the checkstop signal from the RCPU. If debug mode is enabled, then the part enters debug mode upon entering checkstop mode. In this case, the RCPU will not assert the checkstop signal to the reset circuitry. This bit is writable once after soft reset. 0 = No reset will occur when checkstop is asserted 1 = Reset will occur when checkstop is asserted Loss of lock reset enable 0 = Loss of lock does not cause HRESET assertion 1 = Loss of lock causes HRESET assertion Note: if limp mode is enabled, use the COLIR feature instead of setting the LOLRE bit. See 8.12.3 Change of Lock Interrupt Register (COLIR).
19
TMIST
20 21
CSRC
22:23
LPM
24
CSR
25
LOLRE
MPC555
/ MPC556
MOTOROLA 8-33
USERS MANUAL

Table 8-10 PLPRCR Bit Descriptions (Continued)
Bit(s) 26 Name Reserved The DIVF bits control the value of the pre-divider in the SPLL circuit. The DIVF bits can be read and written at any time. However, the DIVF field can be write-protected by setting the MF and pre-divider lock (MFPDL) bit in the SCCR. Changing the DIVF bits causes the SPLL to lose lock. Description
27:31
DIVF
8.12.3 Change of Lock Interrupt Register (COLIR) The COLIR is 16-bit read/write register. It controls the change of lock interrupt generation, and is used for reporting a loss of lock interrupt source. It contains the interrupt request level and the interrupt status bit. This register is readable and writable at any time. A status bit is cleared by writing a one (writing a zero does not affect a status bits value). The COLIR is memory mapped into the MPC555 / MPC556 USIU register map. COLIR Change of Lock Interrupt Register
MSB 0 1 2 3 4 5 6 7 8 COLIS 9 10 11 12 13 Reserved
0x2F C28C
14 LSB 15
COLIRQ RESET: 0 0 0 0 0 0 0 0
ReCOLIE served
Table 8-11 COLIR Bit Descriptions

Bit(s) 0:7 Name COLIRQ Description Change of lock interrupt request level. These bits determine the interrupt priority level of the change of lock. To specify certain level, the appropriate one of these bits should be set. If set (one), the bit indicates that a change in the PLL lock status was detected. The PLL was locked and lost lock, or the PLL was unlocked and got locked. The bit should be cleared by writing a one. Reserved Change of Lock Interrupt enable. If COLIE bit is asserted, an interrupt will generate when the COLIS bit is asserted. 0 = Change of lock Interrupt disable 1 = Change of lock Interrupt enable Reserved
8 9
COLIS
10
COLIE
10:15
8.12.4 VDDSRAM Control Register (VSRMCR) This register contains control bits for enabling or disabling the VDDSRAM supply detection circuit. There are also four bits that indicate the failure detection. All four bits have the same function and are required to improve the detection capability in extreme cases.
MPC555
/ MPC556
MOTOROLA 8-34
USERS MANUAL

VSRMCR VDDSRAM Control Register
MSB 0 0 1 2 3 4 5 VSRDE 6 7 8 9 10 11 12 13
0x2F C290
14 LSB 15
LVSRS HARD RESET: U U U U
RESERVED
Table 8-12 VSRMCR Bit Descriptions

Bit(s) 0 Name Reserved Loss of VDDSRAM sticky. These status bits indicate whether a VDDSRAM supply failure occurred. In addition, when the power is turned on for the first time, VDDSRAM rises and these bits are set. The LVSRS bits are cleared by writing them to ones. A write of zero has no effect on these bits. 0 = No VDDSRAM supply failure was detected 1 = VDDSRAM supply failure was detected VDDSRAM detector disable. 0 = VDDSRAM detection circuit is enabled 1 = VDDSRAM detection circuit is disabled Reserved Description
1:4
LVSRS
5 6:15
VSRDE
MPC555
/ MPC556
MOTOROLA 8-35
USERS MANUAL
MPC555
/ MPC556
MOTOROLA 8-36
USERS MANUAL
SECTION 9 EXTERNAL BUS INTERFACE

The MPC555 / MPC556 bus is a synchronous, burstable bus. Signals driven on this bus are required to make the setup and hold time relative to the bus clocks rising edge. The bus has the ability to support multiple masters. The MPC555 / MPC556 architecture supports byte, half-word, and word operands allowing access to 8-, 16-, and 32-bit data ports through the use of synchronous cycles controlled by the size outputs (TSIZ0, TSIZ1). For accesses to 16- and 8-bit ports, the slave must be controlled by the memory controller.
9.1 Features The external bus interface features are listed below. 32-bit address bus with transfer size indication (only 24 available on pins) 32-bit data bus Bus arbitration logic on-chip supports an external master Internal chip-select and wait state generation to support peripheral or static memory devices through the memory controller Supports various memory (SRAM, EEPROM) types: synchronous and asynchronous, burstable and non-burstable Supports non-wrap bursts Flash ROM programming support Compatible with PowerPC architecture Easy to interface to slave devices Bus is synchronous (all signals are referenced to rising edge of bus clock) Bus can operate at the same frequency as the MPC555 / MPC556 or half the frequency. 9.2 Bus Transfer Signals The bus transfers information between the MPC555 / MPC556 and external memory of a peripheral device. External devices can accept or provide 8, 16, and 32 bits in parallel and must follow the handshake protocol described in this section. The maximum number of bits accepted or provided during a bus transfer is defined as the port width. The MPC555 / MPC556 contains an address bus that specifies the address for the transfer and a data bus that transfers the data. Control signals indicate the beginning and type of the cycle, as well as the address space and size of the transfer. The selected device then controls the length of the cycle with the signal(s) used to terminate the cycle. A strobe signal for the address bus indicates the validity of the address and provides timing information for the data.
EXTERNAL BUS INTERFACE
MOTOROLA 9-1

The MPC555 / MPC556 bus is synchronous. The bus and control input signals must be timed to setup and hold times relative to the rising edge of the clock. Bus cycles can be completed in two clock cycles. For all inputs, the MPC555 / MPC556 latches the level of the input during a sample window around the rising edge of the clock signal. This window is illustrated in Figure 9-1, where tsu and tho are the input setup and hold times, respectively. To ensure that an input signal is recognized on a specific falling edge of the clock, that input must be stable during the sample window. If an input makes a transition during the window time period, the level recognized by the MPC555 / MPC556 is not predictable; however, the MPC555 / MPC556 always resolves the latched level to either a logic high or low before using it. In addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this section.
tho
tsu Clock
Signal
Sample Window
Figure 9-1 Input Sample Window 9.3 Bus Control Signals The MPC555 / MPC556 initiates a bus cycle by driving the address, size, address type, cycle type, and read/write outputs. At the beginning of a bus cycle, TSIZ0 and TSIZ1 are driven with the address type signals. TSIZ0 and TSIZ1 indicate the number of bytes remaining to be transferred during an operand cycle (consisting of one or more bus cycles). These signals are valid at the rising edge of the clock in which the transfer start (TS) signal is asserted. The read/write (RD/WR) signal determines the direction of the transfer during a bus cycle. Driven at the beginning of a bus cycle, RD/WR is valid at the rising edge of the clock in which TS is asserted. The logic level of RD/WR only changes when a write cycle is preceded by a read cycle or vice versa. The signal may remain low for consecutive write cycles.
MPC555
/ MPC556
MOTOROLA 9-2
USERS MANUAL
32 1 1 2 4 1 1 1
ADDR[0:31] RD/WR BURST TSIZ[0:1] AT[0:3] PTR STS (BI) BDIP
Address and Transfer Attributes
TS
Transfer Start
1 1 1
RSV KR CR
Reservation Protocol
32
DATA[0:31]
Data
1 1 1 1
RETRY BI (STS) TA TEA
Transfer Cycle Termination
1 1 1
BR BG BB
Arbitration
Figure 9-2 MPC555 / MPC556 Bus Signals 9.4 Bus Interface Signal Descriptions Table 9-1 diatribes each signal in the bus interface unit. More detailed descriptions can be found in subsequent subsections.
MPC555
/ MPC556
MOTOROLA 9-3
USERS MANUAL

.
Table 9-1 MPC555 / MPC556 SIU Signals

Signal Name Pins Active I/O O High I Description Specifies the physical address of the bus transaction. Driven by an external bus master when it owns the external bus. Only for testing purposes. Driven by the MPC555 / MPC556 along with the address when it owns the external bus. Driven high indicates that a read access is in progress. Driven low indicates that a write access is in progress. Driven by an external master when it owns the external bus. Driven high indicates that a read access is in progress. Driven low indicates that a write access is in progress. Driven by the MPC555 / MPC556 along with the address when it owns the external bus. Driven low indicates that a burst transfer is in progress. Driven high indicates that the current transfer is not a burst. Driven by an external master when it owns the external bus. Driven low indicates that a burst transfer is in progress. Driven high indicates that the current transfer is not a burst. The MPC555 / MPC556 does not support burst accesses to internal slaves. Driven by the MPC555 / MPC556 along with the address when it owns the external bus. Specifies the data transfer size for the transaction. Driven by an external master when it owns the external bus. Specifies the data transfer size for the transaction. Driven by the MPC555 / MPC556 along with the address when it owns the external bus. Indicates additional information about the address on the current transaction. Only for testing purposes. Driven by the MPC555 / MPC556 along with the address when it owns the external bus. Indicates additional information about the address on the current transaction. Only for testing purposes. Driven by the MPC555 / MPC556 along with the address when it owns the external bus. Indicates additional information about the address on the current transaction. Only for testing purposes. Address and Transfer Attributes ADDR[0:31] Address bus 24 (8:31)
O RD/WR 1 Read/write I HIgh
O BURST 1 Burst transfer I Low
TSIZ[0:1] 2 Transfer size High
AT[0:3] 3 Address type High
I RSV 1 Reservation transfer I PTR 1 Program trace I High Low
MPC555
/ MPC556
MOTOROLA 9-4
USERS MANUAL

Table 9-1 MPC555 / MPC556 SIU Signals (Continued)
Signal Name Pins Active I/O Description In the case of regular transaction, this signal is driven by the slave device to indicate that the MPC555 / MPC556 must relinquish the ownership of the bus and retry the cycle. When an external master owns the bus and the internal MPC555 / MPC556 bus initiates access to the external bus at the same time, this signal is used to cause the external master to relinquish the bus for one clock to solve the contention. Driven by the MPC555 / MPC556 when it owns the external bus. It is part of the burst protocol. When BDIP is asserted, the second beat in front of the current one is requested by the master. This signal is negated prior to the end of a burst to terminate the burst data phase early. Driven by an external master when it owns the external bus. When BDIP is asserted, the second beat in front of the current one is requested by the master. This signal is negated prior to the end of a burst to terminate the burst data phase early. The MPC555 / MPC556 does not support burst accesses to internal slaves. Transfer Start O TS 1 Transfer start I Low Driven by the MPC555 / MPC556 when it owns the external bus. Indicates the start of a transaction on the external bus. Driven by an external master when it owns the external bus. It indicates the start of a transaction on the external bus or (in show cycle mode) signals the beginning of an internal transaction. Driven by the MPC555 / MPC556 when it owns the external bus. Indicates the start of a transaction on the external bus or signals the beginning of an internal transaction in show cycle mode. Each PowerPC CPU has its own CR signal. Assertion of CR instructs the bus master to clear its reservation; some other master has touched its reserved space. This is a pulsed signal. In case of a bus cycle initiated by a STWCX instruction issued by the RCPU to a non-local bus on which the storage reservation has been lost, this signal is used by the non-local bus interface to backoff the cycle. Refer to 9.5.9 Storage Reservation for details.
RETRY
Low O
BDIP 1 Burst data in progress I Low
STS 1 Special transfer start Low O
Reservation Protocol CR 1 Cancel reservation Low I
KR 1 Kill reservation Low I
MPC555
/ MPC556
MOTOROLA 9-5
USERS MANUAL

Signal Name Pins Active I/O Data The data bus has the following byte lane assignments: Data Byte DATA[0:7] DATA[8:15] DATA[16:23] DATA[24:31] Byte Lane 0 1 2 3 Description
DATA[0:31]
32 Data bus
High
Driven by the MPC555 / MPC556 when it owns the external bus and it initiated a write transaction to a slave device. For single beat transactions, the byte lanes not selected for the transfer by ADDR[30:31] and TSIZ[0:1] do not supply valid data. In addition, the MPC555 / MPC556 drives DATA[0:31] when an external master owns the external bus and initiated a read transaction to an internal slave module. Driven by the slave in a read transaction. For single beat transactions, the MPC555 / MPC556 does not sample byte lanes that are not selected for the transfer by ADDR[30:31] and TSIZ[0:1]. In addition, an external master that owns the bus and initiated a write transaction to an internal slave module drives DATA[0:31].
Transfer Cycle Termination Driven by the slave device to which the current transaction was addressed. Indicates that the slave has received the data on the write cycle or returned data on the read cycle. If the transaction is a burst, TA should be asserted for each one of the transaction beats. Driven by the MPC555 / MPC556 when the slave device is controlled by the on-chip memory controller or when an external master initiated a transaction to an internal slave module. Driven by the slave device to which the current transaction was addressed. Indicates that an error condition has occurred during the bus cycle. Driven by the MPC555 / MPC556 when the internal bus monitor detected an erroneous bus condition, or when an external master initiated a transaction to an internal slave module and an internal error was detected. Driven by the slave device to which the current transaction was addressed. Indicates that the current slave does not support burst mode. Driven by the MPC555 / MPC556 when the slave device is controlled by the on-chip memory controller. the MPC555 / MPC556 also asserts BI for any external master burst access to internal MPC555 / MPC556 memory space.
I TA 1 Transfer acknowledge O LOW
I TEA Transfer error acknowledge 1 Low O
I BI 1 Burst inhibit Low O
MPC555
/ MPC556
MOTOROLA 9-6
USERS MANUAL

Signal Name Pins Active I/O ARBITRATION BR 1 Bus request Low O I When the internal arbiter is enabled, BR assertion indicates that an external master is requesting the bus. Driven by the MPC555 / MPC556 when the internal arbiter is disabled and the chip is not parked. When the internal arbiter is enabled, the MPC555 / MPC556 asserts this signal to indicate that an external master may assume ownership of the bus and begin a bus transaction. The BG signal should be qualified by the master requesting the bus in order to ensure it is the bus owner: Qualified bus grant = BG & ~ BB When the internal arbiter is disabled, BG is sampled and properly qualified by the MPC555 / MPC556 when an external bus transaction is to be executed by the chip. When the internal arbiter is enabled, the MPC555 / MPC556 asserts this signal to indicate that it is the current owner of the bus. O When the internal arbiter is disabled, the MPC555 / MPC556 asserts this signal after the external arbiter has granted the ownership of the bus to the chip and it is ready to start the transaction. When the internal arbiter is enabled, the MPC555 / MPC556 samples this signal to get indication of when the external master ended its bus tenure (BB negated). When the internal arbiter is disabled, the BB is sampled to properly qualify the BG line when an external bus transaction is to be executed by the chip. Description
O BG 1 Bus grant Low
BB 1 Bus busy Low
9.5 Bus Operations This section provides a functional description of the system bus, the signals that control it, and the bus cycles provided for data transfer operations. It also describes the error conditions, bus arbitration, and reset operation. The MPC555 / MPC556 generates a system clock output (CLKOUT). This output sets the frequency of operation for the bus interface directly. Internally, the MPC555 / MPC556 uses a phase-lock loop (PLL) circuit to generate a master clock for all of the CPU circuitry (including the bus interface) which is phase-locked to the CLKOUT output signal. All signals for the MPC555 / MPC556 bus interface are specified with respect to the rising edge of the external CLKOUT and are guaranteed to be sampled as inputs or changed as outputs with respect to that edge. Since the same clock edge is referenced for driving or sampling the bus signals, the possibility of clock skew could exist between various modules in a system due to routing or the use of multiple clock lines. It
MPC555
/ MPC556
MOTOROLA 9-7
USERS MANUAL

is the responsibility of the system to handle any such clock skew problems that could occur. 9.5.1 Basic Transfer Protocol The basic transfer protocol defines the sequence of actions that must occur on the MPC555 / MPC556 bus to perform a complete bus transaction. A simplified scheme of the basic transfer protocol is illustrated in Figure 9-3.
Arbitration
Address Transfer
Data Transfer
Termination
Figure 9-3 Basic Transfer Protocol The basic transfer protocol provides for an arbitration phase and an address and data transfer phase. The address phase specifies the address for the transaction and the transfer attributes that describe the transaction. The data phase performs the transfer of data (if any is to be transferred). The data phase may transfer a single beat of data (4 bytes or less) for nonburst operations, a 4-beat burst of data (4 x 4 bytes), an 8-beat burst of data (8 x 2 bytes) or a 16-beat burst of data (16 x 1 bytes). 9.5.2 Single Beat Transfer During the data transfer phase, the data is transferred from master to slave (in write cycles) or from slave to master (on read cycles). During a write cycle, the master drives the data as soon as it can, but never earlier than the cycle following the address transfer phase. The master has to take into consideration the one dead clock cycle switching between drivers to avoid electrical contentions. The master can stop driving the data bus as soon as it samples the TA line asserted on the rising edge of the CLKOUT. During a read cycle, the master accepts the data bus contents as valid at the rising edge of the CLKOUT in which the TA signal is sampled/asserted. 9.5.2.1 Single Beat Read Flow The basic read cycle begins with a bus arbitration, followed by the address transfer, then the data transfer. The handshakes are illustrated in the following flow and timing diagrams as applicable to the fixed transaction protocol.
MPC555
/ MPC556
MOTOROLA 9-8
USERS MANUAL

Master Slave
Request bus (BR)
Receive bus grant (BG) from arbiter
Assert bus busy (BB) if no other master is driving bus Assert transfer start (TS) Drive address and attributes
Receive address
Return data
Assert transfer acknowledge (TA)
Receive data
Figure 9-4 Basic Flow Diagram of a Single Beat Read Cycle
MPC555
/ MPC556
MOTOROLA 9-9
USERS MANUAL
CLKOUT
BR
BG
Receive bus grant and bus busy negated
O O
BB
Assert BB, drive address and assert TS
O
ADDR[0:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA
O
Data is valid
Figure 9-5 Single Beat Read CycleBasic TimingZero Wait States
MPC555
/ MPC556
MOTOROLA 9-10
USERS MANUAL
CLKOUT
BR
BG
O O
BB
assert BB, drive address and assert TS
O
ADDR[0:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA Wait state
O
Data is valid
Figure 9-6 Single Beat Read CycleBasic TimingOne Wait State 9.5.2.2 Single Beat Write Flow The basic write cycle begins with a bus arbitration, followed by the address transfer, then the data transfer. The handshakes are illustrated in the following flow and timing diagrams as applicable to the fixed transaction protocol.
MPC555
/ MPC556
MOTOROLA 9-11
USERS MANUAL
Master
Slave
Request bus (BR)
Receive bus grant (BG) from arbiter
Assert bus busy (BB) if no other master is driving bus Assert transfer start (TS) Drive address and attributes
Drive data
Assert transfer acknowledge (TA)
Interrupt data driving
Figure 9-7 Basic Flow Diagram of a Single Beat Write Cycle
MPC555
/ MPC556
MOTOROLA 9-12
USERS MANUAL
CLKOUT
BR
BG
O O
BB
O
ADDR[0:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA
O
Data is sampled
Figure 9-8 Single Beat Basic Write Cycle Timing, Zero Wait States
MPC555
/ MPC556
MOTOROLA 9-13
USERS MANUAL
CLKOUT
BR
BG
O O
BB
O
ADDR[0:31]
RD/WR
TSIZ[0:1]
BURST, BDIP
TS
O
Data
TA Wait state
O
Data is sampled
Figure 9-9 Single Beat Basic Write Cycle Timing, One Wait State 9.5.2.3 Single Beat Flow with Small Port Size The general case of single beat transfers assumes that the external memory has a 32bit port size. The MPC555 / MPC556 provides an effective mechanism for interfacing with 16-bit and 8-bit port size memories, allowing transfers to these devices when they are controlled by the internal memory controller. In this case, the MPC555 / MPC556 attempts to initiate a transfer as in the normal case. If the bus interface receives a small port size (16 or 8 bits) indication before the transfer acknowledge to the first beat (through the internal memory controller), the MCU initiates successive transactions until the completion of the data transfer. Note that all the transactions initiated to complete the data transfer are considered to be part of an atomic transaction, so the MCU does not allow other unrelated master accesses
MPC555
/ MPC556
MOTOROLA 9-14
USERS MANUAL

or bus arbitration to intervene between the transfers. If any of the transactions except the first is re-tried during an access to a small port, then an exception is generated to the RCPU.
CLKOUT
BR
BG
BB
ADDR[0:1]
ADDR
ADDR + 2
RD/WR
TSIZ[0:1]
00
10
BURST, BDIP
TS
STS
Data
ABCDEFGH
EFGHEFGH
TA
Figure 9-10 Single Beat 32-Bit Data Write Cycle Timing, 16 Bit-Port Size 9.5.3 Burst Transfer The MPC555 / MPC556 uses non-wrapping burst transfers to access operands of up to 16 bytes (four words). A non-wrapping burst access stops accessing the external device when the word address is modulo four. The MPC555 / MPC556 begins the access by supplying a starting address that points to one of the words and requiring the memory device to sequentially drive or sample each word on the data bus. The selectMPC555
/ MPC556
MOTOROLA 9-15
USERS MANUAL

ed slave device must internally increment ADDR28 and ADDR29 (and ADDR30 in the case of a 16-bit port slave device, and also ADDR31 in the case of an 8-bit port slave device) of the supplied address for each transfer, causing the address to reach a fourword boundary, and then stop. The address and transfer attributes supplied by the MPC555 / MPC556 remain stable during the transfers. The selected device terminates each transfer by driving or sampling the word on the data bus and asserting TA. The MPC555 / MPC556 also supports burst-inhibited transfers for slave devices that are unable to support bursting. For this type of bus cycle, the selected slave device supplies or samples the first word the MPC555 / MPC556 points to and asserts the burst-inhibit signal with TA for the first transfer of the burst access. The MPC555 / MPC556 responds by terminating the burst and accessing the remainder of the 16byte block. These remaining accesses use up to three read/write bus cycles (each one for a word) in the case of a 32-bit port width slave, up to seven read/write bus cycles in the case of a 16-bit port width slave, or up to fifteen read/write bus cycles in the case of a 8-bit port width slave. The general case of burst transfers assumes that the external memory has a 32-bit port size. The MPC555 / MPC556 provides an effective mechanism for interfacing with 16-bit port size memories and 8-bit port size memories allowing bursts transfers to these devices when they are controlled by the internal memory controller. In this case, the MPC555 / MPC556 attempts to initiate a burst transfer as in the normal case. If the memory controller signals to the bus interface that the external device has a small port size (8 or 16 bits), and if the burst is accepted, the bus interface completes a burst of 8 or 16 beats. Each of the data beats of the burst transfers effectively only one or two bytes. Note that this burst of 8 or 16 beats is considered an atomic transaction, so the MPC555 / MPC556 does not allow other unrelated master accesses or bus arbitration to intervene between the transfers. 9.5.4 Burst Mechanism In addition to the standard bus signals, the MPC555 / MPC556 burst mechanism uses the following signals: The BURST signal indicates that the cycle is a burst cycle. The burst data in progress (BDIP) signal indicates the duration of the burst data. The burst inhibit (BI) signal indicates whether the slave is burstable. At the start of the burst transfer, the master drives the address, the address attributes, and the BURST signal to indicate that a burst transfer is being initiated, and asserts TS. If the slave is burstable, it negates the burst-inhibit (BI) signal. If the slave cannot burst, it asserts BI. During the data phase of a burst write cycle the master drives the data. It also asserts BDIP if it intends to drive the data beat following the current data beat. When the slave has received the data, it asserts the signal transfer acknowledge to indicate to the master that it is ready for the next data transfer. The master again drives the next data
MPC555
/ MPC556
MOTOROLA 9-16
USERS MANUAL

and asserts or negates the BDIP signal. If the master does not intend to drive another data beat following the current one, it negates BDIP to indicate to the slave that the next data beat transfer is the last data of the burst write transfer. BDIP has two basic timings: normal and late (see Figure 9-13 and Figure 9-14). In the late timing mode, assertion of BDIP is delayed by the number of wait states in the first data beat. This implies that for zero-wait-state cycles, BDIP assertion time is identical in normal and late modes. Cycles with late BDIP generation can occur only during cycles for which the memory controller generates TA internally. Refer to SECTION 10 MEMORY CONTROLLER for more information. In the MPC555 / MPC556, no internal master initiates write bursts. The MPC555 / MPC556 is designed to perform this kind of transaction in order to support an external master that is using the memory controller services. Refer to 10.7 Memory Controller External Master Support. During the data phase of a burst read cycle, the master receives data from the addressed slave. If the master needs more than one data beat, it asserts BDIP. Upon receiving the second-to-last data beat, the master negates BDIP. The slave stops driving new data after it receives the negation of the BDIP signal at the rising edge of the clock.
MPC555
/ MPC556
MOTOROLA 9-17
USERS MANUAL
Master
Request Bus (BR) Receive bus grant (BG) from arbiter
Slave
Assert Bus Busy (BB) if No Other Master is Driving Assert Transfer Start (TS) Drive Address and Attributes Drive BURST Asserted
Receive Address ADDR[28:29] mod 4 = ? =0 Assert BDIP Return Data Assert Transfer Acknowledge (TA)
Receive Data =1 Assert BDIP
BDIP Asserted
No
Drive Last Data & Assert TA
Yes Return Data Assert Transfer Acknowledge (TA)
Receive Data =2 Assert BDIP
BDIP Asserted Yes Return Data Assert Transfer Acknowledge (TA)
No
Receive Data BDIP Asserted =3 Yes Negate Burst Data in Progress (BDIP)
No
Return Data Assert Transfer Acknowledge (TA)
BDIP Asserted Receive Sata Yes
No
Figure 9-11 Basic Flow Diagram Of A Burst Read Cycle

MPC555
/ MPC556
MOTOROLA 9-18
USERS MANUAL
CLKOUT
BR
BG
BB
ADDR[0:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS Last Beat Expects Another Data BDIP
O
Data
TA
Data is Valid
Data is Valid
Data is Valid
Data is Valid
Figure 9-12 Burst-Read Cycle32-Bit Port SizeZero Wait State
MPC555
/ MPC556
MOTOROLA 9-19
USERS MANUAL
CLKOUT
BR
BG
BB
ADDR[0:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS Last Beat Expects Another Data BDIP Normal Late
O O
Data
TA
Wait State
Data is Valid
Data is Valid
Data is Valid
Data is Valid
Figure 9-13 Burst-Read Cycle32-Bit Port SizeOne Wait State
MPC555
/ MPC556
MOTOROLA 9-20
USERS MANUAL
CLKOUT
BR
BG
BB
ADDR[0:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS Last Beat BDIP Normal or Late Expects Another Data
O O
O
Data
TA
Data is Valid
Data is Valid Wait State
Data is Valid
Data is Valid
Figure 9-14 Burst-Read Cycle32-Bit Port SizeWait States Between Beats
MPC555
/ MPC556
MOTOROLA 9-21
USERS MANUAL
CLKOUT
BR
BG
BB
ADDR[0:31]
ADDR[28:31] = 0000
RD/WR
TSIZ[0:1]
00
BURST
TS
BDIP
Data[0:15]
TA
Figure 9-15 Burst-Read Cycle, 16-Bit Port Size
MPC555
/ MPC556
MOTOROLA 9-22
USERS MANUAL

External Master
Request Bus (BR) Receive Bus Grant (BG) from Arbiter Assert Bus Busy (BB) if No Other Master is Driving Assert Transfer Start (TS) Drive Address and Attributes Drive BURST Asserted MTS Asserted (from MPC555) Drive data ADDR[28:29] mod 4 = ? =0 Assert BDIP Sample Data Assert Transfer Acknowledge (TA)
Slave
Receive Address
Drive Data =1 Assert BDIP
BDIP Asserted
No
Dont Sample Next Data
Yes Sample Data Assert Transfer Acknowledge (TA)
Drive Data =2 Assert BDIP
BDIP Asserted Yes Sample Data Assert Transfer Acknowledge (TA)
No
Drive Data BDIP Asserted =3 Yes Negate Burst Data in Progress (BDIP)
No
Sample Data Assert Transfer Acknowledge (TA)
BDIP Asserted Stop Driving Data Yes
No
Figure 9-16 Basic Flow Diagram of a Burst Write Cycle

MPC555
/ MPC556
MOTOROLA 9-23
USERS MANUAL
CLKOUT
BR (from external master)
BG
(from external master) BB (from external master)
ADDR[0:31]
ADDR[28:29] = 00
RD/WR
(from external master)
TSIZ[0:1]
00
BURST (from external master)
TS (from external master)

MTS
Last Beat Will Drive Another Data

BDIP
(from external master)
Data
TA
Data Data Data Data is Sampled is Sampled is Sampledis Sampled
Figure 9-17 Burst-Write Cycle, 32-Bit Port Size, Zero Wait States
MPC555
/ MPC556
MOTOROLA 9-24
USERS MANUAL
CLKOUT
BR
BG
BB
ADDR[0:27]
ADDR[28:29]
ADDR[30:31]
RD/WR
TSIZ[0:1]
00
BURST*
TS
BDIP*
Data
TA
BI
* BURST and BDIP will be asserted for one cycle if the RCPU core requests a burst, but the USIU splits it into a sequence of normal cycles.
Figure 9-18 Burst-Inhibit Cycle, 32-Bit Port Size (Emulated Burst)
MPC555
/ MPC556
MOTOROLA 9-25
USERS MANUAL
CLKOUT
BR
BG
BB
ADDR(0:29)
n (n modulo 4 = 1)
ADDR[30:31]
RD/WR
TSIZ[0:1]
00
BURST
TS Expects Another Data BDIP
O
Data
TA
BI
Figure 9-19 Non-Wrap Burst with Three Beats
MPC555
/ MPC556
MOTOROLA 9-26
USERS MANUAL
CLKOUT
BR
BG
BB
ADDR[0:29]
n (n modulo 4 = 3)
ADDR[30:31]
00
RD/WR
TSIZ[0:1]
00
BURST
TS
BDIP First and Last Beat Data
Is Never Asserted
TA
O
DATA is Sampled
Figure 9-20 Non-Wrap Burst with One Data Beat
MPC555
/ MPC556
MOTOROLA 9-27
USERS MANUAL

9.5.5 Alignment and Packaging of Transfers The MPC555 / MPC556 external bus requires natural address alignment: Byte accesses allow any address alignment Half-word accesses require address bit 31 to equal zero Word accesses require address bits 30 31 to equal zero Burst accesses require address bits 30 31 to equal zero The MPC555 / MPC556 performs operand transfers through its 32-bit data port. If the transfer is controlled by the internal memory controller, the MPC555 / MPC556 can support 8- and 16-bit data port sizes. The bus requires that the portion of the data bus used for a transfer to or from a particular port size be fixed. A 32-bit port must reside on DATA[0:31], a 16-bit port must reside on DATA[0:15], and an 8-bit port must reside on DATA[0:7]. The MPC555 / MPC556 always tries to transfer the maximum amount of data on all bus cycles. For a word operation, it always assumes that the port is 32 bits wide when beginning the bus cycle. In Figure 9-21, Figure 9-22, Table 9-2, and Table 9-3, the following conventions are used: OP0 is the most-significant byte of a word operand and OP3 is the least-significant byte. The two bytes of a half-word operand are either OP0 (most-significant) and OP1 or OP2 (most-significant) and OP3, depending on the address of the access. The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on the address of the access.
0 OP0 OP1 OP2 OP3 31 Word
OP0
OP1 Half-word OP2 OP3
OP0 OP1 Byte OP2 OP3
Figure 9-21 Internal Operand Representation Figure 9-22 illustrates the device connections on the data bus.
MPC555
/ MPC556
MOTOROLA 9-28
USERS MANUAL

0 OP0 OP1 OP2 OP3 31 Interface Output Register DATA[24:31]
DATA[0:7]
DATA[8:15]
DATA[16:23]
OP0
OP1
OP2
OP3
32-bit Port Size
OP0
OP1 16-bit Port Size OP3
OP2
OP0 OP1 8-bit Port Size OP2 OP3
Figure 9-22 Interface To Different Port Size Devices Table 9-2 lists the bytes required on the data bus for read cycles.
MPC555
/ MPC556
MOTOROLA 9-29
USERS MANUAL

Table 9-2 Data Bus Requirements For Read Cycles
Transfer Size TSIZE [0:1] Address ADDR [30:31] 00 01 10 11 00 10 00 DATA [0:7] OP0 OP0 OP0 32-bit Port Size DATA [8:15] OP1 OP1 OP1 DATA [16:23] OP2 OP2 OP2 DATA [24:31] OP3 OP3 OP3 16-bit Port Size DATA [0:7] OP0 OP2 OP0 OP2 OP0 DATA [8:15] OP1 OP3 OP1 OP3 OP1 8-bit Port Size DATA [0:7] OP0 OP1 OP2 OP3 OP0 OP2 OP0
01 Byte 01 01 01 Half-word Word 10 10 00
NOTE: denotes a byte not required during that read cycle.
Table 9-3 lists the patterns of the data transfer for write cycles when the MPC555 / MPC556 initiates an access. Table 9-3 Data Bus Contents for Write Cycles
Transfer Size Address TSIZE[0:1] 01 Byte 01 01 01 Half-word Word 10 10 00 ADDR [30:31] 00 01 10 11 00 10 00 DATA [0:7] OP0 OP1 OP2 OP3 OP0 OP2 OP0 External Data Bus Pattern DATA [8:15] OP1 OP3 OP1 OP3 OP1 DATA [16:23] OP2 OP2 OP2 DATA [24:31] OP3 OP3 OP3
NOTE: denotes a byte not driven during that write cycle.
9.5.6 Arbitration Phase The external bus design provides for a single bus master at any one time, either the MPC555 / MPC556 or an external device. One or more of the external devices on the bus can have the capability of becoming bus master for the external bus. Bus arbitration may be handled either by an external central bus arbiter or by the internal on-chip arbiter. In the latter case, the system is optimized for one external bus master besides the MPC555 / MPC556. The arbitration configuration (external or internal) is set at system reset. Each bus master must have bus request (BR), bus grant (BG), and bus busy (BB) signals. The device that needs the bus asserts BR. The device then waits for the arbiter to assert BG. In addition, the new master must look at BB to ensure that no other master is driving the bus before it can assert BB to assume ownership of the bus. Any time the arbiter has taken the bus grant away from the master and the master wants to exMPC555
/ MPC556
MOTOROLA 9-30
USERS MANUAL

ecute a new cycle, the master must re-arbitrate before a new cycle can be executed. The MPC555 / MPC556, however, guarantees data coherency for access to a small port size and for decomposed bursts. This means that the MPC555 / MPC556 will not release the bus before the completion of the transactions that are considered atomic. Figure 9-23 describes the basic protocol for bus arbitration.
Requesting Device Request the Bus 1. Assert BR Grant Bus Arbitration 1. Assert BG Arbiter
Acknowledge Bus Mastership 1. Wait for BB to be negated. 2. Assert BB to become next master 3. Negate BR Terminate Arbitration 1. Negate BG (or keep asserted to park bus master)
Operate as Bus Master 1. Perform data transfer
Release Bus Mastership 1. Negate BB
Figure 9-23 Bus Arbitration Flowchart 9.5.6.1 Bus Request The potential bus master asserts BR to request bus mastership. BR should be negated as soon as the bus is granted, the bus is not busy, and the new master can drive the bus. If more requests are pending, the master can keep asserting its bus request as long as needed. When configured for external central arbitration, the MPC555 / MPC556 drives this signal when it requires bus mastership. When the internal on-chip arbiter is used, this signal is an input to the internal arbiter and should be driven by the external bus master.
MPC555
/ MPC556
MOTOROLA 9-31
USERS MANUAL

9.5.6.2 Bus Grant The arbiter asserts BG to indicate that the bus is granted to the requesting device. This signal can be negated following the negation of BR or kept asserted for the current master to park the bus. When configured for external central arbitration, BG is an input signal to the MPC555 / MPC556 from the external arbiter. When the internal on-chip arbiter is used, this signal is an output from the internal arbiter to the external bus master. 9.5.6.3 Bus Busy BB assertion indicates that the current bus master is using the bus. New masters should not begin transfer until this signal is negated. The bus owner should not relinquish or negate this signal until the transfer is complete. To avoid contention on the BB line, the master should three-state this signal when it gets a logical one value. This requires the connection of an external pull-up resistor to ensure that a master that acquires the bus is able to recognize the BB line negated, regardless of how many cycles have passed since the previous master relinquished the bus. Refer to Figure 9-24.
Master External Bus
TS MPC555 BB
Slave 2
Figure 9-24 Masters Signals Basic Connection
MPC555
/ MPC556
MOTOROLA 9-32
USERS MANUAL
CLKOUT
BR0
BG0
BR1
BG1
BB
ADDR & Attr.
TS
TA
Master 0 Turns On and Drives Signals
Master 0 Master 1 Negates BB Turns On and and Turns Off Drives Signals (Three-state Controls)
Figure 9-25 Bus Arbitration Timing Diagram 9.5.6.4 Internal Bus Arbiter The MPC555 / MPC556 can be configured at system reset to use the internal bus arbiter. In this case, the MPC555 / MPC556 will be parked on the bus. The parking feature allows the MPC555 / MPC556 to skip the bus request phase, and if BB is negated, assert BB and initiate the transaction without waiting for BG from the arbiter. The priority of the external device relative to the internal MPC555 / MPC556 bus masters is programmed in the SIU module configuration register. If the external device requests the bus and the MPC555 / MPC556 does not require it, or if the external device has higher priority than the current internal bus master, the MPC555 / MPC556 grants the bus to the external device. Table 9-4 describes the priority mechanism used by the internal arbiter.
MPC555
/ MPC556
MOTOROLA 9-33
USERS MANUAL

Table 9-4 Priority Between Internal and External Masters over External Bus1
Type Parked access2 Instruction access Data access External access Direction Internal external Internal external Internal external external external/internal Priority 0 3 4 EARP3 (could be programmed to 0 7)
NOTES: 1. External master will be granted external bus ownership if EARP is greater than the internal access priority. 2. Parked access is instruction or data access from the RCPU which is initiated on the internal bus without requesting it first in order to improve performance. 3. Refer to 6.13.1.1 SIU Module Configuration Register.
Figure 9-26 illustrates the internal finite-state machine that implements the arbiter protocol.
MPC555
/ MPC556
MOTOROLA 9-34
USERS MANUAL
External Owner BG = 0 BB = t.s External Master Requests Bus

BR
MPC555 / MPC556 Internal Master With Higher Priority than the External Device Requires the Bus
=
R
0 =1
BB
BR = 1
Ext Master Release Bus
1, B
BB = 0
IDLE
BG = 1 BB = t.s
MPC555 / MPC556 Bus Wait BG = 1 BB = t.s MCU Needs the Bus
MPC555 / MPC556 No Longer Needs the Bus MPC555 / MPC556 BR = 0 External Device With Higher Priority than the Current Internal Bus Master Requests the Bus Owner BG = 1 BB = 0
BB = 1
MPC555 / MPC556 Still Needs the Bus
Figure 9-26 Internal Bus Arbitration State Machine 9.5.7 Address Transfer Phase Signals Address transfer phase signals include the following: Transfer start Address bus Transfer attributes Transfer attributes signals include RD/WR, BURST, TSIZ[0:1], AT[0:3], STS, and BDIP. With the exception of the BDIP, these signals are available at the same time as the address bus.
MPC555
/ MPC556
MOTOROLA 9-35
USERS MANUAL

9.5.7.1 Transfer Start This signal (TS) indicates the beginning of a transaction on the bus addressing a slave device. This signal should be asserted by a master only after the ownership of the bus was granted by the arbitration protocol. This signal is asserted for the first cycle of the transaction only and is negated in successive clock cycles until the end of the transaction. The master should three-state this signal when it relinquishes the bus to avoid contention between two or more masters in this line. This situation indicates that an external pull-up resistor should be connected to the TS signal to avoid having a slave recognize this signal as asserted when no master drives it. Refer to Figure 9-24. 9.5.7.2 Address Bus The address bus consists of 32 bits, with ADDR[0] the most significant bit and ADDR[31] the least significant bit. The bus is byte-addressable, so each address can address one or more bytes. The address and its attributes are driven on the bus with the transfer start signal and kept valid until the bus master receives the transfer acknowledge signal from the slave. To distinguish the individual byte, the slave device must observe the TSIZ signals. 9.5.7.3 Read/Write A high value on the RD/WR line indicates a read access. A low value indicates a write access. 9.5.7.4 Burst Indicator BURST is driven by the bus master at the beginning of the bus cycle along with the address to indicate that the transfer is a burst transfer. The MPC555 / MPC556 supports a non-wrapping, four-beat maximum, critical word first burst type. The maximum burst size is 16 bytes. For a 32-bit port, the burst includes four beats. For a 16-bit port, the burst includes 8 beats. For an 8-bit port, the burst includes 16 beats at most. Note that 8- and 16-bit ports must be controlled by the memory controller. The actual size of the burst is determined by the address of the starting word of the burst. Refer to Table 9-5 and Table 9-6. Table 9-5 Burst Length and Order
Starting Address ADDR[28:29] 00 01 10 11 Burst Order (Assuming 32-bit Port Size) word 0 word 1 word 2 word 3 word 1 word 2 word 3 word 2 word 3 word 3 Burst Length in Words (Beats) 4 3 2 1 Burst Length in Bytes 16 12 8 4 BDIP never asserted Comments
MPC555
/ MPC556
MOTOROLA 9-36
USERS MANUAL

9.5.7.5 Transfer Size The transfer size signals (TSIZ[0:1]) indicate the size of the requested data transfer. During each transfer, the TSIZ signals indicate how many bytes are remaining to be transferred by the transaction. The TSIZ signals can be used with BURST and ADDR[30:31] to determine which byte lanes of the data bus are involved in the transfer. For nonburst transfers, the TSIZ signals specify the number of bytes starting from the byte location addressed by ADDR[30:31]. In burst transfers, the value of TSIZ is always 00. Table 9-6 BURST/TSIZE Encoding
BURST Negated Negated Negated Negated Asserted TSIZ(0:1) 01 10 11 00 00 Transfer Size Byte Half-word x Word Burst (16 bytes)
9.5.7.6 Address Types The address type (AT[0:3]), program trace (PTR), and reservation transfer (RSV) signals are outputs that indicate one of 16 address types. These types are designated as either a normal or alternate master cycle, user or supervisor, and instruction or data type. The address type signals are valid at the rising edge of the clock in which the special transfer start (STS) signal is asserted. A special use of the PTR and RSV signals is for the reservation protocol described in 9.5.9 Storage Reservation. Refer to 9.5.13 Show Cycle Transactions for information on show cycles. Table 9-7 summarizes the pins used to define the address type. Table 9-8 lists all the definitions achieved by combining these pins. Table 9-7 Address Type Pins
Pin STS TS AT0 AT1 AT2 AT3 PTR RSV Function 0 = Special transfer 1 = Normal transfer 0 = Start of transfer 1 = No transfer Must equal zero on MPC555 / MPC556 0 = Supervisor mode 1 = User mode 0 = Instruction 1 = Data Reservation/Program Trace 0 = Program trace 1 = No program trace 0 = Reservation data 1 = No reservation
MPC555
/ MPC556
MOTOROLA 9-37
USERS MANUAL

:
Table 9-8 Address Types Definition

STS 1 TS x AT0 x AT1 x AT2 x 0 0 1 01 0 0 1 1 1 ? ? 0 0 1 1 0 0 1 1 1 ? ? AT3 x 0 1 0 1 0 1 0 1 ? 0 1 0 1 0 1 0 1 ? PTR 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 RSV 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 No transfer RCPU, normal instruction, program trace, supervisor mode RCPU, normal instruction, supervisor mode RCPU, reservation data, supervisor mode RCPU, normal data, supervisor mode RCPU, normal instruction, program trace, user mode RCPU, normal instruction, user mode RCPU, reservation data, user mode RCPU, normal data, user mode Reserved RCPU, show cycle address instruction, program trace, supervisor mode RCPU, show cycle address instruction, supervisor mode RCPU, reservation show cycle data, supervisor mode RCPU, show cycle data, supervisor mode RCPU, show cycle address instruction, program trace, user mode RCPU, show cycle address instruction, user mode RCPU, reservation show cycle data, user mode RCPU, show cycle data, user mode Reserved Address Space Definitions
NOTES: 1. Cases in which both TS and STS are asserted indicate normal cycles with the show cycle attribute.
9.5.7.7 Burst Data in Progress This signal is sent from the master to the slave to indicate that there is a data beat following the current data beat. The master uses this signal to give the slave advance warning of the remaining data in the burst. BDIP can also be used to terminate the burst cycle early. Refer to 9.5.3 Burst Transfer and 9.5.4 Burst Mechanism for more information. 9.5.8 Termination Signals The EBI uses three termination signals: Transfer acknowledge (TA) Burst inhibit (BI) Transfer error acknowledge (TEA) 9.5.8.1 Transfer Acknowledge Transfer acknowledge indicates normal completion of the bus transfer. During a burst cycle, the slave asserts this signal with every data beat returned or accepted.
MPC555
/ MPC556
MOTOROLA 9-38
USERS MANUAL

9.5.8.2 Burst Inhibit A slave sends the BI signal to the master to indicate that the addressed device does not have burst capability. If this signal is asserted, the master must transfer in multiple cycles and increment the address for the slave to complete the burst transfer. For a system that does not use the burst mode at all, this signal can be tied low permanently. 9.5.8.3 Transfer Error Acknowledge The TEA signal terminates a bus cycle under one or more bus error conditions. The current bus cycle must be aborted. This signal overrides any other cycle termination signals, such as transfer acknowledge. 9.5.8.4 Termination Signals Protocol The transfer protocol was defined to avoid electrical contention on lines that can be driven by various sources. To this end, a slave must not drive signals associated with the data transfer until the address phase is completed and it recognizes the address as its own. The slave must disconnect from signals immediately after it has acknowledged the cycle and no later than the termination of the next address phase cycle. This means that the termination signals must be connected to power through a pull-up resistor to avoid the situation in which a master samples an undefined value in any of these signals when no real slave is addressed. Refer to Figure 9-27 and Figure 9-28.
Slave 1 External Bus
MCU
Acknowledge Signals
Slave 2
Figure 9-27 Termination Signals Protocol Basic Connection
MPC555
/ MPC556
MOTOROLA 9-39
USERS MANUAL
CLKOUT
ADDR[0:31]
Slave 1
Slave 2
RD/WR
TSIZ[0:1]
TS
Data
TA, BI, TEA
Slave 1 Slave 2 Slave 1 Slave 2 negates acknowledge allowed to drive negates acknowledge allowed to drive acknowledge signals signals and turns off acknowledge signals signals and turns off
Figure 9-28 Termination Signals Protocol Timing Diagram 9.5.9 Storage Reservation The MPC555 / MPC556 storage reservation protocol supports a multi-level bus structure. For each local bus, storage reservation is handled by the local reservation logic. The protocol tries to optimize reservation cancellation such that a PowerPC processor is notified of storage reservation loss on a remote bus only when it has issued a stwcx cycle to that address. That is, the reservation loss indication comes as part of the stwcx cycle. This method avoids the need to have very fast storage reservation loss indication signals routed from every remote bus to every PowerPC master. The storage reservation protocol makes the following assumptions: Each processor has, at most, one reservation flag lwarx sets the reservation flag lwarx by the same processor clears the reservation flag related to a previous lwarx instruction and again sets the reservation flag stwcx by the same processor clears the reservation flag Store by the same processor does not clear the reservation flag Some other processor (or other mechanism) store to the same address as an existing reservation clears the reservation flag In case the storage reservation is lost, it is guaranteed that stwcx will not modify the storage
MPC555
/ MPC556
MOTOROLA 9-40
USERS MANUAL

The reservation protocol for a single-level (local) bus is illustrated in Figure 9-29. The protocol assumes that an external logic on the bus carries out the following functions: Snoops accesses to all local bus slaves Holds one reservation for each local master capable of storage reservations Sets the reservation when that master issues a load and reserve request Clears the reservation when some other master issues a store to the reservation address
MPC555 / MPC556 External Bus
External Bus Interface
Master Bus AT[0:3], RSV, R/W, TS
lwarx S R Q
Enable external stwcx access
ADDR[0:29]
CR
Reservation Logic
CR
CLKOUT
Figure 9-29 Reservation On Local Bus The MPC555 / MPC556 samples the CR line at the rising edge of CLKOUT. When this signal is asserted, the reservation flag is reset. The EBI samples the logical value of the reservation flag prior to externally starting a bus cycle initiated by the RCPU stwcx instruction. If the reservation flag is set, the EBI begins with the bus cycle. If the reservation flag is reset, no bus cycle is initiated externally, and this situation is reported to the RCPU. The reservation protocol for a multi-level (local) bus is illustrated in Figure 9-30. The system describes the situation in which the reserved location is sited in the remote bus.
MPC555
/ MPC556
MOTOROLA 9-41
USERS MANUAL
External Bus (Local Bus) External Bus Interface
AT[0:3], RSV, R/W, TS
MPC555 / MPC556
ADDR[0:29] Local Master Accesseses with lwarx to Remove Bus Address KR Q S R Buses Interface A Master in the Remote Bus Write to the Reserved Location
Remote Bus
Figure 9-30 Reservation On Multilevel Bus Hierarchy In this case, the bus interface block implements a reservation flag for the local bus master. The reservation flag is set by the bus interface when a load with reservation is issued by the local bus master and the reservation address is located on the remote bus. The flag is reset when an alternative master on the remote bus accesses the same location in a write cycle. If the MPC555 / MPC556 begins a memory cycle to the previously reserved address (located in the remote bus) as a result of an stwcx instruction, the following two cases can occur: If the reservation flag is set, the buses interface acknowledges the cycle in a normal way If the reservation flag is reset, the bus interface should assert the KR. However,
MPC555
/ MPC556
MOTOROLA 9-42
USERS MANUAL

the bus interface should not perform the remote bus write-access or abort it if the remote bus supports aborted cycles. In this case the failure of the stwcx instruction is reported to the RCPU. 9.5.10 Bus Exception Control Cycles The MPC555 / MPC556 bus architecture requires assertion of TA from an external device to signal that the bus cycle is complete. TA is not asserted in the following cases: The external device does not respond Various other application-dependent errors occur External circuitry can provide TEA when no device responds by asserting TA within an appropriate period of time after the MPC555 / MPC556 initiates the bus cycle (it can be the internal bus monitor). This allows the cycle to terminate and the processor to enter exception-processing for the error condition (each one of the internal masters causes an internal interrupt under this situation). To properly control termination of a bus cycle for a bus error, TEA must be asserted at the same time or before TA is asserted. TEA should be negated before the second rising edge after it was sampled as asserted to avoid the detection of an error for the next initiated bus cycle. TEA is an open drain pin that allows the wired-or of any different sources of error generation. 9.5.10.1 Retrying a Bus Cycle When an external device asserts the RETRY signal during a bus cycle, the MPC555 / MPC556 enters a sequence in which it terminates the current transaction, relinquishes the ownership of the bus, and retries the cycle using the same address, address attributes, and data (in the case of a write cycle). Figure 9-31 illustrates the behavior of the MPC555 / MPC556 when the RETRY signal is detected as a termination of a transfer. As seen in this figure, in the case when the internal arbiter is enabled, the MPC555 / MPC556 negates BB and asserts BG in the clock cycle following the retry detection. This allows any external master to gain bus ownership. In the next clock cycle, a normal arbitration procedure occurs again. As shown in the figure, the external master did not use the bus, so the MPC555 / MPC556 initiates a new transfer with the same address and attributes as before. In Figure 9-32, the same situation is shown except that the MPC555 / MPC556 is working with an external arbiter. In this case, in the clock cycle after the RETRY signal is detected asserted, BR is negated together with BB. One clock cycle later, the normal arbitration procedure occurs again.
MPC555
/ MPC556
MOTOROLA 9-43
USERS MANUAL
CLKOUT
BR
BG (output)
BB
Allow External Master to Gain the Bus
ADDR[0:31]
ADDR
ADDR
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY (input)
Figure 9-31 Retry Transfer TimingInternal Arbiter
MPC555
/ MPC556
MOTOROLA 9-44
USERS MANUAL
CLKOUT
BR (output)
BG
BB
ADDR[0:31]
ADDR
ADDR
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY (input)
Figure 9-32 Retry Transfer TimingExternal Arbiter When the MPC555 / MPC556 initiates a burst access, the bus interface recognizes the RETRY assertion as a retry termination only if it detects it before the first data beat was acknowledged by the slave device. When the RETRY signal is asserted as a termination signal on any data beat of the access after the first (being the first data beat acknowledged by a normal TA assertion), the MPC555 / MPC556 recognizes RETRY as a transfer error acknowledge.
MPC555
/ MPC556
MOTOROLA 9-45
USERS MANUAL
CLKOUT
BR
BG (output)
BB
ADDR[0:31]
ADDR
ADDR
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
BI
RETRY
O
If Asserted Will Cause Transfer Error
Figure 9-33 Retry On Burst Cycle If a burst access is acknowledged on its first beat with a normal TA but with the BI signal asserted, the following single-beat transfers initiated by the MPC555 / MPC556 to complete the 16-byte transfer recognizes the RETRY signal assertion as a transfer error acknowledge. In the case in which a small port size causes the MPC555 / MPC556 to break a bus transaction into several small transactions, terminating any transaction with RETRY
MPC555
/ MPC556
MOTOROLA 9-46
USERS MANUAL

causes a transfer error acknowledge. See 9.5.2.3 Single Beat Flow with Small Port Size. 9.5.10.2 Termination Signals Protocol Summary Table 9-9 summarizes how the MPC555 / MPC556 recognizes the termination signals provided by the slave device that is addressed by the initiated transfer. Table 9-9 Termination Signals Protocol
TEA Asserted Negated Negated TA X Asserted Negated RETRY X X Asserted Action Transfer error termination Normal transfer termination Retry transfer termination
9.5.11 Bus Operation in External Master Modes When an external master takes ownership of the external bus and the MPC555 / MPC556 is programmed for external master mode operation, the external master can access the internal space of the MPC555 / MPC556 (see 6.2 External Master Modes). In an external master mode, the external master owns the bus, and the direction of most of the bus signals is inverted, relative to its direction when the MPC555 / MPC556 owns the bus. The external master gets ownership of the bus and asserts TS in order to initiate an external master access. The access is directed to the internal bus only if the input address matches the internal address space. The access is terminated with one of the followings outputs: TA, TEA, or RETRY. If the access completes successfully, the MPC555 / MPC556 asserts TA, and the external master can proceed with another external master access or relinquish the bus. If an address or data error is detected internally, the MPC555 / MPC556 asserts TEA for one clock. TEA should be negated before the second rising edge after it is sampled asserted in order to avoid the detection of an error for the next bus cycle initiated. TEA is an open drain pin, and the negation timing depends on the attached pullup. The MPC555 / MPC556 asserts the RETRY signal for one clock in order to retry the external master access. If the address of the external access does not match the internal memory space, the internal memory controller can provide the chip-select and control signals for accesses that belong to one of the memory controller regions. This feature is explained in SECTION 10 MEMORY CONTROLLER. Figure 9-34 and Figure 9-35 illustrate the basic flow of read and write external master accesses.
MPC555
/ MPC556
MOTOROLA 9-47
USERS MANUAL
External Master
MPC555 / MPC556
Request Bus (BR)
Receives Bus Grant (BG) From Arbiter
Asserts Bus Busy (BB) if No Other Master is Driving Assert Transfer Start (TS)
Drives Address and Attributes
Receives Address
Address in Internal Memory Map
No
Yes
Memory Returns Data Controller Asserts CSx If In Range
Asserts Transfer Acknowledge (TA)
Receives Data
Figure 9-34 Basic Flow of an External Master Read Access
MPC555
/ MPC556
MOTOROLA 9-48
USERS MANUAL
External Master
MPC555 / MPC556
Request Bus (BR)
Receives Bus Grant (BG) From Arbiter
Asserts Bus Busy (BB) if No Other Master is Driving Assert Transfer Start (TS) Drives Address and Attributes
Receives Address
Drives Data
No
Yes
Memory Controller Asserts CSx If In Range Receives Data
Figure 9-35 Basic Flow of an External Master Write Access ,Figure 9-36, Figure 9-37 and Figure 9-38 describe read and write cycles from an external master accessing internal space in the MPC555 / MPC556. Note that the miniMPC555
/ MPC556
MOTOROLA 9-49
USERS MANUAL

mum number of wait states for such access is two clocks. The accesses in these figures are valid for both peripheral mode and slave mode.
CLKOUT
BR (input)
Use the Internal Arbiter
BG
Receive Bus Grant and Bus Busy Negated
O O
BB
Assert BB, Drive Address and Assert TS
O
ADDR[0:31]
RD/WR
TSIZ[0:1]
BURST
BDIP
TS (input)
O
Data
TA (output) Minimum 2 Wait States DATA is valid
Figure 9-36 Peripheral Mode: External Master Reads from MPC555 / MPC556 Two Wait States
MPC555
/ MPC556
MOTOROLA 9-50
USERS MANUAL
CLKOUT
BR(input)
Use the Internal Arbiter
BG
Receive Bus Grant and Bus Busy Negated
O O
BB
Assert BB, Drive Address and Assert TS
O
ADDR[0:31]
RD/WR
TSIZ[0:1]
BURST
BDIP
TS (input)
O
Data
TA (output) Minimum 2 Wait States DATA is sampled
Figure 9-37 Peripheral Mode: External Master Writes to MPC555 / MPC556; Two Wait States
MPC555
/ MPC556
MOTOROLA 9-51
USERS MANUAL

9.5.12 Contention Resolution on External Bus When the MPC555 / MPC556 is in slave mode, external master access to the MPC555 / MPC556 internal bus can be terminated with relinquish and retry in order to allow a pending internal-to-external access to be executed. The RETRY signal functions as an output that signals the external master to release the bus ownership and retry the access after one clock. Figure 9-38 describes the flow of an external master retried access. Figure 9-39 shows the timing when an external access is retried and a pending internal-to-external access follows.
MPC555
/ MPC556
MOTOROLA 9-52
USERS MANUAL

External Master
MPC555 / MPC556
Request Bus (BR)
Receives BusGrant (BG) from Arbiter
Asserts Bus Busy (BB) if No Other Master is Driving Assert Transfer Start (TS) Drives Address and Attributes
Assert Retry
Release Bus Request (BR) for One Clock and Request Bus (BR) Again Wait Until Bus Busy Negated (No Other Master is Driving) Assert Bus Busy (BB) Assert Transfer Start (TS) Drives Address and Attributes
Receives Address
No
Yes
Memory Controller Asserts CSx If In Range
Returns Data
Receives Data
Figure 9-38 Flow of Retry of External Master Read Access
MPC555
/ MPC556
MOTOROLA 9-53
USERS MANUAL
CLKOUT
BR
BG (output)
BB
Allow Internal Access to Gain the Bus ADDR (ext)ernal ADDR (internal)
ADDR[0:31]
RD/WR
TSIZ[0:1]
BURST
TS
Data
TA
RETRY(output)
O Note: the delay for the internal to external cycle may be one clock or greater.
Figure 9-39 Retry of External Master Access (Internal Arbiter) 9.5.13 Show Cycle Transactions Show cycles are accesses to the CPUs internal bus devices. These accesses are driven externally for emulation, visibility, and debugging purposes. A show cycle can have one address phase and one data phase, or just an address phase in the case of instruction show cycles. The cycle can be a write or a read access. The data for both the read and write accesses should be driven by the bus master. (This is different from normal bus read and write accesses.) The address and data of the show cycle must each be valid on the bus for one clock. The data phase must not require a transfer ac-
MPC555
/ MPC556
MOTOROLA 9-54
USERS MANUAL

knowledge to terminate the bus show cycle. In a burst show cycle only the first data beat is shown externally. Refer to Table 9-8 for show cycle transaction encodings. Instruction show cycle bus transactions have the following characteristics (see Figure 9-40): One clock cycle Address phase only STS assertion only (no TA assertion)
I
CLKOUT
BR (in)
BG (out)
BB
ADDR[0:31]
ADDR1
ADDR2
RD/WR
TSIZ[0:1]
BURST
TS
STS
Data (three-state)
TA
Normal Non-Show Cycle Bus Transaction
Instruction Show Cycle Bus Transaction
Figure 9-40 Instruction Show Cycle Transaction
MPC555
/ MPC556
MOTOROLA 9-55
USERS MANUAL

Both read and write data show cycles have the following characteristics (see Figure 9-41): Two clock cycle duration Address valid for two clock cycles Data is valid only in the second clock cycle STS signal only is asserted (no TA or TS)
CLKOUT
BR (in)
BG (out)
BB
ADDR[0:31]
ADDR1
ADDR2
RD/WR
TSIZ[0:1]
BURST
TS
STS
Data TA
DATA1
DATA2
Read Data Show Cycle Bus Transaction Write Data Show Cycle Bus Transaction
Figure 9-41 Data Show Cycle Transaction
MPC555
/ MPC556
MOTOROLA 9-56
USERS MANUAL
SECTION 10 MEMORY CONTROLLER

The memory controller generates interface signals to support a glueless interface to external memory and peripheral devices. It supports four regions, each with its own programmed attributes. The four regions are reflected on four chip-select pins. Read and write strobes are also provided. The memory controller operates in parallel with the external bus interface to support external cycles. When an access to one of the memory regions is initiated, the memory controller takes ownership of the external signals and controls the access until its termination. Refer to Figure 10-1.
ADDR[0:31] EBI Bus
External Bus Interface
DATA[0:31] Control Bus
Internal Bus
U-bus Interface
WE[0:3]/BE[0:3] Memory Controller Bus
Memory Controller
OE CS[0:3]
Figure 10-1 Memory Controller Function Within the USIU 10.1 Overview The memory controller provides a glueless interface to EPROM, static RAM (SRAM), Flash EPROM (FEPROM), and other peripherals. The general-purpose chip-selects are available on lines CS[0] through CS[3]. CS[0] also functions as the global (boot)
MEMORY CONTROLLER
MOTOROLA 10-1

chip-select for accessing the boot flash EEPROM. The chip select allows zero to 30 wait states. Figure 10-2 is a block diagram of the MPC555 / MPC556 memory controller.
INTERNAL ADDRESSES [0:16, AT[0:2]
Base Register
Option Register
0 (OR0) 1 (OR1) 2 (OR2) 0 (OR0) 1 (OR1) 2 (OR2)
Base Register 3 (BR3)
Option Register 3 (OR3) Dual Mapping Option Register (DMOR)
Dual Mapping Base Register (DMBR)
Region Match Logic
ATTRIBUTES
CS[0:3] Expired Wait State Counter Load WE/BE[0:3] OE
General-Purpose Chip-Select Machine (GPCM)
Figure 10-2 Memory Controller Block Diagram Most memory controller features are common to all four banks. (For features unique to the CS[0] bank, refer to 10.4 Global (Boot) Chip-Select Operation.) A full 32-bit address decode for each memory bank is possible with 17 bits having address masking. The full 32-bit decode is available, even if all 32 address bits are not sent to the MPC555 / MPC556 pins. Each memory bank includes a variable block size of 32 Kbytes, 64 Kbytes and up to 4 Gbytes. Each memory bank can be selected for read-only or read/write operation. The access to a memory bank can be restricted to certain address type codes for system protection. The address type comparison occurs with a mask option as well.
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-2
USERS MANUAL

From zero to 30 wait states can be programmed with TA generation. Four byte-write and read-enable signals (WE/BE[0:3]) are available for each byte that is written to memory. An output enable (OE) signal is provided to eliminate external glue logic. A memory transfer start (MTS) strobe permits one master on a bus to access external memory through the chip selects on another. The memory controller functionality allows MPC555 / MPC556-based systems to be built with little or no glue logic. A minimal system using no glue logic is shown in Figure 10-3. In this example CS[0] is used for the 16-bit boot EPROM and CS[1] is used for the 32-bit SRAM. The WE/BE[0:3] signals are used both to program the EPROM and to enable write access to various bytes in the RAM.
Address CS[0] OE
Address CE CE OE OE WE/BE[0:1]
Data [0:15]
DATA[0:15]
EPROM
MPC555 / MPC556
Address CS[1] WE/BE[0:3] CE WE/BE[0:3]
W
[0:31] Data OE
SRAM
Figure 10-3 MPC555 / MPC556 Simple System Configuration 10.2 Memory Controller Architecture The memory controller consists of a basic machine that handles the memory access cycle: the general-purpose chip-select machine (GPCM). When a new access to external memory is requested by any of the internal masters, the address of the transfer (with 17 bits having mask) and the address type (with 3 bits having mask) are compared to each one of the valid banks defined in the memory controller. Refer to Figure 10-4.
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-3
USERS MANUAL
Base Address
RB ARB A RB A RB A RB A O O O O O O O O O RB A RB A
[0] [1] [2] [3] [4] [15] [16]
Address Mask
M
[0]
M
[1]
M
[2]
M
[3]
M
[4]
M
[5]
M
[6]
M
[7]
OOOO M
[16]
A[0:16]
M[0:16]
comp comp comp comp comp comp comp comp comp comp comp
Match
Figure 10-4 Bank Base Address and Match Structure When a match is found on one of the memory banks, its attributes are selected for the functional operation of the external memory access: Read-only or read/write operation Number of wait states for a single memory access, and for any beat in a burst access Burst-inhibit indication. Internal burst requests are still possible during burst-inhibited cycles; the memory controller emulates the burst cycles Port size of the external device Note that if more than one region matches the internal address supplied, then the lowest region is selected to provide the attributes and the chip select. 10.2.1 Associated Registers Status bits for each memory bank are found in the memory control status register (MSTAT). The MSTAT reports write-protect violations for all the banks. Each of the four banks has a base register (BR) and an option register (OR). The BRx and ORx registers contain the attributes specific to bank x. The base register contains a valid bit (V) that indicates that the register information for that chip select is valid. 10.2.2 Port Size Configuration The memory controller supports dynamic bus sizing. Defined 8-bit ports can be accessed as odd or even bytes. Defined 16-bit ports, when connected to data bus lines zero to 15, can be accessed as odd bytes, even bytes, or even half-words. Defined 32bit ports can be accessed as odd bytes, even bytes, odd half-words, even half-words,
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-4
USERS MANUAL

or words on word boundaries. The port size is specified by the PS bits in the base register. 10.2.3 Write-Protect Configuration The WP bit in each base register can restrict write access to its range of addresses. Any attempt to write this area results in the associated WPER bit being set in the MSTAT. If an attempt to access an external device results in a write-protect violation, the memory controller considers the access to be no match. No chip-select line is asserted externally, and the memory controller does not terminate the cycle. The external bus interface generates a normal cycle on the external bus. Since the memory controller does not acknowledge the cycle internally, the cycle may be terminated by external logic asserting TA or by the on-chip bus monitor asserting TEA. 10.2.4 Address and Address Space Checking The base address is written to the BR. The address mask bits for the address are written to the OR. The address type access value, if desired, is written to the AT bits in the BR. The ATM bits in the OR can be used to mask this value. If address type checking is not desired, program the ATM bits to zero. Each time an external bus cycle access is requested, the address and address type are compared with each one of the banks. If a match is found, the attributes defined for this bank in its BR and OR are used to control the memory access. If a match is found in more than one bank, the lowest bank matched handles the memory access (e.g., bank zero is selected over bank one). Note that when an external master accesses a slave on the bus, the internal AT[0:2] lines reaching the memory controller are forced to 100. 10.2.5 Burst Support Burst support is for read only. The memory controller supports burst accesses of external burstable memory. To enable bursts, clear the BI in the appropriate base register. Bursts are four beats and non-wrapping. That is, the memory controller executes up to four one-word accesses, but when a modulo four limit is reached, the burst is terminated (even if fewer than four words have been accessed). When the SIU initiates a burst access, if no match is found in any of the memory controllers regions then a burst access is initiated to the external bus. The termination of each beat for this access is externally controlled (i.e., the user is responsible for terminating each data beat using the bus termination protocol). To support different types of memory devices, the memory controller supports two types of timing for the BDIP signal: normal and late. Note that the BDIP pin itself is controlled by the external bus interface logic. Refer to Figure 9-13 and Figure 9-14 in SECTION 9 EXTERNAL BUS INTERFACE. / MPC556
MPC555
MEMORY CONTROLLER
MOTOROLA 10-5
USERS MANUAL

If the memory controller is used to support an external master accessing an external device with bursts, the BDIP input pin is used to indicate to the memory controller when the burst is terminated. For addition details, refer to 9.5.3 Burst Transfer. 10.3 Chip-Select Timing The GPCM allows a glueless and flexible interface between the MPC555 / MPC556 and SRAM, EPROM, EEPROM, ROM devices and external peripherals. When an address and address type matches the values programmed in the BR and OR for one of the memory controller banks, the attributes for the memory cycle are taken from the OR and BR registers as well. These attributes include the following fields: CSNT, ACS, SCY, BSCY, WP, TRLX, BI, PS, and SETA.
Byte write and read-enable signals (WE/BE[0:3]) are available for each byte that is written to or read from memory. An output enable (OE) signal is provided to eliminate external glue logic for read cycles. Upon system reset, a global (boot) chip select is available. This provides a boot ROM chip select before the system is fully configured. Table 10-1 summarizes the chip-select timing options. Table 10-1 Timing Attributes Summary
Timing Attribute Access speed Bits/Fields TRLX Description The TRLX (timing relaxed) bit determines strobe timing to be fast or relaxed. The EHTR (extended hold time on read accesses) bit is provided for devices that have long disconnect times from the data bus on read accesses. EHTR specifies whether the next cycle is delayed one clock cycle following a read cycle, to avoid data bus contentions. EHTR applies to all cycles following a read cycle except for another read cycle to the same region. The ACS (address-to-chip-select setup) and CSNT (chip-select negation time) bits cause the timing of the strobes to be the same as the address bus timing, or cause the strobes to have setup and hold times relative to the address bus. From zero to 15 wait states can be programmed for any cycle that the memory controller generates. The transfer is then terminated internally. In simplest case, the cycle length equals (2 + SCY) clock cycles, where SCY represents the programmed number of wait states (cycle length in clocks). The number of wait states is doubled if the TRLX bit is set. When the SETA (external transfer acknowledge) bit is set, TA must be generated externally, so that external hardware determines the number of wait states.
Intercycle space time
EHTR
Synchronous or asynchronous device
ACS, CSNT
Wait states
SCY, BSCY, SETA, TRLX
Note that when a bank is configured for TA to be generated externally (SETA bit is set) and the TRLX is set, the memory controller requires the external device to provide at least one wait state before asserting TA to complete the transfer. In this case, the minimum transfer time is three clock cycles. The internal TA generation mode is enabled if the SETA bit in the OR register is negated. However, if the TA pin is asserted externally at least two clock cycles before the
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-6
USERS MANUAL

wait states counter has expired, this assertion terminates the memory cycle. When SETA is cleared, it is forbidden to assert external TA less than two clocks before the wait states counter expires. 10.3.1 Memory Devices Interface Example Figure 10-5 describes the basic connection between the MPC555 / MPC556 and a static memory device. In this case CSx is connected directly to the chip enable (CE) of the memory device. The WE/BE[0:3] lines are connected to the respective W in the memory device where each WE/BE line corresponds to a different data byte.
MPC555 / MPC556 Address
Memory
Address
CSx OE WE/BE
CE OE W
Data
Data
Figure 10-5 MPC555 / MPC556 GPCMMemory Devices Interface In Figure 10-6, the CSx timing is the same as that of the address lines output. The strobes for the transaction are supplied by the OE and the WE/BE lines (if programmed as WE/BE). Because the ACS bits in the corresponding ORx register = 00, CS is asserted at the same time that the address lines are valid. Note that because CSNT is set, the WE signal is negated a quarter of a clock earlier than normal.
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-7
USERS MANUAL
Clock
Address
TS
TA
CSNT = 1, ACS = 00
CS
WE/BE
OE
Data
Note: In this and subsequent timing diagrams in this section, the data bus refers to a read cycle. In a write cycle, the data immediately follows TS.
Figure 10-6 Memory Devices Interface Basic Timing (ACS = 00,TRLX = 0) 10.3.2 Peripheral Devices Interface Example Figure 10-7 illustrates the basic connection between the MPC555 / MPC556 and an external peripheral device. In this case CSx is connected directly to the chip enable (CE) of the memory device and the R/W line is connected to the R/W in the peripheral device. The CSx line is the strobe output for the memory access.
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-8
USERS MANUAL

MPC555 / MPC556
Peripheral Address
Address
CSx RD/WR
CE R/W
Data
Data
Figure 10-7 Peripheral Devices Interface The CSx timing is defined by the setup time required between the address lines and the CE line. The memory controller allows the user to specify the CS timing to meet the setup time required by the peripheral device. This is accomplished through the ACS field in the base register. In Figure 10-8, the ACS bits are set to 11, so CSx is asserted half a clock cycle after the address lines are valid.
CLOCK ACS = 11 Address
TS
CSNT = 1
TA
CS
RD/WR
Data
Figure 10-8 Peripheral Devices Basic Timing (ACS = 11,TRLX = 0)

MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-9
USERS MANUAL

10.3.3 Relaxed Timing Examples The TRLX field is provided for memory systems that need a more relaxed timing between signals. When TRLX is set and ACS = 0b00, the memory controller inserts an additional cycle between address and strobes (CS line and WE/OE). When TRLX and CSNT are both set in a write to memory, the strobe lines (WE/BE[0:3] and CS, if ACS = 0b00) are negated one clock earlier than in the regular case. Note that in the case of a bank selected to work with external transfer acknowledge (SETA = 1) and TRLX = 1, the memory controller does not support external devices providing TA to complete the transfer with zero wait states. The minimum access duration in this case equals three clock cycles. Figure 10-9 shows a read access with relaxed timing. Note the following:
Strobes (OE and CS) assertion time is delayed one clock relative to address (TRLX bit set effect). Strobe (CS) is further delayed (half-clock) relative to address due to ACS field being set to 11. Total cycle length = 5, is determined as follows: Two clocks for basic cycle SCY = 1 determines 1 wait state, which is multiplied by two due to TRLX being set. Extra clock is added due to TRLX effect on the strobes.
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-10
USERS MANUAL
CLOCK
Address
ACS = 00 & TRLX = 1
TS
ACS = 11 & TRLX = 1
TA
CS
RD/WR
WEBS = 0,Line Acts as BE in Read.
WE/BE
OE
Data
Figure 10-9 Relaxed TimingRead Access (ACS = 11, SCY = 1, TRLX = 1)
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-11
USERS MANUAL

Figure 10-10 through Figure 10-12 are examples of write accesses using relaxed timing. In Figure 10-10, note the following points: Because TRLX is set, assertion of the CS and WE strobes is delayed by one clock cycle. CS assertion is delayed an additional one quarter clock cycle because ACS = 10. The total cycle length = three clock cycles, determined as follows: The basic memory cycle requires two clock cycles. An extra clock cycle is required due to the effect of TRLX on the strobes.
CLOCK
Address
TS
ACS = 10
TA
CS
RD/WR
WE/BE
OE
Data
Figure 10-10 Relaxed TimingWrite Access (ACS = 10, SCY = 0, CSNT = 0, TRLX = 1)
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-12
USERS MANUAL

In Figure 10-11, note the following: Because the TRLX bit is set, the assertion of the CS and WE strobes is delayed by one clock cycle. Because ACS = 11, the assertion of CS is delayed an additional half clock cycle. Because CSNT = 1, WE is negated one clock cycle earlier than normal. (Refer to Figure 10-6). The total cycle length is four clock cycles, determined as follows: The basic memory cycle requires two clock cycles. Two extra clock cycles are required due to the effect of TRLX on the assertion and negation of the CS and WE strobes.
Clock
Address
TS
ACS =11
ACS!=00 & CSNT = 1
TA
CS
RD/WR
WE/BE
OE CSNT = 1 Data
Figure 10-11 Relaxed Timing Write Access (ACS = 11, SCY = 0, CSNT = 1, TRLX = 1)
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-13
USERS MANUAL

In Figure 10-12, notice the following: Because ACS = 0, TRLX being set does not delay the assertion of the CS and WE strobes. Because CSNT = 1, WE/BE is negated one clock cycle earlier than normal. (Refer to Figure 10-6). CS is not negated one clock cycle earlier, since ACS = 00. The total cycle length is three clock cycles, determined as follows: The basic memory cycle requires two clock cycles. One extra clock cycle is required due to the effect of TRLX on the negation of the WE/BE strobes.
CLOCK
Address
TS
No Effect, ACS = 00
TA
CS
RD/WR
WE/BE
OE CSNT = 1 Data
Figure 10-12 Relaxed Timing Write Access (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1 10.3.4 Extended Hold Time on Read Accesses For devices that require a long disconnection time from the data bus on read accesses, the bit EHTR in the corresponding OR register can be set. In this case any MPC555 / MPC556 access to the external bus following a read access to the referred memory bank is delayed by one clock cycle unless it is a read access to the same bank. Figure
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-14
USERS MANUAL

10-13 through Figure 10-16 show the effect of the EHTR bit on memory controller timing. Figure 10-13 shows a write access following a read access. Because EHTR = 0, no extra clock cycle is inserted between memory cycles.
CLOCK
Address
TS
TA
CSx
CSy
RD/WR
OE Tdt Data
Figure 10-13 Consecutive Accesses (Write After Read, EHTR = 0)
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-15
USERS MANUAL

Figure 10-14 shows a write access following a read access when EHTR = 1. An extra clock is inserted between the cycles. For a write cycle following a read, this is true regardless of whether both accesses are to the same region.
CLOCK
Address
TS
TA
CSx
CSy
RD/WR
OE
Tdt
Data
Extra clock before next cycle starts.
Long Tdt allowed
Figure 10-14 Consecutive Accesses (Write After Read, EHTR = 1)
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-16
USERS MANUAL

Figure 10-15 shows consecutive accesses from different banks. Because EHTR = 1 (and the accesses are to different banks), an extra clock cycle is inserted.
Clock
Address
TS
TA
CSx
CSy
RD/WR
OE
Tdt
Data
Extra Clock Before Next Cycle Starts
Long Tdt Allowed
Figure 10-15 Consecutive Accesses (Read After Read From Different Banks, EHTR = 1)
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-17
USERS MANUAL

Figure 10-16 shows two consecutive read cycles from the same bank. Even though EHTR = 1, no extra clock cycle is inserted between the memory cycles. (In the case of two consecutive read cycles to the same region, data contention is not a concern.)
CLOCK
Address
TS
TA
CSx
CSy
RD/WR
OE Tdt Data
Figure 10-16 Consecutive Accesses (Read After Read From Same Bank, EHTR = 1) 10.3.5 Summary of GPCM Timing Options Table 10-2 summarizes the different combinations of timing options.
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-18
USERS MANUAL

Table 10-2 Programming Rules for Strobes Timing
TRLX 0 0 0 0 0 0 0 0 Access Type Read Read Read Write Write Write Write Write Write Read Read Read Write Write Write Write Write Write ACS 00 10 11 00 10 11 00 10 11 00 10 11 00 10 11 00 10 11 CSNT X X X 0 0 0 1 1 1 X X X 0 0 0 1 1 1 Address to CS Asserted 0 1/4 * clock 1/2 * clock 0 1/4 * clock 1/2 * clock 0 1/4 * clock 1/2 * clock 0 (1 + 1/4) * clock (1 + 1/2) * clock 0 (1 + 1/4) * clock (1 + 1/2) * clock 0 (1 + 1/4) * clock (1 + 1/2) * clock CS Address to WE/BE OE Negated to WE/BE or Negated to Negated to Add/Data OE Add/Data Add/Data Asserted Invalid Invalid Invalid 1/4 * clock 1/4 * clock 1/4 * clock 1/4 * clock 1/4 * clock 1/4 * clock 1/4 * clock 1/2 * clock 1/2 * clock 1/4 * clock 1/4 * clock 1/4 * clock 1/4 * clock 1/4 * clock 1/4 * clock 1/4 * clock (1 + 1/2) * clock (1 + 1/2) * clock 3/4 * clock 3/4 * clock 3/4 * clock 3/4 * clock 3/4 * clock 3/4 * clock 3/4 * clock 3/4 * clock 3/4 * clock 3/4 clock (1 + 3/4) * clock (1 + 3/4) * clock 3/4 clock (1 + 3/4) * clock (1 + 3/4) clock 3/4 clock (1 + 3/4) clock (1 + 3/4) clock X X X 1/4 * clock 1/4 * clock 1/4 * clock 1/2 * clock 1/2 * clock 1/2 * clock X X X 1/4 * clock 1/4 * clock 1/4 * clock (1 + 1/2) * clock (1 + 1/2) * clock (1 + 1/2) * clock 1/4 * clock 1/4 * clock 1/4 * clock X X X X X X 1/4 * clock 1/4 * clock 1/4 * clock X X X X X X Total Number of Cycles 2 + SCY 2 + SCY 2 + SCY 2 + SCY 2 + SCY 2 + SCY 2 + SCY 2 + SCY 2 + SCY 2+ 2 * SCY 3+ 2 * SCY 3+ 2 * SCY 2+ 2 * SCY 3+ 2 * SCY 3+ 2 * SCY 3+ 2 * SCY 4+ 2 * SCY 4+ 2 * SCY
0 1 1 1 1 1 1 1 1 1
NOTE: Timing in this table refers to the typical timing only. Consult the electrical characteristics for exact worstcase timing values. 1/4 clock actually means 0 to 1/4 clock, 1/2 clock means 1/4 to 1/2 clock.
Additional timing rules not covered in Table 10-2 include the following: If SETA = 1, an external TA signal is required to terminate the cycle. If TRLX = 1 and SETA = 1, the minimum cycle length = 3 clock cycles (even if SCY = 0000) If TRLX = 1, the number of wait states = 2 * SCY & 2 * BSCY If EHTR = 1, an extra (idle) clock cycle is inserted between a read cycle and a following read cycle to another region, or between a read cycle and a following write cycle to any region. If LBDIP = 1 (late BDIP assertion), the BDIP pin is asserted only after the number of wait states for the first beat in a burst have elapsed. See Figure 9-13 in SECTION 9 EXTERNAL BUS INTERFACE as well as 9.5.4 Burst Mechanism. Note that this function can operate only when the cycle termination is internal, using the number of wait states programmed in one of the ORx registers
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-19
USERS MANUAL

10.4 Global (Boot) Chip-Select Operation Global (boot) chip-select operation allows address decoding for a boot ROM before system initialization. CS[0] is the global chip-select output. Its operation differs from that of the other external chip-select outputs following a system reset. When the RCPU begins accessing memory after a system reset, CS[0] is asserted for every address, unless an internal device (register) is accessed. The global chip select provides a programmable port size at system reset using the reset BPS pins ([4:5]) of the reset configuration word, allowing a boot ROM to be located anywhere in the address space. For more information, see 7.5.2 Hard Reset Configuration Word. The global chip select does not provide write protection and responds to all address types. CS[0] operates in this way until the first write to the CS[0] option register (OR0). The pin can be programmed to continue decoding a range of addresses after this write, provided the preferred address range is first loaded into base register zero. After the first write to OR0, the global chip select can only be restarted with a system reset. The memory controller operates in boot mode until the user modifies the values in OR0 and BR to the ones desired. Table 10-3 shows the initial values of the boot bank in the memory controller. Table 10-3 Boot Bank Fields Values After Hard Reset
Field PS WP V AM[0:16] ATM[0:2] CSNT ACS[0:1] BI SCY[0:3] BSCY[0:2] SETA TRLX Value (Binary) From reset configuration 0 From reset configuration 0 0000 0000 0000 0000 000 0 00 1 1111 011 0 0
NOTE If the MPC555 / MPC556 is configured (in the reset configuration word) to use the internal flash EEPROM as boot memory CS[0] is not asserted.
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-20
USERS MANUAL

10.5 Write and Byte Enable Signals The GPCM determines the timing and value of the WE/BE signals if allowed by the port size of the accessed bank, the transfer size of the transaction and the address accessed. The functionality of the WE/BE[0:3] pins depends upon the value of the write enable/ byte select (WEBS) bit in the corresponding BR register. Setting WEBS to 1 will enable these pins as BE, while resetting it to zero will enable them as WE. WE is asserted only during write access, while BE is asserted for both read and write accesses. The timing of the WE/BE pins remains the same in either case, and is determined by the TRLX, ACS and CSNT bits. The upper WE/BE (WE[0]/BE[0]) indicates that the upper eight bits of the data bus (D0D7) contains valid data during a write/read cycle. The upper-middle write byte enable (WE[1]/BE[1]) indicates that the upper-middle eight bits of the data bus (D8D15) contains valid data during a write/read cycle. The lower-middle write byte enable (WE[2]/BE[2]) indicates that the lower-middle eight bits of the data bus (D16D23) contains valid data during a write/read cycle. The lower write/read enable (WE[3]/ BE[3]) indicates that the lower eight bits of the data bus contains valid data during a write cycle. The write/byte enable lines affected in a transaction for 32-bit port (PS = 00), a 16-bit port (PS = 10) and a 8-bit port (PS = 01) are shown in Table 10-4. This table shows which write enables are asserted (indicated with an X) for different combinations of port size and transfer size Table 10-4 Write Enable/Byte Enable Signals Function
Address Transfer Size TSIZ 0 Byte 0 0 0 HalfWord Word 1 1 0 1 1 1 1 0 0 0 A30 0 0 1 1 0 1 0 32-bit Port Size 16-bit Port Size 8-bit Port Size
WE[0] WE[1] WE[2] WE[3] WE[0] WE[1] WE[2] WE[3] WE[0] WE[1] WE[2] WE[3] / / / / / / / / / / / / A31 BE[0] BE[1] BE[2] BE[3] BE[0] BE[1] BE[2] BE[3] BE[0] BE[1] BE[2] BE[3]
0 1 0 1 0 0 0
X X X X X X X X X X X X
X X X X X X X X X X
X X X X X X X
10.6 Dual Mapping of the Internal Flash EEPROM Array The user can enable mapping of the internal flash EEPROM (CMF) module to an external memory region controlled by the memory controller. Only one region can be programmed to be dual-mapped. When dual mapping is enabled (DME bit is set in DMBR), an internal address matches the dual-mapped address range (as programmed in the DMBR), and the cycle type matches AT/ATM field in DMBR/DMOR registers, then the following occur: The internal flash memory does not respond to that address
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-21
USERS MANUAL

The memory controller takes control of the external access The attributes for the access are taken from one of the base and option registers of the appropriate chip select The chip-select region selected is determined by the CS line select bit field (10.8.5 Dual Mapping Base Register (DMBR)). Note that dual mapping can operate only for addresses within the FLASH pre-allocated address (up to 2 Mbytes). This is achieved by programming only six bits for the base address (11:16); The upper bits are always set as follows: bus_addr[0:10]={0000000,isb[0:2],0} Where ISB[0:2] represents the bit field in IMMR register that determines the location of the address map of the MPC555 / MPC556. With dual mapping, aliasing of address spaces may occur. This happens when the user maps the dual-mapped region into a region which is also mapped into one of the four regions available in the memory controller. If the user writes code or data to the dual-mapped region, care must be taken to avoid overwriting this code or data by normal accesses of the chip-select region. There is a match if: bus_address[0:16] == {0000000,isb[0:2],0,dmbr_reg_value[1:6]} Care must also be taken to avoid overwriting normal CSx data with dual-mapped code or data. One way to avoid this situation is by disabling the chip-select region and enabling only the dual-mapped region (DME = 1, but Vx = 0, where x = selected region, 0.3). Figure 10-17 illustrates the phenomena.
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-22
USERS MANUAL
MPC555 / MPC556 Memory Map
Physical External Memory
Dual Mapping
CSx
Dual-Map region
Flash
External CSx
Figure 10-17 Aliasing Phenomena Illustration The default state is to allow dual-mapping data accesses only; this means that dual mapping is possible only for data accesses on the internal bus. Also, the default state takes the lower two Mbytes of the MPC555 / MPC556 internal flash memory. Hence, caution should be taken to change the dual-mapping setup before the first data access. NOTE Dual mapping is not supported for an external master when the memory controller serves the access; In such a case, the MPC555 / MPC556 terminates the cycle by asserting TEA.
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-23
USERS MANUAL

10.7 Memory Controller External Master Support The memory controller in the MPC555 / MPC556 supports accesses initiated by both internal and external bus masters to external memories. If the address of any master is mapped within the internal MPC555 / MPC556 address space, the access will be directed to the internal device, and will be ignored by the memory controller. If the address is not mapped internally, but rather mapped to one of the memory contoller regions, the memory controller will provide the appropriate chip select and strobes as programmed in the corresponding region (see 6.13.1.3 External Master Control Register (EMCR). The MPC555 / MPC556 supports only synchronous external bus masters. This means that the external master works with CLKOUT and implements the MPC555 / MPC556 bus protocol to access a slave device.
A synchronous master initiates a transfer by asserting TS. The ADDR[0:31] signals must be stable from the rising edge of CLKOUT during which TS is sampled, until the last TA acknowledges the transfer. Since the external master works synchronously with the MPC555 / MPC556, only setup and hold times around the rising edge of CLKOUT are important. Once the TS is detected/asserted, the memory controller compares the address with each one of its defined valid banks to find a possible match. But, since the external address space is shorter than the internal space, the actual addess that is used for comparing against the memory controller regions is in the format of: {00000000, bits 8:16 of the external address}. In the case where a match is found, the controls to the memory devices are generated and the transfer acknowledge indication (TA) is supplied to the master. Since it takes two clocks for the external address to be recognized and handled by the memory controller, the TS which is generated by the external master is ahead of the corresponding CS and strobes which are asserted by the memory controller. This 2clock delay might cause problems in some synchronous memories. To overcome this, the memory controller generates the MTS (memory transfer start) strobe which can be used in the slaves memory instead of the external masters TS signal. As seen in Figure 10-18, the MTS strobe is synchronized to the assertion of CS by the memory controller so that the external memory can latch the external masters address correctly. To activate this feature, the MTSC bit must be set in the SIUMCR register. Refer to 6.13.1.1 SIU Module Configuration Register for more information. When the external master accesses the internal flash when it is disabled, then the access is terminated with transfer error acknowledge (TEA pin) asserted, and the memory controller does not support this access in any way. When the memory controller serves an external master, the BDIP pin becomes an input pin. This pin is watched by the memory controller to detect when the burst is terminated.
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-24
USERS MANUAL

Synchronous External Master
TA MPC555 / MPC556 TA TS MTS Address CSx
TS
BDIP
Data
ADDR
BURST
Memory
TS Address CE OE W BDIP Data BURST
OE WE/BE BDIP Data BURST
Note that the memory controllers BDIP line is used as a burst_in_progress signal.
Figure 10-18 Synchronous External Master Configuration For GPCMHandled Memory Devices
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-25
USERS MANUAL
Address Match & Compare
Memory Device Access
CLOCK
ADDR[0:31]
RD/WR
BURST
TSIZE
TS
MTS
TA
CS
WE/BE
OE
Data
Figure 10-19 Synchronous External Master Basic Access (GPCM Controlled) Note that since the MPC555 / MPC556 has only 24 address pins, the eight most significant internal address lines are driven as 0x0000_0000, and so compared in the memory controllers regions.
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-26
USERS MANUAL

10.8 Programming Model The following registers are used to control the memory controller. Table 10-5 Memory Controller Address Map
Address 0x2F C100 0x2F C104 0x2F C108 0x2F C10C 0x2F C110 0x2F C114 0x2F C118 Register Base Register Bank 0 (BR0) Option Register Bank 0 (OR0) Base Register Bank 1 (BR1) Option Register Bank 1 (OR1) Base Register Bank 2 (BR2) Option Register Bank 2 (OR2) Base Register Bank 3 (BR3) Option Register Bank 3 (OR3) Reserved Dual-Mapping Base Register (DMBR) Dual-Mapping Option Register (DMOR) Reserved Memory Status Register (MSTAT)
0x2F C11C 0x2F C120 0x13F 0x2F C140 0x2F C144 0x2F C148 0x2F C174 0x2F C178
Note: In all subsequent registers bit tables, if two reset values are given: the upper is for CSx, x = 1, 2, 3, and the lower is dedicated to CS[0].
10.8.1 General Memory Controller Programming Notes 1. In the case of an external master that accesses an internal MPC555 / MPC556 module (in slave or peripheral mode), if that slave device address also matches one of the memory controllers regions, the memory controller will not issue any CS for this access, nor will it terminate the cycle. Thus, this practice should be avoided. Be aware also that any internal slave access prevents memory controller operation. 2. If the memory controller serves an external master, then it can support accesses to 32-bit port devices only. This is because the MPC555 / MPC556 external bus interface cannot initiate extra cycles to complete an access to a smaller port-size device as it does not own the external bus. 3. When the SETA bit in the base register is set, then the timing programming for the various strobes (CS, OE and WE/BE) may become meaningless.
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-27
USERS MANUAL

10.8.2 Memory Controller Status Registers (MSTAT)
,
MSTAT Memory Controller Status Register

MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13
0x2F C178
14 LSB 15
RESERVED HARD RESET: 0 0 0 0 0 0 0 0
WPER WPER WPER WPER 0 1 2 3
RESERVED
Table 10-6 MSTAT Bit Descriptions

Bit(s) 0:7 Name Reserved Description
8:11
Write protection error for bank x. This bit is asserted when a write-protect error occurs for the WPER0 associated memory bank. A bus monitor (responding to TEA assertion) will, if enabled, prompt WPER3 the user to read this register if TA is not asserted during a write cycle. WPERx is cleared by writing one to the bit or by performing a system reset. Writing a zero has no effect on WPER. Reserved
12:15
10.8.3 Memory Controller Base Registers (BR0 BR3)

,
BR0 BR3 Memory Controller Base Registers 0 3 0x2F C100, C108, C110, C118
MSB 0 1 2 3 4 5 6 7 BA HRESET U U U U U U U U U U U U U U U U 8 9 10 11 12 13 14 15
16
17
18
19
20
21
22 RESERV ED
23
24
25
26
27
28
29
30
LSB 31 V
BA
AT
PS
WP
RESERVED
WEBS TBDIP LBDIP SETA
BI
HRESET U U U U ID[4:5]* 0 0 0 0 0 0 0 1 ID3**
* Reset value is determined by the value on the internal data bus during reset. ** The BR0 Reset value is determined by the value on the internal data bus during reset (reset-configuration word). The reset value of the V bit of BR1-3 = 0.
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-28
USERS MANUAL

Table 10-7 BR0 BR3 Bit Descriptions
Bit(s) Name Description Base address. These bits are compared to the corresponding unmasked address signals among ADDR[0:16] to determine if a memory bank controlled by the memory controller is being accessed by an internal bus master. (The address types are also compared.) These bits are used in conjunction with the AM[0:16] bits in the OR. Address type. This field can be used to require accesses of the memory bank to be limited to a certain address space type. These bits are used in conjunction with the ATM bits in the OR. Note that the address type field uses only AT[0:2] and does not need AT[3] to define the memory type space. For a full definition of address types, refer to 9.5.7.6 Address Types. Port size 00 = 32-bit port 01 = 8-bit port 10 = 16-bit port 11 = Reserved Reserved Write protect. An attempt to write to the range of addresses specified in a base address register that has this bit set can cause the TEA signal to be asserted by the bus-monitor logic (if enabled), causing termination of this cycle. 0 = Both read and write accesses are allowed 1 = Only read accesses are allowed. The CSx signal and TA are not asserted by the memory controller on write cycles to this memory bank. WPER is set in the MSTAT register if a write to this memory bank is attempted Reserved Write-enable/byte-select. This bit controls the functionality of the WE/BE pads. 0 = The WE/BE pads operate as WE 1 = The WE/BE pads operate as BE Toggle-burst data in progress. TBDIP determines how long the BDIP strobe will be asserted for each data beat in the burst cycles. Late-burst-data-in-progress (LBDIP). This bit determines the timing of the first assertion of the BDIP pin in burst cycles. 28 LBDIP Note: it is not allowed to set both LBDIP and TBDIP bits in a regions base registers; the behavior of the design in such cases is unpredictable. 0 = Normal timing for BDIP assertion (asserts one clock after negation of TS 1 = Late timing for BDIP assertion (asserts after the programmed number of wait states External transfer acknowledge 0 = TA generated internally by memory controller 1 = TA generated by external logic. Note that programming the timing of CS/WE/OE strobes may have no meaning when this bit is set Burst inhibit 0 = Memory controller drives BI negated (high). The bank supports burst accesses. 1 = Memory controller drives BI asserted (low). The bank does not support burst accesses. Note: Following a system reset, the BI bit is set in OR0. Valid bit. When set, this bit indicates that the contents of the base-register and option-register pair are valid. The CS signal does not assert until the V-bit is set. Note that an access to a region that has no V-bit set may cause a bus monitor timeout. Note also that following a system reset, the V-bit in BR0 reflects the value of ID3 in the reset configuration word.
0:16
BA
17:19
AT
20:21
PS
22
23
WP
24:25 26
WEBS
27
TBDIP
29
SETA
30
BI
31
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-29
USERS MANUAL

10.8.4 Memory Controller Option Registers (OR0 OR3)
,
OR0 OR3 Memory Controller Option Registers 0 3

MSB 0 1 2 3 4 5 6 7 AM* HRESET: (OR[1:3]) U U U U U U U U U U U U 8 9 10 11
0x2F C104, C10C, C114, C11C

12 13 14 15
HRESET (OR0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 AM*
17
18 ATM
19
20 CSNT
21 ACS
22
23 EHTR
24
25 SCY
26
27
28
29 BSCY
30
LSB 31 TRLX
HRESET: (OR[1:3]): U U U U U U U U U U U U U U U U
HRESET (OR0) 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0
*It is recommended that this field would hold values that are the power of 2 minus 1 (e.g., - 23 - 1 = 7 [0b111]).
Table 10-8 OR0 OR3 Bit Descriptions

Bit(s) Name Description Address mask. This field allows masking of any corresponding bits in the associated base register. Masking the address bits independently allows external devices of different size address ranges to be used. Any clear bit masks the corresponding address bit. Any set bit causes the corresponding address bit to be used in comparison with the address pins. Address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. This field can be read or written at anytime. Following a system reset, the AM bits are reset in OR0. Address type mask. This field masks selected address type bits, allowing more than one address space type to be assigned to a chip-select. Any set bit causes the corresponding address type code bits to be used as part of the address comparison. Any cleared bit masks the corresponding address type code bit. Clear the ATM bits to ignore address type codes as part of the address comparison. Note that the address type field uses only AT[0:2] and does not need AT[3] to define the memory type space. Following a system reset, the ATM bits are reset in OR0. Chip-select negation time. Following a system reset, the CSNT bit is reset in OR0. 0 = CS/WE are negated normally. 1 = CS/WE are negated a quarter of a clock earlier than normal Following a system reset, the CSNT bit is reset in OR0. Address to chip-select setup. Following a system reset, the ACS bits are reset in OR0. 00 = CS is asserted at the same time that the address lines are valid. 01 = Reserved 10 = CS is asserted a quarter of a clock after the address lines are valid. 11 = CS is asserted half a clock after the address lines are valid Following a system reset, the ACS bits are reset in OR0.
0:16
AM
17:19
ATM
20
CSNT
21:22
ACS
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-30
USERS MANUAL

Table 10-8 OR0 OR3 Bit Descriptions (Continued)
Bit(s) Name Description Extended hold time on read accesses. This bit, when asserted, inserts an idle clock cycle after a read access from the current bank and any MPC555 / MPC556 write accesses or read accesses to a different bank. 0 = Memory controller generates normal timing 1 = Memory controller generates extended hold timing Cycle length in clocks. This four-bit value represents the number of wait states inserted in the single cycle, or in the first beat of a burst, when the GPCM handles the external memory access. Values range from from 0 (0b0000) to 15 (0b1111). This is the main parameter for determining the length of the cycle. 24:27 SCY The total cycle length may vary depending on the settings of other timing attributes. The total memory access length is (2 + SCY) x Clocks. If the user has selected an external TA response for this memory bank (by setting the SETA bit), then the SCY field is not used. NOTE: Following a system reset, the SCY bits are set to 0b1111 in OR0. Burst beats length in clocks. This field determines the number of wait states inserted in all burst beats except the first, when the GPCM starts handling the external memory access and thus using SCY[0:3] as the main parameter for determining the length of that cycle. The total cycle length may vary depending on the settings of other timing attributes. The total memory access length for the beat is is (1 + BSCY) x Clocks. 28:30 BSCY If the user has selected an external TA response for this memory bank (by setting the SETA bit) then BSCY[0:3] are not used. 000 = 0-clock-cycle (1 clock per data beat) 001 = 1-clock-cycle wait states (2 clocks per data beat) 010 = 2-clock-cycle wait states (3 clocks per data beat) 011 = 3-clock-cycle wait states (4 clocks per data beat) 1xx = Reserved Timing relaxed. This bit, when set, modifies the timing of the signals that control the memory devices during a memory access to this memory region. Relaxed timing multiplies by two the number of wait states determined by the SCY and BSCY fields. Refer to 10.3.5 Summary of GPCM Timing Options for a full list of the effects of this bit on pins timing. 0 = Normal timing is generated by the GPCM. 1 = Relaxed timing is generated by the GPCM Following a system reset, the TRLX bit is set in OR0.
23
EHTR
31
TRLX
10.8.5 Dual Mapping Base Register (DMBR)

,
DMBR Dual Mapping Base Register

MSB 0 0 HARD RESET: 0 16 U 17 U 18 U 19 U 20 U 21 U 22 0 23 0 24 0 25 0 26 0 27 1 28 0 29 1 2 3 BA 4 5 6 7 8 RESERVED 9 10 11 AT 12 13
0x2F C140
14 RESERVED 15
0 30
0 LSB 31 DME
RESERVED HARD RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0
DMCS
ID31*
*The reset value is a reset configuration word value extracted from the indicated internal data bus lines.
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-31
USERS MANUAL

Table 10-9 DMBR Bit Descriptions
Bit(s) 0 Name Reserved Base address. The base address field is compared (along with the address type field) to the address of the address bus to determine whether an address should be dual-mapped by one of the memory banks controlled by the memory controller. These bits are used in conjunction with the AM[11:16] bits in the OR. Bit 10: is cleared at reset. That way, the default range for the dual mapping is 2 Mbytes. Note that by setting this bit, the range becomes 4 Mbyte, which includes memory space beyond the flash EEPROM memory. 7:9 Reserved Address type. This field can be used to specify that accesses involving the memory bank are limited to a certain address space type. These bits are used in conjunction with the ATM bits in the OR. The default value at reset is to map data only. For a full definition of address types, refer to 9.5.7.6 Address Types. Reserved Dual-mapping chip select. This field determines which chip-select pin is assigned for dual mapping. 000 = CS[0] 001 = CS[1] 010 = CS[2] 011 = CS[3] 1xx = Reserved Dual mapping enabled. This bit indicates that the contents of the dual-mapping registers and associated base and option registers are valid and enables the dual-mapping operation. The default value at reset comes from the internal data bus that reflects the reset configuration word. See 10.6 Dual Mapping of the Internal Flash EEPROM Array for more information. 0 = Dual mapping is not active 1 = Dual mapping is active Description
1:6
BA
10:12
AT
13:27
28:30
DMCS
31
DME
10.8.6 Dual-Mapping Option Register

,
DMOR Dual-Mapping Option Register

MSB 0 0 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 3 AM* 4 5 6 7 8 RESERVED 9 10 11 ATM 12 13
0x2F C144
14 RESERVED 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
*It is recommended that this field would hold values that are the power of 2 minus 1 (e.g., - 23 - 1 = 7 [0b111]).
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-32
USERS MANUAL

Table 10-10 DMOR Bit Descriptions
Bit(s) 0 Name Reserved Address mask. The address mask field of each option register provides for masking any of the corresponding bits in the associated base register. By masking the address bits independently, external devices of different size address ranges can be used. Any clear bit masks the corresponding address bit. Any set causes the corresponding address bit to be used in the comparison with the address pins. Address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. This field can be read or written at any time. Reserved Address type mask. This field can be used to mask certain address type bits, allowing more than one address space type to be assigned to a chip select. Any set bit causes the corresponding address type code bits to be used as part of the address comparison. Any cleared bit masks the corresponding address type code bit. 10:12 ATM To instruct the memory controller to ignore address type codes as part of the address comparison, clear the ATM bits. Note: Following a system reset, the ATM bits are cleared in DMOR, except the ATM2 bit. This means that only data accesses are dual mapped. Refer to the address types definition in Table 9-8. 13:31 Reserved Description
1:6
AM
7:9
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-33
USERS MANUAL
MPC555
/ MPC556
MEMORY CONTROLLER
MOTOROLA 10-34
USERS MANUAL
SECTION 11 L-BUS TO U-BUS INTERFACE (L2U)

The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses. The L2U is bi-directional. It allows load/store accesses not intended for the L-bus data RAM to go to the U-bus. It also allows code execution from the L-bus data RAM and read/write accesses from the U-bus to the L-bus.
The L2U directs bus traffic between the L-bus and the U-bus. When transactions start concurrently on both buses, the L2U interface arbitrates to select which transaction is handled. The top priority is assigned to U-bus to L-bus accesses; lower priority is assigned to the load/store accesses by the RCPU. 11.1 General Features Non-pipelined master and slave on U-bus Does not start two back-to-back accesses on the U-bus Supports the U-bus pipelining by starting a cycle on the U-bus when U-bus pipe depth is zero or one Does not accept back-to-back accesses from the U-bus master Non-pipelined master and slave on the L-bus Generates module selects for L-bus memory-mapped resources within a programmable, contiguous block of storage Programmable data memory protection unit (DMPU) L-bus and U-bus snoop logic for PowerPC reservation protocol L2U does not support dual mapping of L-bus or IMB3 space Show cycles for RCPU accesses to the SRAM (none, all, writes) Protection for SRAM accesses from the U-bus side (all accesses to the SRAM from the U-bus side are blocked once the SRAM protection bit is set) 11.2 DMPU Features Supports four memory regions whose base address and size can be programmed Available sizes are 4 Kbytes, 8 Kbytes, 16 Kbytes, 32 Kbytes, 64 Kbytes, 128 Kbytes, 256 Kbytes, 512 Kbytes, 1 Mbyte, 2 Mbytes, 4 Mbytes, 8 Mbytes, and 16 Mbytes Region must start on the specified region size boundary Overlap between regions is allowed Each of the four regions supports the following attributes: Access protection: user or supervisor Guarded attribute: speculative or non-speculative Enable/disable option Read only option
MPC555 / MPC556 USERS MANUAL L-BUS TO U-BUS INTERFACE (L2U) MOTOROLA 11-1

Supports a default global entry for memory space not covered by other regions: Default access protection Default guarded attribute Interrupt generated upon: Access violation Load from guarded region Write to read-only region The PowerPC MSR[DR] bit (data relocate) controls DMPU protection on/off operation Programming is done using PowerPCs mtspr/mfspr instructions to/from implementation specific special purpose registers. No protection for accesses to the SRAM module on the L-bus (SRAM has its own protection options)
11.3 L2U Block Diagram Figure 11-1 shows a block diagram of the L-bus to U-bus interface.
L-bus
L-bus Interface
Address Decode
Reservation Control
DMPU
U-bus Interface
U-bus
Figure 11-1 L2U Bus Interface Block Diagram 11.4 Modes Of Operation The L2U Module can operate in the following modes: Normal Mode Reset Operation Factory Test Mode Peripheral Mode
MPC555
/ MPC556
L-BUS TO U-BUS INTERFACE (L2U)
MOTOROLA 11-2
USERS MANUAL

11.4.1 Normal Mode In normal mode (master or slave) the L2U module acts as a bi-directional protocol translator. In master mode the CPU is fully operational, and there is no external master access to the U-bus. Slave mode enables an external master to access any internal bus slave while the CPU is fully operational. The L2U transfers load/store accesses from the RCPU to the U-bus and the read/write accesses by the U-bus master to the L-bus. In addition to the bus protocol translation, the L2U supports other functions such as show cycles, data memory protection and PowerPC reservation protocol. When a load from the U-bus resource or store to the U-bus resource is issued by the RCPU, it is compared against the DMPU region access (address and attribute) comparators. If none of the access attributes are violated, the access is directed to the Ubus by the L2U module. If the DMPU detects an access violation, it informs the error status to the master initiating the cycle. When show cycles are enabled, accesses to all of the L-bus resources by the RCPU are made visible on the U-bus side by the L2U. The L2U is responsible for handling the effects of reservations on the L-bus and the U-bus. For the L-bus and the U-bus, the L2U detects reservation losses and updates the RCPU core with the reservation status. 11.4.2 Reset Operation Upon soft reset assertion, the L2U goes to an idle state and all pending accesses are ignored. The L2U module control registers are not initialized on the assertion of a soft reset, keeping the system configuration unchanged. Upon assertion of hard reset, the L2U control registers are initialized to their reset states. While reset (hard or soft) is asserted on the U-bus, the L2U asserts the corresponding L-bus reset signals. The L2U also drives the reset configuration word from the U-bus to the L-bus upon assertion of hard reset. 11.4.3 Factory Test Mode Factory test mode is a special mode of operation that allows access to the internal modules for testing. This mode is not intended for general use and is not supported for normal applications. 11.4.4 Peripheral Mode In the peripheral mode of operation the RCPU is shut down and an alternative master on the external bus can perform accesses to any internal bus (U-bus and L-bus) slave. The external master can also access the internal PowerPC special registers that are located in L2U. In order to access one of these PowerPC registers the EMCR[CONT] bit in the USIU must be cleared.
MPC555
/ MPC556
MOTOROLA 11-3
USERS MANUAL

11.5 Data Memory Protection The data memory protection unit (DMPU) in the L2U module provides access protection for the memory regions on the U-bus side from load/store accesses by the RCPU. (Only U-bus space is protected.) The DMPU does not protect PowerPC register accesses initiated by the RCPU on the L-bus. The user can assign up to four regions of access protection attributes and can assign global attributes to any space not included in the active regions. When it detects an access violation, the L2U generates an exception request to the CPU.
Access attribute
Address
Region0 Address and size Region1 Address and size Region2 Address and size Region3 Address and size
Match select
Region0 protection/attribute Region1 protection/attribute Region2 protection/attribute Region3 protection/attribute Global protection/attribute Specific Error Interrupts to Core RegionProtection/Attribute
MSRDR
Exception Logic ACCESS GRANTED
Figure 11-2 DMP Basic Functional Diagram 11.5.1 Functional Description Data memory protection is assigned on a regional basis. Default manipulation of the DMPU is done on a global region. The DMPU has control registers which contain the following information: region protection on/off, region base address, region size, and the regions access permissions. Each regions protection attributes can be turned on/ off by configuring the enable attribute bit (ENRx) located in the global region attribute register. During each load/store access from the RCPU core to the U-bus, the address is compared to the value in the region base address register of each enabled region. Any access that matches the specific region within its appropriate size, as defined by the region size field (RS) of the region attribute register, sets a match indication.
MPC555
/ MPC556
MOTOROLA 11-4
USERS MANUAL

When more than one match indication occurs, the effective region is the region with the highest priority. Priority is determined by region number; highest priority corresponds to the lowest region number. When no match occurs, the effective region is the global region. The global region has the lowest priority. The region attribute register also contains the regions protection fields. The protection field (PP) of the effective region is compared to the access attributes. If the attributes match, the access is permitted. When the access is permitted, a U-bus access may be generated according to the specific attribute of the effective region. When the access by the RCPU is not permitted, the L2U module asserts a data memory storage exception to the RCPU.
For speculative load/store accesses from the RCPU to a region marked as guarded (G bit of region attribute register is set), the L2U asks the RCPU to retry the L-bus cycle until either the access is not speculative, or it is canceled by the RCPU. In the case of attempted accesses to a guarded region together with any other protection violation (no access), the L2U retries the access. The L2U handles this event as a data storage violation only when the access becomes non-speculative. Note that access protection is active only when the PowerPCs MSR[DR] = 1. When MSR[DR] = 0, DMPU exceptions are disabled, all accesses are considered to be to a guarded memory area, and no speculative accesses are allowed. In this case, if the Lbus master [RCPU] initiates a non-SRAM cycle (access through the L2U) that is marked speculative, the L2U asks the RCPU to retry the L-bus cycle until either the access is not speculative, or it is canceled by the RCPU core. Note that the programmer must not overlap the SRAM memory space with any enabled region. Overlapping an enabled region with SRAM memory space disables the L2U data memory protection for that region. If an enabled region overlaps with the L-bus space, the DMPU ignores all accesses to addresses within the L-bus space. If an enabled region overlaps with PowerPC register addresses, the DMPU ignores any access marked as a PowerPC access. 11.5.2 Associated Registers The following registers are used to control the DMPU of the L2U module. All the registers are special purpose registers which are accessed via the PowerPC mtspr/mfspr instructions. The registers are also accessed by an external master when EMCR[CONT] = 0. See 11.8 L2U Programming Model for register diagrams and bit descriptions.
MPC555
/ MPC556
MOTOROLA 11-5
USERS MANUAL

.
Table 11-1 DMPU Registers

Name L2U_RBA0 L2U_RBA1 L2U_RBA2 L2U_RBA3 L2U_RA0 L2U_RA1 L2U_RA2 L2U_RA3 L2U_GRA Description Region Base Address Register 0 Region Base Address Register 1 Region Base Address Register 2 Region Base Address Register 3 Region Attribute Register 0 Region Attribute Register 1 Region Attribute Register 2 Region Attribute Register 3 Global Region Attribute
CAUTION The appropriate DMPU registers must be programmed before the MSR[DR] bit is set. Otherwise, DMPU operation is not guaranteed. Program the region base address in the L2U_RBAx registers to the lower boundary of the region specified by the corresponding L2U_RAx[RS] field. If the region base address does not correspond to the boundary of the block size programmed in the L2U_RAx, the DMPU snaps the region base to the lower boundary of that block. For example, if the block size is programmed to 16 Kbytes for region zero (i.e. L2U_RA0[RS] = 0 x 3) and the region base address is programmed to 0x1FFF(i.e., L2U_RBA0[RBA] = 0 x 1), then the effective base address of region zero is 0 x 0. See Figure 11-3.
0x0000 0000 region 0 (16 Kbytes) Resulting Region 0x0000 1FFF Actual Programmed Region 0x0000 3FFF
0x0000 5FFF
Figure 11-3 Region Base Address Example It is the users responsibility to program only legal region sizes. The L2U does not check whether the value is legal. If the user programs an illegal region size, the region calculation may not be successful.
MPC555
/ MPC556
MOTOROLA 11-6
USERS MANUAL

11.5.3 L-bus Memory Access Violations All L-bus slaves have their own access protection logic. For consistency, all storage access violations have the same termination result. Thus access violations for load/ store accesses started by the RCPU always have the same termination from all slaves: assertion of the data storage exception. All other L-bus masters cause machine check exceptions. 11.6 Reservation Support The RCPU storage reservation protocol supports a multi-level bus structure. For each local bus, storage reservation is handled by the local reservation logic. The protocol tries to optimize reservation cancellation such that a PowerPC processor (RCPU) is notified of storage reservation loss on a remote bus (U-bus, IMB or external bus) only when it has issued a stwcx cycle to that address. That is, the reservation loss indication comes as part of the stwcx cycle. 11.6.1 The Reservation Protocol The reservation protocol operates under the following assumptions: Each processor has at most 1 reservation flag A lwarx instruction sets the reservation flag Another lwarx instruction by same processor clears the reservation flag related to a previous lwarx instruction and sets again the reservation flag A stwcx instruction by same processor clears the reservation flag A store instruction by same processor does not clear the reservation flag Some other processor (or other mechanism) store to an address with an existing reservation clears the reservation flag In case the storage reservation is lost, it is guaranteed that stwcx will not modify the storage 11.6.2 L2U Reservation Support The L2U is responsible for handling the effects of reservations on the L-bus and the U-bus. For the L-bus and the U-bus, the L2U detects reservation losses. The reservation logic in the L2U performs the following functions: Snoops accesses to all L-bus and U-bus slaves Holds one reservation (address) for the core Sets the reservation flag when the CPU issues a load-with-reservation request The unit for reservation is one word. A byte or half-word store request by another master will clear the reservation flag. A load-with-reservation request by the CPU updates the reservation address related to a previous load-with-reservation request and sets the reservation flag for the new location. A store-with-reservation request by the CPU clears the reservation flag. A store request by the CPU does not clear the flag. A store request by some other master to the reservation address clears the reservation flag.
MPC555
/ MPC556
MOTOROLA 11-7
USERS MANUAL

If the storage reservation is lost, it is guaranteed that a store-with-reservation request by the CPU will not modify the storage. The L2U does not start a store-with-reservation cycle on the U-bus if the reserved location on the U-bus has been touched by another master. The L2U drives the reservation status back to the core. When the reserved location in the SRAM on the L-bus is touched by an alternate master, on the following clock, the L2U indicates to the CPU that the reservation has been touched. On assertion of the cancel-reservation signal, the RCPU clears the internal reservation bit. If an stwcx cycle has been issued at the same time, the RCPU aborts the cycle. Storage reservation is set regardless of the termination status (address or data phase) of the lwarx access. Storage reservation is cleared regardless of the data phase termination status of the stwcx access if the address phase is terminated normally. Storage reservation will be cleared regardless of the data phase termination status of the write requests by another master to the reserved address if the address phase of the write access is terminated normally on the destination (U-bus/L-bus) bus. If the programmable memory map of the part is modified between a lwarx and a stwcx instruction, the reservation is not guaranteed. 11.6.3 Reserved Location (Bus) and Possible Actions Once the CPU core reserves a memory location, the L2U module is responsible for snooping L-bus and U-bus for possible intrusion of the reserved location. Under certain circumstances, the L2U depends on the USIU or the UIMB to provide status of reservation on external bus and the IMB3 respectively. Table 11-2 lists all reservation protocol cases supported by the L2U snooping logic.
MPC555
/ MPC556
MOTOROLA 11-8
USERS MANUAL

Table 11-2 Reservation Snoop Support
Reserved Location On L-bus Intruding Alternate Master L-Master U-Master U-bus L-Master U-Master External Bus L-Master U-Master Ext-Master IMB3 L-Master U-Master IMB3-Master Action Taken on stwcx cycle Request to cancel the reservation.1 Request to cancel the reservation. Block stwcx2 Block stwcx Block stwcx Block stwcx Transfer Status3 Block stwcx Block stwcx Transfer Status
NOTES: 1. If the RCPU tries to modify (stwcx) that location, the L2U does not have enough time to stop the write access from completing. In this case, the L2U will drive cancel-reservation signal back to the core as soon as it comes to know that the alternate master on the U-bus has touched the reserved location. 2. If the RCPU tries to modify (stwcx) that location, the L2U does not start the cycle on the U-bus and it communicates to the core that the current write has been aborted by the slave with no side effects. 3. If the RCPU tries to modify (stwcx) that location, the L2U runs a write-cycle-with-reservation request on the U-bus. The L2U samples the status of the reservation along with the U-bus cycle termination signals and it communicates to the core if the current write has been aborted by the slave with no side effects.
11.7 L-Bus Show Cycle Support The L2U module provides support for L-bus show cycles. L-bus show cycles are external visibility cycles that reflect activity on the L-bus that would otherwise not be visible to the external bus. L-bus show cycles are software controlled. 11.7.1 Programming Show Cycles L-bus show cycles are disabled during reset and must be configured by writing the appropriate bits in the L2U_MCR control register. L-bus show cycles are programmed by setting the LSHOW[0:1] bits in the L2U_MCR. The Table 11-3 shows the configurations of the LSHOW[0:1] bits. Table 11-3 L2U_MCR LSHOW Modes
LSHOW 00 01 10 11 Action Disable L-bus show cycles Show address and data of all L-bus space write cycles Reserved (Disable L-bus show cycles) Show address and data of all L-bus space read and write cycles
11.7.2 Performance Impact When show cycles are enabled in the L2U module, there is a performance penalty on the L-bus. This occurs because the L2U module does not support more than one access being processed at any time. To ensure that only one access at a time can be
MPC555
/ MPC556
MOTOROLA 11-9
USERS MANUAL

processed, and not lose an L-bus access that would have been show cycled, the L2U module will arbitrate for the L-bus whenever it is processing any access. This L-bus arbitration will prevent any other L-bus master from starting a cycle that might turn out to be a qualifiable L-bus show cycle. For L-bus show cycles, the minimum performance impact on the L-bus will be three clocks. This minimum impact assumes that the L-bus slave access is a 1-clock access, and the L2U module acquires immediate bus grant on the U-bus. The L2U has to wait two clocks before completing the show cycle on the U-Bus, thus using up five clocks for the complete process. A retried access on the L-bus (no address acknowledge) that qualifies to be show cycled, will be accepted when it is actually acknowledged. This will cause a 1-clock delay before an L-bus master can retry the access on the L-bus, because the L2U module will release L-bus one clock later. L2U asserts the internal bus request signal on the U-bus for a minimum of two clocks when starting a show cycle on the U-bus. 11.7.3 Show Cycle Protocol The L2U module behaves as both a master and a slave on the U-bus during show cycles. The L2U starts the U-bus transfer as a a bus master and then completes the address phase and data phase of the cycle as a slave. The L2U follows U-bus protocol of in-order termination of the data phase. The USIU can control the start of show cycles on the U-bus by asserting the no-show cycle indicator. This will cause the L2U module to release the U-bus for at least one clock before retrying the show cycle. 11.7.4 L-Bus Write Show Cycle Flow The L2U performs the following sequence of actions for an L-bus-write show cycle. 1. Arbitrates for the L-bus to prevent any other L-bus cycles from starting 2. Latches the address and the data of the L-bus access, along with all address attributes 3. Waits for the termination of the L-bus access and latches the termination status (data error) 4. Arbitrate for the U-bus, and when granted, starts the U-bus access, asserting show cycle request on the U-bus, along with address, attributes and the write data. The L2U module provides address recognize and acknowledgment for the address phase. If the no-show cycle indicator from the U-bus is asserted, the L2U does not start the show cycle. The L2U module releases the U-bus until the no-show cycle indicator is negated and then arbitrates for the U-bus again. 5. When the L2U module has U-bus data bus grant, it drives the data phase termination handshakes on the U-bus. 6. Releases the L-bus
MPC555
/ MPC556
MOTOROLA 11-10
USERS MANUAL

11.7.5 L-Bus Read Show Cycle Flow The L2U performs the following sequence of actions for an L-bus read show cycle. 1. Arbitrates for the L-bus to prevent any other L-bus cycle from starting 2. Latches the address of the L-bus access, along with all address attributes 3. Waits for the data phase termination on the L-bus and latch the read data, and the termination status from the L-bus 4. Arbitrate for the U-bus, and when granted, starts the U-bus access, asserting the show cycle request on the U-bus, along with address attributes. The L2U module provides address recognize/acknowledgment for the address phase. If the no-show cycle indicator from the U-bus is asserted, the L2U does not start the show cycle. The L2U module releases the U-bus until the no-show cycle indicator is negated and then arbitrates for the U-bus again. 5. When the L2U module has U-bus data bus grant, it drives the read data and the data phase termination handshakes on the U-bus 6. Release the L-bus. 11.7.6 Show Cycle Support Guidelines The following are the guidelines for L2U show cycle support: The L2U module provides address and data for all qualifying L-bus cycles when the appropriate mode bits are set in the L2U_MCR. The L2U-module-only show cycles L-bus activity that is not targeted for the U-bus or the L2U module internal registers, irrespective of the termination status of such activity. The L2U module does not show cycle any access to a PowerPC special purpose register. The L2U does not start a show cycle for an L-bus access that is retried. This decision to not start the show cycle causes a clock delay before the cycle can be retried, since the L2U module will have arbitrated away the L-bus immediately on detecting the show cycle, before the retry information is available. The L2U module does not show cycle any L-bus activity that is aborted. The L2U module backs off the U-bus if the USIU inhibits show cycle activity on the U-bus. The L2U does not show cycle any L-bus addresses that fall in the L-bus SRAM address space if the SRAM Protection [SP] bit is set in the L2U_MCR. Table 11-4 summarizes the L2U show cycle support.
MPC555
/ MPC556
MOTOROLA 11-11
USERS MANUAL

Table 11-4 L2U Show Cycle Support Chart
Case 1 2 3 4 5 Destination
L-bus Slave1 L2U 2 U-bus/E-bus 3 L-bus slave L-bus slave
LB AACK
No X X Yes Yes
LB ABORT
X X X No Yes
Comments
Not show cycled [Cycle will be retried one clock later]4 Not show cycled Not show cycled Show cycled Not show cycled [L-bus will be released next clock]
1. L-bus slave includes all address in the L-bus address space. 2. L2U indicates L2U registers. 3. U-bus/E-bus refers to all destinations through the L2U interface. 4. There will be a 1-clock turnaround because the L-bus retry information is not available in time to negate the Lbus arbitration. Note: X indicates dont care conditions.
11.8 L2U Programming Model The L2U control registers control the L2U bus interface and the DMPU. They are accessible via the MPC555 / MPC556 mtspr and mfspr instructions. They are also accessible by an external master when EMCR[CONT] bit is cleared. L2U control registers are accessible from both the L-bus side and the U-bus side in one clock cycle. As with all SPRs, L2U registers are accessible in supervisor mode only. Any unimplemented bits in L2U registers return 0s on a read, and the writes to those register bits are ignored. The Table 11-5 shows L2U registers along with their SPR numbers and hexadecimal addresses which are used to access L2U registers during a peripheral mode access.
.
Table 11-5 L2U (PPC) Register Decode

Name L2U_MCR L2U_RBA0 L2U_RBA1 L2U_RBA2 L2U_RBA3 L2U_RA0 L2U_RA1 L2U_RA2 L2U_RA3 L2U_GRA SPR # 568 792 793 794 795 824 825 826 827 536 SPR5:9 10001 11000 11000 11000 11000 11001 11001 11001 11001 10000 SPR0:4 11000 11000 11001 11010 11011 11000 11001 11010 11011 11000 Address for External Master Access 0x0000_3110 0x0000_3180 0x0000_3380 0x0000_3580 0x0000_3780 0x0000_3190 0x0000_3390 0x0000_3590 0x0000_3790 0x0000_3100 Access SUPR SUPR SUPR SUPR SUPR SUPR SUPR SUPR SUPR SUPR Description L2U Module Configuration Register Region Base Address Register 0 Region Base Address Register 1 Region Base Address Register 2 Region Base Address Register 3 Region Attribute Register 0 Region Attribute Register 1 Region Attribute Register 2 Region Attribute Register 3 Global Region Attribute
MPC555
/ MPC556
MOTOROLA 11-12
USERS MANUAL

For these registers a bus cycle will be performed on the L-bus and the U-bus with the address as shown inTable 11-6.
.
Table 11-6 Hex Address For SPR Cycles

A0:17
0
A18:22
spr0:4
A23:27
spr5:9
A28:31
0
11.8.1 U-bus Access The L2U registers are accessible from the U-bus side only if it is a supervisor mode data access and the register address is correct and it is indicated on the U-bus that it is a PPC register access.
A user mode access, or an access marked as instruction, to L2U registers from the Ubus side will cause a data error on the U-bus. 11.8.2 Transaction Size All L2U registers are defined by PowerPC architecture as being 32-bit registers. There is no PowerPC instruction to access either a half word or a byte of the special purpose register. All L2U registers are only word accessible (read and write) in peripheral mode. A half-word or byte access in peripheral mode will result in a word transaction. 11.8.3 L2U Module Configuration Register (L2U_MCR) The L2U module configuration register (L2U_MCR) is used to control the L2U module operation. L2U_MCR L2U Module Configuration Register
MSB 0 SP 1 2 3 4 5 6 7 8 9 RESERVED 10 11 12 13
SPR 568
14 15
LSHOW
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MPC555
/ MPC556
MOTOROLA 11-13
USERS MANUAL

Table 11-7 L2U_MCR Bit Descriptions
Bit(s) Name Description SRAM Protection (SP) bit is used to protect the SRAM on the L-bus from U-bus accesses. This bit can be set or cleared from the L-bus side. It can be set or cleared from the U-bus side when factory test mode is enabled. When not in factory test mode, any attempt to set or clear the SP bit from the U-bus side has no affect. 0 SP Once this bit is set, the L2U blocks all SRAM accesses initiated by the U-bus masters and the access is terminated with a data error on the U-bus. If L-bus show cycles are enabled, setting this bit will disable L-bus SRAM show cycles. LSHOW bits are used to configure the show cycle mode for cycles accessing the L-bus slave e.g. SRAM 00 = Disable show cycles 01 = Show address and data of all L-bus space write cycles 10 = Reserved 11 = Show address and data of all L-bus space read and write cycles Reserved
1:2
LSHOW
3:31
11.8.4 Region Base Address Registers (L2U_RBAx) The region base address register defines the base address of a specific region protected by the data memory protection unit. There are four registers (x = 0...3), one for each supported region. L2U_RBAx L2U Region x Base Address Register
MSB 0 1 2 3 4 5 6 7 RBA RESET: x x x x x x x x x x x x x x x x 8 9 10 11 12
SPR 792 795

13 14 15
16
17 RBA
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
RESERVED
RESET: x x x x 0 0 0 0 0 0 0 0 0 0 0 0
x = Undefined
Table 11-8 L2U_RBAx Bit Descriptions

Bit(s) 0:19 20:31 Name RBA Description Region base address. The RBA field provides the base address of the region. The region base address should start on the block boundary for the corresponding block size attribute specified in the region attribute register (L2U_RAx). Reserved
MPC555
/ MPC556
MOTOROLA 11-14
USERS MANUAL

11.8.5 Region Attribute Registers (L2U_RAx) Each region attribute register defines the protection attributes associated with a specific region protected by the data memory protection unit. There are four registers (x = 0...3), one for each supported region. L2U_RAx L2U Region X Attribute Register
MSB 0 1 2 3 4 5 6 7 8 9 10 11 RS 12
SPR 824 827

13 14 15
RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0
16
17 RS
18
19
20 PP
21
22
23 RESERVED
24
25 G
26
27
28
29
30
LSB 31
RESERVED
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 11-9 L2U_RAx Bit Descriptions

Bit(s) 0:7 Name Reserved Region size 0000_0000_0000 = 4 Kbytes 0000_0000_0001 = 8 Kbytes 0000_0000_0011 = 16 Kbytes 0000_0000_0111 = 32 Kbytes 0000_0000_1111 = 64 Kbytes 0000_0001_1111 = 128 Kbytes 0000_0011_1111 = 256 Kbytes 0000_0111_1111 = 512 Kbytes 0000_1111_1111 = 1 Mbyte 0001_1111_1111 = 2 Mbytes 0011_1111_1111 = 4 Mbytes 0111_1111_1111 = 8 Mbytes 1111_1111_1111 = 16 Mbytes Protection bits 00 = No supervisor access, no user access 01 = Supervisor read/write access, no user access 10 = Supervisor read/write access, user read-only access 11 = Supervisor read/write access, user read/write access Reserved Guarded attribute 0 = Not guarded from speculative accesses 1 = Guarded from speculative accesses Reserved Description
8:19
RS
20:21
PP
22:24 25 26:31
11.8.6 Global Region Attribute Register The global region attribute register defines the protection attributes associated with the memory region which is not protected under the four DMPU regions. This register also provides enable/disable control for the four DMPU regions.
MPC555
/ MPC556
MOTOROLA 11-15
USERS MANUAL

L2U_GRA L2U Global Region Attribute Register
MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13
SPR 536
14 15
ENR0 ENR1 ENR2 ENR3 RESET: 0 0 0 0 0 0 0 0 0
RESERVED
16
17
18
19
20 PP
21
22
23 RESERVED
24
25 G
26
27
28
29
30
LSB 31
RESERVED RESET: 0 0 0 0 0
RESERVED
Table 11-10 L2U_GRA Bit Descriptions

Bit(s) 0 Name ENR0 Enable attribute for region 0 0 = Region attribute is off 1 = Region attribute is on Enable attribute for region 1 0 = Region attribute is off 1 = Region attribute is on Enable attribute for region 2 0 = Region attribute is off 1 = Region attribute is on Enable attribute for region 3 0 = Region attribute is off 1 = Region attribute is on Reserved Protection bits 00 = No supervisor access, no user access 01 = Supervisor read/write access, no user access 10 = Supervisor read/write access, user read-only access 11 = Supervisor read/write access, user read/write access Reserved Guarded attribute 0 = Not guarded from speculative accesses 1 = Guarded from speculative accesses Reserved Description
ENR1
ENR2
3 4:19
ENR3
20:21
PP
22:24 25 26:31
MPC555
/ MPC556
MOTOROLA 11-16
USERS MANUAL
SECTION 12 U-BUS TO IMB3 BUS INTERFACE (UIMB)

The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3. The UIMB interface consists of seven submodules that control bus interface timing, address decode, data multiplexing, intrasystem communication (interrupts), and clock generation to allow communication between U-bus and the IMB3. The seven submodules are: U-bus interface IMB3 interface Address decoder Data multiplexer Interrupt synchronizer Clock control Scan control 12.1 Features Provides complete interfacing between the U-bus and the IMB3: 15 bits (32 Kbytes) of address decode on IMB3 32-bit data bus Read/write access to IMB3 module registers1 Interrupt synchronizer Monitoring of accesses to unimplemented addresses within UIMB interface address range Burst-inhibited accesses to the modules on IMB3 Support of 32-bit and 16-bit BIUs for IMB3 modules Half and full speed operation of IMB3 bus with respect to U-bus Simple slave only U-bus interface implementation Supports alternate master on IMB3 Transparent mode operation not supported Relinquish and retry not supported Supports scan control for modules on the IMB3 and on the U-bus NOTE Modules on the IMB3 bus can only be reset by SRESET. Some modules may have a module reset, also.
1.
The user should not perform instruction fetches from modules on the IMB. U-BUS TO IMB3 BUS INTERFACE (UIMB) MOTOROLA 12-1

12.2 UIMB Block Diagram
U-bus Interface Address Decode Data Mux
U-bus
IMB3 Interface
IMB3
Scan Control
Interrupt Synchronizer
Clock Control
Figure 12-1 UIMB Interface Module Block Diagram 12.3 Clock Module The clock module within the UIMB interface generates the IMB clock. The IMB clock is the main timing reference used within the IMB modules. The IMB clock is often referred to in the IMB module sections as FSYS or IMB3 clock. The IMB clock is generated based on the STOP and HSPEED bits in the UIMB module configuration register (UMCR). If the STOP bit is 1, the IMB clock is not generated. If the STOP bit is 0 and the HSPEED bit is 0, the IMB clock is generated as the inversion of the internal system clock. This is the same frequency as the CLKOUT if EBDF is 0b00 full speed external bus. (See Figure 12-2.) If the HSPEED bit is 1, then the IMB clock is one-half of the internal system frequency. (See Figure 12-3.) Table 12-1 STOP and HSPEED Bit Functionality
STOP 0 0 1 HSPEED 0 1 X Functionality IMB bus frequency is the same as U-bus frequency. IMB bus frequency is half that of the U-bus frequency. IMB clock is not generated.
MPC555
/ MPC556
U-BUS TO IMB3 BUS INTERFACE (UIMB)
MOTOROLA 12-2
USERS MANUAL
CLKOUT
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
IMB Clock
B4
B1
B2
B3
B4
B1
B2
B3
Figure 12-2 IMB Clock Full-Speed IMB Bus
CLKOUT
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
IMB Clock
B4
B1
B2
B3
Figure 12-3 IMB Clock Half-Speed IMB Bus Table 12-2 shows the number of system clock cycles that the UIMB requires to perform each type of bus cycle. It is assumed in this table that the IMB3 is available to the UIMB at all times (fastest possible case). Table 12-2 Bus Cycles and System Clock Cycles
Bus Cycle (from U-bus Transfer Start to U-bus Transfer Acknowledge) Normal write Normal read Dynamically-sized write Dynamically-sized read Number of System Clock Cycles Full Speed 4 4 6 6 6 6 10 10 Half Speed
NOTE The UIMB interface dynamically interprets the port size of the addressed module during each bus cycle, allowing bus transfers to and from 16-bit and 32-bit IMB modules. During a bus transaction, the slave module on the IMB signals its port size (16- or 32-bit) via an internal port size signal. 12.4 Interrupt Operation The interrupts from the modules on the IMB3 are propagated to the interrupt controller in the USIU through the UIMB interface. The UIMB interrupt synchronizer latches the Interrupts from the IMB3 and drives them onto the U-bus, where they are latched by the USIU interrupt controller.
MPC555
/ MPC556
MOTOROLA 12-3
USERS MANUAL

12.4.1 Interrupt Sources and Levels on IMB The IMB3 has eight interrupt lines. There can be a maximum of 32 levels of interrupts from the modules on IMB bus. A single module can be a source for more than one interrupt. For example, the QSMCM can generate two interrupts (one for QSCI1/QSCI2 and another for QSPI). In this case, the QSMCM has two interrupt sources. Each of these two sources can assert the interrupt on any of the 32 levels. It is possible for multiple interrupt sources to assert the same interrupt level. To reduce the latency, it is a good practice for each interrupt source to assert an interrupt on a level on which no other interrupt source is mapped. 12.4.2 IMB Interrupt Multiplexing The IMB has 10 lines for interrupt support. Eight lines are for interrupts and two for ILBS. These lines will transfer the 32 interrupt levels to the interrupt synchronizer. A diagram of the interrupt flow is shown in Figure 12-4.
IMB interrupt UIPEND 8 (0:7) (8:15) Byte Count Byte-enables Byte-enable to IMB 2 Block 4 (16:23) (24:31) 8
U-bus Interrupt Level[0:7]
U-bus Data[0:31]
Figure 12-4 Interrupt Synchronizer Signal Flow Latching 32 interrupt levels using eight IMB interrupt lines is accomplished with a 4:1 time-multiplexing scheme. The UIMB drives two signals (ILBS[0:1]) with a multiplexer select code that tells all interrupting modules on the IMB about which group of signals to drive during the next clock. 12.4.3 ILBS Sequencing The IMB interface drives the ILBS signals continuously, incrementing through a code sequence (00, 01, 10, 11) once every clock The IRQMUX[0:1] bits in the IMB module configuration register select which type of multiplexing the Interrupt synchronizer will perform. The IRQMUX field can select time-multiplexing protocols for 8, 16, 24 or 32 interrupt sources. These protocols would take one, two, three or four clocks, respectively.
MPC555
/ MPC556
MOTOROLA 12-4
USERS MANUAL

Table 12-4 shows ILBS sequencing. Programming IRQMUX[0:1] to 00 disables time multiplexing. In this case the ILBS lines remain at 00 at all times, as shown in Table 12-4. In this mode, no interrupts from IMB modules which assert on levels 8 through 31 are ever latched by the Interrupt synchronizer. Time multiplexing is disabled during reset, but the reset default value enables time multiplexing as soon as reset is released if the reset default value is not 00. The timing for the scheme and the values of ILBS and the interrupt levels driven onto the IMB IRQ lines are shown in Figure 12-5. This scheme causes a maximum latency of four clocks and an average latency of two clocks before the interrupt request can reach the interrupt synchronizer.
IMB CLOCK
ILBS [0:1]
00
01
10
11
00
01
10
11
IMB LVL[0:7]]
LVL 0:7
LVL 8:15
LVL 16:23
LVL 24:31
LVL 0:7
Figure 12-5 Time-Multiplexing Protocol for IRQ pins
Table 12-3 ILBS Signal functionality

ILBS[0:1] 00 01 10 11 Description IMB interrupt sources mapped onto 0:7 levels will drive interrupts onto IMB IRQ[0:7] IMB interrupt sources mapped onto 8:15 levels will drive interrupts onto IMB IRQ[0:7] IMB interrupt sources mapped onto 16:23 levels will drive interrupts onto IMB IRQ[0:7] IMB interrupt sources mapped onto 24:31 levels will drive interrupts onto IMB IRQ[0:7]
The IRQMUX bits determine how many levels of IMB interrupts are sampled. Refer to Table 12-4.
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Table 12-4 IRQMUX Functionality

IRQMUX[0:1] 00 01 10 11 ILBS sequence 00, 00, 00..... 00, 01, 00, 01.... 00, 01, 10, 00, 01, 10,..... 00, 01, 10, 11, 00, 01, 10, 11,.... Description Latch 0:7 IMB interrupt levels Latch 0:15 IMB interrupt levels Latch 0:23 IMB interrupt levels Latch 0:31 IMB interrupt levels
MPC555
/ MPC556
MOTOROLA 12-5
USERS MANUAL

12.4.4 Interrupt Synchronizer The interrupt synchronizer latches the 32 levels of interrupts from the IMB bus into a register which can be read by the CPU or other U-bus master. Since there are only eight lines for interrupts on the IMB and 32 levels of interrupts are possible, the 32 interrupt levels are multiplexed onto eight IMB interrupt lines. Apart from latching these interrupts in the register (UIPEND register), the interrupt synchronizer drives the interrupts onto the U-bus, where they are latched by the interrupt controller in the USIU. If IMB modules drive interrupts on any of the 24 levels (levels eight through 31), they will be latched in the Interrupt pending register (UIPEND) in the UIMB. If any of the register bits 7 to 31 are set, then bit 7 will be set as well. Software must poll this register to find out which of the levels 7 to 31 are asserted.
The UIPEND register contains a status bit for each of the 32 interrupt levels. Each bit of the register is a read-only status bit, reflecting the current state of the corresponding interrupt signal. For each of the 32 interrupt levels, a corresponding bit of the UIPEND register is set. Figure 12-4 shows how the eight interrupt lines are connected to the UIPEND register to represent 32 levels of interrupts. Figure 12-6 shows the implementation of the interrupt synchronizer.
UIPEND LVL 0-7
U-bus Interrupt Level[0:7] 8
7 LVL7
IMB LVL [0:7]
LVL 8-31
24 RESET State Machine IMBCLOCK 32
OR
U-bus Data[0:31]
ILBS [0:1]
Figure 12-6 Interrupt Synchronizer Block diagram
MPC555
/ MPC556
MOTOROLA 12-6
USERS MANUAL

12.5 Programming Model Table 12-5 lists the registers used for configuring and testing the UIMB module. The address offset shown in this table is from the start of the block reserved for UIMB registers. As shown in Figure 1-3 in 1.3 MPC555 / MPC556 Address Map, this block begins at offset 0x30 7F80 from the start of the MPC555 / MPC556 internal memory map (the last 128-byte sub-block of the UIMB interface memory map). Table 12-5 UIMB Interface Register Map
Access S1 Base Address 0x30 7F80 0x30 7F84 0x30 7F8C 0x30 7F90 0x30 7F94 0x30 7F9C 0x30 7FA0 Register UIMB Module Configuration Register (UMCR) See Table 12-6 for bit descriptions. Reserved UIMB Test Control Register (UTSTCREG) Reserved Reserved Interrupt Request Pending (UIPEND) See 12.5.3 Pending Interrupt Request Register (UIPEND) for bit descriptions.
S/T
NOTES: 1. S = Supervisor mode only, T = Test mode only
Any word, half-word or byte access to a 32-bit location within the UIMB interface register decode block that is unimplemented (defined as reserved) causes the UIMB interface to asserting a data error exception on the U-bus.The entire 32-bit location must be defined as reserved in order for a data error exception to be asserted. Unimplemented bits in a register return zero when read. 12.5.1 UIMB Module Configuration Register (UMCR) The UIMB module configuration register (UMCR) is accessible in supervisor mode only. UMCR UIMB Module Configuration Register
MSB 0 STOP 1 2 3 HSPEE D 4 5 6 7 8 9 10 11 12 13
0x30 7F80
14 15
IRQMUX
RESERVED
HRESET: 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
RESERVED HRESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MPC555
/ MPC556
MOTOROLA 12-7
USERS MANUAL

Table 12-6 UMCR Bit Descriptions
Bit(s) Name Stop enable. 0 = Enable system clock for IMB bus 1 = Disable IMB system clock To avoid complications at restart and data corruption, system software must stop each slave on the IMB before setting the STOP bit. Software must also ensure that all IMB interrupts have been serviced before setting this bit. Interrupt request multiplexing. These bits control the multiplexing of the 32 possible interrupt requests onto the eight IMB interrupt request lines. 00 = Disables the multiplexing scheme on the interrupt controller within this interface. What this means is that the IMB IRQ [0:7] signals are non-multiplexed, only providing 8 (0-7) interrupt request lines to the interrupt controller 01 = Enables the IMB IRQ control logic to perform a 2-to-1 multiplexing to allow transferring of 16 (0-15) interrupt sources 10 = Enables the IMB IRQ control logic to perform a 3-to-1 multiplexing to allow transferring of 24 (0-23) interrupt sources 11 = Enables the IMB IRQ control logic to perform a 4-to-1 multiplexing to allow transferring of 32 (0-31) interrupt sources Half speed. The HSPEED bit controls the frequency at which the IMB3 runs with respect to the U-bus. This is a modify-once bit. Software can write the reset value of this bit any number of times. However, once logic 0 is written to this location, any attempt to rewrite this bit to a logic 1 will have no effect. 0 = IMB frequency is the same as that of the U-bus 1 = IMB frequency is one half that of the U-bus Reserved Description
STOP
1:2
IRQMUX
HSPEED
4:31
12.5.2 Test control register (UTSTCREG) The UTSTCREG register is used for factory testing only. 12.5.3 Pending Interrupt Request Register (UIPEND) The UIPEND register is a read-only status register which reflects the state of the 32 interrupt levels. The state of the IRQ0 is shown in bit 0, the state of IRQ1 is shown in bit 1 and so on. This register is accessible only in supervisor mode. UIPEND Pending Interrupt Request Register
MSB 0 LVL0 1 LVL1 2 LVL2 3 LVL3 4 LVL4 5 LVL5 6 LVL6 7 LVL7 8 LVL8 9 LVL9 10 LVL0 11 12 13
0x30 7FA0
14 15
LVL11 LVL12 LVL13 LVL14 LVL15
HRESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 LVL16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
IRQ17 LVL18 LVL19 LVL20 LVL21 LVL22 LVL23 LVL24 LVL25 LVL26 LVL27 LVL28 LVL29 LVL30 LVL31
HRESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MPC555
/ MPC556
MOTOROLA 12-8
USERS MANUAL

Table 12-7 UIPEND Bit Descriptions
Bit(s) 0:31 Name LVLx Description Pending interrupt request level. Accessible only in supervisor mode. LVLx identifies the interrupt source as UIMB LVLx, where x is the interrupt number.
MPC555
/ MPC556
MOTOROLA 12-9
USERS MANUAL
MPC555
/ MPC556
MOTOROLA 12-10
USERS MANUAL
SECTION 13 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64

The MPC555 / MPC556 includes two independent queued analog-to-digital converter (QADC64) modules. For details of QADC64 operation not included in this section, refer to the QADC Reference Manual (QADCRM/AD). 13.1 Overview The QADC64 consists of an analog front-end and a digital control subsystem, which includes an intermodule bus (IMB3) interface block. Refer to Figure 13-1. The analog section includes input pins, channel selection logic, an analog multiplexer, and one sample-and-hold analog circuit. The analog conversion is performed by the digital-to-analog converter (DAC) resistor-capacitor array, a high-gain comparator, and a successive approximation register (SAR). The digital control section contains the conversion sequencing logic. Also included are the periodic/interval timer, control and status registers, the conversion command word (CCW) table RAM, and the result word table RAM.
EXTERNAL TRIGGERS
EXTERNAL MUX ADDRESS
UP TO 16 ANALOG INPUT PINS
REFERENCE INPUTS
ANALOG POWER INPUTS
ANALOG INPUT MULTIPLEXER AND DIGITAL PIN FUNCTIONS
DIGITAL CONTROL
10-BIT ANALOG TO DIGITAL CONVERTER
QUEUE OF 10-BIT CONVERSION COMMAND WORDS (CCW), 64 ENTRIES
10-BIT RESULT TABLE, 64 ENTRIES
INTERMODULE BUS INTERFACE
10-BIT TO 16-BIT RESULT ALIGNMENT
IMB
Figure 13-1 QADC64 Block Diagram
QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
MOTOROLA 13-1

13.2 Features Each QADC64 module offers the following features: Internal sample and hold Up to 16 analog input channels using internal multiplexing Directly supports up to four external multiplexers (for example, the MC14051) Up to 41 total input channels with internal and external multiplexing Programmable input sample time for various source impedances Two conversion command queues with a total of 64 entries Sub-queues possible using pause mechanism Queue complete and pause software interrupts available on both queues Queue pointers indicate current location for each queue Automated queue modes initiated by: External edge trigger [queues 1 and 2] and gated mode [queue 1 only] Periodic/interval timer, within QADC64 module [queues 1 and 2] Software command [queues 1 and 2] Single-scan or continuous-scan of queues 64 result registers Output data readable in three formats: Right-justified unsigned Left-justified signed Left-justified unsigned Unused analog channels can be used as digital ports 13.3 QADC64 Pin Functions The two QADC64 modules use the following 38 pins: Two analog reference pins, to which all analog input voltages are scaled (shared by the two modules) 32 analog input pins (16 per module, with three analog inputs per module multiplexed with multiplex address signals) Two analog power pins (shared by the two modules) Two external trigger pins (shared by the two modules) The 16 channel/port pins in either module can support up to 41 channels when external multiplexing is used (including internal channels). All of the channel pins can also be used as general-purpose digital port pins. The following paragraphs describe QADC64 pin functions. Figure 13-2 shows the QADC64 module pins.
MPC555
/ MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64

MOTOROLA 13-2
USERS MANUAL
VSS DIGITAL POWER (SHARED W/ OTHER MODULES) VDD ANALOG POWER & GROUND VSSA VDDA VRH VRL VSSE VDDH
ANALOG REFERENCES OUTPUT DRIVER GROUND OUTPUT DRIVER SUPPLY
PORT B ANALOG INPUTS, EXT MUX INPUTS, DIGITAL INPUTS
PORT A ANALOG INPUTS, EXT MUX ADDRESS OUTPUTS, DIGITAL I/O
AN0/ANW/PQB0 AN1/ANX/PQB1 AN2/ANY/PQB2 AN3/ANZ/PQB3 AN48/PQB4 AN49/PQB5 AN50/PQB6 AN51/PQB7 AN52/MA0/PQA0 AN53/MA1/PQA1 AN54/MA2/PQA2 AN55/PQA3 AN56/PQA4 AN57/PQA5 AN58/PQA6 AN59/PQA7
PORT B
QADC64
ANALOG MULTIPLEXER PORT A
ANALOG CONVERTER
DIGITAL RESULTS AND CONTROL
ETRIG1 ETRIG2
QADC64 PINOUT
Figure 13-2 QADC64 Input and Output Signals 13.3.1 Port A Pin Functions The eight port A pins can be used as analog inputs, or as a bi-directional 8-bit digital input/output port. 13.3.1.1 Port A Analog Input Pins When used as analog inputs, the eight port A pins are referred to as AN[59:52]. Due to the digital output drivers associated with port A, the analog characteristics of port A are different from those of port B. All of the analog signal input pins may be used for at least one other purpose. 13.3.1.2 Port A Digital Input/Output Pins Port A pins are referred to as PQA when used as a bidirectional 8-bit digital input/output port. These eight pins may be used for general-purpose digital input signals or digital output signals.
MPC555

MOTOROLA 13-3
USERS MANUAL

Port A pins are connected to a digital input synchronizer during reads and may be used as general purpose digital inputs. Since port A read captures the data on all pins, including those used for digital outputs or analog inputs, the user should employ a masking operation to filter the inappropriate bits from the input byte. Each port A pin is configured as an input or output by programming the port data direction register (DDRQA). Digital input signal states are read into the PORTQA data register when DDRQA specifies that the pins are inputs. Digital data in PORTQA is driven onto the port A pins when the corresponding bits in DDRQA specify outputs. 13.3.2 Port B Pin Functions The eight port B pins can be used as analog inputs, or as an 8-bit digital input-only port. Refer to the following paragraphs for more information.
13.3.2.1 Port B Analog Input Pins When used as analog inputs, the eight port B pins are referred to as AN[51:48]/ AN[3:0]. Since port B functions as analog and digital input-only, the analog characteristics are different from those of port A. All of the analog signal input pins may be used for at least one other purpose. 13.3.2.2 Port B Digital Input Pins Port B pins are referred to as PQB[7:0] when used as an 8-bit digital input-only port. In addition to functioning as analog input pins, the port B pins are also connected to the input of a synchronizer during reads and may be used as general-purpose digital inputs. Since port B pins are input-only, there is no associated data direction register. Digital input signal states are read from the PORTQB data register. Since a port B read captures the data on all pins, including those used for analog inputs, the user should employ a masking operation to filter the inappropriate bits from the input byte. 13.3.3 External Trigger Input Pins The QADC64 has two external trigger pins (ETRIG[2:1]). Each of the two external trigger pins is associated with one of the scan queues. When a queue is in external trigger mode, the corresponding external trigger pin is configured as a digital input. 13.3.4 Multiplexed Address Output Pins In non-multiplexed mode, the 16 channel pins are connected to an internal multiplexer which routes the analog signals into the A/D converter. In externally multiplexed mode, the QADC64 allows automatic channel selection through up to four external 1-of-8 multiplexer chips. The QADC64 provides a 3-bit multiplexed address output to the external multiplexer chips to allow selection of one of eight inputs. The multiplexed address output signals MA[2:0] can be used as multiplex address output bits or as general-purpose I/O.
MPC555

MOTOROLA 13-4
USERS MANUAL

When externally-multiplexed mode is enabled, MA[2:0] are used as the address inputs for up to four 1-of-8 multiplexer chips (for example, the MC14051 and the MC74HC4051). Since MA[2:0] are digital outputs in multiplexed mode, the software programmed input/output direction and data for these pins in DDQA[2:0], DDRQA, and PQA[2:0] is ignored, and the value for MA[2:0] is taken from the currently executing CCW. 13.3.5 Multiplexed Analog Input Pins In externally-multiplexed mode, four of the port B pins are redefined to each represent a group of eight input channels. Refer to Table 13-1. The analog output of each external multiplexer chip is connected to one of the AN[w, x, y, z] inputs in order to convert a channel selected by the MA[2:0] multiplexed address outputs. Table 13-1 Multiplexed Analog Input Channels
Multiplexed Analog Input ANw ANx ANy ANz Channels Even-numbered channels from 0 to 14 Odd-numbered channels from 1 to 15 Even-numbered channels from 16 to 30 Odd-numbered channels from 17 to 31
13.3.6 Voltage Reference Pins VRH and VRL are the dedicated input pins for the high and low reference voltages. Separating the reference inputs from the power supply pins allows for additional external filtering, which increases reference voltage precision and stability, and subsequently contributes to a higher degree of conversion accuracy. 13.3.7 Dedicated Analog Supply Pins VDDA and VSSA pins supply power to the analog subsystems of the QADC64 module. Dedicated power is required to isolate the sensitive analog circuitry from the normal levels of noise present on the digital power supply. 13.3.8 External Digital Supply Pin Each port A pin includes a digital output driver, an analog input signal path, and a digital input synchronizer. The VSS pin provides the ground level for the drivers on the port A pins. VDDH provides the supply level for the drivers on port A pins. 13.3.9 Digital Supply Pins VDD and VSS provide the power for the digital portions of the QADC64, and for all other digital MCU modules.
MPC555

MOTOROLA 13-5
USERS MANUAL

13.4 QADC64 Bus Interface The QADC64 supports to 8-bit, 16-bit, and 32-bit data transfers, at even and odd addresses. Coherency of results read, (ensuring that all results read were taken consecutively in one scan) is not guaranteed. For example, if two consecutive 16-bit locations in a result area are read, the QADC64 could change one 16-bit location in the result area between the bus cycles. There is no holding register for the second 16-bit location. All read and write accesses that require more than one 16-bit access to complete occur as two or more independent bus cycles. Depending on bus master protocol, these accesses could include misaligned and 32-bit accesses. Normal reads-from and writes-to the QADC64 require two clock cycles. However, if the CPU tries to access locations that are also accessible to the QADC64 while the QADC64 is accessing them, the bus cycle will require additional clock cycles. The QADC64 may insert from one to four wait states in the process of a CPU read from or write to such a location. 13.5 Module Configuration The QADC64 module configuration register (QADC64MCR) defines freeze and stop mode operation, supervisor space access, and interrupt arbitration priority. Unimplemented bits read zero and writes have no effect. QADC64MCR is typically written once when software initializes the QADC64, and not changed thereafter. Refer to 13.12.1 QADC64 Module Configuration Register for register and bit descriptions. 13.5.1 Low-Power Stop Mode When the STOP bit in QADC64MCR is set, the clock signal to the A/D converter is disabled, effectively turning off the analog circuitry. This results in a static, low power consumption, idle condition. Low-power stop mode aborts any conversion sequence in progress. Because the bias currents to the analog circuits are turned off in low-power stop mode, the QADC64 requires some recovery time to stabilize the analog circuits after the STOP bit is cleared. In low-power stop mode, the BIU state machine and logic do not shut down, and the QADC64MCR, the interrupt register (QADC64INT), and the test register (QADC64TEST) are fully accessible and are not reset. The data direction register (DDRQA), port data register (PORTQA/PORTQB), and control register zero (QACR0) are not reset and are read-only accessible. The RAM is not reset and is not accessible. Control register one (QACR1), control register two (QACR2), and the status registers (QASR0 and QASR1) are reset and are read-only accessible. In addition, the periodic/ interval timer is held in reset during stop mode. If the STOP bit is clear, low-power stop mode is disabled. The STOP bit must be clear to program CCWs into RAM or read results from RAM. 13.5.2 Freeze Mode The QADC64 enters freeze mode when background debug mode is enabled and a breakpoint is processed. This is indicated by assertion of the FREEZE line on the
MPC555

MOTOROLA 13-6
USERS MANUAL

IMB3. The FRZ bit in QADC64MCR determines whether or not the QADC64 responds to an IMB FREEZE assertion. Freeze mode is useful when debugging an application. When the IMB FREEZE line is asserted and the FRZ bit is set, the QADC64 finishes any conversion in progress and then freezes. Depending on when the FREEZE is asserted, there are three possible queue freeze scenarios: When a queue is not executing, the QADC64 freezes immediately When a queue is executing, the QADC64 completes the current conversion and then freezes If during the execution of the current conversion, the queue operating mode for the active queue is changed, or a queue 2 abort occurs, the QADC64 freezes immediately When the QADC64 enters the freeze mode while a queue is active, the current CCW location of the queue pointer is saved. During freeze, the analog clock, QCLK, is held in reset and the periodic/interval timer is held in reset. External trigger events that occur during the freeze mode are not captured. The BIU remains active to allow IMB access to all QADC64 registers and RAM. Although the QADC64 saves a pointer to the next CCW in the current queue, the software can force the QADC64 to execute a different CCW by writing new queue operating modes for normal operation. The QADC64 looks at the queue operating modes, the current queue pointer, and any pending trigger events to decide which CCW to execute. If the FRZ bit is clear, assertion of the IMB FREEZE line is ignored. 13.5.3 Supervisor/Unrestricted Address Space The QADC64 memory map is divided into two segments: supervisor-only data space and assignable data space. Access to supervisor-only data space is permitted only when the CPU is operating in supervisor mode. Assignable data space can have either restricted to supervisor-only data space access or unrestricted supervisor and user data space accesses. The SUPV bit in QADC64MCR designates the assignable space as supervisor or unrestricted. Attempts to read or write supervisor-only data space when the CPU is not in supervisor mode cause the bus master to assert the internal transfer error acknowledge (TEA) signal. The supervisor-only data space segment contains the QADC64 global registers, which include QADC64MCR, QADC64TEST, and QADC64INT. The supervisor/unrestricted space designation for the CCW table, the result word table, and the remaining QADC64 registers is programmable. 13.6 General-Purpose I/O Port Operation QADC64 port pins, when used as general-purpose input, are conditioned by a synchronizer with an enable feature. The synchronizer is not enabled until the QADC64 decodes an IMB bus cycle which addresses the port data register to minimize the highMPC555

MOTOROLA 13-7
USERS MANUAL

current effect of mid-level signals on the inputs used for analog signals. Digital input signals must meet the input low voltage (VIL) or input high voltage (VIH) specifications. If an analog input pin does not meet the digital input pin specifications when a digital port read operation occurs, an indeterminate state is read. To avoid reading inappropriate values on analog inputs, the user software should employ a masking operation. During a port data register read, the actual value of the pin is reported when its corresponding bit in the data direction register defines the pin to be an input (port A only). When the data direction bit specifies the pin to be an output, the content of the port data register is read. By reading the latch which drives the output pin, software instructions that read data, modify it, and write the result, like bit manipulation instructions, work correctly.
There is one special case to consider for digital I/O port operation. When the MUX (externally multiplexed) bit is set in QACR0, the data direction register settings are ignored for the bits corresponding to PQA[2:0], the three multiplexed address MA[2:0] output pins. The MA[2:0] pins are forced to be digital outputs, regardless of the data direction setting, and the multiplexed address outputs are driven. The data returned during a port data register read is the value of the multiplexed address latches which drive MA[2:0], regardless of the data direction setting. 13.6.1 Port Data Register QADC64 ports A and B are accessed through two 8-bit port data registers (PORTQA and PORTQB). Port A pins are referred to as PQA when used as an 8-bit input/output port. Port A can also be used for analog inputs AN[59:52] and external multiplexer address outputs MA[2:0]. Port B pins are referred to as PQB when used as an 8-bit input-only digital port. Port B can also be used for non-multiplexed AN[51:48]/AN[3:0] and multiplexed ANz, ANy, ANx, ANw analog inputs. PORTQA and PORTQB are unaffected by reset. Refer to 13.12.4 Port A/B Data Register for register and bit descriptions. 13.6.2 Port Data Direction Register The port data direction register (DDRQA) is associated with the port A digital I/O pins. These bi-directional pins may have somewhat higher leakage and capacitance specifications. Any bit in this register set to one configures the corresponding pin as an output. Any bit in this register cleared to zero configures the corresponding pin as an input. Software is responsible for ensuring that DDRQA bits are not set to one on pins used for analog inputs. When a DDRQA bit is set to one and the pin is selected for analog conversion, the voltage sampled is that of the output digital driver as influenced by the load. NOTE
MPC555

MOTOROLA 13-8
USERS MANUAL

Caution should be exercised when mixing digital and analog inputs. This should be minimized as much as possible. Input pin rise and fall times should be as large as possible to minimize AC coupling effects. Since port B is input-only, a data direction register is not needed. Read operations on the reserved bits in DDRQA return zeros, and writes have no effect. Refer to 13.12.5 Port Data Direction Register for register and bit descriptions. 13.7 External Multiplexing Operation External multiplexers concentrate a number of analog signals onto a few inputs to the analog converter. This is helpful in applications that need to convert more analog signals than the A/D converter can normally provide. External multiplexing also puts the multiplexer closer to the signal source. This minimizes the number of analog signals that need to be shielded due to the close proximity of noisy, high-speed digital signals near the MCU. The QADC64 can use from one to four external multiplexers to expand the number of analog signals that may be converted. Up to 32 analog channels can be converted through external multiplexer selection. The externally multiplexed channels are automatically selected from the channel field of the CCW table, the same as internally multiplexed channels. All of the automatic queue features are available for externally and internally multiplexed channels. The software selects externally multiplexed mode by setting the MUX bit in QACR0. Figure 13-3 shows the maximum configuration of four external multiplexers connected to the QADC64. The external multiplexers select one of eight analog inputs and connect it to one analog output, which becomes an input to the QADC64. The QADC64 provides three multiplexed address signals (MA[2:0]), to select one of eight inputs. These outputs are connected to all four multiplexers. The analog output of each multiplexer is each connected to one of four separate QADC64 inputs ANw, ANx, ANy, and ANz.
MPC555

MOTOROLA 13-9
USERS MANUAL

AN0 AN2 AN4 AN6 AN8 AN10 AN12 AN14
VSSA VDDA MUX V RH VRL VSSE VDDH
ANALOG POWER
ANALOG REFERENCES
MUX AN0/ANW/PQB0 AN1/ANX/PQB1 AN2/ANY/PQB2 AN3/ANZ/PQB3 AN48/PQB4 AN49/PQB5 AN50/PQB6 AN51/PQB7 AN52/MA0/PQA0* AN53/MA1/PQA1* AN54/MA2/PQA2* AN55/PQA3* AN56/PQA4* AN57/PQA5* AN58/PQA6* AN59/PQA7*
MUX
ETRIG1 ETRIG2
EXTERNAL TRIGGERS
Figure 13-3 Example of External Multiplexing When the external multiplexed mode is selected, the QADC64 automatically creates the MA[2:0] output signals from the channel number in each CCW. The QADC64 also converts the proper input channel (ANw, ANx, ANy, and ANz) by interpreting the CCW channel number. As a result, up to 32 externally multiplexed channels appear to the conversion queues as directly connected signals. Software simply puts the channel number of an externally multiplexed channel into a CCW. Figure 13-3 shows that MA[2:0] may also be analog or digital input pins. When external multiplexing is selected, none of the MA[2:0] pins can be used for analog or digital inputs. They become multiplexed address outputs. 13.8 Analog Input Channels The number of available analog channels varies, depending on whether or not external multiplexing is used. A maximum of 16 analog channels are supported by the internal multiplexing circuitry of the converter. Table 13-2 shows the total number of analog input channels supported with zero to four external multiplexers. / MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
MPC555
PORT A
PORT B
QADC64
MUX
ANALOG MULTIPLEXER
ANALOG CONVERTER
DIGITAL RESULTS AND CONTROL
MOTOROLA 13-10
USERS MANUAL

Table 13-2 Analog Input Channels
Number of Analog Input Channels Available Directly Connected + External Multiplexed = Total Channels1 No External MUX Chips 16 One External MUX Chip 12 + 8 = 20 Two External MUX Chips 11 + 16 = 27 Three External MUX Chips 10 + 24 = 34 Four External MUX Chips 9 + 32 = 41
NOTES: 1. When external multiplexing is used, three input channels become multiplexed address outputs, and for each external multiplexer chip, one input channel becomes a multiplexed analog input.
13.9 Analog Subsystem The QADC64 analog subsystem includes a front-end analog multiplexer, a digital to analog converter (DAC) array, a comparator, and a successive approximation register (SAR). The analog subsystem path runs from the input pins through the input multiplexing circuitry, into the DAC array, and through the analog comparator. The output of the comparator feeds into the SAR. Figure 13-4 shows a block diagram of the QADC64 analog submodule.
MPC555

MOTOROLA 13-11
USERS MANUAL

PQA7 CHAN. DECODE & MUX 16: 1 6 CHAN.[5:0] CCW BUF CCW 10 SIGNALS FROM/TO QUEUE CONTROL LOGIC
PQA0 PQB7 BIAS CIRCUIT
SAMPLE BUFFER PQB0
POWER DOWN
BYP
IST
10 BIT A/D CONVERTER
INPUT
STOP RST QCLK
CSAMP
STATE MACHINE & LOGIC WCCW END OF CONV. END OF SMP SAR 10 10 SAR BUF 10 RSAR
VRH 10 BIT RC DAC VRL VDDA ANALOG POWER VSSA COMPARATOR
SAR Timing
SUCCESSIVE APPROXIMATION REGISTER
QADC64 DETAIL BLOCK
Figure 13-4 QADC64 Module Block Diagram 13.9.1 Conversion Cycle Times Total conversion time is made up of initial sample time, final sample time, and resolution time. Initial sample time refers to the time during which the selected input channel is driven by the buffer amplifier onto the sample capacitor. The buffer amplifier can be disabled by means of the BYP bit in the CCW. During the final sampling period, amplifier is bypassed, and the multiplexer input charges the RC DAC array directly. During the resolution period, the voltage in the RC DAC array is converted to a digital value and stored in the SAR. Initial sample time is fixed at two QCLK cycles. Final sample time can be 2, 4, 8, or 16 QCLK cycles, depending on the value of the IST field in the CCW. Resolution time is ten QCLK cycles. Sample and resolution require a minimum of 14 QCLK clocks (7 s with a 2-MHz QCLK). If the maximum final sample time period of 16 QCLKs is selected, the total conversion time is 13.0 s with a 2-MHz QCLK. Figure 13-5 illustrates the timing for conversions. This diagram assumes a final sampling period of two QCLK cycles.
MPC555

MOTOROLA 13-12
USERS MANUAL
BUFFER FINAL SAMPLE TIME SAMPLE N CYCLES: TIME 2 CYCLES (2, 4, 8, 16)
RESOLUTION TIME 10 CYCLES
QCLK
SAMPLE TIME
SUCCESSIVE APPROXIMATION RESOLUTION SEQUENCE
Figure 13-5 Conversion Timing 13.9.1.1 Amplifier Bypass Mode Conversion Timing If the amplifier bypass mode is enabled for a conversion by setting the amplifier bypass (BYP) bit in the CCW, the timing changes to that shown in Figure 13-6. The buffered sample time is eliminated, reducing the potential conversion time by two QCLKs. However, due to internal RC effects, a minimum final sample time of four QCLKs must be allowed. This results in no savings of QCLKs. When using the bypass mode, the external circuit should be of low source impedance, typically less than 10 k. Also, the loading effects of the external circuitry by the QADC64 need to be considered, since the benefits of the sample amplifier are not present. NOTE Because of internal RC time constants, a sample time of two QCKLs in bypass mode for high frequency operation is not recommended.
SAMPLE TIME N CYCLES: (2, 4, 8, 16)
RESOLUTION TIME 10 CYCLES
QCLK
SAMPLE TIME
SUCCESSIVE APPROXIMATION RESOLUTION SEQUENCE
Figure 13-6 Bypass Mode Conversion Timing
MPC555

MOTOROLA 13-13
USERS MANUAL

13.9.2 Front-End Analog Multiplexer The internal multiplexer selects one of the 16 analog input pins or one of three special internal reference channels for conversion. The following are the three special channels: VRH Reference Voltage High VRL Reference Voltage Low (VRH VRL)/2 Mid-Reference Voltage The selected input is connected to one side of the DAC capacitor array. The other side of the DAC array is connected to the comparator input. The multiplexer also includes positive and negative stress protection circuitry, which prevents other channels from affecting the present conversion when excessive voltage levels are applied to the other channels.
13.9.3 Digital-to-Analog Converter Array The digital-to-analog converter (DAC) array consists of binary-weighted capacitors and a resistor-divider chain. The array serves two purposes: The array holds the sampled input voltage during conversion The resistor-capacitor array provides the mechanism for the successive approximation A/D conversion Resolution begins with the MSB and works down to the LSB. The switching sequence is controlled by the SAR logic. 13.9.4 Comparator The comparator is used during the approximation process to sense whether the digitally selected arrangement of the DAC array produces a voltage level higher or lower than the sampled input. The comparator output feeds into the SAR which accumulates the A/D conversion result sequentially, starting with the MSB. 13.9.5 Successive Approximation Register The input of the successive approximation register (SAR) is connected to the comparator output. The SAR sequentially receives the conversion value one bit at a time, starting with the MSB. After accumulating the ten bits of the conversion result, the SAR data is transferred by the queue control logic in the digital section to the appropriate result location, where it may be read by user software. 13.10 Digital Control Subsystem The digital control subsystem includes the clock and periodic/interval timer, control and status registers, the conversion command word table RAM, and the result word table RAM. The central element for control of the QADC64 conversions is the 64-entry CCW table. Each CCW specifies the conversion of one input channel. Depending on the application, one or two queues can be established in the CCW table. A queue is a scan sequence of one or more input channels. By using a pause mechanism, sub-queues can
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be created within the two queues. Each queue can be operated using several different scan modes. The scan modes for queue 1 and queue 2 are programmed in QACR1 and QACR2. Once a queue has been started by a trigger event (any of the ways to cause the QADC64 to begin executing the CCWs in a queue or sub-queue), the QADC64 performs a sequence of conversions and places the results in the result word table. 13.10.1 Queue Priority Queue 1 has execution priority over queue 2 execution. Table 13-3 shows the conditions under which queue 1 asserts its priority: Table 13-3 Queue 1 Priority Assertion
Queue State Inactive
Result A trigger event for queue 1 or queue 2 causes the corresponding queue execution to begin. Queue 2 cannot begin execution until queue 1 reaches completion or the paused state. The status register records the trigger event by reporting the queue 2 status as trigger pending. Additional trigger events for queue 2, which occur before execution can begin, are recorded as trigger overruns. The current queue 2 conversion is aborted. The status register reports the queue 2 status as suspended. Any trigger events occurring for queue 2 while queue 2 is suspended are recorded as trigger overruns. Once queue 1 reaches the completion or the paused state, queue 2 begins executing again. The programming of the resume bit in QACR2 determines which CCW is executed in queue 2.
Queue 1 active/trigger event occurs for Queue 2
Queue 2 active/trigger event occurs for Queue 1
Simultaneous trigger events Queue 1 begins execution and the queue 2 status is changed to trigger pending. occur for Queue 1 and Queue 2 sub-queues paused The pause feature can be used to divide queue 1 and/or queue 2 into multiple subqueues. A sub-queue is defined by setting the pause bit in the last CCW of the subqueue.
Figure 13-7 shows the CCW format and an example of using pause to create subqueues. Queue 1 is shown with four CCWs in each sub-queue and queue 2 has two CCWs in each sub-queue.
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CONVERSION COMMAND WORD (CCW) TABLE P 00 0 0 0 1 0 0 0 1 0 PAUSE PAUSE CHANNEL SELECT, SAMPLE, HOLD, AND A/D CONVERSION BEGIN QUEUE 1 RESULT WORD TABLE 00
P 0
0 BQ2 0 1 0 1 0 1 0 P 1 63 0
END OF QUEUE 1 BEGIN QUEUE 2 PAUSE PAUSE PAUSE
PAUSE END OF QUEUE 2 63

QADC64 CQP
Figure 13-7 QADC64 Queue Operation with Pause The queue operating mode selected for queue 1 determines what type of trigger event causes the execution of each of the sub-queues within queue 1. Similarly, the queue operating mode for queue 2 determines the type of trigger event required to execute each of the sub-queues within queue 2. The choice of single-scan or continuous-scan applies to the full queue, and is not applied to each sub-queue. Once a sub-queue is initiated, each CCW is executed sequentially until the last CCW in the sub-queue is executed and the pause state is entered. Execution can only continue with the next CCW, which is the beginning of the next sub-queue. A sub-queue cannot be executed a second time before the overall queue execution has been completed. Trigger events which occur during the execution of a sub-queue are ignored, except that the trigger overrun flag is set. When continuous-scan mode is selected, a trigger event occurring after the completion of the last sub-queue (after the queue completion flag is set), causes execution to continue with the first sub-queue, starting with the first CCW in the queue.
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When the QADC64 encounters a CCW with the pause bit set, the queue enters the paused state after completing the conversion specified in the CCW with the pause bit. The pause flag is set and a pause software interrupt may optionally be issued. The status of the queue is shown to be paused, indicating completion of a sub-queue. The QADC64 then waits for another trigger event to again begin execution of the next subqueue. 13.10.2 Queue Boundary Conditions The following are queue operation boundary conditions: The first CCW in a queue contains channel 63, the end-of-queue (EOQ) code. The queue becomes active and the first CCW is read. The end-of-queue is recognized, the completion flag is set, and the queue becomes idle. A conversion is not performed. BQ2 (beginning of queue 2) is set at the end of the CCW table (63) and a trigger event occurs on queue 2. 13.12.8 QADC64 Control Register 2 (QACR2) on BQ2. The end-of-queue condition is recognized, a conversion is performed, the completion flag is set, and the queue becomes idle. BQ2 is set to CCW0 and a trigger event occurs on queue 1. After reading CCW0, the end-of-queue condition is recognized, the completion flag is set, and the queue becomes idle. A conversion is not performed. BQ2 (beginning of queue 2) is set beyond the end of the CCW table (64 - 127) and a trigger event occurs on queue 2. Refer to 7.6.3 Control Register two for information on BQ2. The end-of-queue condition is recognized immediately, the completion flag is set, and the queue becomes idle. A conversion is not performed. NOTE Multiple end-of-queue conditions may be recognized simultaneously, although there is no change in the QADC64 behavior. For example, if BQ2 is set to CCW0, CCW0 contains the EOQ code, and a trigger event occurs on queue 1, the QADC64 reads CCW0 and detects both end-of-queue conditions. The completion flag is set for queue 1 only and it becomes idle. Boundary conditions also exist for combinations of pause and end-of-queue. One case is when a pause bit is in one CCW and an end-of-queue condition is in the next CCW. The conversion specified by the CCW with the pause bit set completes normally. The pause flag is set. However, since the end-of-queue condition is recognized, the completion flag is also set and the queue status becomes idle, not paused. Examples of this situation include: The pause bit is set in CCW5 and the channel 63 (EOQ) code is in CCW6 The pause bit is set in CCW63 During queue 1 operation, the pause bit is set in CCW14 and BQ2 points to CCW15
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Another pause and end-of-queue boundary condition occurs when the pause and an end-of-queue condition occur in the same CCW. Both the pause and end-of-queue conditions are recognized simultaneously. The end-of-queue condition has precedence so a conversion is not performed for the CCW and the pause flag is not set. The QADC64 sets the completion flag and the queue status becomes idle. Examples of this situation are: The pause bit is set in CCW0 and EOQ is programmed into CCW0 During queue 1 operation, the pause bit is set in CCW20, which is also BQ2 13.10.3 Scan Modes The QADC64 queuing mechanism provides several methods for automatically scanning input channels. In single-scan mode, a single pass through a sequence of conversions defined by a queue is performed. In continuous-scan mode, multiple passes through a sequence of conversions defined by a queue are executed. The possible modes are: Disabled and reserved mode Software initiated single-scan mode External trigger single-scan mode External gated single-scan mode (queue 1 only) Interval timer single-scan mode Software initiated continuous-scan mode External trigger continuous-scan mode External gated continuous-scan mode (queue 1 only) Interval timer continuous-scan mode The following paragraphs describe the disabled/reserved, single-scan, and continuous-scan operations. 13.10.3.1 Disabled Mode When the disabled mode is selected, the queue is not active. Trigger events cannot initiate queue execution. When both queue 1 and queue 2 are disabled, wait states are not encountered for IMB accesses of the RAM. When both queues are disabled, it is safe to change the QCLK prescaler values. 13.10.3.2 Reserved Mode Reserved mode allows for future mode definitions. When the reserved mode is selected, the queue is not active. CAUTION Do not use a reserved mode. Unspecified operations may result. 13.10.3.3 Single-Scan Modes When the application software wants to execute a single pass through a sequence of conversions defined by a queue, a single-scan queue operating mode is selected. By programming the MQ field in QACR1 or QACR2, the following modes can be selected:
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Software initiated single-scan mode External trigger single-scan mode External gated single-scan mode (queue 1 only) Interval timer single-scan mode NOTE Queue 2 can not be programmed for external gated single-scan mode. In all single-scan queue operating modes, the software must also enable the queue to begin execution by writing the single-scan enable bit to a one in the queues control register. The single-scan enable bits, SSE1 and SSE2, are provided for queue 1 and queue 2 respectively.
Until the single-scan enable bit is set, any trigger events for that queue are ignored. The single-scan enable bit may be set to a one during the write cycle, which selects the single-scan queue operating mode. The single-scan enable bit can be written as a one or a zero, but is always read as a zero. The completion flag, completion interrupt, or queue status are used to determine when the queue has completed. After the single-scan enable bit is set, a trigger event causes the QADC64 to begin execution with the first CCW in the queue. The single-scan enable bit remains set until the queue is completed. After the queue reaches completion, the QADC64 resets the single-scan enable bit to zero. If the single-scan enable bit is written to a one or a zero by the software before the queue scan is complete, the queue is not affected. However, if the software changes the queue operating mode, the new queue operating mode and the value of the single-scan enable bit are recognized immediately. The conversion in progress is aborted and the new queue operating mode takes effect. In the software initiated single-scan mode, the writing of a one to the single-scan enable bit causes the QADC64 to internally generate a trigger event and the queue execution begins immediately. In the other single-scan queue operating modes, once the single-scan enable bit is written, the selected trigger event must occur before the queue can start. The single-scan enable bit allows the entire queue to be scanned once. A trigger overrun is captured if a trigger event occurs during queue execution in the external trigger single-scan mode and the interval timer single-scan mode. In the interval timer single-scan mode, the next expiration of the timer is the trigger event for the queue. After the queue execution is complete, the queue status is shown as idle. The software can restart the queue by setting the single-scan enable bit to a one. Queue execution begins with the first CCW in the queue. Software Initiated Single-Scan Mode. Software can initiate the execution of a scan sequence for queue 1 or 2 by selecting the software initiated single-scan mode, and writing the single-scan enable bit in QACR1 or QACR2. A trigger event is generated internally and the QADC64 immediately begins execution of the first CCW in the queue. If a pause occurs, another trigger event is generated internally, and then execution continues without pausing.
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The QADC64 automatically performs the conversions in the queue until an end-ofqueue condition is encountered. The queue remains idle until the software again sets the single-scan enable bit. While the time to internally generate and act on a trigger event is very short, software can momentarily read the status conditions, indicating that the queue is paused. The trigger overrun flag is never set while in the software initiated single-scan mode. The software initiated single-scan mode is useful in the following applications: Allows software complete control of the queue execution Allows the software to easily alternate between several queue sequences External Trigger Single-Scan Mode. The external trigger single-scan mode is a variation of the external trigger continuous-scan mode, and is also available with both queue 1 and queue 2. The software programs the polarity of the external trigger edge that is to be detected, either a rising or a falling edge. The software must enable the scan to occur by setting the single-scan enable bit for the queue. The first external trigger edge causes the queue to be executed one time. Each CCW is read and the indicated conversions are performed until an end-of-queue condition is encountered. After the queue is completed, the QADC64 clears the single-scan enable bit. Software may set the single-scan enable bit again to allow another scan of the queue to be initiated by the next external trigger edge. The external trigger single-scan mode is useful when the input trigger rate can exceed the queue execution rate. Analog samples can be taken in sync with an external event, even though the software is not interested in data taken from every edge. The software can start the external trigger single-scan mode and get one set of data, and at a later time, start the queue again for the next set of samples. When a pause bit is encountered during external trigger single-scan mode, another trigger event is required for queue execution to continue. Software involvement is not needed to enable queue execution to continue from the paused state. The external trigger single-scan mode is also useful when the software needs to change the polarity of the external trigger so that both the rising and falling edges cause queue execution. External Gated Single-Scan Mode. The QADC64 provides external gating for queue 1 only. When external gated single-scan mode is selected, a transition on the associated external trigger pin initiates queue execution. The polarity of the external gated signal is fixed so only a high level opens the gate and a low level closes the gate. Once the gate is open, each CCW is read and the indicated conversions are performed until the gate is closed. Software must enable the scan to occur by setting the single-scan enable bit for queue 1. If a pause in a CCW is encountered, the pause flag will not set, and execution continues without pausing. While the gate is open, queue 1 executes one time. Each CCW is read and the indicated conversions are performed until an end-of-queue condition is encountered. When queue 1 completes, the QADC64 sets the completion flag (CF1) and clears the
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single-scan enable bit. Software may set the single-scan enable bit again to allow another scan of queue 1 to be initiated during the next open gate. If the gate closes before queue 1 completes execution, the current CCW completes, execution of queue 1 stops, the single-scan enable bit is cleared, and the PF1 bit is set. Software can read the CWPQ1 to determine the last valid conversion in the queue. Software must set the single-scan enable bit again and should clear the PF1 bit before another scan of queue 1 is initiated during the next open gate. The start of queue 1 is always the first CCW in the CCW table. Interval Timer Single-Scan Mode. Both queues can use the periodic/interval timer in a single-scan queue operating mode. The timer interval can range from 128 to 128 Kbytes times the QCLK period in binary multiples. When the interval timer single-scan mode is selected and the software sets the single-scan enable bit in QACR1(2), the timer begins counting. When the time interval elapses, an internal trigger event is created to start the queue and the QADC64 begins execution with the first CCW. The QADC64 automatically performs the conversions in the queue until a pause or an end-of-queue condition is encountered. When a pause occurs, queue execution stops until the timer interval elapses again, and queue execution continues. When the queue execution reaches an end of queue situation the single-scan enable bit is cleared. Software may set the single-scan enable bit again, allowing another scan of the queue to be initiated by the interval timer. The interval timer generates a trigger event whenever the time interval elapses. The trigger event may cause the queue execution to continue following a pause, or may be considered a trigger overrun. Once the queue execution is completed, the single-scan enable bit must be set again to enable the timer to count again. Normally only one queue will be enabled for interval timer single-scan mode and the timer will reset at the end of queue. However, if both queues are enabled for either single-scan or continuous interval timer mode, the end of queue condition will not reset the timer while the other queue is active. In this case, the timer will reset when both queues have reached end of queue. The interval timer single-scan mode can be used in applications which need coherent results, for example: When it is necessary that all samples are guaranteed to be taken during the same scan of the analog pins When the interrupt rate in the periodic timer continuous-scan mode would be too high In sensitive battery applications, where the single-scan mode uses less power than the software initiated continuous-scan mode 13.10.3.4 Continuous-Scan Modes When the application software wants to execute multiple passes through a sequence of conversions defined by a queue, a continuous-scan queue operating mode is se-
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lected. By programming the MQ1(2) field in QACR1(2), the following software initiated modes can be selected: Software initiated continuous-scan mode External trigger continuous-scan mode External gated continuous-scan mode (queue 1 only) Interval timer continuous-scan mode When a queue is programmed for a continuous-scan mode, the single-scan enable bit in the queue control register does not have any meaning or effect. As soon as the queue operating mode is programmed, the selected trigger event can initiate queue execution. In the case of the software initiated continuous-scan mode, the trigger event is generated internally and queue execution begins immediately. In the other continuous-scan queue operating modes, the selected trigger event must occur before the queue can start. A trigger overrun is captured if a trigger event occurs during queue execution in the external trigger continuous-scan mode and the periodic timer continuous-scan mode. After the queue execution is complete, the queue status is shown as idle. Since the continuous-scan queue operating modes allow the entire queue to be scanned multiple times, software involvement is not needed to enable queue execution to continue from the idle state. The next trigger event causes queue execution to begin again, starting with the first CCW in the queue. NOTE In this version of QADC64, coherent samples can be guaranteed. The time between consecutive conversions has been designed to be consistent, provided the sample time bits in both the CCW and IST are identical. However, there is one exception. For queues that end with a CCW containing EOQ code (channel 63), the last queue conversion to the first queue conversion requires one additional CCW fetch cycle. Therefore continuous samples are not coherent at this boundary. In addition, the time from trigger to first conversion can not be guaranteed since it is a function of clock synchronization, programmable trigger events, queue priorities, and so on. Software Initiated Continuous-Scan Mode. When the software initiated continuousscan mode is programmed, the trigger event is generated automatically by the QADC64. Queue execution begins immediately. If a pause is encountered, another trigger event is generated internally, and then execution continues without pausing. When the end-of-queue is reached, another internal trigger event is generated, and queue execution begins again from the beginning of the queue. While the time to internally generate and act on a trigger event is very short, software can momentarily read the status conditions, indicating that the queue is idle. The trigger overrun flag is never set while in the software initiated continuous-scan mode.
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The software initiated continuous-scan mode keeps the result registers updated more frequently than any of the other queue operating modes. The software can always read the result table to get the latest converted value for each channel. The channels scanned are kept up-to-date by the QADC64 without software involvement. Software can read a result value at any time. The software initiated continuous-scan mode may be chosen for either queue, but is normally used only with queue 2. When the software initiated continuous-scan mode is chosen for queue 1, that queue operates continuously and queue 2, being lower in priority, never gets executed. The short interval of time between a queue 1 completion and the subsequent trigger event is not sufficient to allow queue 2 execution to begin. The software initiated continuous-scan mode is a useful choice with queue 2 for converting channels that do not need to be synchronized to anything, or for the slow-tochange analog channels. Interrupts are normally not used with the software initiated continuous-scan mode. Rather, the software reads the latest conversion result from the result table at any time. Once initiated, software action is not needed to sustain conversions of channel. Data read at different locations, however, may or may not be coherent (that is, from the same queue scan sequence). External Trigger Continuous-Scan Mode. The QADC64 provides external trigger pins for both queues. When the external trigger software initiated continuous-scan mode is selected, a transition on the associated external trigger pin initiates queue execution. The polarity of the external trigger signal is programmable, so that the software can choose to begin queue execution on the rising or falling edge. Each CCW is read and the indicated conversions are performed until an end-of-queue condition is encountered. When the next external trigger edge is detected, the queue execution begins again automatically. Software initialization is not needed between trigger events. When a pause bit is encountered in external trigger continuous-scan mode, another trigger event is required for queue execution to continue. Software involvement is not needed to enable queue execution to continue from the paused state. Some applications need to synchronize the sampling of analog channels to external events. There are cases when it is not possible to use software initiation of the queue scan sequence, since interrupt response times vary. External Gated Continuous-Scan Mode. The QADC64 provides external gating for queue 1 only. When external gated continuous-scan mode is selected, a transition on the associated external trigger pin initiates queue execution. The polarity of the external gated signal is fixed so a high level opens the gate and a low level closes the gate. Once the gate is open, each CCW is read and the indicated conversions are performed until the gate is closed. When the gate opens again, the queue execution automatically begins again from the beginning of the queue. Software initialization is not needed between trigger events. If a pause in a CCW is encountered, the pause flag will not set, and execution continues without pausing.
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The purpose of external gated continuous-scan mode is to continuously collect digitized samples while the gate is open and to have the most recent samples available. To ensure consistent sample times in waveform digitizing, for example, the programmer must ensure that all CCWs have identical sample time settings in IST. It is up to the programmer to ensure that the queue is large enough so that a maximum gate open time will not reach an end of queue. However it is useful to take advantage of a smaller queue in the manner described in the next paragraph. In the event that the queue completes before the gate closes, a completion flag will be set and the queue will roll over to the beginning and continue conversions until the gate closes. If the gate remains open and the queue completes a second time, the trigger overrun flag will be set and the queue will roll-over again. The queue will continue to execute until the gate closes or the mode is disabled.
If the gate closes before queue 1 completes execution, the current CCW completes, execution of queue 1 stops and QADC64 sets the PF1 bit to indicate an incomplete queue. Software can read the CWPQ1 to determine the last valid conversion in the queue. In this mode, if the gate opens again execution of queue 1 begins again. The start of queue 1 is always the first CCW in the CCW table. Interval Timer Continuous-Scan Mode. The QADC64 includes a dedicated periodic/ interval timer for initiating a scan sequence on queue 1 and/or queue 2. Software selects a programmable timer interval ranging from 128 to 128 Kbytes times the QCLK period in binary multiples. The QCLK period is prescaled down from the intermodule bus (IMB) MCU clock. When a periodic timer continuous-scan mode is selected for queue 1 and/or queue 2, the timer begins counting. After the programmed interval elapses, the timer generated trigger event starts the appropriate queue. Meanwhile, the QADC64 automatically performs the conversions in the queue until an end-of-queue condition or a pause is encountered. When a pause occurs, the QADC64 waits for the periodic interval to expire again, then continues with the queue. Once end-of-queue has been detected, the next trigger event causes queue execution to begin again with the first CCW in the queue. The periodic timer generates a trigger event whenever the time interval elapses. The trigger event may cause the queue execution to continue following a pause or queue completion, or may be considered a trigger overrun. As with all continuous-scan queue operating modes, software action is not needed between trigger events. Software enables the completion interrupt when using the periodic timer continuousscan mode. When the interrupt occurs, the software knows that the periodically collected analog results have just been taken. The software can use the periodic interrupt to obtain non-analog inputs as well, such as contact closures, as part of a periodic look at all inputs. 13.10.4 QADC64 Clock (QCLK) Generation Figure 13-8 is a block diagram of the clock subsystem. The QCLK provides the timing for the A/D converter state machine, which controls the timing of the conversion. The
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QCLK is also the input to a 17-stage binary divider which implements the periodic/interval timer. To retain the specified analog conversion accuracy, the QCLK frequency (FQCLK) must be within a specified tolerance. See APPENDIX G ELECTRICAL CHARACTERISTICS. Before using the QADC64, the software must initialize the prescaler with values that put the QCLK within the specified range. Though most software applications initialize the prescaler once and do not change it, write operations to the prescaler fields are permitted. NOTE For software compatibility with earlier versions of QADC64, the definition of PSL, PSH, and PSA have been maintained. However, the requirements on minimum time and minimum low time no longer exist. CAUTION A change in the prescaler value while a conversion is in progress is likely to corrupt the result from any conversion in progress. Therefore, any prescaler write operation should be done only when both queues are in the disabled modes.
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ZERO DETECT
RESET QCLK
5 IMB CLOCK (FSYS) 5-BIT DOWN COUNTER LOAD PSH
CLOCK GENERATE 5 PRESCALER RATE SELECTION (FROM CONTROL REGISTER 0): HIGH TIME CYCLES (PSH) LOW TIME CYCLES (PSL) 3
QCLK
ONE'S COMPLEMENT COMPARE 3
SET QCLK
ADD HALF CYCLE TO HIGH (PSA) QADC64 CLOCK ( FSYS / 2 TO FSYS/40 )
INPUT SAMPLE TIME (FROM CCW) 2
A/D CONVERTER STATE MACHINE 10
SAR CONTROL SAR
BINARY COUNTER 9 10 12 15 17 27 28 2 2 211 2 213 214 2 216 2 Queue 1 & 2 TIMER MODE RATE SELECTION 8 2 PERIODIC/INTERVAL TRIGGER EVENT FOR Q1 AND Q2
PERIODIC/INTERVAL TIMER SELECT
Figure 13-8 QADC64 Clock Subsystem Functions To accommodate wide variations of the main MCU clock frequency (IMB clock FSYS), QCLK is generated by a programmable prescaler which divides the MCU IMB clock to a frequency within the specified QCLK tolerance range. To allow the A/D conversion time to be maximized across the spectrum of IMB clock frequencies, the QADC64 prescaler permits the frequency of QCLK to be software selectable. It also allows the duty cycle of the QCLK waveform to be programmable. The software establishes the basic high phase of the QCLK waveform with the PSH (prescaler clock high time) field in QACR0, and selects the basic low phase of QCLK with the prescaler clock low time (PSL) field. The combination of the PSH and PSL parameters establishes the frequency of the QCLK.
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NOTE The guideline for selecting PSH and PSL is select is to maintain approximately 50% duty cycle. So for prescaler values less then 16, or PSH ~= PSL. For prescaler values greater than 16 keep PSL as large as possible. Figure 13-8 shows that the prescaler is essentially a variable pulse width signal generator. A 5-bit down counter, clocked at the IMB clock rate, is used to create both the high phase and the low phase of the QCLK signal. At the beginning of the high phase, the 5-bit counter is loaded with the 5-bit PSH value. When the zero detector finds that the high phase is finished, the QCLK is reset. A 3-bit comparator looks for a ones complement match with the 3-bit PSL value, which is the end of the low phase of the QCLK. The PSA bit was maintained for software compatibility, but has no effect on QADC64.
The following equations define QCLK frequency: High QCLK Time = (PSH + 1) FSYS Low QCLK Time = (PSL + 1) FSYS FQCLK= 1 (High QCLK Time + Low QCLK Time) Where: PSH = 0 to 31, the prescaler QCLK high cycles in QACR0 PSL = 0 to 7, the prescaler QCLK low cycles in QACR0 FSYS = IMB clock frequency FQCLK = QCLK frequency The following are equations for calculating the QCLK high/low phases in Example 1: High QCLK Time = (11 + 1) 40 x 106 = 300 ns Low QCLK Time = (7 + 1) 40 x 106 = 200 ns FQCLK = 1/(300 + 200) = 2 MHz The following are equations for calculating the QCLK high/low phases in Example 2: High QCLK Time = (7 + 1) 32 x 106 = 250 ns Low QCLK Time = (7 + 1) 32 x 106 = 250 ns
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FQCLK = 1/(250 + 250) = 2 MHz Figure 13-9 and Table 13-4 show examples of QCLK programmability. The examples include conversion times based on the following assumption: Input sample time is as fast as possible (IST = 0, 2 QCLK cycles). Figure 13-9 and Table 13-4 also show the conversion time calculated for a single conversion in a queue. For other MCU IMB clock frequencies and other input sample times, the same calculations can be made.
IMB CLOCK FSYS
QCLK EXAMPLES 40 MHz EX1
32 MHz EX2
20 CYCLES
QADC64 QCLK EX
Figure 13-9 QADC64 Clock Programmability Examples
Table 13-4 QADC64 Clock Programmability

Control Register 0 Information Example Number 1 2 Frequency 40 MHz 32 MHz PSH 11 7 PSA 0 0 PSL 7 7 Input Sample Time (IST) =%00 QCLK (MHz) 2.0 2.0 Conversion Time (s) 7.0 7.0
NOTE PSA is maintained for software compatibility but has no functional benefit to this version of the module. The MCU IMB clock frequency is the basis of the QADC64 timing. The QADC64 requires that the IMB clock frequency be at least twice the QCLK frequency. The QCLK frequency is established by the combination of the PSH and PSL parameters in QACR0. The 5-bit PSH field selects the number of IMB clock cycles in the high phase of the QCLK wave. The 3-bit PSL field selects the number of IMB clock cycles in the low phase of the QCLK wave. Example 1 in Figure 13-9 shows that when PSH = 11, the QCLK remains high for twelve cycles of the IMB clock. It also shows that when PSL = 7, the QCLK remains low for eight IMB clock cycles. In Example 2, PSH = 7, the QCLK remains high for eight
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cycles of the IMB clock. It also shows that when PSL = 7, the QCLK remains low for eight IMB clock cycles. 13.10.5 Periodic/Interval Timer The on-chip periodic/interval timer is enabled to generate trigger events at a programmable interval, initiating execution of queue 1 and/or 2. The periodic/interval timer stays reset under the following conditions: Queue 1 and queue 2 are programmed to any queue operating mode which does not use the periodic/interval timer Interval timer single-scan mode is selected, but the single-scan enable bit is set to zero IMB system reset or the master reset is asserted Stop mode is selected Freeze mode is selected Two other conditions which cause a pulsed reset of the timer are: Roll-over of the timer counter A queue operating mode change from one periodic/interval timer mode to another periodic/interval timer mode, depending on which queues are active in timer mode. NOTE The periodic/interval timer will not reset for a queue 2 operating mode change from one periodic/interval timer mode to another periodic/interval timer mode while queue 1 is in an active periodic/interval timer mode. During the low power stop mode, the periodic/interval timer is held in reset. Since low power stop mode causes QACR1 and QACR2 to be reset to zero, a valid periodic or interval timer mode must be written after stop mode is exited to release the timer from reset. When the IMB internal FREEZE line is asserted and a periodic or interval timer mode is selected, the timer counter is reset after the conversion in-progress completes. When the periodic or interval timer mode has been enabled (the timer is counting), but a trigger event has not been issued, the freeze mode takes effect immediately, and the timer is held in reset. When the internal FREEZE line is negated, the timer counter starts counting from the beginning. 13.11 Interrupts The QADC64 supports both polled and interrupt driven operation. Status bits in QASR reflect the operating condition of each queue and can optionally generate interrupts when enabled by the appropriate bits in QACR1 and/or QACR2. Figure 13-10 displays the QADC64 interrupt flow.
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INTERRUPT CONTROL PIE1 PF1 CIE1 CF1

CONVERSION PAUSE ENABLE
CONVERSION PAUSE FLAG CONVERSION COMPLETE INTERRUPT ENABLE
QUEUE 1 (IRL1)
CONVERSION COMPLETE FLAG
INTERRUPT GENERATOR PIE2 PF2 CIE2

CONVERSION PAUSE ENABLE
IRQ[7:0]
CONVERSION PAUSE FLAG CONVERSION COMPLETE INTERRUPT ENABLE
QUEUE 2 (IRL2)
CF2
CONVERSION COMPLETE FLAG
Figure 13-10 QADC64 Interrupt Flow Diagram 13.11.1 Interrupt Sources The QADC64 has four interrupt service sources, each of which is separately enabled. Each time the result is written for the last CCW in a queue, the completion flag for the corresponding queue is set, and when enabled, an interrupt request is generated. In the same way, each time the result is written for a CCW with the pause bit set, the queue pause flag is set, and when enabled, an interrupt request is generated. Table 13-5 displays the status flag and interrupt enable bits which correspond to queue 1 and queue 2 activity. Table 13-5 QADC64 Status Flags and Interrupt Sources
Queue Queue 1 Queue Activity Result written for the last CCW in queue 1 Result written for a CCW with pause bit set in queue 1 Result written for the last CCW in queue 2 Queue 2 Result written for a CCW with pause bit set in queue 2 Status Flag CF1 PF1 CF2 PF2 Interrupt Enable Bit CIE1 PIE1 CIE2 PIE2
Both polled and interrupt-driven QADC64 operations require that status flags must be cleared after an event occurs. Flags are cleared by first reading QASR with the appropriate flag bits set to one, then writing zeros to the flags that are to be cleared. A flag can be cleared only if the flag was a logic one at the time the register was read by the CPU. If a new event occurs between the time that the register is read and the time that it is written, the associated flag is not cleared.
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13.11.2 Interrupt Register The QADC64 interrupt register QADC64INT specifies the priority level of QADC64 interrupt requests The values contained in the IRL1 and IRL2 fields in QADC64INT determine the priority of QADC64 interrupt service requests.The interrupt levels for queue 1 and queue 2 may be different. 13.11.3 Interrupt Levels and Time Multiplexing The QADC64 conditionally generates interrupts to the bus master via the IMB IRQ signals. When the QADC64 sets a status bit assigned to generate an interrupt, the QADC64 drives the IRQ bus. The value driven onto IRQ[7:0] represents the interrupt level assigned to the interrupt source. Under the control of ILBS, each interrupt request level is driven during the time multiplexed bus during one of four different time slots, with eight levels communicated per time slot. No hardware priority is assigned to interrupts. Furthermore, if more than one source on a module requests an interrupt at the same level, the system software must assign a priority to each source requesting at that level. Figure 13-11 displays the interrupt levels on IRQ with ILBS.
IMB3 CLOCK
ILBS [1:0]
00
01
10
11
00
01
10
11
IMB3 IRQ [7:0]
IRQ 0:7
IRQ 8:15
IRQ 16:23
IRQ 24:31
IRQ 0:7
Figure 13-11 Interrupt Levels on IRQ with ILBS 13.12 Programming Model Each QADC64 occupies 1 Kbyte (512 16-bit entries) of address space. The address space consists of ten 16-bit control, status, and port registers; 64 16-bit entries in the CCW table; and 64 16-bit entries in the result table. The result table occupies 192 16bit address locations because the result data is readable in three data alignment formats. Table 13-6 shows the QADC64 memory map. The lowercase x appended to each register name represents A or B for the QADC64_A or QADC64_B module, respectively. The address offset shown is from the base address of the module. Refer to 1.3 MPC555 / MPC556 Address Map to locate each QADC64 module in the MPC555 / MPC556 memory map.
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Table 13-6 QADC64 Address Map
Access Address 0x30 4800 0x30 4C00 0x30 4802 0x30 4C02 0x30 4804 0x30 4C04 0x30 4806 0x30 4C06 0x30 4808 0x30 4C08 0x30 480A 0x30 4C0A 0x30 480C 0x30 4C0C 0x30 480E 0x30 4C0E 0x30 4810, 0x30 4C10 0x30 4812, 0x30 4C12 0x30 4814 0x30 49FE 0x30 4C14 0x30 4DFE 0x30 4A00 0x30 4A7E 0x30 4E00 0x30 4E7E 0x30 4A80 0x30 4AFE 0x30 4E80 0x30 4EFE MSB 0 LSB 15
S1 T2 S
QADC64 Module Configuration Register (QADC64MCR_x) See Table 13-7 for bit descriptions. QADC64 Test Register (QADC64TEST_x) Interrupt Register (QADC64INT_x) See Table 13-8 for bit descriptions. Port A Data (PORTQA_x) See Table 13-10 for bit descriptions. Port B Data (PORTQB_x)
S/U3
S/U S/U S/U S/U S/U S/U --S/U
Port A Data Direction Register (DDRQA_x) See Table 13-10 for bit descriptions. QADC64 Control Register 0 (QACR0_x) See Table 13-11 for bit descriptions. QADC64 Control Register 1 (QACR1_x) See Table 13-12 for bit descriptions. QADC64 Control Register 2 (QACR2_x) See Table 13-14 for bit descriptions. QADC64 Status Register 0 (QASR0_x) See Table 13-16 for bit descriptions. QADC64 Status Register 1 (QASR1_x) See Table 13-18 for bit descriptions. Reserved Conversion Command Word (CCW_x) Table See Table 13-19 for bit descriptions. Result Word Table Right-Justified, Unsigned Result Register (RJURR_x) See 13.12.12 for bit descriptions. Result Word Table Left-Justified, Signed Result Register (LJSRR_x) See 13.12.12 for bit descriptions. Result Word Table Left-Justified, Unsigned Result Register (LJURR_x) See 13.12.12 for bit descriptions.
S/U
S/U
0x30 4B00 0x30 4B7E 0x30 4F00 0x30 4F7E
S/U
0x30 4B80 0x30 4BFE 0x30 4F80 0x30 4FFE
NOTES: 1. S = Supervisor only 2. Access is restricted to supervisor only and factory test mode only. 3. S/U = Unrestricted or supervisor depending on the state of the SUPV bit in the QADC64MCR.
The QADC64 has three global registers for configuring module operation: the module configuration register (QADC64MCR), the interrupt register (QADC64INT), and a test register (QADC64TEST). The global registers are always defined to be in supervisor data space. The CPU allows software to establish the global registers in supervisor data space and the remaining registers and tables in user space.
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All QADC64 analog channel/port pins that are not used for analog input channels can be used as digital port pins. Port values are read/written by accessing the port A and B data registers (PORTQA and PORTQB). Port A pins are specified as inputs or outputs by programming the port data direction register (DDRQA). Port B is an input-only port. 13.12.1 QADC64 Module Configuration Register QADC64MCR QADC64 Module Configuration Register
MSB 0 STOP 1 FRZ 2 3 4 5 6 7 8 SUPV 9 10 11 12 RESERVED
0x30 4800 0x30 4C00

13 14 LSB 15
RESERVED
RESET: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Table 13-7 QADC64MCR Bit Descriptions

Bit(s) Name Description Low-power stop mode enable. When the STOP bit is set, the clock signal to the QADC64 is disabled, effectively turning off the analog circuitry. 0 = Enable QADC64 clock 1 = Disable QADC64 clock FREEZE assertion response. The FRZ bit determines whether or not the QADC64 responds to assertion of the IMB3 FREEZE signal. 0 = QADC64 ignores the IMB3 FREEZE signal 1 = QADC64 finishes any current conversion, then freezes Reserved Supervisor/unrestricted data space. The SUPV bit designates the assignable space as supervisor or unrestricted. 0 = Only the module configuration register, test register, and interrupt register are designated as supervisor-only data space. Access to all other locations is unrestricted 1 = All QADC64 registers and tables are designated as supervisor-only data space Reserved
STOP
FRZ
2:7
SUPV
9:15
13.12.2 QADC64 Test Register QADC64TEST QADC64 Test Register Used for factory test only. 13.12.3 QADC64 Interrupt Register QADC64INT QADC64 Interrupt Register
MSB 0 1 2 IRL1 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 4 5 6 7 IRL2 8 9 10 11 12 13
0x30 4802, 0x30 4C02
0x30 4804 0x30 4C04

14 LSB 15
RESERVED
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Table 13-8 QADC64INT Bit Descriptions
Bit(s) 0:4 Name IRL1 Description Interrupt level for queue 1. A value of 0b00000 provides an interrupt level of 0; 0b11111 provides a level interrupt. All interrupts are presented on the IMB3. Interrupt level priority software determines which level has the highest priority request. Interrupt level for queue 2. A value of 0b00000 provides an interrupt level of 0; 0b11111 provides a level interrupt. All interrupts are presented on the IMB3. Interrupt level priority software determines which level has the highest priority request. Reserved
5:9 10:15
IRL2
13.12.4 Port A/B Data Register QADC64 ports A and B are accessed through two 8-bit port data registers (PORTQA and PORTQB).
PORTQA Port QA Data Register PORTQB Port QB Data Register

MSB 0 PQA7 1 2 3 PQA4 4 PQA3 5 PQA2 6 7 8 9 10 11 12 13
0x30 4806 0x30 4C06

14 LSB 15
PQA6 PQA5
PQA1 PQA0 PQB7 PQB6 PQB5 PQB4 PQB3 PQB2 PQB1 PQB0
RESET: U U U U U U U U U U U U U U U U
ANALOG CHANNEL: AN59 AN58 AN57 AN56 AN55 AN54 AN53 AN52 AN51 AN50 AN49 AN48 AN3 AN2 AN1 AN0
MULTIPLEXED ADDRESS OUTPUTS: MA2 MULTIPLEXED ANALOG INPUTS: ANz ANy ANx ANw MA1 MA0
Table 13-9 PORTQA, PORTQB Bit Descriptions

Bit(s) 0:7 8:15 Name PQA[0:7] PQB[0:7] Description Port A pins are referred to as PQA when used as an 8-bit input/output port. Port A can also be used for analog inputs (AN[59:52]), and external multiplexer address outputs (MA[2:0]). Port B pins are referred to as PQB when used as an 8-bit input-only port. Port B can also be used for non-multiplexed (AN[51:48])/AN[3:0]) and multiplexed (ANz, ANy, ANx, ANw) analog inputs.
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13.12.5 Port Data Direction Register DDRQA Port QA Data Direction Register
MSB 0 DDQA7 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12
0x30 4808 0x30 4C08

13 14 LSB 15
DDQA DDQA DDQA DDQA DDQA DDQA DDQA 6 5 4 3 2 1 0
RESERVED
Table 13-10 DDRQA Bit Descriptions

Bit(s) Name Description
0:7
Bits in this register control the direction of the port QA pin drivers when pins are configured for I/ DDQA[7:0] O. Setting a bit configures the corresponding pin as an output; clearing a bit configures the corresponding pin as an input. This register can be read or written at any time.
13.12.6 QADC64 Control Register 0 (QACR0) Control register zero establishes the QCLK with prescaler parameter fields and defines whether external multiplexing is enabled. All of the implemented control register fields can be read or written, reserved fields read zero and writes have no effect. They are typically written once when the software initializes the QADC64, and not changed afterwards. QACR0 QADC64 Control Register 0
MSB 0 MUX RESET: 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 1 1 2 3 TRG 4 5 RESERVED 6 7 8 9 PSH 10 11 12 PSA
0x30 480A 0x30 4C0A

13 14 PSL LSB 15
RESERVED
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Table 13-11 QACR0 Bit Descriptions
Bit(s) Name Description Externally multiplexed mode. The MUX bit configures the QADC64 for externally multiplexed mode, which affects the interpretation of the channel numbers and forces the MA[2:0] pins to be outputs. 0 = Internally multiplexed, 16 possible channels 1 = Externally multiplexed, 41 possible channels Reserved Trigger assignment. TRG allows the software to assign the ETRIG[2:1] pins to queue 1 and queue 2. 0 = ETRIG1 triggers queue 1; ETRIG2 triggers queue 2 1 = ETRIG1 triggers queue 2; ETRIG2 triggers queue 1 Reserved Prescaler clock high time. The PSH field selects the QCLK high time in the prescaler. PSH value plus 1 represents the high time in IMB clocks Note that this bit location is maintained for software compatibility with previous versions of the QADC64. It serves no functional benefit in the MPC555 / MPC556 and is not operational. Prescaler clock low time. The PSL field selects the QCLK low time in the prescaler. PSL value plus 1 represents the low time in IMB clocks
MUX
1:2
TRG
4:6
PSH PSA PSL
7:11 12 13:15
13.12.7 QADC64 Control Register 1 (QACR1) Control register 1 is the mode control register for the operation of queue 1. The applications software defines the queue operating mode for the queue, and may enable a completion and/or pause interrupt. All of the control register fields are read/write data. However, the SSE1 bit always reads as zero unless the test mode is enabled. Most of the bits are typically written once when the software initializes the QADC64, and not changed afterwards. QACR1 Control Register 1
MSB 0 CIE1 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 PIE1 2 SSE1 3 4 5 MQ1 6 7 8 9 10 11 12
0x30 480C 0x30 4C0C

13 14 LSB 15
RESERVED
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Bit(s) Name Description Queue 1 completion interrupt enable. CIE1 enables completion interrupts for queue 1. The interrupt request is generated when the conversion is complete for the last CCW in queue 1. 0 = Queue 1 completion interrupts disabled 1 = Generate an interrupt request after completing the last CCW in queue 1 Queue 1 pause interrupt enable. PIE1 enables pause interrupts for queue 1. The interrupt request is generated when the conversion is complete for a CCW that has the pause bit set. 0 = Queue 1 pause interrupts disabled 1 = Generate an interrupt request after completing a CCW in queue 1 which has the pause bit set Queue 1 single-scan enable. SSE1 enables a single-scan of queue 1 after a trigger event occurs. The SSE1 bit may be set to a one during the same write cycle that sets the MQ1 bits for the single-scan queue operating mode. The single-scan enable bit can be written as a one or a zero, but is always read as a zero. The SSE1 bit allows a trigger event to initiate queue execution for any single-scan operation on queue 1. The QADC64 clears SSE1 when the single-scan is complete. 3:7 8:15 MQ1 Queue 1 operating mode. The MQ1 field selects the queue operating mode for queue 1. Table 13-13 shows the different queue 1 operating modes. Reserved
CIE1
PIE1
SSE1
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Table 13-13 Queue 1 Operating Modes
MQ1 0b00000 0b00001 0b00010 0b00011 0b00100 0b00101 0b00110 0b00111 0b01000 Operating Modes Disabled mode, conversions do not occur Software triggered single-scan mode (started with SSE1) External trigger rising edge single-scan mode External trigger falling edge single-scan mode Interval timer single-scan mode: time = QCLK period x 27 Interval timer single-scan mode: time = QCLK period x 28 Interval timer single-scan mode: time = QCLK period x 29 Interval timer single-scan mode: time = QCLK period x 210 Interval timer single-scan mode: time = QCLK period x 211 Interval timer single-scan mode: time = QCLK period x 212 Interval timer single-scan mode: time = QCLK period x 213 Interval timer single-scan mode: time = QCLK period x 214 Interval timer single-scan mode: time = QCLK period x 215 Interval timer single-scan mode: time = QCLK period x 216 Interval timer single-scan mode: time = QCLK period x 217 External gated single-scan mode (started with SSE1) Reserved mode Software triggered continuous-scan mode External trigger rising edge continuous-scan mode External trigger falling edge continuous-scan mode Periodic timer continuous-scan mode: time = QCLK period x 27 Periodic timer continuous-scan mode: time = QCLK period x 28 Periodic timer continuous-scan mode: time = QCLK period x 29 Periodic timer continuous-scan mode: time = QCLK period x 210 Periodic timer continuous-scan mode: time = QCLK period x 211 Periodic timer continuous-scan mode: time = QCLK period x 212 Periodic timer continuous-scan mode: time = QCLK period x 213 Periodic timer continuous-scan mode: time = QCLK period x 214 Periodic timer continuous-scan mode: time = QCLK period x 215 Periodic timer continuous-scan mode: time = QCLK period x 216 Periodic timer continuous-scan mode: time = QCLK period x 217 External gated continuous-scan mode
0b01001 0b01010 0b01011 0b01100 0b01101 0b01110 0b01111 0b10000 0b10001 0b10010 0b10011 0b10100 0b10101 0b10110 0b10111 0b11000 0b11001 0b11010 0b11011 0b11100 0b11101 0b11110 0b11111
13.12.8 QADC64 Control Register 2 (QACR2) Control register two is the mode control register for the operation of queue 2. Software specifies the queue operating mode of queue 2, and may enable a completion and/or a pause interrupt. All control register fields are read/write data, except the SSE2 bit,
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which is readable only when the test mode is enabled. Most of the bits are typically written once when the software initializes the QADC64, and not changed afterwards. QACR2 Control Register 2
MSB 0 CIE2 RESET: 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 PIE2 2 SSE2 3 4 5 MQ2 6 7 8 RESUME 9 10 11 12 BQ2
0x30 480E 0x30 4C0E

13 14 LSB 15
Bit(s)
Name
Description Queue 2 completion interrupt enable. CIE2 enables completion interrupts for queue 2. The interrupt request is generated when the conversion is complete for the last CCW in queue 2. 0 = Queue 2 completion interrupts disabled. 1 = Generate an interrupt request after completing the last CCW in queue 2. Queue 2 pause interrupt enable. PIE2 enables pause interrupts for queue 2. The interrupt request is generated when the conversion is complete for a CCW that has the pause bit set. 0 = Queue 2 pause interrupts disabled. 1 = Generate an interrupt request after completing a CCW in queue 2 which has the pause bit set. Queue 2 single-scan enable bit. SSE2 enables a single-scan of queue 2 after a trigger event occurs. The SSE2 bit may be set to a one during the same write cycle that sets the MQ2 bits for the single-scan queue operating mode. The single-scan enable bit can be written as a one or a zero, but is always read as a zero. The SSE2 bit allows a trigger event to initiate queue execution for any single-scan operation on queue 2. The QADC64 clears SSE2 when the single-scan is complete.
CIE2
PIE2
SSE2
3:7
MQ2
Queue 2 operating mode. The MQ2 field selects the queue operating mode for queue 2. Table 13-15 shows the bits in the MQ2 field which enable different queue 2 operating modes.
Queue 2 resume. RESUME selects the resumption point after queue 2 is suspended by queue 1. If RESUME is changed during execution of queue 2, the change is not recognized until an endRESUME of-queue condition is reached, or the queue operating mode of queue 2 is changed. 0 = After suspension, begin execution with the first CCW in queue 2 or the current sub-queue. 1 = After suspension, begin execution with the aborted CCW in queue 2. Beginning of queue 2. The BQ2 field indicates the location in the CCW table where queue 2 begins. The BQ2 field also indicates the end of queue 1 and thus creates an end-of-queue condition for queue 1. Setting BQ2 to any value 64 (0b1000000) allows the entire RAM space for queue 1 CCWs.
9:15
BQ2
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Table 13-15 Queue 2 Operating Modes
MQ2 0b00000 0b00001 0b00010 0b00011 0b00100 0b00101 0b00110 0b00111 0b01000 Operating Modes Disabled mode, conversions do not occur Software triggered single-scan mode (started with SSE2) External trigger rising edge single-scan mode External trigger falling edge single-scan mode Interval timer single-scan mode: interval = QCLK period x 27 Interval timer single-scan mode: interval = QCLK period x 28 Interval timer single-scan mode: interval = QCLK period x 29 Interval timer single-scan mode: interval = QCLK period x 210 Interval timer single-scan mode: interval = QCLK period x 211 Interval timer single-scan mode: interval = QCLK period x 212 Interval timer single-scan mode: interval = QCLK period x 213 Interval timer single-scan mode: interval = QCLK period x 214 Interval timer single-scan mode: interval = QCLK period x 215 Interval timer single-scan mode: interval = QCLK period x 216 Interval timer single-scan mode: interval = QCLK period x 217 Reserved mode Reserved mode Software triggered continuous-scan mode (started with SSE2) External trigger rising edge continuous-scan mode External trigger falling edge continuous-scan mode Periodic timer continuous-scan mode: period = QCLK period x 27 Periodic timer continuous-scan mode: period = QCLK period x 28 Periodic timer continuous-scan mode: period = QCLK period x 29 Periodic timer continuous-scan mode: period = QCLK period x 210 Periodic timer continuous-scan mode: period = QCLK period x 211 Periodic timer continuous-scan mode: period = QCLK period x 212 Periodic timer continuous-scan mode: period = QCLK period x 213 Periodic timer continuous-scan mode: period = QCLK period x 214 Periodic timer continuous-scan mode: period = QCLK period x 215 Periodic timer continuous-scan mode: period = QCLK period x 216 Periodic timer continuous-scan mode: period = QCLK period x 217 Reserved mode
0b01001 0b01010 0b01011 0b01100 0b01101 0b01110 0b01111 0b10000 0b10001 0b10010 0b10011 0b10100 0b10101 0b10110 0b10111 0b11000 0b11001 0b11010 0b11011 0b11100 0b11101 0b11110 0b11111
13.12.9 QADC64 Status Register 0 (QASR0) QASR0 contains information about the state of each queue and the current A/D conversion. Except for the four flag bits (CF1, PF1, CF2, and PF2) and the two trigger overrun bits (TOR1 and TOR2), all of the status register fields contain read-only data.
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The four flag bits and the two trigger overrun bits are cleared by writing a zero to the bit after the bit was previously read as a one. QASR0 QADC64 Status Register
MSB 0 CF1 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 PF1 2 CF2 3 PF2 4 TOR1 5 TOR2 6 7 QS 8 9 10 11 12 CWP
0x30 4810 0x30 4C10

13 14 LSB 15
Table 13-16 QASR0 Bit Descriptions
Bit(s)
Name
Description Queue 1 completion flag. CF1 indicates that a queue 1 scan has been completed. CF1 is set by the QADC64 when the conversion is complete for the last CCW in queue 1, and the result is stored in the result table. 0 = Queue 1 scan is not complete 1 = Queue 1 scan is complete Queue 1 pause flag. PF1 indicates that a queue 1 scan has reached a pause. PF1 is set by the QADC64 when the current queue 1 CCW has the pause bit set, the selected input channel has been converted, and the result has been stored in the result table. 0 = Queue 1 has not reached a pause 1 = Queue 1 has reached a pause Queue 2 completion flag. CF2 indicates that a queue 2 scan has been completed. CF2 is set by the QADC64 when the conversion is complete for the last CCW in queue 2, and the result is stored in the result table. 0 = Queue 2 scan is not complete 1 = Queue 2 scan is complete Queue 2 pause flag. PF2 indicates that a queue 2 scan has reached a pause. PF2 is set by the QADC64 when the current queue 2 CCW has the pause bit set, the selected input channel has been converted, and the result has been stored in the result table. 0 = Queue 2 has not reached a pause 1 = Queue 2 has reached a pause Queue 1 trigger overrun. TOR1 indicates that an unexpected queue 1 trigger event has occurred. TOR1 can be set only while queue 1 is active.
CF1
PF1
CF2
PF2
TOR1
A trigger event generated by a transition on ETRIG1/ETRIG2 may be recorded as a trigger overrun. TOR1 can only be set when using an external trigger mode. TOR1 cannot occur when the software initiated single-scan mode or the software initiated continuous-scan mode is selected. 0 = No unexpected queue 1 trigger events have occurred 1 = At least one unexpected queue 1 trigger event has occurred Queue 2 trigger overrun. TOR2 indicates that an unexpected queue 2 trigger event has occurred. TOR2 can be set when queue 2 is in the active, suspended, and trigger pending states. A trigger event generated by a transition depending on the value of TRG in QACR or ETRIG1/ ETRIG2 or by the periodic/interval timer may be recorded as a trigger overrun. TOR2 can only be set when using an external trigger mode or a periodic/interval timer mode. Trigger overruns cannot occur when the software initiated single-scan mode and the software initiated continuousscan mode are selected. 0 = No unexpected queue 2 trigger events have occurred 1 = At least one unexpected queue 2 trigger event has occurred
TOR2
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Table 13-16 QASR0 Bit Descriptions (Continued)
Bit(s) Name Description Queue status. This 4-bit read-only field indicates the current condition of queue 1 and queue 2. QS[0:1] are associated with queue 1, and QS[2:3] are associated with queue 2. Since the queue priority scheme interlinks the operation of queue 1 and queue 2, the status bits should be considered as one 4-bit field. Table 13-17 shows the bit encodings of the QS field. 10:15 CWP Command word pointer. CWP indicates which CCW is executing at present, or was last completed. The CWP is a read-only field; writes to it have no effect.
6:9
QS
Table 13-17 Queue Status

QS Description Queue 1 idle, queue 2 idle Queue 1 idle, queue 2 paused Queue 1 idle, queue 2 active Queue 1 idle, queue 2 trigger pending Queue 1 paused, queue 2 idle Queue 1 paused, queue 2 paused Queue 1 paused, queue 2 active Queue 1 paused, queue 2 trigger pending Queue 1 active, queue 2 idle Queue 1 active, queue 2 paused Queue 1 active, queue 2 suspended Queue 1 active, queue 2 trigger pending Reserved Reserved Reserved Reserved 0b0000 0b0001 0b0010 0b0011 0b0100 0b0101 0b0110 0b0111 0b1000 0b1001 0b1010 0b1011 0b1100 0b1101 0b1110 0b1111
13.12.10 QADC64 Status Register 1 (QASR1) The QASR1 contains two fields: command word pointers for queue 1 and queue 2. QASR1 Status Register1
MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13
0x30 4812 0x30 4C12

14 LSB 15
CWPQ1
RESERVED
CWPQ2
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Table 13-18 QASR0 Bit Descriptions
Bit(s) 0:1 Name Reserved Command word pointer for queue 1. This field is a software read-only field, and write operations have no effect. CWPQ1 allows software to read the last executed CCW in queue 1, regardless which queue is active. The CWPQ1 field is a CCW word pointer with a valid range of 0 to 63. In contrast to CWP, CPWQ1 is updated when the conversion result is written. When the QADC64 finishes a conversion in queue 1, both the result register is written and the CWPQ1 are updated. Finally, when queue 1 operation is terminated after a CCW is read that is defined as BQ2, CWP points to BQ2 while CWPQ1 points to the last CCW queue 1. During the stop mode, the CWPQ1 is reset to 63, since the control registers and the analog logic are reset. When the freeze mode is entered, the CWPQ1 is unchanged; it points to the last executed CCW in queue 1. Description
2:7
CWPQ1
8:9
Reserved Command word pointer for queue 2. This field is a software read-only field, and write operations have no effect. CWPQ2 allows software to read the last executed CCW in queue 2, regardless which queue is active. The CWPQ2 field is a CCW word pointer with a valid range of 0 to 63.
10:15
CWPQ2
In contrast to CWP, CPWQ2 is updated when the conversion result is written. When the QADC64 finishes a conversion in queue 2, both the result register is written and the CWPQ2 are updated. During the stop mode, the CWPQ2 is reset to 63, since the control registers and the analog logic are reset. When the freeze mode is entered, the CWP is unchanged; it points to the last executed CCW in queue 2.
13.12.11 Conversion Command Word Table The CCW table is a RAM, 64 words long and 10 bits wide, which can be programmed by the software to request conversions of one or more analog input channels. The entries in the CCW table are 10-bit conversion command words. The CCW table is written by software and is not modified by the QADC64. Each CCW requests the conversion of an analog channel to a digital result. The CCW specifies the analog channel number, the input sample time, and whether the queue is to pause after the current CCW. The ten implemented bits of the CCW word are read/write data. They may be written when the software initializes the QADC64. Unimplemented bits are read as zeros, and write operations have no effect. Each location in the CCW table corresponds to a location in the result word table. When a conversion is completed for a CCW entry, the 10-bit result is written in the corresponding result word entry. The QADC64 provides 64 CCW table entries. The beginning of queue 1 is always the first location in the CCW table. The first location of queue 2 is specified by the beginning of queue 2 pointer (BQ2) in QACR2. To dedicate the entire CCW table to queue 1, software must do the following: Program queue 2 to be in the disabled mode, and Program the beginning of BQ2 to 64. To dedicate the entire CCW table to queue 2, software must do the following: Program queue 1 to be in the disabled mode Program BQ2 to be the first location in the CCW table.
MPC555

MOTOROLA 13-43
USERS MANUAL

Figure 13-12 illustrates the operation of the queue structure.
CONVERSION COMMAND WORD (CCW) TABLE 00 BEGIN Queue 1 CHANNEL SELECT, SAMPLE, HOLD, AND A/D CONVERSION RESULT WORD TABLE
00
END OF Queue 1 BQ2 BEGIN Queue 2
63
END OF Queue 2
63
10-BIT CONVERSION COMMAND WORD FORMAT LSB 6 7 P BYP 8 IST 9 10 11 12 CHAN 13 14 MSB 15 MSB 0 1 0 2
10-BIT RESULT, READABLE IN THREE 16-BIT FORMATS 3 4 0 0 5 0 6 7 8 9 LSB 10 11 12 13 14 15 RESULT
0 0
RIGHT JUSTIFIED, UNSIGNED RESULT P = PAUSE AFTER CONVERSION UNTIL NEXT TRIGGER BYP = BYPASS BUFFER AMPLIFIER IST = INPUT SAMPLE TIME CHAN = CHANNEL NUMBER AND END-OF-QUEUE CODE MSB 0 1 2 3 4 5 6 7 8 9 LSB 10 11 12 13 14 15 0 0 0 0 0 0
RESULT
LEFT JUSTIFIED, UNSIGNED RESULT MSB 0 1 S 2 3 4 5 6 7 8 9 LSB 10 11 12 13 14 15 0 0 0 0 0 0
RESULT
LEFT JUSTIFIED, SIGNED RESULT S = SIGN BIT

QADC64 C
Figure 13-12 QADC64 Conversion Queue Operation To prepare the QADC64 for a scan sequence, the software writes to the CCW table to specify the desired channel conversions. The software also establishes the criteria for initiating the queue execution by programming the queue operating mode. The queue operating mode determines what type of trigger event causes queue execution to begin. Trigger event refers to any of the ways to cause the QADC64 to begin executing the CCWs in a queue or sub-queue. An external trigger is only one of the possible trigger events. A scan sequence may be initiated by the following: A software command
MPC555

MOTOROLA 13-44
USERS MANUAL

Expiration of the periodic/interval timer External trigger signal External gated signal (queue 1 only) The software also specifies whether the QADC64 is to perform a single pass through the queue or is to scan continuously. When a single-scan mode is selected, the software selects the queue operating mode and sets the single-scan enable bit. When a continuous-scan mode is selected, the queue remains active in the selected queue operating mode after the QADC64 completes each queue scan sequence. During queue execution, the QADC64 reads each CCW from the active queue and executes conversions in three stages: Initial sample Final sample Resolution During initial sample, a buffered version of the selected input channel is connected to the sample capacitor at the output of the sample buffer amplifier. During the final sample period, the sample buffer amplifier is bypassed, and the multiplexer input charges the sample capacitor directly. Each CCW specifies a final input sample time of 2, 4, 8, or 16 QCLK cycles. When an analog-to-digital conversion is complete, the result is written to the corresponding location in the result word table. The QADC64 continues to sequentially execute each CCW in the queue until the end of the queue is detected or a pause bit is found in a CCW. When the pause bit is set in the current CCW, the QADC64 stops execution of the queue until a new trigger event occurs. The pause status flag bit is set, which may cause an interrupt to notify the software that the queue has reached the pause state. After the trigger event occurs, the paused state ends and the QADC64 continues to execute each CCW in the queue until another pause is encountered or the end of the queue is detected. The following indicate the end-of-queue condition: The CCW channel field is programmed with 63 (0x3F) to specify the end of the queue The end of queue 1 is implied by the beginning of queue 2, which is specified in the BQ2 field in QACR2 The physical end of the queue RAM space defines the end of either queue When any of the end-of-queue conditions are recognized, a queue completion flag is set, and if enabled, an interrupt is issued to the software. The following situations prematurely terminate queue execution: Since queue 1 is higher in priority than queue 2, when a trigger event occurs on queue 1 during queue 2 execution, the execution of queue 2 is suspended by aborting the execution of the CCW in progress, and the queue 1 execution begins. When queue 1 execution is completed, queue 2 conversions restart with the first CCW entry in queue 2 or the first CCW of the queue 2 sub-queue being ex/ MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
MPC555
MOTOROLA 13-45
USERS MANUAL

ecuted when queue 2 was suspended. Alternately, conversions can restart with the aborted queue 2 CCW entry. The RESUME bit in QACR2 allows the software to select where queue 2 begins after suspension. By choosing to re-execute all of the suspended queue 2 queue and sub-queue CCWs, all of the samples are guaranteed to have been taken during the same scan pass. However, a high trigger event rate for queue 1 can prohibit the completion of queue 2. If this occurs, the software may choose to begin execution of queue 2 with the aborted CCW entry. Software can change the queue operating mode to disabled mode. Any conversion in progress for that queue is aborted. Putting a queue into the disabled mode does not power down the converter. Software can change the queue operating mode to another valid mode. Any conversion in progress for that queue is aborted. The queue restarts at the beginning of the queue, once an appropriate trigger event occurs. For low power operation, software can set the stop mode bit to prepare the module for a loss of clocks. The QADC64 aborts any conversion in progress when the stop mode is entered. When the freeze enable bit is set by software and the IMB internal FREEZE line is asserted, the QADC64 freezes at the end of the conversion in progress. When internal FREEZE is negated, the QADC64 resumes queue execution beginning with the next CCW entry. CCW Conversion Command Word Table
MSB 0 1 2 3 4 5 6 P 7 BYP 8 IST 9 10
0x30 4A00 0x30 4A7E 0x30 4E00 0x30 4E7E

11 12 13 14 LSB 15
RESERVED RESET: 0 0 0 0 0 0
CHAN
MPC555

MOTOROLA 13-46
USERS MANUAL

Table 13-19 CCW Bit Descriptions
Bit(s) 0:5 Name Reserved Pause. The pause bit allows the creation of sub-queues within queue 1 and queue 2. The QADC64 performs the conversion specified by the CCW with the pause bit set, and then the queue enters the pause state. Another trigger event causes execution to continue from the pause to the next CCW. 0 = Do not enter the pause state after execution of the current CCW. 1 = Enter the pause state after execution of the current CCW. Sample amplifier bypass. Setting BYP enables the amplifier bypass mode for a conversion, and subsequently changes the timing. Refer to 13.9.1.1 Amplifier Bypass Mode Conversion Timing for more information. 0 = Amplifier bypass mode disabled. 1 = Amplifier bypass mode enabled. Input sample time. The IST field specifies the length of the sample window. Longer sample times permit more accurate A/D conversions of signals with higher source impedances, especially if BYP = 1. 00 = QCKL period x 2 01 = QCKL period x 4 10 = QCKL period x 8 11 = QCKL period x 16 Channel number. The CHAN field selects the input channel number corresponding to the analog input pin to be sampled and converted. The analog input pin channel number assignments and the pin definitions vary depending on whether the QADC64 is operating in multiplexed or nonmultiplexed mode. The queue scan mechanism sees no distinction between an internally or externally multiplexed analog input. If CHAN specifies a reserved channel number (channels 32 to 47) or an invalid channel number (channels 4 to 31 in non-multiplexed mode), the low reference level (VRL) is converted. Programming the channel field to channel 63 indicates the end of the queue. Channels 60 to 62 are special internal channels. When one of these channels is selected, the sample amplifier is not used. The value of VRL, VRH, or (VRH VRL)/2 is placed directly into the converter. Programming the input sample time to any value other than two for one of the internal channels has no benefit except to lengthen the overall conversion time. Table 13-20 shows the channel number assignments for the non-multiplexed mode. Table 1321 shows the channel number assignments for the multiplexed mode. Description
BYP
8:9
IST
10:15
CHAN
MPC555

MOTOROLA 13-47
USERS MANUAL

Table 13-20 Non-Multiplexed Channel Assignments and Pin Designations
Non-multiplexed Input Pins Port Pin Name PQB0 PQB1 PQB2 PQB3 PQB4 PQB5 PQB6 PQB7 PQA0 PQA1 PQA2 PQA3 PQA4 PQA5 PQA6 PQA7 Analog Pin Name AN0 AN1 AN2 AN3 AN48 AN49 AN50 AN51 AN52 AN53 AN54 AN55 AN56 AN57 AN58 AN59 VRL VRH Other Functions Invalid Reserved (VRH VRL)/2 End of Queue Code Pin Type (I/O) I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I I Channel Number in CHAN Binary 000000 000001 000010 000011 000100 to 011111 10XXXX 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Decimal 0 1 2 3 4 to 31 32 to 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Table 13-21 Multiplexed Channel Assignments and Pin Designations

Multiplexed Input Pins Port Pin Name PQB0 PQB1 PQB2 PQB3 PQB4 PQB5 PQB6 PQB7 PQA0 PQA1 PQA2 PQA3 PQA4 PQA5 PQA6 PQA7 Analog Pin Name ANw ANx ANy ANz AN48 AN49 AN50 AN51 AN55 AN56 AN57 AN58 AN59 VRL VRH Other Functions Reserved MA0 MA1 MA2 (VRH -VRL)/2 End of Queue Code Pin Type (I/O) I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I I Channel Number in CHAN Binary 00xxx0 00xxx1 01xxx0 01xxx1 10xxxx 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Decimal 0 to 14 even 1 to 15 odd 16 to 30 even 17 to 31 odd 32 to 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
MPC555

MOTOROLA 13-48
USERS MANUAL

13.12.12 Result Word Table The result word table is a 64-word long, 10-bit wide RAM. The QADC64 writes a result word after completing an analog conversion specified by the corresponding CCW. The result word table can be read or written, but in normal operation, software reads the result word table to obtain analog conversions from the QADC64. Unimplemented bits are read as zeros, and write operations have no effect. While there is only one result word table, the data can be accessed in three different alignment formats: Right-justified, with zeros in the higher order unused bits. Left-justified, with the most significant bit inverted to form a sign bit, and zeros in the unused lower order bits. Left-justified, with zeros in the unused lower order bits. The left-justified, signed format corresponds to a half-scale, offset binary, twos complement data format. The data is routed onto the IMB according to the selected format. The address used to access the table determines the data alignment format. All write operations to the result word table are right-justified. RJURR Right-Justified, Unsigned Result Register
MSB 0 1 2 3 4 5 6 7 8 9 10
0x30 4A80 0x30 4AFE 0x30 4E80 0x30 4EFE

11 12 13 14 LSB 15
RESERVED RESET: 0 0 0 0 0 0
RESULT
The conversion result is unsigned, right-justified data. Unused bits return zero when read. LJSRR Left-Justified, Signed Result Register
MSB 0 S1 RESET: 0 0 0 0 0 0 1 2 3 4 5 RESULT 6 7 8 9 10
0x30 4B00 0x30 4B7E 0x30 4F00 0x30 4F7E

11 12 13 14 LSB 15
RESERVED
NOTES: 1. S = Sign bit.
The conversion result is signed, left-justified data. Unused bits return zero when read.
MPC555

MOTOROLA 13-49
USERS MANUAL

LJURR Left-Justified, Unsigned Result Register
MSB 0 1 2 3 4 5 6 7 8 9 10
0x30 4B80 0x30 4BFE 0x30 4F80 0x30 4FFE

11 12 13 14 LSB 15
RESULT RESET: 0 0
RESERVED
The conversion result is unsigned, left-justified data. Unused bits return zero when read.
MPC555

MOTOROLA 13-50
USERS MANUAL
SECTION 14 QUEUED SERIAL MULTI-CHANNEL MODULE

14.1 Overview The queued serial multi-channel module (QSMCM) provides three serial communication interfaces: the queued serial peripheral interface (QSPI) and two serial communications interfaces (SCI1 and SCI2). These submodules communicate with the CPU via a common slave bus interface unit (SBIU).
The QSPI is a full-duplex, synchronous serial interface for communicating with peripherals and other MCUs. It is enhanced from the original SPI in the QSMCM (queued serial module) to include a total of 160 bytes of queue RAM to accommodate more receive, transmit, and control information. The QSPI is fully compatible with the SPI systems found on other Motorola devices. The dual, independent SCIs are used to communicate with external devices and other MCUs via an asynchronous serial bus. Each SCI is a full-duplex universal asynchronous receiver transmitter (UART) serial interface. The original QSMCM SCI is enhanced by the addition of an SCI and a common external baud clock source. The SCI1 has the ability to use the resultant baud clock from SCI2 as the input clock source for the SCI1 baud rate generator. Also, the SCI1 has an additional mode of operation that allows queuing of transmit and receive data frames. If the queue feature is enabled, a set of 16 entry queues is allocated for the receive and/or transmit operation. 14.2 Block Diagram Figure 14-1 depicts the major components of the QSMCM.
QUEUED SERIAL MULTI-CHANNEL MODULE
MOTOROLA 14-1
IMB3* SBIU
MISO/QGPIO4 MOSI/QGPIO5 SCK/QGPIO6 PCS[0]/SS/QGPIO0
Port QS
QSPI QSPI QUEUE RAM
PCS1/QGPIO1 PCS2/QGPIO2 PCS3/QGPIO3
DSCI
2 SCI1 Receive and Transmit Queue 2 SCI2
TXD1/QGPO1 RXD1/QGPI1 TXD2/QGPO2 RXD2/QGPI2
ECK
*Note: SBIU Bus and interface to IMB3 are each 16 bits wide.
Figure 14-1 QSMCM Block Diagram 14.3 Signal Descriptions The QSMCM has 12 external pins, as shown in Figure 14-1. Seven of the pins, if not in use for their submodule function, can be used as general-purpose I/O port pins. The RXDx and TXDx pins can alternately serve as general-purpose input-only and outputonly signals, respectively. ECK is a dedicated clock pin. For detailed descriptions of QSMCM signals, refer to 14.6 QSMCM Pin Control Registers, 14.7.3 QSPI Pins, and 14.8.6 SCI Pins. 14.4 Memory Map The QSMCM memory map, shown in Table 14-1, includes the global registers, the QSPI and dual SCI control and status registers, and the QSPI RAM. The QSMCM memory map can be divided into supervisor-only data space and assignable data space. The address offsets shown are from the base address of the QSMCM module. Refer to 1.3 MPC555 / MPC556 Address Map for a diagram of the MPC555 / MPC556 internal memory map.
MPC555
/ MPC556
MOTOROLA 14-2
USERS MANUAL

Table 14-1 QSMCM Register Map
Access1 S T S S S/U S/U Address 0x30 5000 0x30 5002 0x30 5004 0x30 5006 0x30 5008 0x30 500A 0x30 500C 0x30 500E 0x30 5010 0x30 5012 0x30 5014 0x30 5016 0x30 5018 0x30 501A 0x30 501C 0x30 501E 0x30 5020 0x30 5022 0x30 5024 0x30 5026 0x30 5028 0x30 502A Reserved MSB2 0 QSMCM Module Configuration Register (QSMCMMCR) See Table 14-4 for bit descriptions. QSMCM Test Register (QTEST) Dual SCI Interrupt Level (QDSCI_IL) See Table 14-5 for bit descriptions. Reserved Reserved Queued SPI Interrupt Level (QSPI_IL) See Table 14-6 for bit descriptions. SCI1Control Register 0 (SCC1R0) See Table 14-23 for bit descriptions. SCI1Control Register 1 (SCC1R1) See Table 14-24 for bit descriptions. SCI1 Status Register (SC1SR) See Table 14-25 for bit descriptions. SCI1 Data Register (SC1DR) See Table 14-26 for bit descriptions. Reserved Reserved QSMCM Port Q Data Register (PORTQS) See 14.6.1 Port QS Data Register (PORTQS) for bit descriptions. QSMCM Data Direction Register (DDRQS) See Table 14-11 for bit descriptions. LSB 15
S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U
QSMCM Pin Assignment Register (PQSPAR) See Table 14-10 for bit descriptions.
QSPI Control Register 0 (SPCR0) See Table 14-13 for bit descriptions. QSPI Control Register 1 (SPCR1) See Table 14-15 for bit descriptions. QSPI Control Register 2 (SPCR2) See Table 14-16 for bit descriptions. QSPI Control Register 3 (SPCR3) See Table 14-17 for bit descriptions. QSPI Status Register (SPSR) See Table 14-18 for bit descriptions.
SCI2 Control Register 0 (SCC2R0) SCI2 Control Register 1 (SCC2R1) SCI2 Status Register (SC2SR) SCI2 Data Register (SC2DR) QSCI1 Control Register (QSCI1CR) See Table 14-30 for bit descriptions. QSCI1 Status Register (QSCI1SR) See Table 14-31 for bit descriptions.
MPC555
/ MPC556
MOTOROLA 14-3
USERS MANUAL

Table 14-1 QSMCM Register Map (Continued)
Access1 S/U S/U S/U S/U S/U Address 0x30 502C 0x30 504A 0x30 504C 0x30 506A 0x30 506C 0x30 513F3 0x30 5140 0x30 517F 0x30 5180 0x30 51BF 0x30 51C0 0x30 51DF MSB2 0 Transmit Queue Locations (SCTQ) Receive Queue Locations (SCRQ) Reserved Receive Data RAM (REC.RAM) Transmit Data RAM (TRAN.RAM) Command RAM (COMD.RAM) LSB 15
S/U
NOTES: 1. S = Supervisor access only S/U = Supervisor access only or unrestricted user access (assignable data space). 2. 8-bit registers, such as SPCR3 and SPSR, are on 8-bit boundaries. 16-bit registers such as SPCR0 are on 16-bit boundaries. 3. Note that QRAM offsets have been changed from the original (modular family) QSMCM.
The supervisor-only data space segment contains the QSMCM global registers. These registers define parameters needed by the QSMCM to integrate with the MCU. Access to these registers is permitted only when the CPU is operating in supervisor mode. Assignable data space can be either restricted to supervisor-only access or unrestricted to both supervisor and user accesses. The supervisor (SUPV) bit in the QSMCM module configuration register (QSMCMMCR) designates the assignable data space as either supervisor or unrestricted. If SUPV is set, then the space is designated as supervisor-only space. Access is then permitted only when the CPU is operating in supervisor mode. If SUPV is clear, both user and supervisor accesses are permitted. To clear SUPV, the CPU must be in supervisor mode. The QSMCM assignable data space segment contains the control and status registers for the QSPI and SCI submodules, as well as the QSPI RAM. All registers and RAM can be accessed on byte (8-bits), half-word (16-bits), and word (32-bit) boundaries. Word accesses require two consecutive IMB3 bus cycles. 14.5 QSMCM Global Registers The QSMCM global registers contain system parameters used by the QSPI and SCI submodules for interfacing to the CPU and the intermodule bus. The global registers are listed in Table 14-2 QSMCM Global Registers
MPC555
/ MPC556
MOTOROLA 14-4
USERS MANUAL

Table 14-2 QSMCM Global Registers
Access1 S T S S Address 0x30 5000 0x30 5002 0x30 5004 0x30 5006 MSB2 QSMCM Module Configuration Register (QSMCMMCR) See Table 14-4 for bit descriptions. QSMCM Test Register (QTEST) Dual SCI Interrupt Level (QDSCI_IL) See Table 14-5 for bit descriptions. Reserved Reserved Queued SPI Interrupt Level (QSPI_IL) See Table 14-6 for bit descriptions. LSB
NOTES: 1. S = Supervisor access only S/U = Supervisor access only or unrestricted user access (assignable data space). 2. 8-bit registers reside on 8-bit boundaries. 16-bit registers reside on 16-bit boundaries.
14.5.1 Low-Power Stop Operation When the STOP bit in QSMCMMCR is set, the IMB clock input to the QSMCM is disabled and the module enters a low-power operating state. QSMCMMCR is the only register guaranteed to be readable while STOP is asserted. The QSPI RAM is not readable in low-power stop mode. However, writes to RAM or any register are guaranteed valid while STOP is asserted. STOP can be written by the CPU and is cleared by reset. System software must bring each submodule to an orderly stop before setting STOP to avoid data corruption. The SCI receiver and transmitter should be disabled after transfers in progress are complete. The QSPI can be halted by setting the HALT bit in SPCR3 and then setting STOP after the HALTA flag is set. 14.5.2 Freeze Operation The FRZ1 bit in QSMCMMCR determines how the QSMCM responds when the IMB3 FREEZE signal is asserted. FREEZE is asserted when the CPU enters background debug mode. Setting FRZ1 causes the QSPI to halt on the first transfer boundary following FREEZE assertion. FREEZE causes the SCI1 transmit queue to halt on the first transfer boundary following FREEZE assertion. 14.5.3 Access Protection The SUPV bit in the QMCR defines the assignable QSMCM registers as either supervisor-only data space or unrestricted data space. When the SUPV bit is set, all registers in the QSMCM are placed in supervisor-only space. For any access from within user mode, the IMB3 address acknowledge (AACK) signal is asserted and a bus error is generated. Because the QSMCM contains a mix of supervisor and user registers, AACK is asserted for either supervisor or user mode accesses, and the bus cycle remains internal. If a supervisor-only register is accessed in user mode, the module responds as if an access had been made to an unauthorized register location, and a bus error is generated.
MPC555
/ MPC556
MOTOROLA 14-5
USERS MANUAL

14.5.4 QSMCM Interrupts The interrupt structure of the IMB3 supports a total of 32 interrupt levels that are time multiplexed on the IRQB[0:7] lines as seen in Figure 14-2.
IMB3 CLOCK
ILBS[1:0]
00
01
10
11
00
01
10
11
IMB3 IRQ[7:0]
IRQ 7:0
IRQ 15:8
IRQ 23:16
IRQ 31:24
IRQ 7:0
Figure 14-2 QSMCM Interrupt Levels In this structure, all interrupt sources place their asserted level on a time multiplexed bus during four different time slots, with eight levels communicated per slot. The ILBS[0:1] signals indicate which group of eight are being driven on the interrupt request lines. Table 14-3 Interrupt Levels
ILBS[0:1] 00 01 10 11 Levels 0:7 8:15 16:23 24:31
The QSMCM module is capable of generating one of the 32 possible interrupt levels on the IMB3. The levels that the interrupt will drive can be programmed into the interrupt request level (ILDSCI and ILQSPI) bits located in the interrupt configuration register (QDSCI_IL and QSPI_IL). This value determines which interrupt signal (IRQB[0:7]) is driven onto the bus during the programmed time slot. Figure 14-3 shows a block diagram of the interrupt hardware.
MPC555
/ MPC556
MOTOROLA 14-6
USERS MANUAL
2 ILBS[1:0] SCI1 and 2 Int Lev Reg. [4:0] QSPI[4:0] Int Lev Reg. [4:0] 5 5
SCI_1 Interrupt SCI_2 Interrupt QSPI Interrupt
Interrupt Level Encoder
Interrupt Level Decoder 8
IRQ[7:0]
Figure 14-3 QSPI Interrupt Generation 14.5.5 QSMCM Configuration Register (QSMCMMCR) The QSMCMMCR contains parameters for interfacing to the CPU and the intermodule bus. This register can be modified only when the CPU is in supervisor mode. QSMCMMCR QSMCM Configuration Register
MSB 0 STOP RESET: 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 FRZ1 2 3 4 5 6 7 8 SUPV 9 10 RESERVED 11 12 13 IARB
0x30 5000
14 LSB 15
RESERVED
MPC555
/ MPC556
MOTOROLA 14-7
USERS MANUAL

Table 14-4 QSMCMMCR Bit Descriptions
Bit(s) 0 Name STOP Description Stop enable. Refer to 14.5.1 Low-Power Stop Operation. 0 = Normal clock operation 1 = Internal clocks stopped Freeze1 bit. Refer to 14.5.2 Freeze Operation. 0 = Ignore the FREEZE signal 1 = Halt the QSMCM (on transfer boundary) Reserved Supervisor /Unrestricted. Refer to 14.5.3 Access Protection. 0 = Assigned registers are unrestricted (user access allowed) 1 = Assigned registers are restricted (only supervisor access allowed) Reserved This field currently has no effect. It is implemented for future interrupt arbitration schemes.
1 2:7 8 9:11
FRZ1 SUPV IARB
12:15
14.5.6 QSMCM Test Register (QTEST) The QTEST register is used for factory testing of the MCU. 14.5.7 QSMCM Interrupt Level Registers (QDSCI_IL, QSPI_IL) The QDSCI_ILI and QSPI_IL registers determine the interrupt level requested by the QSMCM. The two SCI submodules (DSCI) share a 5-bit interrupt level field, ILDSCI. The QSPI uses a separate field, ILQSPI. The level value is used to determine which interrupt is serviced first when two or more modules or external peripherals simultaneously request an interrupt. The user can select among 32 levels. This register can be accessed only when the CPU is in supervisor mode. QDSCI_IL QSM2 Dual SCI Interrupt Level Register
MSB 0 1 Reserved RESET: 0 0 0 0 0 0 0 0 2 3 4 5 ILDSCI 6 7 8 9 10 11 12 13
0x30 5004
14 LSB 15
RESERVED
Table 14-5 QDSCI_IL Bit Descriptions

Bit(s) 0:2 3:7 8:15 Name ILDSCI Reserved Interrupt level of SCIs 00000 = lowest interrupt level request (level 0) 11111 = highest interrupt level request (level 31) Reserved Description
MPC555
/ MPC556
MOTOROLA 14-8
USERS MANUAL

QSPI_IL QSPI Interrupt Level Register
MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13
0x30 5006
14 LSB 15
RESERVED RESET: 0 0 0 0 0 0 0 0
ILQSPI
Table 14-6 QSPI_IL Bit Descriptions

Bit(s) 0:10 11:15 Name ILQSPI Reserved Interrupt level of SPI 00000 = lowest interrupt level request (level 0) 11111 = highest interrupt level request (level 31) Description
14.6 QSMCM Pin Control Registers Table 14-7 lists the three QSMCM pin control registers. Table 14-7 QSMCM Pin Control Registers
Address 0x30 5014 Register QSMCM Port Data Register (PORTQS) See 14.6.1 Port QS Data Register (PORTQS) for bit descriptions. PORTQS Pin Assignment Register (PQSPAR) See Table 14-11 for bit descriptions. PORTQS Data Direction Register (DDRQS) See Table 14-11 for bit descriptions.
0x30 5016 0x30 5017
The QSMCM uses 12 pins. Eleven of the pins, when not being used by the serial subsystems, form a parallel port on the MCU. (The ECK pin is a dedicated external clock source.) The port QS pin assignment register (PQSPAR) governs the usage of QSPI pins. Clearing a bit assigns the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the QSPI. PQSPAR does not affect operation of the SCI. When the SCIx transmitter is disabled, TXDx is a discrete output; when the SCIx receiver is disabled, RXDx is a discrete input. When the SCIx transmitter or receiver is enabled, the associated TXDx or RXDx pin is assigned its SCI function. The port QS data direction register (DDRQS) determines whether QSPI pins are inputs or outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the pin an output. DDRQS affects both QSPI function and I/O function. Table 14-10 summarizes the effect of DDRQS bits on QSPI pin function.
MPC555
/ MPC556
MOTOROLA 14-9
USERS MANUAL

DDRQS does not affect SCI pin function. TXDx pins are always outputs, and RXDx pins are always inputs, regardless of whether they are functioning as SCI pins or as PORTQS pins. The port QS data register (PORTQS) latches I/O data. PORTQS writes drive pins defined as outputs. PORTQS reads return data present on the pins. To avoid driving undefined data, write the first data to PORTQS before configuring DDRQS. Table 14-8 Effect of DDRQS on QSPI Pin Function
QSMCM Pin Mode Master MISO DDQS0 Slave Master MOSI Slave SCK1 Master Slave Master PCS[0]/SS Slave Master PCS[1:3] Slave DDQS[4:6] DDQS3 DDQS2 DDQS1 DDRQS Bit Bit State 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Pin Function Serial data input to QSPI Disables data input Disables data output Serial data output from QSPI Disables data output Serial data output from QSPI Serial data input to QSPI Disables data input Clock output from QSPI Clock input to QSPI Assertion causes mode fault Chip-select output QSPI slave select input Disables slave select input Disables chip-select output Chip-select output Inactive Inactive
NOTES: 1. SCK/QGPIO6 is a digital I/O pin unless the SPI is enabled (SPE set in SPCR1), in which case it becomes the QSPI serial clock SCK.
14.6.1 Port QS Data Register (PORTQS) PORTQS determines the actual input or output value of a QSMCM port pin if the pin is defined as general-purpose input or output. All QSMCM pins except the ECK pin can be used as general-purpose input and/or output. When the SCIx transmitter is disabled, TXDx is a discrete output; when the SCIx receiver is disabled, RXDx is a discrete input. Writes to this register affect the pins defined as outputs; reads of this register return the actual value of the pins.
MPC555
/ MPC556
MOTOROLA 14-10
USERS MANUAL

PORTQS Port QS Data Register
MSB 0 1 2 3 4 5 6 7 8 0 9 10 11 12
0x30 5014
13 QDSCK 14 LSB 15
QDRX QDTX QDRX QDTX D2 D2 D1 D1
QDPC QDPC QDPC QDPC S3 S2 S1 S0
QD- QDMIMOSI SO
14.6.2 PORTQS Pin Assignment Register (PQSPAR) PQSPAR determines which of the QSPI pins, with the exception of the SCK pin, are used by the QSPI submodule, and which pins are available for general-purpose I/O. Pins may be assigned on a pin-by-pin basis. If the QSPI is disabled, the SCK pin is automatically assigned its general-purpose I/O function (QGPIO6). QSPI pins designated by PQSPAR as general-purpose I/O pins are controlled only by PQSDDR and PQSPDR; the QSPI has no effect on these pins. PQSPAR does not affect the operation of the SCI submodule. Table 14-9 summarizes the QSMCM pin functions. Table 14-9 QSMCM Pin Functions
PORTQS Function QGPI2 QGPO2 QGPI1 QGPO1 QGPIO6 QGPIO5 QGPIO4 QGPIO3 QGPIO2 QGPIO1 QGPIO0 QSMCM Function RXD2 TXD2 RXD1 TXD1 SCK MOSI MISO PCS[3] PCS[2] PCS[1] PCS[0]
PQSPAR PORTQS Pin Assignment Register

MSB 0 0 RESET: 0 0 0 0 0 0 0 0 1 2 3 4 5 0 6 7 8 9 10 11 12
0x30 5016
13 14 LSB 15
QPAP QPAP QPAP QPAP CS3 CS2 CS1 CS0
QPA- QPAM MOSI ISO
DDRQS*
*See bit descriptions in Table 14-11.
MPC555
/ MPC556
MOTOROLA 14-11
USERS MANUAL

Table 14-10 PQSPAR Bit Descriptions
Bit(s) 0 1 2 3 4 5 6 Name QPAPCS3 QPAPCS2 QPAPCS1 QPAPCS0 QPAMOSI QPAMISO DDRQS Reserved 0 = Pin is assigned QGPIO3 1 = Pin is assigned PCS3 function 0 = Pin is assigned QGPIO2 1 = Pin is assigned PCS2 function 0 = Pin is assigned QGPIO1 1 = Pin is assigned PCS1 function 0 = Pin is assigned QGPIO0 1 = Pin is assigned PCS[0] function Reserved 0 = Pin is assigned QGPIO5 1 = Pin is assigned MOSI function 0 = Pin is assigned QGPIO4 1 = Pin is assigned MISO function PORSTQS data direction register. See 14.6.3 PORTQS Data Direction Register (DDRQS). Description
7 8:15
14.6.3 PORTQS Data Direction Register (DDRQS) DDRQS assigns QSPI pin as an input or an output regardless of whether the QSPI submodule is enabled or disabled. All QSPI pins are configured during reset as general-purpose inputs. This register does not affect SCI operation. The TXD1 and TXD2 remain output pins dedicated to the SCI submodules, and the RXD1, RXD2 and ECK pins remain input pins dedicated to the SCI submodules. DDRQS PORTQS Data Direction Register
MSB 0 1 2 3 4 5 6 7 8 0 9 QDDPCS3 10 QDDPCS2 11 QDDPCS1 12 QDDPCS0 13 QDDSCK
0x30 5016
14 QDDMOSI LSB 15 QDDMISO
PQSPAR* RESET:
MPC555
/ MPC556
MOTOROLA 14-12
USERS MANUAL

Table 14-11 DDRQS Bit Descriptions
Bit(s) 0:7 8 9 Name PQSPAR QDDPCS3 Description PORTSQS pin assignment register. See 14.6.2 PORTQS Pin Assignment Register (PQSPAR). Reserved QSPI pin data direction for the pin PCS3 0 = Pin direction is input 1 = Pin direction is output QSPI pin data direction for the pin PCS2 0 = Pin direction is input 1 = Pin direction is output QSPI pin data direction for the pin PCS1 0 = Pin direction is input 1 = Pin direction is output QSPI pin data direction for the pin PCS[0] 0 = Pin direction is input 1 = Pin direction is output QSPI pin data direction for the pin SCK 0 = Pin direction is input 1 = Pin direction is output QSPI pin data direction for the pin MOSI 0 = Pin direction is input 1 = Pin direction is output QSPI pin data direction for the pin MISO 0 = Pin direction is input 1 = Pin direction is output
10
QDDPCS2
11
QDDPCS1
12
QDDPCS0
13
QDDSCK
14
QPDMOSI
15
QPDMISO
14.7 Queued Serial Peripheral Interface The queued serial peripheral interface (QSPI) is used to communicate with external devices through a synchronous serial bus. The QSPI is fully compatible with SPI systems found on other Motorola products, but has enhanced capabilities. The QSPI can perform full duplex three-wire or half duplex two-wire transfers. Several transfer rates, clocking, and interrupt-driven communication options are available. Figure 14-4 is a block diagram of the QSPI.
MPC555
/ MPC556
MOTOROLA 14-13
USERS MANUAL
QUEUE CONTROL BLOCK QUEUE POINTER 4
COMPARATOR
DONE
4 END QUEUE POINTER
A D D R E S S R E G I S T E R
160-BYTE QSPI RAM
CONTROL LOGIC STATUS REGISTER
CONTROL REGISTERS 4 DELAY COUNTER 4 CHIP SELECT COMMAND
MSB
PROGRAMMABLE LOGIC ARRAY
LSB
M S
8/16-BIT SHIFT REGISTER Rx/Tx DATA REGISTER
MOSI
M S
MISO PCS[0]/SS
2 PCS[2:1] BAUD RATE GENERATOR SCK
QSPI BLOCK
Figure 14-4 QSPI Block Diagram Serial transfers of eight to 16 bits can be specified. Programmable transfer length simplifies interfacing to devices that require different data lengths. An inter-transfer delay of approximately 0.8 to 204 s (using a 40-MHz IMB clock) can be programmed. The default delay is 17 clocks (0.425 s at 40 MHz). Programmable delay simplifies the interface to devices that require different delays between transfers.
MPC555
/ MPC556
MOTOROLA 14-14
USERS MANUAL

A dedicated 160-byte RAM is used to store received data, data to be transmitted, and a queue of commands. The CPU can access these locations directly. This allows serial peripherals to be treated like memory-mapped parallel devices. The command queue allows the QSPI to perform up to 32 serial transfers without CPU intervention. Each queue entry contains all the information needed by the QSPI to independently complete one serial transfer. A pointer identifies the queue location containing the data and command for the next serial transfer. Normally, the pointer address is incremented after each serial transfer, but the CPU can change the pointer value at any time. Support for multiple-tasks can be provided by segmenting the queue. The QSPI has four peripheral chip-select pins. The chip-select signals simplify interfacing by reducing CPU intervention. If the chip-select signals are externally decoded, 16 independent select signals can be generated. Wrap-around mode allows continuous execution of queued commands. In wraparound mode, newly received data replaces previously received data in the receive RAM. Wrap-around mode can simplify the interface with A/D converters by continuously updating conversion values stored in the RAM. Continuous transfer mode allows transfer of an uninterrupted bit stream. From 8 to 512 bits can be transferred without CPU intervention. Longer transfers are possible, but minimal intervention is required to prevent loss of data. A standard delay of 17 IMB clocks (0.8 s with a 40-MHz IMB clock) is inserted between the transfer of each queue entry. 14.7.1 QSPI Registers The QSPI memory map, shown in Table 14-12, includes the QSMCM global and pin control registers, four QSPI control registers (SPCR[0:3]), the status register (SPSR), and the QSPI RAM. Registers and RAM can be read and written by the CPU. The memory map can be divided into supervisor-only data space and assignable data space. The address offsets shown are from the base address of the QSMCM module. Refer to 1.3 MPC555 / MPC556 Address Map for a diagram of the MPC555 / MPC556 internal memory map.
MPC555
/ MPC556
MOTOROLA 14-15
USERS MANUAL

Table 14-12 QSPI Register Map
Access1 S/U S/U S/U S/U S/U S/U Address 0x30 5018 0x30 501A 0x30 501C 0x30 501E/ 0x30 501F 0x30 5140 0x30 517F 0x30 5180 0x30 51BF 0x30 51C0 0x30 51DF MSB2 QSPI Control Register 0 (SPCR0) See Table 14-13 for bit descriptions. QSPI Control Register 1 (SPCR1) See Table 14-15 for bit descriptions. QSPI Control Register 2 (SPCR2) See Table 14-16 for bit descriptions. QSPI Control Register 3 (SPCR3) See Table 14-17 for bit descriptions. QSPI Status Register (SPSR) See Table 14-18 for bit descriptions. LSB
Receive Data RAM (32 half-words) Transmit Data RAM (32 half-words) Command RAM (32 bytes)
S/U
NOTES: 1. S = Supervisor access only S/U = Supervisor access only or unrestricted user access (assignable data space). 2. 8-bit registers, such as SPCR3 and SPSR, are on 8-bit boundaries. 16-bit registers such as SPCR0 are on 16-bit boundaries.
To ensure proper operation, set the QSPI enable bit (SPE) in SPCR1 only after initializing the other control registers. Setting this bit starts the QSPI. Rewriting the same value to a control register does not affect QSPI operation with the exception of writing NEWQP in SPCR2. Rewriting the same value to these bits causes the RAM queue pointer to restart execution at the designated location. Before changing control bits, the user should halt the QSPI. Writing a different value into a control register other than SPCR2 while the QSPI is enabled may disrupt operation. SPCR2 is buffered, preventing any disruption of the current serial transfer. After the current serial transfer is completed, the new SPCR2 value becomes effective. 14.7.1.1 QSPI Control Register 0 SPCR0 contains parameters for configuring the QSPI before it is enabled. The CPU has read/write access to SPCR0, but the QSPI has read access only. SPCR0 must be initialized before QSPI operation begins. Writing a new value to SPCR0 while the QSPI is enabled disrupts operation. SPCR0 QSPI Control Register 0
MSB 0 MSTR RESET: 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 WOM Q 2 3 BITS 4 5 6 7 8 9 10 11 12 13
0x30 5018
14 LSB 15
CPOL CPHA
SPBR
MPC555
/ MPC556
MOTOROLA 14-16
USERS MANUAL

Table 14-13 SPCR0 Bit Descriptions
Bit(s) 0 Name MSTR Description Master/slave mode select 0 = QSPI is a slave device and only responds to externally generated serial transfers. 1 = QSPI is the system master and can initiate transmission to external SPI devices. Wired-OR mode for QSPI pins. This bit controls the QSPI pins regardless of whether they are used as general-purpose outputs or as QSPI outputs, and regardless of whether the QSPI is enabled or disabled. 0 = Pins designated for output by DDRQS operate in normal mode. 1 = Pins designated for output by DDRQS operate in open drain mode. Bits per transfer. In master mode, when BITSE is set in a command RAM byte, BITS determines the number of data bits transferred. When BITSE is cleared, eight bits are transferred regardless of the value in BITS. In slave mode, the BITS field always determines the number of bits the QSPI will receive during each transfer before storing the received data. Data transfers from 8 to 16 bits are supported. Illegal (reserved) values default to eight bits.Table 14-14 shows the number of bits per transfer. Clock polarity. CPOL is used to determine the inactive state of the serial clock (SCK). It is used with CPHA to produce a desired clock/data relationship between master and slave devices. 0 = The inactive state of SCK is logic zero. 1 = The inactive state of SCK is logic one. Clock phase. CPHA determines which edge of SCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce a desired clock/data relationship between master and slave devices. 0 = Data is captured on the leading edge of SCK and changed on the trailing edge of SCK. 1 = Data is changed on the leading edge of SCK and captured on the trailing edge of SCK Serial clock baud rate. The QSPI uses a modulus counter to derive the SCK baud rate from the MCU IMB clock. Baud rate is selected by writing a value from 2 to 255 into SPBR. The following equation determines the SCK baud rate: 8:15 SPBR SCK Baud Rate = 2 x SPBR Refer to 14.7.5.2 Baud Rate Selection for more information. fSYS
WOMQ
2:5
BITS
CPOL
CPHA
Table 14-14 Bits Per Transfer

BITS[3:0] 0000 0001 to 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits per Transfer 16 Reserved (defaults to 8) 8 9 10 11 12 13 14 15
MPC555
/ MPC556
MOTOROLA 14-17
USERS MANUAL

14.7.1.2 QSPI Control Register 1 SPCR1 enables the QSPI and specifies transfer delays. The CPU has read/write access to SPCR1, but the QSPI has read access only to all bits except SPE. SPCR1 must be written last during initialization because it contains SPE. The QSPI automatically clears this bit after it completes all serial transfers or when a mode fault occurs. Writing a new value to SPCR1 while the QSPI is enabled disrupts operation. SPCR1 QSPI Control Register 1
MSB 0 SPE RESET: 1 2 3 4 DSCKL 5 6 7 8 9 10 11 DTL 12 13
0x30 501A
14 LSB 15

Bit(s) 0 Name SPE Description QSPI enable. Refer to 14.7.4.1 Enabling, Disabling, and Halting the SPI. 0 = QSPI is disabled. QSPI pins can be used for general-purpose I/O. 1 = QSPI is enabled. Pins allocated by PQSPAR are controlled by the QSPI. Delay before SCK. When the DSCK bit is set in a command RAM byte, this field determines the length of the delay from PCS valid to SCK transition. The following equation determines the actual delay before SCK: 1:7 DSCKL DSCKL PCS to SCK Delay = ------------------fSYS where DSCKL equals is in the range of 1 to 127. Refer to 14.7.5.3 Delay Before Transfer for more information. Length of delay after transfer. When the DT bit is set in a command RAM byte, this field determines the length of the delay after a serial transfer. The following equation is used to calculate the delay:
8:15
DTL
32 D TL Delay after Transfer = ----------------------f SYS
where DTL is in the range of 1 to 255. A zero value for DTL causes a delay-after-transfer value of 8192 FSYS (204.8 s with a 40-MHz IMB clock). Refer to 14.7.5.4 Delay After Transfer for more information.
14.7.1.3 QSPI Control Register 2 SPCR2 contains QSPI queue pointers, wraparound mode control bits, and an interrupt enable bit. The CPU has read/write access to SPCR2, but the QSPI has read access only. Writes to this register are buffered. New SPCR2 values become effective only after completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execution to restart at the designated location. Reads of SPCR2 return the current value of the register, not the buffer.
MPC555
/ MPC556
MOTOROLA 14-18
USERS MANUAL

SPCR2 QSPI Control Register 2
MSB 0 1 2 3 4 5 ENDQP 6 7 8 9 Reserved 10 11 12 13 NEWQP
0x30 501C
14 LSB 15
SPIFIE WREN WRTO RESET: 0 0 0 0 0

Bit(s) 0 Name SPIFIE Description SPI finished interrupt enable. Refer to 14.7.4.2 QSPI Interrupts. 0 = QSPI interrupts disabled 1 = QSPI interrupts enabled Wrap enable. Refer to 14.7.5.7 Master Wraparound Mode. 0 = Wraparound mode disabled. 1 = Wraparound mode enabled. Wrap to. When wraparound mode is enabled and after the end of queue has been reached, WRTO determines which address the QSPI executes next. The end of queue is determined by an address match with ENDQP. 0 = Wrap to pointer address 0x0 1 = Wrap to address in NEWQP Ending queue pointer. This field determines the last absolute address in the queue to be completed by the QSPI. After completing each command, the QSPI compares the queue pointer value of the just-completed command with the value of ENDQP. If the two values match, the QSPI sets SPIF to indicate it has reached the end of the programmed queue. Refer to 14.7.4 QSPI Operation for more information. Reserved New queue pointer value. This field contains the first QSPI queue address. Refer to 14.7.4 QSPI Operation for more information.
WREN
WRTO
3:7
ENDQP
8:10 11:15
NEWQP
14.7.1.4 QSPI Control Register 3 SPCR3 contains the loop mode enable bit, halt and mode fault interrupt enable, and the halt control bit. The CPU has read/write access to SPCR3, but the QSPI has read access only. SPCR3 must be initialized before QSPI operation begins. Writing a new value to SPCR3 while the QSPI is enabled disrupts operation. SPCR3 QSPI Control Register
MSB 0 1 2 Reserved RESET: 0 0 0 0 0 0 0 0 3 4 5 LOOP Q 6 HMIE 7 HALT 8 9 10 11 12 13
0x30 501E
14 LSB 15
SPSR*
MPC555
/ MPC556
MOTOROLA 14-19
USERS MANUAL

Bit(s) 0:4 5 Name LOOPQ Reserved QSPI loop mode. LOOPQ controls feedback on the data serializer for testing. 0 = Feedback path disabled. 1 = Feedback path enabled. HALTA and MODF interrupt enable. HMIE enables interrupt requests generated by the HALTA status flag or the MODF status flag in SPSR. 0 = HALTA and MODF interrupts disabled. 1 = HALTA and MODF interrupts enabled. Halt QSPI. When HALT is set, the QSPI stops on a queue boundary. It remains in a defined state from which it can later be restarted. Refer to 14.7.4.1 Enabling, Disabling, and Halting the SPI. 0 = QSPI operates normally. 1 = QSPI is halted for subsequent restart. SPSR. SeeTable 14-18 for bit descriptions. Description
HMIE
HALT
8:15
14.7.1.5 QSPI Status Register The SPSR contains information concerning the current serial transmission. Only the QSPI can set bits in this register. To clear status flags, the CPU reads SPSR with the flags set and then writes the SPSR with zeros in the appropriate bits. Writes to CPTQP have no effect. SPSR QSPI Status Register
MSB 0 1 2 3 4 5 6 7 8 SPIF 9 MODF 10 HALTA 11 12 13 CPTQP
0x30 501E
14 LSB 15
SPCR3*
MPC555
/ MPC556
MOTOROLA 14-20
USERS MANUAL

Table 14-18 SPSR Bit Descriptions
Bit(s) 0:7 Name SPCR3 See bit descriptions in Table 14-17. QSPI finished flag. SPIF is set after execution of the command at the address in ENDQP in SPCR2. If wraparound mode is enabled (WREN = 1), the SPIF is set, after completion of the command defined by ENDQP, each time the QSPI cycles through the queue. 0 = QSPI is not finished 1 = QSPI is finished Mode fault flag. The QSPI asserts MODF when the QSPI is in master mode (MSTR = 1) and the SS input pin is negated by an external driver. Refer to 14.7.8 Mode Fault for more information. 0 = Normal operation 1 = Another SPI node requested to become the network SPI master while the QSPI was enabled in master mode (SS input taken low). Halt acknowledge flag. HALTA is set when the QSPI halts in response to setting the HALT bit in SPCR3. HALTA is also set when the IMB3 FREEZE signal is asserted, provided the FRZ1 bit in the QSMCMMCR is set. To prevent undefined operation, the user must not modify any QSPI control registers or RAM while the QSPI is halted. If HMIE in SPCR3 is set the QSPI sends interrupt requests to the CPU when HALTA is asserted. 0 = QSPI is not halted. 1 = QSPI is halted Completed queue pointer. CPTQP points to the last command executed. It is updated when the current command is complete. When the first command in a queue is executing, CPTQP contains either the reset value 0x0 or a pointer to the last command completed in the previous queue. If the QSPI is halted, CPTQP may be used to determine which commands have not been executed. The CPTQP may also be used to determine which locations in the receive data segment of the QSPI RAM contain valid received data. Description
SPIF
MODF
10
HALTA
11:15
CPTQP
14.7.2 QSPI RAM The QSPI contains a 160-byte block of dual-ported static RAM that can be accessed by both the QSPI and the CPU. Because of this dual access capability, up to two wait states may be inserted into CPU access time if the QSPI is in operation. The size and type of access of the QSPI RAM by the CPU affects the QSPI access time. The QSPI allows byte, half-word, and word accesses. Only word accesses of the RAM by the CPU are coherent because these accesses are an indivisible operation. If the CPU makes a coherent access of the QSPI RAM, the QSPI cannot access the QSPI RAM until the CPU is finished. However, a word or misaligned word access is not coherent because the CPU must break its access of the QSPI RAM into two parts, which allows the QSPI to access the QSPI RAM between the two accesses by the CPU. The RAM is divided into three segments: receive data RAM, transmit data RAM, and command data RAM. Receive data is information received from a serial device external to the MCU. Transmit data is information stored for transmission to an external device. Command data defines transfer parameters. Figure 14-5 shows RAM organization.
MPC555
/ MPC556
MOTOROLA 14-21
USERS MANUAL

0x30 5140
RR0 RR1 RR2 Receive RAM RRD RRE RRF Half-Word
0x30 5180
TR0 TR1 TR2 Transmit RAM TRD TRE TRF Half-Word
0x30 51C0
CR0 CR1 CR2 Command RAM CRD CRE CRF Byte
0x30 517F
0x30 51BF
0x30 51DF
Figure 14-5 QSPI RAM
14.7.2.1 Receive RAM Data received by the QSPI is stored in this segment, to be read by the CPU. Data stored in the receive RAM is right-justified,( i.e., the least significant bit is always in the right-most bit position within the word regardless of the serial transfer length). Unused bits in a receive queue entry are set to zero by the QSPI upon completion of the individual queue entry. The CPU can access the data using byte, half-word, or word addressing. The CPTQP value in SPSR shows which queue entries have been executed. The CPU uses this information to determine which locations in receive RAM contain valid data before reading them. 14.7.2.2 Transmit RAM Data that is to be transmitted by the QSPI is stored in this segment. The CPU normally writes one word of data into this segment for each queue command to be executed. If the corresponding peripheral, such as a serial input port, is used solely to input data, then this segment does not need to be initialized. Data must be written to transmit RAM in a right-justified format. The QSPI cannot modify information in the transmit RAM. The QSPI copies the information to its data serializer for transmission. Information remains in transmit RAM until overwritten. 14.7.2.3 Command RAM Command RAM is used by the QSPI in master mode. The CPU writes one byte of control information to this segment for each QSPI command to be executed. The QSPI cannot modify information in command RAM. Command RAM consists of 32 bytes. Each byte is divided into two fields. The peripheral chip-select field, enables peripherals for transfer. The command control field provides transfer options.
MPC555
/ MPC556
MOTOROLA 14-22
USERS MANUAL

A maximum of 32 commands can be in the queue. These bytes are assigned an address from 0x00 to 0x1F. Queue execution by the QSPI proceeds from the address in NEWQP through the address in ENDQP. (Both of these fields are in SPCR2.) CR[0:F] Command RAM 0x30 51C0 0x30 51DF
7 CONT CONT
6 BITSE BITSE
5 DT DT
4 DSCK DSCK
3 PCS3 PCS3
2 PCS2 PCS2
1 PCS1 PCS1
0 PCS01 PCS01
Command Control
Peripheral Chip Select
NOTES: 1. The PCS[0] bit represents the dual-function PCS[0]/SS.
Table 14-19 Command RAM Bit Descriptions

Bit(s) 0 Name CONT Description Continue 0 = Control of chip selects returned to PORTQS after transfer is complete. 1 = Peripheral chip selects remain asserted after transfer is complete. Bits per transfer enable 0 = Eight bits 1 = Number of bits set in BITS field of SPCR0. Delay after transfer 0 = Delay after transfer is 17 FSYS. 1 = SPCR1 DTL[7:0] specifies delay after transfer PCS valid to SCK. PCS to SCK Delay 0 = PCS valid to SCK delay is one-half SCK. 1 = SPCR1 DSCKL[6:0] specifies delay from PCS valid to SCK. Peripheral chip selects. Use peripheral chip-select bits to select an external device for serial data transfer. More than one peripheral chip select may be activated at a time, and more than one peripheral chip can be connected to each PCS pin, provided proper fanout is observed. PCS[0] shares a pin with the slave select (SS) signal, which initiates slave mode serial transfer. If SS is taken low when the QSPI is in master mode, a mode fault occurs.
BITSE
DT
DSCK
4:7
PCS[3:0]
Refer to 14.7.5 Master Mode Operation for more information on the command RAM. 14.7.3 QSPI Pins Seven pins are associated with the QSPI. When not needed by the QSPI, they can be configured for general-purpose I/O. Table 14-20 identifies the QSPI pins and their functions. Register DDRQS determines whether the pins are designated as input or output. The user must initialize DDRQS for the QSPI to function correctly.
MPC555
/ MPC556
MOTOROLA 14-23
USERS MANUAL

Table 14-20 QSPI Pin Functions
Pin Names Master in slave out Master out slave in Serial clock Peripheral chip selects Peripheral chip select Slave select3 Slave select4
2
Mnemonic MISO MOSI SCK1 PCS[1:3] PCS[0]/ SS SS
Mode Master Slave Master Slave Master Slave Master Master Slave Master
Function Serial data input to QSPI Serial data output from QSPI Serial data output from QSPI Serial data input to QSPI Clock output from QSPI clock Input to QSPI Outputs select peripheral(s) Output selects peripheral(s) Input selects the QSPI May cause mode fault
NOTES: 1. All QSPI pins (except SCK) can be used as general-purpose I/O if they are not used by the QSPI while the QSPI is operating. SCK can only be used for general-purpose I/O if the QSPI is disabled. 2. An output (PCS[0]) when the QSPI is in master mode. 3. An input (SS) when the QSPI is in slave mode. 4. An input (SS) when the QSPI is in master mode; useful in multimaster systems.
14.7.4 QSPI Operation The QSPI uses a dedicated 160-byte block of static RAM accessible by both the QSPI and the CPU to perform queued operations. The RAM is divided into three segments: 32 command control bytes, 64 transmit data bytes, and 64 receive data bytes. Once the CPU has set up a queue of QSPI commands, written the transmit data segment with information to be sent, and enabled the QSPI, the QSPI operates independently of the CPU. The QSPI executes all of the commands in its queue, sets a flag indicating completion, and then either interrupts the CPU or waits for CPU intervention. QSPI RAM is organized so that one byte of command data, one word of transmit data, and one word of receive data correspond to each queue entry, 0x0 to 0x2F. The CPU initiates QSPI operation by setting up a queue of QSPI commands in command RAM, writing transmit data into transmit RAM, then enabling the QSPI. The QSPI executes the queued commands, sets a completion flag (SPIF), and then either interrupts the CPU or waits for intervention. There are four queue pointers. The CPU can access three of them through fields in QSPI registers. The new queue pointer (NEWQP), contained in SPCR2, points to the first command in the queue. An internal queue pointer points to the command currently being executed. The completed queue pointer (CPTQP), contained in SPSR, points to the last command executed. The end queue pointer (ENDQP), contained in SPCR2, points to the final command in the queue. The internal pointer is initialized to the same value as NEWQP. During normal operation, the command pointed to by the internal pointer is executed, the value in the internal pointer is copied into CPTQP, the internal pointer is incremented, and then the sequence repeats. Execution continues at the internal pointer address unless the
MPC555
/ MPC556
MOTOROLA 14-24
USERS MANUAL

NEWQP value is changed. After each command is executed, ENDQP and CPTQP are compared. When a match occurs, the SPIF flag is set and the QSPI stops and clears SPE, unless wraparound mode is enabled. At reset, NEWQP is initialized to 0x0. When the QSPI is enabled, execution begins at queue address 0x0 unless another value has been written into NEWQP. ENDQP is initialized to 0x0 at reset but should be changed to the last queue entry before the QSPI is enabled. NEWQP and ENDQP can be written at any time. When NEWQP changes, the internal pointer value also changes. However, if NEWQP is written while a transfer is in progress, the transfer is completed normally. Leaving NEWQP and ENDQP set to 0x0 transfers only the data in transmit RAM location 0x0. 14.7.4.1 Enabling, Disabling, and Halting the SPI The SPE bit in the SPCR1 enables or disables the QSPI submodule. Setting SPE causes the QSPI to begin operation. If the QSPI is a master, setting SPE causes the QSPI to begin initiating serial transfers. If the QSPI is a slave, the QSPI begins monitoring the PCS[0]/SS pin to respond to the external initialization of a serial transfer. When the QSPI is disabled, the CPU may use the QSPI RAM. When the QSPI is enabled, both the QSPI and the CPU have access to the QSPI RAM. The CPU has both read and write access to all 160 bytes of the QSPI RAM. The QSPI can read-only the transmit data segment and the command control segment and can write-only the receive data segment of the QSPI RAM. The QSPI turns itself off automatically when it is finished by clearing SPE. An error condition called mode fault (MODF) also clears SPE. This error occurs when PCS[0]/ SS is configured for input, the QSPI is a system master (MSTR = 1), and PCS[0]/SS is driven low externally. Setting the HALT bit in SPCR3 stops the QSPI on a queue boundary. The QSPI halts in a known state from which it can later be restarted. When HALT is set, the QSPI finishes executing the current serial transfer (up to 16 bits) and then halts. While halted, if the command control bit (CONT of the QSPI RAM) for the last command was asserted, the QSPI continues driving the peripheral chip select pins with the value designated by the last command before the halt. If CONT was cleared, the QSPI drives the peripheral chip-select pins to the value in register PORTQS. If HALT is set during the last command in the queue, the QSPI completes the last command, sets both HALTA and SPIF, and clears SPE. If the last queue command has not been executed, asserting HALT does not set SPIF or clear SPE. QSPI execution continues when the CPU clears HALT. To stop the QSPI, assert the HALT bit in SPCR3, then wait until the HALTA bit in SPSR is set. SPE can then be safely cleared, providing an orderly method of shutting down the QSPI quickly after the current serial transfer is completed. The CPU can disable the QSPI immediately by clearing SPE. However, loss of data from a current serial transfer may result and confuse an external SPI device.
MPC555
/ MPC556
MOTOROLA 14-25
USERS MANUAL

14.7.4.2 QSPI Interrupts The QSPI has three possible interrupt sources but only one interrupt vector. These sources are SPIF, MODF, and HALTA. When the CPU responds to a QSPI interrupt, the user must ascertain the interrupt cause by reading the SPSR. Any interrupt that was set may then be cleared by writing to SPSR with a zero in the bit position corresponding to the interrupt source. The SPIFIE bit in SPCR2 enables the QSPI to generate an interrupt request upon assertion of the SPIF status flag. Because it is buffered, the value written to SPIFIE applies only upon completion of the queue (the transfer of the entry indicated by ENDPQ). Thus, if a single sequence of queue entries is to be transferred (i.e., no WRAP), then SPIFIE should be set to the desired state before the first transfer.
If a sub-queue is to be used, the same CPU write that causes a branch to the subqueue may enable or disable the SPIF interrupt for the sub-queue. The primary queue retains its own selected interrupt mode, either enabled or disabled. The SPIF interrupt must be cleared by clearing SPIF. Subsequent interrupts may then be prevented by clearing SPIFIE. Clearing SPIFIE does not immediately clear an interrupt already caused by SPIF. 14.7.4.3 QSPI Flow The QSPI operates in either master or slave mode. Master mode is used when the MCU initiates data transfers. Slave mode is used when an external device initiates transfers. Switching between these modes is controlled by MSTR in SPCR0. Before entering either mode, appropriate QSMCM and QSPI registers must be initialized properly. In master mode, the QSPI executes a queue of commands defined by control bits in each command RAM queue entry. Chip-select pins are activated, data is transmitted from the transmit RAM and received by the receive RAM. In slave mode, operation proceeds in response to SS pin assertion by an external SPI bus master. Operation is similar to master mode, but no peripheral chip selects are generated, and the number of bits transferred is controlled in a different manner. When the QSPI is selected, it automatically executes the next queue transfer to exchange data with the external device correctly. Although the QSPI inherently supports multi-master operation, no special arbitration mechanism is provided. A mode fault flag (MODF) indicates a request for SPI master arbitration. System software must provide arbitration. Note that unlike previous SPI systems, MSTR is not cleared by a mode fault being set nor are the QSPI pin output drivers disabled. The QSPI and associated output drivers must be disabled by clearing SPE in SPCR1. Figure 14-6 shows QSPI initialization. Figure 14-7 through Figure 14-11 show QSPI master and slave operation. The CPU must initialize the QSMCM global and pin registers and the QSPI control registers before enabling the QSPI for either mode of operation. The command queue must be written before the QSPI is enabled for master
MPC555
/ MPC556
MOTOROLA 14-26
USERS MANUAL

mode operation. Any data to be transmitted should be written into transmit RAM before the QSPI is enabled. During wraparound operation, data for subsequent transmissions can be written at any time.
Begin
Initialize QSMCM Global Registers
Initialize PQSPAR, PORTQS, and DDRQS in this Order
QSPI Initialization Initialize QSPI Control Registers
Initialize QSPI RAM
Enable QSPI
Y MSTR = 1 ? N
A2
A1
Figure 14-6 Flowchart of QSPI Initialization Operation
MPC555
/ MPC556
MOTOROLA 14-27
USERS MANUAL

QSPI Cycle Begins (Master Mode) A1
Is QSPI Disabled? N
Has NEWQP Been Written?
Working Queue Pointer Changed to NEWQP
N Read Command Control and Transmit Data From RAM Using Queue Pointer Address
Assert Peripheral Chip Select(s)
Is PCS To SCK Delay Programmed? N
Y Execute Programmed Delay
Execute Standard Delay
Execute Serial Transfer
Store Received Data In RAM Using Queue Pointer Address
B1
Figure 14-7 Flowchart of QSPI Master Operation (Part 1)
MPC555
/ MPC556
MOTOROLA 14-28
USERS MANUAL
B1
Write Queue Pointer To CPTQP Status Bits
Is Continue Bit Asserted? N
Negate Peripheral Chip Selects
Is Delay After Transfer Asserted? N
Execute Programmed Delay
Execute Standard Delay
C1
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/ MPC556
MOTOROLA 14-29
USERS MANUAL
C1
Is this the Last Command in the Queue? N
Assert SPIF Status Flag
Is Interrupt Enable Bit SPIFIE Set? N
Request Interrupt
Increment Working Queue Pointer
Is Wrap Enable Bit Set? N Disable QSPI A1
Reset Working Queue Pointer to NEWQP or 0x0000
Is HALT Or FREEZE Asserted? N
Halt QSPI and Set HALTA
Is Interrupt Enable Bit HMIE Set? N
Request Interrupt
Is HALT Or FREEZE Asserted? N A1
MPC555
/ MPC556
MOTOROLA 14-30
USERS MANUAL

QSPI Cycle Bgins (Slave Mode A2
Is QSPI Disabled? N
Has NEWQP Been Written?
Queue Pointer Changed to NEWQP
N Read Transmit Data From RAM Using Queue Pointer Address
Is Slave Select Pin Asserted? N
Execute Serial Transfer When SCK Received
Store Received Data In RAM Using Queue Pointer Address
Write Queue Pointer to CPTQP Status Bits
B2
Figure 14-10 Flowchart of QSPI Slave Operation (Part 1)
MPC555
/ MPC556
MOTOROLA 14-31
USERS MANUAL
C2
Is this the Last Command in the Queue? N
Set SPIF Status Flag
Is Interrupt Enable Bit SPIFIE Set? N
Request Interrupt
Increment Working Queue Pointer
Is Wrap Enable Bit Asserted? N Disable QSPI A2
Reset Working Queue Pointer To NEWQP or 0x0000
Is HALT or FREEZE Asserted? N
Halt QSPI and Set HALTA
Is Interrupt Enable Bit HMIE Set? N
Request Interrupt
Is HALT Or FREEZE Asserted? N A2
QSPI SLV2 FLOW6
Figure 14-11 Flowchart of QSPI Slave Operation (Part 2) Normally, the SPI bus performs synchronous bi-directional transfers. The serial clock on the SPI bus master supplies the clock signal SCK to time the transfer of data. Four
MPC555
/ MPC556
MOTOROLA 14-32
USERS MANUAL

possible combinations of clock phase and polarity can be specified by the CPHA and CPOL bits in SPCR0. Data is transferred with the most significant bit first. The number of bits transferred per command defaults to eight, but can be set to any value from eight to sixteen bits by writing a value into the BITS field in SPCR0 and setting BITSE in command RAM. Typically, SPI bus outputs are not open drain unless multiple SPI masters are in the system. If needed, the WOMQ bit in SPCR0 can be set to provide wired-OR, open drain outputs. An external pull-up resistor should be used on each output line. WOMQ affects all QSPI pins regardless of whether they are assigned to the QSPI or used as general-purpose I/O. 14.7.5 Master Mode Operation Setting the MSTR bit in SPCR0 selects master mode operation. In master mode, the QSPI can initiate serial transfers, but cannot respond to externally initiated transfers. When the slave select input of a device configured for master mode is asserted, a mode fault occurs. Before QSPI operation begins, PQSPAR must be written to assign the necessary pins to the QSPI. The pins necessary for master mode operation are MISO, MOSI, SCK, and one or more of the chip-select pins. MISO is used for serial data input in master mode, and MOSI is used for serial data output. Either or both may be necessary, depending on the particular application. SCK is the serial clock output in master mode and must be assigned to the QSPI for proper operation. The PORTQS data register must next be written with values that make the QGPIO[6]/ SCK (bit 13 QDSCK of PORTQS) and QGPIO[3:0]/PCS[3:0] (bits 12:9 QDPCS[3:0] of PORTQS) outputs inactive when the QSPI completes a series of transfers. Pins allocated to the QSPI by PQSPAR are controlled by PORTQS when the QSPI is inactive. PORTQS I/O pins driven to states opposite those of the inactive QSPI signals can generate glitches that momentarily enable or partially clock a slave device. For example, if a slave device operates with an inactive SCK state of logic one (CPOL = 1) and uses active low peripheral chip-select PCS[0], the QDSCK and QDPCS0 bits in PORTQS must be set to 0b11. If QDSCK and QDPCS0 = 0b00, falling edges will appear on QGPIO[6]/SCK and GPIO[0]/PCS[0] as the QSPI relinquishes control of these pins and PORTQS drives them to logic zero from the inactive SCK and PCS[0] states of logic one. Before master mode operation is initiated, QSMCM register DDRQS is written last to direct the data flow on the QSPI pins used. Configure the SCK, MOSI and appropriate chip-select pins PCS[3:0] as outputs. The MISO pin must be configured as an input. After pins are assigned and configured, write appropriate data to the command queue. If data is to be transmitted, write the data to transmit RAM. Initialize the queue pointers as appropriate.
MPC555
/ MPC556
MOTOROLA 14-33
USERS MANUAL

QSPI operation is initiated by setting the SPE bit in SPCR1. Shortly after SPE is set, the QSPI executes the command at the command RAM address pointed to by NEWQP. Data at the pointer address in transmit RAM is loaded into the data serializer and transmitted. Data that is simultaneously received is stored at the pointer address in receive RAM. When the proper number of bits have been transferred, the QSPI stores the working queue pointer value in CPTQP, increments the working queue pointer, and loads the next data for transfer from transmit RAM. The command pointed to by the incremented working queue pointer is executed next, unless a new value has been written to NEWQP. If a new queue pointer value is written while a transfer is in progress, that transfer is completed normally.
When the CONT bit in a command RAM byte is set, PCS pins are continuously driven to specified states during and between transfers. If the chip-select pattern changes during or between transfers, the original pattern is driven until execution of the following transfer begins. When CONT is cleared, the data in register PORTQS is driven between transfers. The data in PORTQS must match the inactive states of SCK and any peripheral chip-selects used. When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point, the QSPI clears SPE and stops unless wraparound mode is enabled. 14.7.5.1 Clock Phase and Polarity In master mode, data transfer is synchronized with the internally-generated serial clock SCK. Control bits, CPHA and CPOL, in SPCR0, control clock phase and polarity. Combinations of CPHA and CPOL determine upon which SCK edge to drive outgoing data from the MOSI pin and to latch incoming data from the MISO pin. 14.7.5.2 Baud Rate Selection Baud rate is selected by writing a value from two to 255 into the SPBR field in SPCR0. The QSPI uses a modulus counter to derive the SCK baud rate from the MCU IMB clock. The following expressions apply to the SCK baud rate: f SYS
SCK Baud Rate = ------------------------2 SPBR
or
SPBR = ------------------------------------------------------------------------2 SCK Baud Rate Desired
f SYS
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/ MPC556
MOTOROLA 14-34
USERS MANUAL

Giving SPBR a value of zero or one disables the baud rate generator. SCK is disabled and assumes its inactive state. At reset, the SCK baud rate is initialized to one eighth of the IMB clock frequency. Table 14-21 provides some example SCK baud rates with a 40-MHz IMB clock. Table 14-21 Example SCK Frequencies with a 40-MHz IMB Clock
Division Ratio 4 6 8 14 SPBR Value 2 3 4 7 14 29 140 255 SCK Frequency 10.00 MHz 6.67 MHz 5.00 MHz 2.86 MHz 1.43 MHz 689 kHz 143 kHz 78.43 kHz
28 58 280 510
14.7.5.3 Delay Before Transfer The DSCK bit in each command RAM byte inserts either a standard (DSCK = 0) or user-specified (DSCK = 1) delay from chip-select assertion until the leading edge of the serial clock. The DSCKL field in SPCR1 determines the length of the user-defined delay before the assertion of SCK. The following expression determines the actual delay before SCK:
DSCKL PCS to SCK Delay = -------------------
f SYS
where DSCKL is in the range from 1 to 127. NOTE A zero value for DSCKL causes a delay of 128 IMB clocks, which equals 3.2 s for a 40-MHz IMB clock. Because of design limits, a DSCKL value of one defaults to the same timing as a value of two. When DSCK equals zero, DSCKL is not used. Instead, the PCS valid-to-SCK transition is one-half the SCK period. 14.7.5.4 Delay After Transfer Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to complete conversion. Writing a value to the DTL field in SPCR1 specifies a delay period. The DT bit in each command RAM byte determines whether the standard delay period
MPC555
/ MPC556
MOTOROLA 14-35
USERS MANUAL

(DT = 0) or the specified delay period (DT = 1) is used. The following expression is used to calculate the delay:
32 DTL Delay after Transfer = -----------------------
f SYS
where DTL is in the range from one to 255. A zero value for DTL causes a delay-after-transfer value of 8192 IMB clock frequency (204.8 s with a 40-MHz IMB clock). If DT is zero in a command RAM byte, a standard delay is inserted.
17 Standard Delay after Transfer = ------------f SYS Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to complete conversion. Adequate delay between transfers must be specified for long data streams because the QSPI requires time to load a transmit RAM entry for transfer. Receiving devices need at least the standard delay between successive transfers. If the IMB clock is operating at a slower rate, the delay between transfers must be increased proportionately. 14.7.5.5 Transfer Length There are two transfer length options. The user can choose a default value of eight bits, or a programmed value from eight (0b1000) to 16 (0b0000) bits, inclusive. Reserved values (from 0b0001 to 0b0111) default to eight bits. The programmed value must be written into the BITS field in SPCR0. The BITSE bit in each command RAM byte determines whether the default value (BITSE = 0) or the BITS value (BITSE = 1) is used. 14.7.5.6 Peripheral Chip Selects Peripheral chip-select signals are used to select an external device for serial data transfer. Chip-select signals are asserted when a command in the queue is executed. Signals are asserted at a logic level corresponding to the value of the PCS[3:0] bits in each command byte. More than one chip-select signal can be asserted at a time, and more than one external device can be connected to each PCS pin, provided proper fanout is observed. PCS[0] shares a pin with the slave select SS signal, which initiates slave mode serial transfer. If SS is taken low when the QSPI is in master mode, a mode fault occurs.
MPC555
/ MPC556
MOTOROLA 14-36
USERS MANUAL

To configure a peripheral chip select, set the appropriate bit in PQSPAR, then configure the chip-select pin as an output by setting the appropriate bit in DDRQS. The value of the bit in PORTQS that corresponds to the chip-select pin determines the base state of the chip-select signal. If the base state is zero, chip-select assertion must be active high (PCS bit in command RAM must be set); if base state is one, assertion must be active low (PCS bit in command RAM must be cleared). PORTQS bits are cleared during reset. If no new data is written to PORTQS before pin assignment and configuration as an output, the base state of chip-select signals is zero and chip-select pins are configured for active-high operation. 14.7.5.7 Master Wraparound Mode Wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can wrap to pointer address 0x0 or to the address pointed to by NEWQP, depending on the state of the WRTO bit in SPCR2. In wraparound mode, the QSPI cycles through the queue continuously, even while the QSPI is requesting interrupt service. SPE is not cleared when the last command in the queue is executed. New receive data overwrites previously received data in receive RAM. Each time the end of the queue is reached, the SPIF flag is set. SPIF is not automatically reset. If interrupt-driven QSPI service is used, the service routine must clear the SPIF bit to end the current interrupt request. Additional interrupt requests during servicing can be prevented by clearing SPIFIE, but SPIFIE is buffered. Clearing it does not end the current request. Wraparound mode is exited by clearing the WREN bit or by setting the HALT bit in SPCR3. Exiting wraparound mode by clearing SPE is not recommended, as clearing SPE may abort a serial transfer in progress. The QSPI sets SPIF, clears SPE, and stops the first time it reaches the end of the queue after WREN is cleared. After HALT is set, the QSPI finishes the current transfer, then stops executing commands. After the QSPI stops, SPE can be cleared. 14.7.6 Slave Mode Clearing the MSTR bit in SPCR0 selects slave mode operation. In slave mode, the QSPI is unable to initiate serial transfers. Transfers are initiated by an external SPI bus master. Slave mode is typically used on a multi-master SPI bus. Only one device can be bus master (operate in master mode) at any given time. Before QSPI operation is initiated, QSMCM register PQSPAR must be written to assign necessary pins to the QSPI. The pins necessary for slave mode operation are MISO, MOSI, SCK, and PCS[0]/SS. MISO is used for serial data output in slave mode, and MOSI is used for serial data input. Either or both may be necessary, depending on the particular application. SCK is the serial clock input in slave mode and must be assigned to the QSPI for proper operation. Assertion of the active-low slave select signal SS initiates slave mode operation. Before slave mode operation is initiated, DDRQS must be written to direct data flow on the QSPI pins used. Configure the MOSI, SCK and PCS[0]/SS pins as inputs. The MISO pin must be configured as an output.
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/ MPC556
MOTOROLA 14-37
USERS MANUAL

After pins are assigned and configured, write data to be transmitted into transmit RAM. Command RAM is not used in slave mode, and does not need to be initialized. Set the queue pointers, as appropriate. When SPE is set and MSTR is clear, a low state on the slave select PCS[0]/SS pin begins slave mode operation at the address indicated by NEWQP. Data that is received is stored at the pointer address in receive RAM. Data is simultaneously loaded into the data serializer from the pointer address in transmit RAM and transmitted. Transfer is synchronized with the externally generated SCK. The CPHA and CPOL bits determine upon which SCK edge to latch incoming data from the MISO pin and to drive outgoing data from the MOSI pin. Because the command RAM is not used in slave mode, the CONT, BITSE, DT, DSCK, and peripheral chip-select bits have no effect. The PCS[0]/SS pin is used only as an input. The SPBR, DT and DSCKL fields in SPCR0 and SPCR1 bits are not used in slave mode. The QSPI drives neither the clock nor the chip-select pins and thus cannot control clock rate or transfer delay. Because the BITSE option is not available in slave mode, the BITS field in SPCR0 specifies the number of bits to be transferred for all transfers in the queue. When the number of bits designated by BITS[3:0] has been transferred, the QSPI stores the working queue pointer value in CPTQP, increments the working queue pointer, and loads new transmit data from transmit RAM into the data serializer. The working queue pointer address is used the next time PCS[0]/SS is asserted, unless the RCPU writes to NEWQP first. The QSPI shifts one bit for each pulse of SCK until the slave select input goes high. If SS goes high before the number of bits specified by the BITS field is transferred, the QSPI resumes operation at the same pointer address the next time SS is asserted. The maximum value that the BITS field can have is 16. If more than 16 bits are transmitted before SS is negated, pointers are incremented and operation continues. The QSPI transmits as many bits as it receives at each queue address, until the BITS value is reached or SS is negated. SS does not need to go high between transfers as the QSPI transfers data until reaching the end of the queue, whether SS remains low or is toggled between transfers. When the QSPI reaches the end of the queue, it sets the SPIF flag. If the SPIFIE bit in SPCR2 is set, an interrupt request is generated when SPIF is asserted. At this point, the QSPI clears SPE and stops unless wraparound mode is enabled. Slave wraparound mode is enabled by setting the WREN bit in SPCR2. The queue can wrap to pointer address 0x0 or to the address pointed to by NEWQP, depending on the state of the WRTO bit in SPCR2. Slave wraparound operation is identical to master wraparound operation.
MPC555
/ MPC556
MOTOROLA 14-38
USERS MANUAL

14.7.6.1 Description of Slave Operation After reset, the QSMCM registers and the QSPI control registers must be initialized as described above. Although the command control segment is not used, the transmit and receive data segments may, depending upon the application, need to be initialized. If meaningful data is to be sent out from the QSPI, the user should write the data to the transmit data segment before enabling the QSPI. If SPE is set and MSTR is not set, a low state on the slave select (PCS[0]/SS) pin commences slave mode operation at the address indicated by NEWQP. The QSPI transmits the data found in the transmit data segment at the address indicated by NEWQP, and the QSPI stores received data in the receive data segment at the ad-dress indicated by NEWQP. Data is transferred in response to an external slave clock input at the SCK pin.
Because the command control segment is not used, the command control bits and peripheral chip-select codes have no effect in slave mode operation. The QSPI does not drive any of the four peripheral chip-selects as outputs. PCS[0]/SS is used as an input. Although CONT cannot be used in slave mode, a provision is made to enable receipt of more than 16 data bits. While keeping the QSPI selected (PCS[0]/SS is held low), the QSPI stores the number of bits, designated by BITS, in the current receive data segment address, increments NEWQP, and continues storing the remaining bits (up to the BITS value) in the next receive data segment address. As long as PCS[0]/SS remains low, the QSPI continues to store the incoming bit stream in sequential receive data segment addresses, until either the value in BITS is reached or the end-of-queue address is used with wraparound mode disabled. When the end of the queue is reached, the SPIF flag is asserted, optionally causing an interrupt. If wraparound mode is disabled, any additional incoming bits are ignored. If wraparound mode is enabled, storing continues at either address 0x0 or the address of NEWQP, depending on the WRTO value. When using this capability to receive a long incoming data stream, the proper delay between transfers must be used. The QSPI requires time, approximately 0.425 s with a 40-MHz IMB clock, to prefetch the next transmit RAM entry for the next transfer. Therefore, the user may select a baud rate that provides at least a 0.6-s delay between successive transfers to ensure no loss of incoming data. If the IMB clock is operating at a slower rate, the delay between transfers must be increased proportionately. Because the BITSE option in the command control segment is no longer available, BITS sets the number of bits to be transferred for all transfers in the queue until the CPU changes the BITS value. As mentioned above, until PCS[0]/SS is negated (brought high), the QSPI continues to shift one bit for each pulse of SCK. If PCS[0]/SS is negated before the proper number of bits (according to BITS) is received, the next time the QSPI is selected it resumes storing bits in the same receive-data segment address where it left off. If more than 16 bits are transferred before negating the PCS[0]/ SS, the QSPI stores the number of bits indicated by BITS in the current receive data segment address, then increments the address and continues storing as described
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MOTOROLA 14-39
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above. Note that PCS[0]/SS does not necessarily have to be negated between transfers. Once the proper number of bits (designated by BITS) are transferred, the QSPI stores the received data in the receive data segment, stores the internal working queue pointer value in CPTQP, increments the internal working queue pointer, and loads the new transmit data from the transmit data segment into the data serializer. The internal working queue pointer address is used the next time PCS[0]/SS is asserted, unless the CPU writes to the NEWQP first. The DT and DSCK command control bits are not used in slave mode. As a slave, the QSPI does not drive the clock line nor the chip-select lines and, therefore, does not generate a delay.
In slave mode, the QSPI shifts out the data in the transmit data segment. The transmit data is loaded into the data serializer (refer to Figure 14-1) for transmission. When the PCS[0]/SS pin is pulled low the MISO pin becomes active and the serializer then shifts the 16 bits of data out in sequence, most significant bit first, as clocked by the incoming SCK signal. The QSPI uses CPHA and CPOL to determine which incoming SCK edge the MOSI pin uses to latch incoming data, and which edge the MISO pin uses to drive the data out. The QSPI transmits and receives data until reaching the end of the queue (defined as a match with the address in ENDQP), regardless of whether PCS[0]/SS remains selected or is toggled between serial transfers. Receiving the proper number of bits causes the received data to be stored. The QSPI always transmits as many bits as it receives at each queue address, until the BITS value is reached or PCS[0]/SS is negated. 14.7.7 Slave Wraparound Mode When the QSPI reaches the end of the queue, it always sets the SPIF flag, whether wraparound mode is enabled or disabled. An optional interrupt to the CPU is gen-erated when SPIF is asserted. At this point, the QSPI clears SPE and stops unless wraparound mode is enabled. A description of SPIFIE bit can be found in 4.3.3 QSPI Control Register 2 (SPCR2). In wraparound mode, the QSPI cycles through the queue continuously. Each time the end of the queue is reached, the SPIF flag is set. If the CPU fails to clear SPIF, it remains set, and the QSPI continues to send interrupt requests to the CPU (assuming SPIFIE is set). The user may avoid causing CPU interrupts by clearing SPIFIE. As SPIFIE is buffered, clearing it after the SPIF flag is asserted does not immediately stop the CPU interrupts, but only prevents future interrupts from this source. To clear the current interrupt, the CPU must read QSPI register SPSR with SPIF asserted, followed by a write to SPSR with zero in SPIF (clear SPIF). Execution continues in wraparound mode even while the QSPI is requesting interrupt service from the CPU. The internal working queue pointer is incremented to the next address and the commands are executed again. SPE is not cleared by the QSPI. New receive data overwrites previously received data located in the receive data segment.
MPC555
/ MPC556
MOTOROLA 14-40
USERS MANUAL

Wraparound mode is properly exited in two ways: a) The CPU may disable wraparound mode by clearing WREN. The next time end of the queue is reached, the QSPI sets SPIF, clears SPE, and stops; and, b) The CPU sets HALT. This second method halts the QSPI after the current transfer is completed, allowing the CPU to negate SPE. The CPU can immediately stop the QSPI by clearing SPE; however, this method is not recommended, as it causes the QSPI to abort a serial transfer in process. 14.7.8 Mode Fault MODF is asserted by the QSPI when the QSPI is the serial master (MSTR = 1) and the slave select (PCS[0]/SS) input pin is pulled low by an external driver. This is possible only if the PCS[0]/SS pin is configured as input by QDDR. This low input to SS is not a normal operating condition. It indicates that a multimaster system conflict may exist, that another MCU is requesting to become the SPI network master, or simply that the hardware is incorrectly affecting PCS[0]/SS. SPE in SPCR1 is cleared, disabling the QSPI. The QSPI pins revert to control by QPDR. If MODF is set and HMIE in SPCR3 is asserted, the QSPI generates an interrupt to the CPU. The CPU may clear MODF by reading SPSR with MODF asserted, followed by writing SPSR with a zero in MODF. After correcting the mode fault problem, the QSPI can be re-enabled by asserting SPE. The PCS[0]/SS pin may be configured as a general-purpose output instead of input to the QSPI. This inhibits the mode fault checking function. In this case, MODF is not used by the QSPI. 14.8 Serial Communication Interface The dual, independent, serial communication interface (DSCI) communicates with external devices through an asynchronous serial bus. The two SCI modules are functionally equivalent, except that the SCI1 also provides 16-deep queue capabilities for the transmit and receive operations. The SCIs are fully compatible with other Motorola SCI systems. The DSCI has all of the capabilities of previous SCI systems as well as several significant new features. Figure 14-12 is a block diagram of the SCI transmitter. Figure 14-13 is a block diagram of the SCI receiver.
MPC555
/ MPC556
MOTOROLA 14-41
USERS MANUAL

(WRITE-ONLY) SCxDR Tx BUFFER TRANSMITTER BAUD RATE CLOCK
START STOP
10 (11)-BIT Tx SHIFT REGISTER
H (8) 7 6 5 4 3 2 1 0 L
PIN BUFFER AND CONTROL

OPEN DRAIN OUTPUT MODE ENABLE FORCE PIN DIRECTION (OUT)
TxD
SIZE 8/9
TRANSFER Tx BUFFER
BREAKJAM 0's
SHIFT ENABLE
TRANSMITTER CONTROL LOGIC
LOOPS
WOMS
WAKE
JAM ENABLE
PARITY GENERATOR
PREAMBLEJAM 1's
RDRF
RWU
TCIE
TDRE
IDLE
SBK
RAF
ILIE
RIE
TIE
OR
ILT
RE
NF
PE
TC
PT
15
SCCxR1 CONTROL REGISTER 1 TIE TCIE
15
SCxSR STATUS REGISTER
PF 0 INTERNAL DATA BUS
TE
TDRE
TC
SCI Rx REQUESTS
SCI INTERRUPT REQUEST
Figure 14-12 SCI Transmitter Block Diagram
MPC555
/ MPC556
FE
MOTOROLA 14-42
USERS MANUAL

RECEIVER BAUD RATE CLOCK START
16 DATA RECOVERY
STOP
10 (11)-BIT Rx SHIFT REGISTER
RxD
PIN BUFFER
H (8) 7 6 5 4 3 2 1 0 L MSB ALL ONES
PARITY
DETECT
WAKE-UP LOGIC LOOPS WOMS
WAKE
RWU
TCIE
15
SBK 0
ILIE
RIE
TIE
ILT
SCCxR1 CONTROL REGISTER 1
RE
PE
PT
TE
SCxDR Rx BUFFER (READ-ONLY) RDRF RAF TDRE IDLE OR NF FE TC PF 0
15
SCxSR STATUS REGISTER
SCI Tx REQUESTS
SCI INTERRUPT REQUEST
INTERNAL DATA BUS
Figure 14-13 SCI Receiver Block Diagram
MPC555
/ MPC556
MOTOROLA 14-43
USERS MANUAL

14.8.1 SCI Registers The SCI programming model includes the QSMCM global and pin control registers and the DSCI registers. The DSCI registers, listed in Table 14-22, consist of five control registers, three status registers, and 34 data registers. All registers may be read or written at any time by the CPU. Rewriting the same value to any DSCI register does not disrupt operation; however, writing a different value into a DSCI register when the DSCI is running may disrupt operation. To change register values, the receiver and transmitter should be disabled with the transmitter allowed to finish first. The status flags in register SCxSR can be cleared at any time. Table 14-22 SCI Registers
Address 0x30 5008 0x30 500A 0x30 500C
Name SCC1R0 SCC1R1 SC1SR
Usage SCI1 Control Register 0 See Table 14-23 for bit descriptions. SCI1 Control Register 1 See Table 14-24 for bit descriptions. SCI1 Status Register See Table 14-25 for bit descriptions. SCI1 Data Register Transmit Data Register (TDR1)* Receive Data Register (RDR1)* See Table 14-26 for bit descriptions. SCI2 Control Register 0 SCI2 Control Register 1 SCI2 Status Register SCI2 Data Register Transmit Data Register (TDR2)* Receive Data Register (RDR2)* QSCI1 Control Register Interrupts, wrap, queue size and enables for receive and transmit, QTPNT. See Table 14-30 for bit descriptions. QSCI1 Status Register OverRun error flag, queue status flags, QRPNT, and QPEND. See Table 14-31 for bit descriptions.
0x30 500E (non-queue mode only) 0x30 5020 0x30 5022 0x30 5024 0x30 5026
SC1DR
SCC2R0 SCC2R1 SC2SR SC2DR
0x30 5028
QSCI1CR
0x30 502A
QSCI1SR
0x30 502C 0x30 504A 0x30 504C-6A
QSCI1 Transmit Queue QSCI1 Transmit Queue Data locations (on Memory Area half-word boundary) QSCI1 Receive Queue QSCI1 Receive Queue Data locations (on Memory Area half-word boundary)
*Reads access the RDRx; writes access the TDRx.
During SCIx initialization, two bits in the SCCxR1 should be written last: the transmitter enable (TE) and receiver enable (RE) bits, which enable SCIx. Registers SCCxR0 and SCCxR1 should both be initialized at the same time or before TE and RE are asserted. A single half-word write to SCCxR1 can be used to initialize SCIx and enable the transmitter and receiver.
MPC555
/ MPC556
MOTOROLA 14-44
USERS MANUAL

14.8.2 SCI Control Register 0 SCCxR0 contains the SCIx baud rate selection field and two bits controlling the clock source. The baud rate must be set before the SCI is enabled. The CPU can read and write SCCxR0 at any time. Changing the value of SCCxR0 bits during a transfer operation can disrupt the transfer. Before changing register values, allow the SCI to complete the current transfer, then disable the receiver and transmitter. SCCxR0 SCI Control Register 0
MSB 0 OTHR 1 LNKBD 2 0 3 4 5 6 7 8 9 SCxBR 10 11 12 13
0x30 5008
14 LSB 15
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
Table 14-23 SCCxR0 Bit Descriptions

Bit(s) 0 1 2 Name OTHR LNKBD Description This bit is reserved and should always be programmed to 0. This bit is reserved and should always be programmed to 0. Reserved SCI baud rate. The SCI baud rate is programmed by writing a 13-bit value to this field. Writing a value of zero to SCxBR disables the baud rate generator. Baud clock rate is calculated as follows: f SYS SCI Baud Rate = --------------------------------32 SCxBR
3:15
SCxBR
where SCxBR is in the range of 1 to 8191.

Refer to 14.8.7.3 Baud Clock for more information.
14.8.3 SCI Control Register 1 SCCxR1 contains SCIx configuration parameters, including transmitter and receiver enable bits, interrupt enable bits, and operating mode enable bits. The CPU can read or write this register at any time. The SCI can modify the RWU bit under certain circumstances. Changing the value of SCCxR1 bits during a transfer operation can disrupt the transfer. Before changing register values, allow the SCI to complete the current transfer, then disable the receiver and transmitter.
MPC555
/ MPC556
MOTOROLA 14-45
USERS MANUAL

SCCxR1 SCI Control Register 1
MSB 0 0 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 LOOPS 2 WOM S 3 ILT 4 PT 5 PE 6 M 7 WAKE 8 TIE 9 TCIE 10 RIE
0x30 500A, 0x30 5022

11 ILIE 12 TE 13 RE 14 RWU LSB 15 SBK
Table 14-24 SCCxR1 Bit Descriptions

Bit(s) 0 1 Name LOOPS Reserved Loop mode 0 = Normal SCI operation, no looping, feedback path disabled. 1 = SCI test operation, looping, feedback path enabled. Wired-OR mode for SCI Pins 0 = If configured as an output, TXD is a normal CMOS output. 1 = If configured as an output, TXD is an open drain output. Idle-line detect type. Refer to 14.8.7.8 Idle-Line Detection. 0 = Short idle-line detect (start count on first one). 1 = Long idle-line detect (start count on first one after stop bit(s)). Parity type. Refer to 14.8.7.4 Parity Checking. 0 = Even parity. 1 = Odd parity. Parity enable. Refer to 14.8.7.4 Parity Checking. 0 = SCI parity disabled. 1 = SCI parity enabled. Mode select. Refer to 14.8.7.2 Serial Formats. 0 = 10-bit SCI frame. 1 = 11-bit SCI frame. Wakeup by address mark. Refer to 14.8.7.9 Receiver Wake-Up. 0 = SCI receiver awakened by idle-line detection. 1 = SCI receiver awakened by address mark (last bit set). Transmit interrupt enable 0 = SCI TDRE interrupts disabled. 1 = SCI TDRE interrupts enabled. Transmit complete interrupt enable 0 = SCI TC interrupts disabled. 1 = SCI TC interrupts enabled. Receiver interrupt enable 0 = SCI RDRF and OR interrupts disabled. 1 = SCI RDRF and OR interrupts enabled. Idle-line interrupt enable 0 = SCI IDLE interrupts disabled. 1 = SCI IDLE interrupts enabled. Transmitter enable 0 = SCI transmitter disabled (TXD pin can be used as general-purpose output) 1 = SCI transmitter enabled (TXD pin dedicated to SCI transmitter). Receiver Enable 0 = SCI receiver disabled (RXD pin can be used as general-purpose input). 1 = SCI receiver enabled (RXD pin is dedicated to SCI receiver). Description
WOMS
ILT
PT
PE
WAKE
TIE
TCIE
10
RIE
11
ILIE
12
TE
13
RE
MPC555
/ MPC556
MOTOROLA 14-46
USERS MANUAL

Table 14-24 SCCxR1 Bit Descriptions (Continued)
Bit(s) 14 Name RWU Description Receiver wakeup. Refer to 14.8.7.9 Receiver Wake-Up. 0 = Normal receiver operation (received data recognized). 1 = Wakeup mode enabled (received data ignored until receiver is awakened). Send break 0 = Normal operation. 1 = Break frame(s) transmitted after completion of current frame.
15
SBK
14.8.4 SCI Status Register (SCxSR) SCxSR contains flags that show SCI operating conditions. These flags are cleared either by SCIx hardware or by a read/write sequence. The sequence consists of reading the SCxSR (either the upper byte, lower byte, or the entire half-word) with a flag bit set, then reading (or writing, in the case of flags TDRE and TC) the SCxDR (either the lower byte or the half-word). The contents of the two 16-bit registers SCxSR and SCxDR appear as upper and lower half-words, respectively, when the SCxSR is read into a 32-bit register. An upper byte access of SCxSR is meaningful only for reads. Note that a word read can simultaneously access both registers SCxSR and SCxDR. This action clears the receive status flag bits that were set at the time of the read, but does not clear the TDRE or TC flags. To clear TC, the SCxSR read must be followed by a write to register SCxDR (either the lower byte or the half-word). The TDRE flag in the status register is readonly. If an internal SCI signal for setting a status bit comes after the CPU has read the asserted status bits but before the CPU has read or written the SCxDR, the newly set status bit is not cleared. Instead, SCxSR must be read again with the bit set and SCxDR must be read or written before the status bit is cleared. NOTE None of the status bits are cleared by reading a status bit while it is set and then writing zero to that same bit. Instead, the procedure outlined above must be followed. Note further that reading either byte of SCxSR causes all 16 bits to be accessed, and any status bits already set in either byte are armed to clear on a subsequent read or write of SCxDR. SCxSR SCIx Status Register
MSB 0 1 2 3 RESERVED RESET: 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 4 5 6 7 TDRE 8 TC 9 RDRF 10 RAF
0x30 500C, 0x30 5024

11 IDLE 12 OR 13 NF 14 FE LSB 15 PF
MPC555
/ MPC556
MOTOROLA 14-47
USERS MANUAL

Table 14-25 SCxSR Bit Descriptions
Bit(s) 0:6 Name Reserved Transmit data register empty. TDRE is set when the byte in TDRx is transferred to the transmit serial shifter. If this bit is zero, the transfer is yet to occur and a write to TDRx will overwrite the previous value. New data is not transmitted if TDRx is written without first clearing TDRE. 0 = Transmit data register still contains data to be sent to the transmit serial shifter. 1 = A new character can now be written to the transmit data register. For transmit queue operation, this bit should be ignored by software. Transmit complete. TC is set when the transmitter finishes shifting out all data, queued preambles (mark/idle-line), or queued breaks (logic zero). 0 = SCI transmitter is busy. 1 = SCI transmitter is idle. For transmit queue operation, TC is cleared when SCxSR is read with TC set, followed by a write to SCTQ[0:15]. Receive data register full. RDRF is set when the contents of the receive serial shifter are transferred to register RDRx. If one or more errors are detected in the received word, the appropriate flag(s) (NF, FE, or PF) are set within the same clock cycle. 0 = Receive data register is empty or contains previously read data. 1 = Receive data register contains new data. For receiver queue operation, this bit should be ignored by software. Receiver active flag. RAF indicates whether the receiver is busy. This flag is set when the receiver detects a possible start bit and is cleared when the chosen type of idle line is detected. RAF can be used to reduce collisions in systems with multiple masters. 0 = SCI receiver is idle. 1 = SCI receiver is busy. Idle line detected. IDLE is set when the receiver detects an idle-line condition (reception of a minimum of 10 or 11 consecutive ones as specified by ILT in SCCxR1). This bit is not set by the idleline condition when RWU in SCCxR1 is set. Once cleared, IDLE is not set again until after RDRF is set (after the line is active and becomes idle again). If a break is received, RDRF is set, allowing a subsequent idle line to be detected again. 11 IDLE Under certain conditions, the IDLE flag may be set immediately following the negation of RE in SCCxR1. System designs should ensure this causes no detrimental effects. 0 = SCI receiver did not detect an idle-line condition. 1 = SCI receiver detected an idle-line condition. For receiver queue operation, IDLE is cleared when SCxSR is read with IDLE set, followed by a read of SCRQ[0:15]. Overrun error. OR is set when a new byte is ready to be transferred from the receive serial shifter to register RDRx, and RDRx is already full (RDRF is still set). Data transfer is inhibited until OR is cleared. Previous data in RDRx remains valid, but additional data received during an overrun condition (including the byte that set OR) is lost. 12 OR Note that whereas the other receiver status flags (NF, FE, and PF) reflect the status of data already transferred to RDRx, the OR flag reflects an operational condition that resulted in a loss of data to RDRx. 0 = RDRF is cleared before new data arrives. 1 = RDRF is not cleared before new data arrives. Description
TDRE
TC
RDRF
10
RAF
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/ MPC556
MOTOROLA 14-48
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Table 14-25 SCxSR Bit Descriptions (Continued)
Bit(s) Name Description Noise error flag. NF is set when the receiver detects noise on a valid start bit, on any of the data bits, or on the stop bit(s). It is not set by noise on the idle line or on invalid start bits. Each bit is sampled three times for noise. If the three samples are not at the same logic level, the majority value is used for the received data value, and NF is set. NF is not set until the entire frame is received and RDRF is set. 13 NF Although no interrupt is explicitly associated with NF, an interrupt can be generated with RDRF, and the interrupt handler can check NF. 0 = No noise detected in the received data. 1 = Noise detected in the received data. For receiver queue operation NF is cleared when SCxSR is read with NF set, followed by a read of SCRQ[0:15]. Framing error. FE is set when the receiver detects a zero where a stop bit (one) was expected. A framing error results when the frame boundaries in the received bit stream are not synchronized with the receiver bit counter. FE is not set until the entire frame is received and RDRF is set. 14 FE Although no interrupt is explicitly associated with FE, an interrupt can be generated with RDRF, and the interrupt handler can check FE. 0 = No framing error detected in the received data. 1 = Framing error or break detected in the received data. Parity error. PF is set when the receiver detects a parity error. PF is not set until the entire frame is received and RDRF is set. 15 PF Although no interrupt is explicitly associated with PF, an interrupt can be generated with RDRF, and the interrupt handler can check PF. 0 = No parity error detected in the received data. 1 = Parity error detected in the received data.
14.8.5 SCI Data Register (SCxDR) The SCxDR consists of two data registers located at the same address. The receive data register (RDRx) is a read-only register that contains data received by the SCI serial interface. Data is shifted into the receive serial shifter and is transferred to RDRx. The transmit data register (TDRx) is a write-only register that contains data to be transmitted. Data is first written to TDRx, then transferred to the transmit serial shifter, where additional format bits are added before transmission. SCxDR SCI Data Register
MSB 0 1 2 3 RESERVED RESET: 0 0 0 0 0 0 0 U U U U U U U U U 4 5 6 7 8 9 10
0x30 500E, 0x30 5026

11 12 13 14 LSB 15
R8/T8 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0
MPC555
/ MPC556
MOTOROLA 14-49
USERS MANUAL

Table 14-26 SCxSR Bit Descriptions
Bit(s) 0:6 Name Reserved R[7:0]/T[7:0] contain either the eight data bits received when SCxDR is read, or the eight data bits to be transmitted when SCxDR is written. R8/T8 are used when the SCI is configured for nine-bit operation (M = 1). When the SCI is configured for 8-bit operation, R8/T8 have no meaning or effect. Accesses to the lower byte of SCxDR triggers the mechanism for clearing the status bits or for initiating transmissions whether byte, half-word, or word accesses are used. Description
7:15
R[8:0]/ T[8:0]
14.8.6 SCI Pins The RXD1 and RXD2 pins are the receive data pins for the SCI1 and SCI2, respectively. TXD1 and TXD2 are the transmit data pins for the two SCI modules. An external clock pin, ECK, is common to both SCIs. The pins and their functions are listed in Table 14-27. Table 14-27 SCI Pin Functions
Pin Names Receive Data Transmit Data Mnemonic RXD1, RXD2 TXD1, TXD2 Mode Receiver disabled Receiver enabled Transmitter disabled Transmitter enabled Receiver disabled Receiver enabled Transmitter disabled Transmitter enabled Function General purpose input Serial data input to SCI General purpose output Serial data output from SCI Not used Alternate input source to baud Not used Alternate input source to baud
External Clock
ECK
14.8.7 SCI Operation The SCI can operate in polled or interrupt-driven mode. Status flags in SCxSR reflect SCI conditions regardless of the operating mode chosen. The TIE, TCIE, RIE, and ILIE bits in SCCxR1 enable interrupts for the conditions indicated by the TDRE, TC, RDRF, and IDLE bits in SCxSR, respectively. 14.8.7.1 Definition of Terms Bit-time The time required to transmit or receive one bit of data, which is equal to one cycle of the baud frequency. Start bit One bit-time of logic zero that indicates the beginning of a data frame. A start bit must begin with a one-to-zero transition and be preceded by at least three receive time samples of logic one. Stop bit One bit-time of logic one that indicates the end of a data frame. Frame A complete unit of serial information. The SCI can use 10-bit or 11-bit frames. Data frame A start bit, a specified number of data or information bits, and at least one stop bit. Idle frame A frame that consists of consecutive ones. An idle frame has no start bit.
MPC555
/ MPC556
MOTOROLA 14-50
USERS MANUAL

Break frame A frame that consists of consecutive zeros. A break frame has no stop bits. 14.8.7.2 Serial Formats All data frames must have a start bit and at least one stop bit. Receiving and transmitting devices must use the same data frame format. The SCI provides hardware support for both 10-bit and 11-bit frames. The M bit in SCCxR1 specifies the number of bits per frame. The most common data frame format for NRZ (non-return to zero) serial interfaces is one start bit, eight data bits (LSB first), and one stop bit (ten bits total). The most common 11-bit data frame contains one start bit, eight data bits, a parity or control bit, and one stop bit. Ten-bit and 11-bit frames are shown in Table 14-28.
Table 14-28 Serial Frame Formats

10-bit Frames Start 1 1 1 Start 1 1 Data 7 7 8 11-bit Frames Data 7 8 Parity/Control 1 1 Stop 2 1 Parity/Control 1 Stop 2 1 1
14.8.7.3 Baud Clock The SCI baud rate is programmed by writing a 13-bit value to the SCxBR field in SCI control register zero (SCCxR0). The baud rate is derived from the MCU IMB clock by a modulus counter. Writing a value of zero to SCxBR[12:0] disables the baud rate generator. The baud rate is calculated as follows: f SYS = -----------------------32 SCxBR or f SYS = -----------------------------------------------------32 SCI Baud Rate Desired
SCI Baud Rate
SCxBR
where SCxBR is in the range {1, 2, 3, ..., 8191}.
MPC555
/ MPC556
MOTOROLA 14-51
USERS MANUAL

The SCI receiver operates asynchronously. An internal clock is necessary to synchronize with an incoming data stream. The SCI baud rate generator produces a receive time sampling clock with a frequency 16 times that of the SCI baud rate. The SCI determines the position of bit boundaries from transitions within the received waveform, and adjusts sampling points to the proper positions within the bit period. Table 14-29 shows possible baud rates for a 40-MHz IMB clock. The maximum baud rate with this IMB clock speed is 1250 Kbaud. Table 14-29 Examples of SCIx Baud Rates1
Nominal Baud Rate 1,250,000.00 57,600.00 38,400.00 32,768.00 28,800.00 19,200.00 14,400.00 9,600.00 4,800.00 2,400.00 1,200.00 600.00 300.00 Actual Baud Rate 1,250,000.00 56,818.18 37,878.79 32,894.74 29,069.77 19,230.77 14,367.81 9,615.38 4,807.69 2,399.23 1,199.62 600.09 299.98 Percent Error 0.00 -1.36 -1.36 0.39 0.94 0.16 -0.22 0.16 0.16 -0.03 -0.03 0.02 -0.01 Value of SCxBR 1 22 33 38 43 65 87 130 260 521 1042 2083 4167
NOTES: 1. These rates are based on a 40-MHz IMB clock.
14.8.7.4 Parity Checking The PT bit in SCCxR1 selects either even (PT = 0) or odd (PT = 1) parity. PT affects received and transmitted data. The PE bit in SCCxR1 determines whether parity checking is enabled (PE = 1) or disabled (PE = 0). When PE is set, the MSB of data in a frame (i.e., the bit preceding the stop bit) is used for the parity function. For transmitted data, a parity bit is generated. For received data, the parity bit is checked. When parity checking is enabled, the PF bit in the SCI status register (SCxSR) is set if a parity error is detected. Enabling parity affects the number of data bits in a frame, which can in turn affect frame size. Table 14-24 shows possible data and parity formats. 14.8.7.5 Transmitter Operation The transmitter consists of a serial shifter and a parallel data register (TDRx) located in the SCI data register (SCxDR). The serial shifter cannot be directly accessed by the CPU. The transmitter is double-buffered, which means that data can be loaded into the TDRx while other data is shifted out. The TE bit in SCCxR1 enables (TE = 1) and disables (TE = 0) the transmitter. The shifter output is connected to the TXD pin while the transmitter is operating (TE = 1, or TE = 0 and transmission in progress). Wired-OR operation should be specified when more than one transmitter is used on the same SCI bus. The WOMS bit in
MPC555
/ MPC556
MOTOROLA 14-52
USERS MANUAL

SCCxR1 determines whether TXD is an open drain (wired-OR) output or a normal CMOS output. An external pull-up resistor on TXD is necessary for wired-OR operation. WOMS controls TXD function, regardless of whether the pin is used by the SCI or as a general-purpose output pin. Data to be transmitted is written to SCxDR, then transferred to the serial shifter. Before writing to TDRx, the user should check the transmit data register empty (TDRE) flag in SCxSR. When TDRE = 0, the TDRx contains data that has not been transferred to the shifter. Writing to SCxDR again overwrites the data. If TDRE = 1, then TDRx is empty, and new data may be written to TDRx, clearing TDRE. As soon as the data in the transmit serial shifter has shifted out and if a new data frame is in TDRx (TDRE = 0), then the new data is transferred from TDRx to the transmit serial shifter and TDRE is set automatically. An interrupt may optionally be generated at this point. The transmission complete (TC) flag in SCxSR shows transmitter shifter state. When TC = 0, the shifter is busy. TC is set when all shifting operations are completed. TC is not automatically cleared. The processor must clear it by first reading SCxSR while TC is set, then writing new data to SCxDR, or writing to SCTQ[0:15] for transmit queue operation. The state of the serial shifter is checked when the TE bit is set. If TC = 1, an idle frame is transmitted as a preamble to the following data frame. If TC = 0, the current operation continues until the final bit in the frame is sent, then the preamble is transmitted. The TC bit is set at the end of preamble transmission. The SBK bit in SCCxR1 is used to insert break frames in a transmission. A non-zero integer number of break frames are transmitted while SBK is set. Break transmission begins when SBK is set, and ends with the transmission in progress at the time either SBK or TE is cleared. If SBK is set while a transmission is in progress, that transmission finishes normally before the break begins. To ensure the minimum break time, toggle SBK quickly to one and back to zero. The TC bit is set at the end of break transmission. After break transmission, at least one bit-time of logic level one (mark idle) is transmitted to ensure that a subsequent start bit can be detected. If TE remains set, after all pending idle, data and break frames are shifted out, TDRE and TC are set and TXD is held at logic level one (mark). When TE is cleared, the transmitter is disabled after all pending idle, data, and break frames are transmitted. The TC flag is set, and control of the TXD pin reverts to PQSPAR and DDRQS. Buffered data is not transmitted after TE is cleared. To avoid losing data in the buffer, do not clear TE until TDRE is set. Some serial communication systems require a mark on the TXD pin even when the transmitter is disabled. Configure the TXD pin as an output, then write a one to either QDTX1 or QDTX2 of the PORTQS register. See 14.6.1. When the transmitter releases control of the TXD pin, it reverts to driving a logic one output.
MPC555
/ MPC556
MOTOROLA 14-53
USERS MANUAL

To insert a delimiter between two messages, to place non-listening receivers in wakeup mode between transmissions, or to signal a re-transmission by forcing an idle-line, clear and then set TE before data in the serial shifter has shifted out. The transmitter finishes the transmission, then sends a preamble. After the preamble is transmitted, if TDRE is set, the transmitter marks idle. Otherwise, normal transmission of the next sequence begins. Both TDRE and TC have associated interrupts. The interrupts are enabled by the transmit interrupt enable (TIE) and transmission complete interrupt enable (TCIE) bits in SCCxR1. Service routines can load the last data frame in a sequence into SCxDR, then terminate the transmission when a TDRE interrupt occurs. Two SCI messages can be separated with minimum idle time by using a preamble of 10 bit-times (11 if a 9-bit data format is specified) of marks (logic ones). Follow these steps: 1. Write the last data frame of the first message to the TDRx 2. Wait for TDRE to go high, indicating that the last data frame is transferred to the transmit serial shifter 3. Clear TE and then set TE back to one. This queues the preamble to follow the stop bit of the current transmission immediately. 4. Write the first data frame of the second message to register TDRx In this sequence, if the first data frame of the second message is not transferred to TDRx prior to the finish of the preamble transmission, then the transmit data line (TXDx pin) marks idle (logic one) until TDRx is written. In addition, if the last data frame of the first message finishes shifting out (including the stop bit) and TE is clear, TC goes high and transmission is considered complete. The TXDx pin reverts to being a general-purpose output pin. 14.8.7.6 Receiver Operation The receiver can be divided into two segments. The first is the receiver bit processor logic that synchronizes to the asynchronous receive data and evaluates the logic sense of each bit in the serial stream. The second receiver segment controls the functional operation and the interface to the CPU including the conversion of the serial data stream to parallel access by the CPU. Receiver Bit Processor The receiver bit processor contains logic to synchronize the bit-time of the incom-ing data and to evaluate the logic sense of each bit. To accomplish this an RT clock, which is 16 times the baud rate, is used to sample each bit. Each bit-time can thus be divided into 16 time periods called RT1RT16. The receiver looks for a possible start bit by watching for a high-to-low transition on the RXDx pin and by assigning the RT time labels appropriately. When the receiver is enabled by writing RE in SCCxR1 to one, the receiver bit processor logic begins an asynchronous search for a start bit. The goal of this search is to gain synchronization with a frame. The bit-time synchronization is done at the beginning of each frame so that small differences in the baud rate of the receiver and transmitter are not cumulative. SCIx also synchronizes on all one-to-zero transitions
MPC555
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in the serial data stream, which makes SCIx tolerant to small frequency variations in the received data stream. The sequence of events used by the receiver to find a start bit is listed below. 1. Sample RXDx input during each RT period and maintain these samples in a serial pipeline that is three RT periods deep. 2. If RXDx is low during this RT period, go to step 1. 3. If RXDx is high during this RT period, store sample and proceed to step 4. 4. If RXDx is low during this RT period, but not high for the previous three RT periods (which is noise only), set an internal working noise flag and go to step 1, since this transition was not a valid start bit transition. 5. If RXDx is low during this RT period and has been high for the previous three RT periods, call this period RT1, set RAF, and proceed to step 6. 6. Skip RT2 but place RT3 in the pipeline and proceed to step 7. 7. Skip RT4 and sample RT5. If both RT3 and RT5 are high (RT1 was noise only), set an internal working noise flag. Go to step 3 and clear RAF. Otherwise, place RT5 in the pipeline and proceed to step 8. 8. Skip RT6 and sample RT7. If any two of RT3, RT5, or RT7 is high (RT1 was noise only), set an internal working noise flag. Go to step 3 and clear RAF. Otherwise, place RT7 in the pipeline and proceed to step 9. 9. A valid start bit is found and synchronization is achieved. From this point on until the end of the frame, the RT clock will increment starting over again with RT1 on each one-to-zero transition or each RT16. The beginning of a bit-time is thus defined as RT1 and the end of a bit-time as RT16. Upon detection of a valid start bit, synchronization is established and is maintained through the reception of the last stop bit, after which the procedure starts all over again to search for a new valid start bit. During a frame's reception, SCIx resynchronizes the RT clock on any one-to-zero transitions. Additional logic in the receiver bit processor determines the logic level of the re-ceived bit and implements an advanced noise-detection function. During each bit-time of a frame (including the start and stop bits), three logic-sense samples are taken at RT8, RT9, and RT10. The logic sense of the bit-time is decided by a majority vote of these three samples. This logic level is shifted into register RDRx for every bit except the start and stop bits. If RT8, RT9, and RT10 do not all agree, an internal working noise flag is set. Additionally for the start bit, if RT3, RT5, and RT7 do not all agree, the internal working noise flag is set. If this flag is set for any of the bit-times in a frame, the NF flag in SCxSR is set concurrently with the RDRF flag in SCxSR when the data is transferred to register RDRx. The user must determine if the data received with NF set is valid. Noise on the RXDx pin does not necessarily corrupt all data. The operation of the receiver bit processor is shown in Figure 14-14. This example demonstrates the search for a valid start bit and the synchronization procedure as outlined above. The possibilities of noise durations greater than one bit-time are not considered in this examples. / MPC556
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Perceived Start Bit Actual Start Bit LSB
1 1 1 1 1 1 1 1 1 0 R T 1 * R T 1 * R T 1 * R T 1 * R T 1 * R T 1 * R T 1 * R T 1 *
0 0 0 0 R T 1 1 R T 1 2 R T 1 3 R T 1 4 R T 1 5 R R R R T T T T 1 1 2 3 6 *
R R R R R R R R R R R T T T T T T T T T T T 1 1 2 3 4 5 6 7 8 9 1 * 0
* Restart RT Clock
Figure 14-14 Start Search Example 14.8.7.7 Receiver Functional Operation The RE bit in SCCxR1 enables (RE = 1) and disables (RE = 0) the receiver. The receiver contains a receive serial shifter and a parallel receive data register (RDRx) located in the SCI data register (SCxDR). The serial shifter cannot be directly accessed by the CPU. The receiver is double-buffered, allowing data to be held in the RDRx while other data is shifted in. Receiver bit processor logic drives a state machine that determines the logic level for each bit-time. This state machine controls when the bit processor logic is to sample the RXD pin and also controls when data is to be passed to the receive serial shifter. A receive time clock is used to control sampling and synchronization. Data is shifted into the receive serial shifter according to the most recent synchronization of the receive time clock with the incoming data stream. From this point on, data movement is synchronized with the MCU IMB clock. Operation of the receiver state machine is detailed in the Queued Serial Module Reference Manual (QSMRM/AD). The number of bits shifted in by the receiver depends on the serial format. However, all frames must end with at least one stop bit. When the stop bit is received, the frame is considered to be complete, and the received data in the serial shifter is transferred to the RDRx. The receiver data register flag (RDRF) is set when the data is transferred. The stop bit is always a logic one. If a logic zero is sensed during this bit-time, the FE flag in SCxSR is set. A framing error is usually caused by mismatched baud rates between the receiver and transmitter or by a significant burst of noise. Note that a framing error is not always detected; the data in the expected stop bit-time may happen to be a logic one. Noise errors, parity errors, and framing errors can be detected while a data stream is being received. Although error conditions are detected as bits are received, the noise
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flag (NF), the parity flag (PF), and the framing error (FE) flag in SCxSR are not set until data is transferred from the serial shifter to the RDRx. RDRF must be cleared before the next transfer from the shifter can take place. If RDRF is set when the shifter is full, transfers are inhibited and the overrun error (OR) flag in SCxSR is set. OR indicates that the RDRx needs to be serviced faster. When OR is set, the data in the RDRx is preserved, but the data in the serial shifter is lost. When a completed frame is received into the RDRx, either the RDRF or OR flag is always set. If RIE in SCCxR1 is set, an interrupt results whenever RDRF is set. The receiver status flags NF, FE, and PF are set simultaneously with RDRF, as appropriate. These receiver flags are never set with OR because the flags apply only to the data in the receive serial shifter. The receiver status flags do not have separate interrupt enables, since they are set simultaneously with RDRF and must be read by the user at the same time as RDRF. When the CPU reads SCxSR and SCxDR in sequence, it acquires status and data, and also clears the status flags. Reading SCxSR acquires status and arms the clearing mechanism. Reading SCxDR acquires data and clears SCxSR. 14.8.7.8 Idle-Line Detection During a typical serial transmission, frames are transmitted isochronically and no idle time occurs between frames. Even when all the data bits in a frame are logic ones, the start bit provides one logic zero bit-time during the frame. An idle line is a sequence of contiguous ones equal to the current frame size. Frame size is determined by the state of the M bit in SCCxR1. The SCI receiver has both short and long idle-line detection capability. Idle-line detection is always enabled. The idle-line type (ILT) bit in SCCxR1 determines which type of detection is used. When an idle-line condition is detected, the IDLE flag in SCxSR is set. For short idle-line detection, the receiver bit processor counts contiguous logic one bittimes whenever they occur. Short detection provides the earliest possible recognition of an idle-line condition, because the stop bit and contiguous logic ones before and after it are counted. For long idle-line detection, the receiver counts logic ones after the stop bit is received. Only a complete idle frame causes the IDLE flag to be set. In some applications, software overhead can cause a bit-time of logic level one to occur between frames. This bit-time does not affect content, but if it occurs after a frame of ones when short detection is enabled, the receiver flags an idle line. When the ILIE bit in SCCxR1 is set, an interrupt request is generated when the IDLE flag is set. The flag is cleared by reading SCxSR and SCxDR in sequence. For receiver queue operation, IDLE is cleared when SCxSR is read with IDLE set, followed by a read of SCRQ[0:15]. IDLE is not set again until after at least one frame has been received (RDRF = 1). This prevents an extended idle interval from causing more than one interrupt.
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14.8.7.9 Receiver Wake-Up The receiver wake-up function allows a transmitting device to direct a transmission to a single receiver or to a group of receivers by sending an address frame at the start of a message. Hardware activates each receiver in a system under certain conditions. Resident software must process address information and enable or disable receiver operation. A receiver is placed in wake-up mode by setting the RWU bit in SCCxR1. While RWU is set, receiver status flags and interrupts are disabled. Although the software can clear RWU, it is normally cleared by hardware during wake-up. The WAKE bit in SCCxR1 determines which type of wake-up is used. When WAKE = 0, idle-line wake-up is selected. When WAKE = 1, address-mark wake-up is selected. Both types require a software-based device addressing and recognition scheme. Idle-line wake-up allows a receiver to sleep until an idle line is detected. When an idle line is detected, the receiver clears RWU and wakes up. The receiver waits for the first frame of the next transmission. The data frame is received normally, transferred to the RDRx, and the RDRF flag is set. If software does not recognize the address, it can set RWU and put the receiver back to sleep. For idle-line wake-up to work, there must be a minimum of one frame of idle line between transmissions. There must be no idle time between frames within a transmission. Address mark wake-up uses a special frame format to wake up the receiver. When the MSB of an address-mark frame is set, that frame contains address information. The first frame of each transmission must be an address frame. When the MSB of a frame is set, the receiver clears RWU and wakes up. The data frame is received normally, transferred to the RDRx, and the RDRF flag is set. If software does not recognize the address, it can set RWU and put the receiver back to sleep. Address mark wake-up allows idle time between frames and eliminates idle time between transmissions. However, there is a loss of efficiency because of an additional bit-time per frame. 14.8.7.10 Internal Loop Mode The LOOPS bit in SCCxR1 controls a feedback path in the data serial shifter. When LOOPS is set, the SCI transmitter output is fed back into the receive serial shifter. TXD is asserted (idle line). Both transmitter and receiver must be enabled before entering loop mode. 14.9 SCI Queue Operation 14.9.1 Queue Operation of SCI1 for Transmit and Receive The SCI1 serial module allows for queueing on transmit and receive data frames. In the standard mode, in which the queue is disabled, the SCI1 operates as previously defined (i.e. transmit and receive operations done via SC1DR). However, if the SCI1 queue feature is enabled (by setting the QTE and/or QRE bits within QSCI1CR) a set of 16 entry queues is allocated for the receive and/or transmit operation. Through soft-
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ware control the queue is capable of continuous receive and transfer operations within the SCI1 serial unit. 14.9.2 Queued SCI1 Status and Control Registers The SCI1 queue uses the following registers: QSCI1 control register (QSCI1CR, address offset 0x28) QSCI1 status register (QSCI1SR, address offset 0x2A) 14.9.2.1 QSCI1 Control Register QSCI1CR QSCI1 Control Register
MSB
0x30 5028
LSB 7 QBHEI 8 0 9 QTE 10 QRE 11 QTW E 12 13 14 15
1 QTPNT
4 QTHFI
QBH- QTHE FI I
QTSZ
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Table 14-30 QSCI1CR Bit Descriptions
Bit(s) 0:3 Name QTPNT Description Queue transmit pointer. QTPNT is a 4-bit counter used to indicate the next data frame within the transmit queue to be loaded into the SC1DR. This feature allows for ease of testability. This field is writable in test mode only; otherwise it is read-only. Receiver queue top-half full interrupt. When set, QTHFI enables an SCI1 interrupt whenever the QTHF flag in QSCI1SR is set. The interrupt is blocked by negating QTHFI. This bit refers to the queue locations SCRQ[0:7]. 0 = QTHF interrupt inhibited 1 = Queue top-half full (QTHF) interrupt enabled Receiver queue bottom-half full interrupt. When set, QBHFI enables an SCI1 interrupt whenever the QBHF flag in QSCI1SR is set. The interrupt is blocked by negating QBHFI. This bit refers to the queue locations SCRQ[8:15]. 0 = QBHF interrupt inhibited 1 = Queue bottom-half full (QBHF) interrupt enabled Transmitter queue top-half empty interrupt. When set, QTHEI enables an SCI1 interrupt whenever the QTHE flag in QSCI1SR is set. The interrupt is blocked by negating QTHEI. This bit refers to the queue locations SCTQ[0:7]. 0 = QTHE interrupt inhibited 1 = Queue top-half empty (QTHE) interrupt enabled Transmitter queue bottom-half empty interrupt. When set, QBHEI enables an SCI1 interrupt whenever the QBHE flag in QSCI1SR is set. The interrupt is blocked by negating QBHEI. This bit refers to the queue locations SCTQ[8:15]. 0 = QBHE interrupt inhibited 1 = Queue bottom-half empty (QBHE) interrupt enabled Reserved Queue transmit enable. When set, the transmit queue is enabled and the TDRE bit should be ignored by software. The TC bit is redefined to indicate when the entire queue is finished transmitting. When clear, the SCI1 functions as described in the previous sections and the bits related to the queue (Section 5.5 and its subsections) should be ignored by software with the exception of QTE. 0 = Transmit queue is disabled 1 = Transmit queue is enabled Queue receive enable. When set, the receive queue is enabled and the RDRF bit should be ignored by software. When clear, the SCI1 functions as described in the previous sections and the bits related to the queue (Section 5.5 and its subsections) should be ignored by software with the exception of QRE. 0 = Receive queue is disabled 1 = Receive queue is enabled Queue transmit wrap enable. When set, the transmit queue is allowed to restart transmitting from the top of the queue after reaching the bottom of the queue. After each wrap of the queue, QTWE is cleared by hardware. 0 = Transmit queue wrap feature is disabled 1 = Transmit queue wrap feature is enabled Queue transfer size. The QTSZ bits allow programming the number of data frames to be transmitted. From 1 (QTSZ = 0b0000) to 16 (QTSZ = 0b1111) data frames can be specified. QTSZ is loaded into QPEND initially or when a wrap occurs.
QTHFI
QBHFI
QTHEI
QBHEI
QTE
10
QRE
11
QTWE
12:15
QTSZ
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14.9.2.2 QSCI1 Status Register QSCI1SR QSCI1 Status Register
MSB 0 1 RESERVED RESET: 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 2 3 QOR 4 5 6 7 8 9 10 11 12 13 14
0x30 502A
LSB 15
QTHF QBHF QTHE QBHE
QRPNT
QPEND
Table 14-31 QSCI1SR Bit Descriptions

Bit(s) 0:2 Name Reserved Receiver queue overrun error. The QOR is set when a new data frame is ready to be transferred from the SC1DR to the queue and the queue is already full (QTHF or QBHF are still set). Data transfer is inhibited until QOR is cleared. Previous data transferred to the queue remains valid. Additional data received during a queue overrun condition is not lost provided the receive queue is re-enabled before OR (SC1SR) is set. The OR flag is set when a new data frame is received in the shifter but the data register (SC1DR) is still full. The data in the shifter that generated the OR assertion is overwritten by the next received data frame, but the data in the SC1DR is not lost. 0 = The queue is empty before valid data is in the SC1DR 1 = The queue is not empty when valid data is in the SC1DR Receiver queue top-half full. QTHF is set when the receive queue locations SCRQ[0:7] are completely filled with new data received via the serial shifter. QTHF is cleared when register QSCI1SR is read with QTHF set, followed by a write of QTHF to zero. 0 = The queue locations SCRQ[0:7] are partially filled with newly received data or is empty 1 = The queue locations SCRQ[0:7] are completely full of newly received data Receiver queue bottom-half full. QBHF is set when the receive queue locations SCRQ[8:15] are completely filled with new data received via the serial shifter. QBHF is cleared when register QSCI1SR is read with QBHF set, followed by a write of QBHF to zero. 0 = The queue locations SCRQ[8:15] are partially filled with newly received data or is empty 1 = The queue locations SCRQ[8:15] are completely full of newly received data Transmitter queue top-half empty. QTHE is set when all the data frames in the transmit queue locations SCTQ[0:7] have been transferred to the transmit serial shifter. QTHE is cleared when register QSCI1SR is read with QTHE set, followed by a write of QTHE to zero. 0 = The queue locations SCTQ[0:7] still contain data to be sent to the transmit serial shifter 1 = New data may now be written to the queue locations SCTQ[0:7] Transmitter queue bottom-half empty. QBHE is set when all the data frames in the transmit queue locations SCTQ[8:15] has been transferred to the transmit serial shifter. QBHE is cleared when register QSCI1SR is read with QBHE set, followed by a write of QBHE to zero. 0 = The queue locations SCTQ[8:15] still contain data to be sent to the transmit serial shifter 1 = New data may now be written to the queue locations SCTQ[8:15] Queue receive pointer. QRPNT is a 4-bit counter used to indicate the position where the next valid data frame will be stored within the receive queue. This field is writable in test mode only; otherwise it is read-only. Queue pending. QPEND is a 4-bit decrementer used to indicate the number of data frames in the queue that are awaiting transfer to the SC1DR. This field is writable in test mode only; otherwise it is read-only. From 1 (QPEND = 0b0000) to 16 (or done, QPEND = 1111) data frames can be specified. Description
QOR
QTHF
QBHF
QTHE
QBHE
8:11
QRPNT
12:15
QPEND
14.9.3 QSCI1 Transmitter Block Diagram The block diagram of the enhancements to the SCI transmitter is shown in Figure 1415.
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SCI Interrupt Request
Queue Control
QTE QPEND[0:3] QTHE QTSZ[0:3] QTHEI QBHEI QTWE
Queue Status
QBHE
Queue Control Logic 4-bits SCI1 Non-Queue Operation SCTQ[0] SCTQ[1]

data bus
SC1DR Tx BUFFER
9-bit 16:1 Mux
SCTQ[15] Transmitter Baud Rate Clock
10 (11) - BIT Tx Shift Register
START
STOP
TxD
H (8) 7 6 5 4 3 2 1 0 L
Figure 14-15 Queue Transmitter Block Enhancements 14.9.4 QSCI1 Additional Transmit Operation Features Available on a single SCI channel (SCI1) implemented by the queue transmit enable (QTE) bit set by software. When enabled, (QTE = 1) the TDRE bit should be ignored by software and the TC bit is redefined (as described later). When the queue is disabled (QTE = 0), the SCI functions in single buffer transfer mode where the queue size is set to one (QTSZ = 0000), and TDRE and TC function as previously defined. Locations SCTQ[0:15] can be used as general purpose 9-bit registers. All other bits pertaining to the queue should be ignored by software. Programmable queue up to 16 transmits (SCTQ[0:15]) which may allow for infinite and continuous transmits. Available transmit wrap function to prevent message breaks for transmits greater
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than 16. This is achieved by the transmit wrap enable (QTWE) bit. When QTWE is set, the hardware is allowed to restart transmitting from the top of the queue (SCTQ[0]). After each wrap, QTWE is cleared by hardware. Transmissions of more than 16 data frames must be performed in multiples of 16 (QTSZ = 0b1111) except for the last set of transmissions. For any single non-continuous transmissions of 16 or less or the last transmit set composed of 16 or fewer data frames, the user is allowed to program QTSZ to the corresponding value of 16 or less where QTWE = 0. Interrupt generation when the top half (SCTQ[0:7]) of the queue has been emptied (QTHE) and the bottom half (SCTQ[8:15]) of the queue has been emptied (QBHE). This may allow for uninterrupted and continuous transmits by indicating to the CPU that it can begin refilling the queue portion that is now emptied. The QTHE bit is set by hardware when the top half is empty or the transmission has completed. The QTHE bit is cleared when the QSCI1SR is read with QTHE set, followed by a write of QTHE to zero. The QBHE bit is set by hardware when the bottom half is empty or the transmission has completed. The QBHE bit is cleared when the QSCI1SR is read with QBHE set, followed by a write of QBHE to zero. In order to implement the transmit queue, QTE must be set (QSCI1CR), TE must be set (SCC1R1), QTHE must be cleared (QSCI1SR), and TDRE must be set (SC1SR). Enable and disable options for the interrupts QTHE and QBHE as controlled by QTHEI and QBHEI respectfully. Programmable 4-bit register queue transmit size (QTSZ) for configuring the queue to any size up to 16 transfers at a time. This value may be rewritten after transmission has started to allow for the wrap feature. 4-bit status register to indicate the number of data transfers pending (QPEND). This register counts down to all 0s where the next count rolls over to all 1s. This counter is writable in test mode; otherwise it is read-only. 4-bit counter (QTPNT) is used as a pointer to indicate the next data frame within the transmit queue to be loaded into the SC1DR. This counter is writable in test mode; otherwise it is read-only. A transmit complete (TC) bit re-defined when the queue is enabled (QTE = 1) to indicate when the entire queue (including when wrapped) is finished transmitting. This is indicated when QPEND = 1111 and the shifter has completed shifting data out. TC is cleared when the SCxSR is read with TC = 1 followed by a write to SCTQ[0:15]. If the queue is disabled (QTE = 0), the TC bit operates as originally designed. When the transmit queue is enabled (QTE = 1), writes to the transmit data register (SC1DR) have no effect.
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14.9.5 QSCI1 Transmit Flow Chart Implementing the Queue
Refers to Action Performed in Parallel TE=0, TC=1, TDRE=1 QTE=0, QTPNT=0, QTWE=0 QTHEI=0, QTHE=1 QBHEI=0, QBHE=1 Reset Hardware Software
Set QTE=1 Set QTHEI, QBHEI Write QTSZ=n Clear QTHE, TC Write SCTQ[0:n] Set TE
QTE=1, TE=1 TDRE=1, QTHE=0? Yes Load QPEND with QTSZ, Reset QTPNT to 0000
No
No QTE, TE=1? Yes Load TDR (SC1DR) With SCTQ[QTPNT] Shift Data Out(TDRE=1) Decrement QPEND, Increment QTPNT Write QTSZ for Wrap Clear QTHE Possible Set of QTWE
Yes QTPNT=1000? Clear QBHE No Yes QBHE=0? Yes Set QBHE QTPNT = 1111? no No QPEND = 1111 yes Clear QTWE Yes QTWE = 1 & QTHE = 0? no Set QTHE, QBHE Clear QTE No Set QTHE
Figure 14-16 Queue Transmit Flow

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Reset
Enable Queue Interrupt QTHEI = 1, If Transmitting Greater than 16 Data Frames, Enable Queue Interrupt QBHEI = 1
Configure the Transmit Flow for First Use of the Queue.
Write QTSZ=n for First Pass Use of the Queue
Read Status Register with TC = 1, Write SCTQ[0:n] (Clears TC) Read Status Register with QTHE=1 Write QTHE = 0 (and QBHE if Transmitting More than 8 Data Frames)
Set QTE and TE = 1
Yes QTHE = 1? No To Wrap, Write New QTSZ=n Set QTWE (Previous QTSZ Must Have Equaled 16) Read QTHE=1, Write QTHE=0 Write New Data SCTQ[0:7] If Finished Transmitting, Then Clear QTE and/or TE DONE
No QBHE = 1? Yes
If Transmitting Greater Than 8 Data Frames on Wrap Read QBHE=1,Write QBHE=0 Write New Data to SCTQ[8:15]
If Finished Transmitting, Then Clear QTE and/or TE DONE
Figure 14-17 Queue Transmit Software Flow
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14.9.6 Example QSCI1 Transmit for 17 Data Bytes Figure 14-18 below shows a transmission of 17 data frames. The bold type indicates the current value for QTPNT and QPEND. The italic type indicates the action just performed by hardware. Regular type indicates the actions that should be performed by software before the next event.
Transmit Queue Enabled QTSZ=1111 (16 Data Frames) QPEND QTPNT 1111 0000 SCTQ[0]
2 QTHE Interrupt Received QTSZ=1111 (16 Data Frames) QPEND QTPNT 0000 1111 SCTQ[0]
0111 1000
SCTQ[7] SCTQ[8]
1000 0111
0111 1000
SCTQ[7] SCTQ[8]
1000 0111
1111
SCTQ[15]
0000
1111
SCTQ[15]
0000
Write New QTSZ for When Wrap Occurs QTSZ=0 (16+1=17),Set QTWE, Clear QTHE Write SCTQ[0] for 17th Transfer
QBHE Interrupt Received (Wrap Occurred) QPEND 0000 1111
QTSZ=0000 (1 Data Frame) QTPNT 0000 SCTQ[0] 0001
Data to beTransferred 0111 1000 SCTQ[7] Available Register Space SCTQ[8]
1111
SCTQ[15] Load QPEND with QTSZ (0) Clear QTWE Reset QTPNT
Figure 14-18 Queue Transmit Example for 17 Data Bytes

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14.9.7 Example SCI Transmit for 25 Data Bytes Figure 14-19 below is an example of a transmission of 25 data frames.
2
Transmit Queue Enabled QTSZ=1111 (16 Data Frames) QTPNT 0000 SCTQ[0]
QTHE Interrupt Received
QPEND 1111
QTSZ=1111 (16 Data Frames) QTPNT 0000 SCTQ[0]
QPEND 1111
0111
SCTQ[7] SCTQ[8]
1000 0111
0111 1000
SCTQ[7] SCTQ[8]
1000 0111
1000
1111
SCTQ[15]
0000
1111
SCTQ[15]
0000
Write QTSZ = 8 (16 + 9 = 25) Write SCTQ [0:7] for 8 More Data Frames Set QTWE Clear QTHE Data to be Transferred
QBHE Interrupt Received (Wrap Occurred) QTSZ=1000 (9 Data Frames) QTPNT 0000 SCTQ[0] QPEND 1000
QTHE Interrupt Received
Available Register Space
QTSZ=1000 (9 Data Frames) QTPNT 0000 SCTQ[0]
QPEND 1000
0111 1000
SCTQ[7] SCTQ[8]
0001 0000
0111 1000 1001
SCTQ[7] SCTQ[8]
0001 0000 1111
1111
SCTQ[15] Load QPEND with QTSZ Clear QTWE Reset QTPNT Write SCTQ[8] Clear QBHE
1111
SCTQ[15]
Figure 14-19 Queue Transmit Example for 25 Data Frames

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14.9.8 QSCI1 Receiver Block Diagram The block diagram of the enhancements to the SCI receiver is shown below in Figure 14-20.
Receiver Baud Rate Clock
10 (11) - BIT Rx Shift Register 6 5 4 3 2 1 0
RxD
H (8) 7
START
STOP
SCxDR Rx BUFFER
SCRQ[0] SCRQ[1]
16:1 Mux
Data Bus
SCI1 Non-Queue Operation
SCRQ[15] 4-bits
Queue Control Logic
QRPNT[0:3]
QBHFI
QTHFI
QBHF
QTHF
Queue Control
QRE
Queue Status
QOR
SCI Interrupt Request
Figure 14-20 Queue Receiver Block Enhancements 14.9.9 QSCI1 Additional Receive Operation Features Available on a single SCI channel (SCI1) implemented by the queue receiver enable (QRE) bit set by software. When the queue is enabled, software should ignore the RDRF bit. When the queue is disabled (QRE = 0), the SCI functions in single buffer receive mode (as originally designed) and RDRF and OR function as previously defined.
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MOTOROLA 14-68
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Locations SCRQ[0:15] can be used as general purpose 9-bit registers. Software should ignore all other bits pertaining to the queue. Only data that has no errors (FE and PF both false) is allowed into the queue. The status flags FE and PF, if set, reflect the status of data not allowed into the queue. The receive queue is disabled until the error flags are cleared via the original SCI mechanism and the queue is re-initialized. The pointer QRPNT indicates the queue location where the data frame would have been stored. Queue size capable to receive up to 16 data frames (SCRQ[0:15]) which may allow for infinite and continuous receives. Interrupt generation can occur when the top half (SCRQ[0:7]) of the queue has been filled (QTHF) and the bottom half (SCRQ[8:15]) of the queue has been filled (QBHF). This may allow for uninterrupted and continuous receives by indicating to the CPU to start reading the queue portion that is now full. The QTHF bit is set by hardware when the top half is full. The QTHF bit is cleared when the SCxSR is read with QTHF set, followed by a write of QTHF to zero. The QBHF bit is set by hardware when the bottom half is full. The QBHF bit is cleared when the SCxSR is read with QBHF set, followed by a write of QBHF to zero. In order to implement the receive queue, the following conditions must be met: QRE must be set (QSCI1CR); RE must be set (SCC1R1); QOR and QTHF must be cleared (QSCI1SR); and OR, PF, and FE must be cleared (SC1SR). Enable and disable options for the interrupts QTHF and QBHF as controlled by the QTHFI and QBHFI, respectfully. 4-bit counter (QRPNT) is used as a pointer to indicate where the next valid data frame will be stored. A queue overrun error flag (QOR) to indicate when the queue is already full when another data frame is ready to be stored into the queue (similar to the OR bit in single buffer mode). The QOR bit can be set for QTHF = 1 or QBHF = 1, depending on where the store is being attempted. The queue can be exited when an idle line is used to indicate when a group of serial transmissions is finished. This can be achieved by using the ILIE bit to enable the interrupt when the IDLE flag is set. The CPU can then clear QRE and/or RE allowing the receiver queue to be exited. For receiver queue operation, IDLE is cleared when SC1SR is read with IDLE set, followed by a read of SCRQ[0:15]. For receiver queue operation, NF is cleared when the SC1SR is read with NF set, followed by a read of SCRQ[0:15]. When noise occurs, the data is loaded into the receive queue, and operation continues unaffected. However, it may not be possible to determine which data frame in the receive queue caused the noise flag to be asserted. The queue is successfully filled (16 data frames) if error flags (FE and PF) are clear, QTHF and QBHF are set, and QRPNT is reset to all zeroes. QOR indicates that a new data frame has been received in the data register (SC1DR), but it cannot be placed into the receive queue due to either the QTHF or QBHF flag being set (QSCI1SR). Under this condition, the receive queue is disabled (QRE = 0). Software may service the receive queue and clear the appropriMPC555
/ MPC556
MOTOROLA 14-69
USERS MANUAL

ate flag (QTHF, QBHF). Data is not lost provided that the receive queue is reenabled before OR (SC1SR) is set, which occurs when a new data frame is received in the shifter but the data register (SC1DR) is still full. The data in the shifter that generated the OR assertion is overwritten by the next received data frame, but the data in the SC1DR is not lost.
MPC555
/ MPC556
MOTOROLA 14-70
USERS MANUAL

14.9.10 QSCI1 Receive Flow Chart Implementing The Queue
Refers to Action Performed In Parallel RE=0, QRWE=0 QRPNT=0000 QRE=0, QOR=0 QTHF=1, QBHF=1 QTHFI=0, QBHFI=0 Reset Hardware
Software
Set QRE Set QTHFI, QBHFI Clear QTHF, QBHF Set RE
QRE/RE=1 QTHF/QOR=0 FE/PE/OR=0 Yes Reset QRPNT to 0000
No
Clear QRE
No QRE, RE=1?
Yes No RDRF=1? Yes No FE, PE = 0?
Yes QRPNT=8 & QBHF QRPNT=0 & QTHF No Load RX Data to SCRQ[QRPNT], Increment QRPNT Yes Set QOR
Clear QTHF
Yes Set QTHF QRPNT = 1000?
No Clear QBHF
Yes Set QBHF QRPNT = 0000? No
Figure 14-21 Queue Receive Flow

MPC555
/ MPC556
MOTOROLA 14-71
USERS MANUAL

14.9.11 QSCI1 Receive Queue Software Flow Chart
Reset
Configure the Receive Queue Enable Queue Interrupts QTHFI, QBHFI = 1, Read Status Register with QTHF & QBHF = 1, Write QTHF & QBHF = 0
Enable ILIE=1 to Detect An Idle Line
FunctionCan Be Used To Indicate When a Group Of Serial Transmissions Is Finished
Set QRE and RE = 1
Yes QTHF=1? No Read Status Register With QTHF = 1 Read SCRQ[0:7] Write QTHF = 0 Yes QBHF = 1? No Read Status Register With QBHF = 1 Read SCRQ[8:15] Write QBHF = 0 Yes IDLE = 1? No Clear QRE and/or RE To Exit the Queue
DONE
Figure 14-22 Queue Receive Software Flow
MPC555
/ MPC556
MOTOROLA 14-72
USERS MANUAL

14.9.12 Example QSCI1 Receive Operation of 17 Data Frames Figure 14-23 shows an example receive operation of 17 data frames. The bold type indicates the current value for the QRPNT. Action of the queue may be followed by starting at the top of the figure and going left to right and then down the page.
Receive Queue Enabled
QTHF Interrupt Received
QRPNT 0000
SCRQ[0]
QRPNT 0000
SCRQ[0]
Data Received Available Space
0111 1000
SCRQ[7] SCRQ[8]
0111 1000
SCRQ[7] SCRQ[8]
1111
SCRQ[15]
1111
SCRQ[15]
Read SCSR and SCRQ[0:7] Clear QTHF
QBHF Interrupt Received QRPNT 0000 SCRQ[0]
IDLE Interrupt Received
QRPNT 0000
SCRQ[0]
0001
0111 1000
SCRQ[7] SCRQ[8]
0111 1000
SCRQ[7] SCRQ[8]
1111
SCRQ[15]
1111
SCRQ[15] Read SCRQ[0] Clear QRE/RE
Read SCRQ[8:15] Clear QBHF
Figure 14-23 Queue Receive Example for 17 Data Bytes
MPC555
/ MPC556
MOTOROLA 14-73
USERS MANUAL
MPC555
/ MPC556
MOTOROLA 14-74
USERS MANUAL
SECTION 15 MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)

The modular I/O system (MIOS) consists of a library of flexible I/O and timer functions including I/O port, counters, input capture, output compare, pulse and period measurement, and PWM. Because the MIOS is composed of submodules, it is easily configurable for different kinds of applications. MIOS1 is the implementation of the MIOS architecture used in the MPC555 / MPC556. The MIOS1 is composed of the following submodules:
One MIOS bus interface submodule (MBISM) One MIOS counter prescaler submodule (MCPSM) Two MIOS modulus counter submodules (MMCSM) 10 MIOS double action submodules (MDASM) Eight MIOS pulse width modulation submodules (MPWMSM) One MIOS 16-bit parallel port I/O submodule (MPIOSM) Two MIOS interrupt request submodules (MIRSM) 15.1 MIOS1 Features The basic features of the MIOS1 are as follows: Modular architecture at the silicon implementation level Disable capability in each submodule to allow power saving when its function is not needed Two 16-bit buses to allow action submodules to use counter data When not used for timing functions, every channel pin can be used as a port pin: I/O, output only or input only, depending on the channel function Submodules pin status bits: MIOS counter prescaler submodule (MCPSM): Centralized counter clock generator Programmable 4-bit modulus down-counter Wide range of possible division ratios: 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 and 16 Count inhibit under software control Two MIOS modulus counter submodules (MMCSM), each with these features: Programmable 16-bit modulus up-counter with built-in programmable 8-bit prescaler clocked by MCPSM output Maximum increment frequency of the counter: clocked by the internal Counter Clock: FSYS /2 clocked by the external pin: FSYS /4 Flag setting and possible interrupt generation on overflow of the up-counter Time counter on internal clock with interrupt capability after a pre-determined time
MODULAR INPUT/OUTPUT SUBSYSTEM (MIOS1)
MOTOROLA 15-1

Optional pin usable as an external event counter (pulse accumulator) with overflow and interrupt capability after a pre-determined number of external events Usable as a regular free-running up-counter Capable of driving a dedicated 16-bit counter bus to provide timing information to action submodules the value driven is the contents of the 16-bit upcounter register Optional pin to externally force a load of the counter with modulus value Ten MIOS double action submodules (MDASM), each with these features: Versatile 16-bit dual action unit allowing two events to occur before software intervention is required Six software selectable modes allowing the MDASM to perform pulse width and period measurements, PWM generation, single input capture and output compare operations as well as port functions Software selection of one of the two possible 16-bit counter buses used for timing operations Flag setting and possible interrupt generation after MDASM action completion Software selection of output pulse polarity Software selection of totem-pole or open-drain output Software readable output pin status Eight MIOS pulse width modulation submodules (MPWMSM), each with these features: Output pulse width modulated (PWM) signal generation with no software involvement Built-in 8-bit programmable prescaler clocked by the MCPSM PWM period and pulse width values provided by software: Double-buffered for glitch-free period and pulse width changes 2-cycle minimum output period/pulse-width increment (50 ns at fSYS = 40 MHz) 50% duty-cycle output maximum frequency: 10 MHz Up to 16 bits output pulse width resolution Wide range of periods: 16 bits of resolution: period range from 3.27 ms (with 50 ns steps) to 6.71 s (with 102.4 s steps) 8 bits of resolution: period range from 12.8 s (with 50 ns steps) to 26.2 ms (with 102.4 s steps) Wide range of frequencies: Maximum output frequency at fSYS = 40 MHz with 16 bits of resolution and divide-by-2 prescaler selection: 305 Hz (3.27 ms.) Minimum output frequency at fSYS = 40 MHz with 16 bits of resolution and divide-by-4096 prescaler selection: 0.15 Hz (6.7 s.) Maximum output frequency at fSYS = 40 MHz with 8 bits of resolution and divide-by-2 prescaler selection: 78125 Hz (12.8 s.) Minimum output frequency at fSYS = 40 MHz with 8 bits of resolution and divide-by-4096 prescaler selection: 38.14 Hz (26.2 ms.) Programmable duty cycle from 0% to 100% Possible interrupt generation after every period
MPC555
/ MPC556
MOTOROLA 15-2
USERS MANUAL

Software selectable output pulse polarity Software readable output pin status Possible use of pin as I/O port when PWM function is not needed MIOS 16-bit parallel port I/O submodule (MPIOSM): 16 parallel input/output pins Simple data direction register (DDR) concept for selection of pin direction 15.2 Submodule Numbering, Naming and Addressing A block is a group of four 16-bit registers. Each of the blocks within the MIOS1 addressing range is assigned a block number. The first block is located at the base address of the MIOS1. The blocks are numbered sequentially starting from 0. Every submodule instantiation is also assigned a number. The number of a given submodule is the block number of the first block of this submodule. A submodule is assigned a name made of its acronym followed by its submodule number. For example, if submodule number 18 were an MPWMSM, it would be named MPWMSM18. This numbering convention does not apply to the MBISM, the MCPSM and the MIRSMs. The MBISM and the MCPSM are unique in the MIOS1 and do not need a number. The MIRSMs are numbered incrementally starting from zero. The MIOS1 base address is defined at the chip level and is referred to as the MIOS1 base address. The MIOS1 addressable range is four Kbytes. The base address of a given implemented submodule within the MIOS1 is the sum of the base address of the MIOS1 and the submodule number multiplied by eight. (Refer to Table 15-36.) This does not apply to the MBISM, the MCPSM and the MIRSMs. For these submodules, refer to the MIOS1 memory map (Figure 15-2). 15.3 MIOS1 Signals The MIOS1 requires 34 pins: 10 MDASM pins, eight MPWMSM pins and 16 MPIOSM pins. The usage of these pins is shown in the block diagram of Figure 15-1 and in the configuration description of Table 15-36. In the figure, MDASM pins have a prefix MDA, MPWMSM pins have a prefix of MPWM and the port pins have a prefix of MPIO. The modulus counter clock and load pins are multiplexed with MDASM pins. The MIOS1 input and output pin names are composed of five fields according to the following convention: M <submodule short_prefix> <submodule number> <pin attribute suffix> (optional) <bit number> (optional)
MPC555
/ MPC556
MOTOROLA 15-3
USERS MANUAL

The pin prefix and suffix for the different MIOS submodules are as follows: MMCSM: submodule short_prefix: MC pin attribute suffix: C for the Clock pin pin attribute suffix: L for the Load pin For example, an MMCSM placed as submodule number n would have its corresponding input clock pin named MMCnC and its input load pin named MMCnL. On the MPC555 / MPC556 MMC6C is input on MDA11 and MMC22C is input on MDA13. The MMC6L is input on MDA12 and MMC22C is input on MDA14. MDASM: submodule short_prefix: DA pin attribute suffix: none For example a MDASM placed as submodule number n would have its corresponding channel I/O pin named MDAn MPWMSM: submodule short_prefix: PWM pin attribute suffix: none For example a MPWMSM placed as submodule number n would have its corresponding channel I/O pin named MPWMn MPIOSM: submodule short_prefix: PIO pin attribute suffix: B For example a MPIOSM placed as submodule number n would have its corresponding I/O pins named MPIOnB0 to MPIOnB15 for bit-0 to bit-15, respectively. In the MIOS1, some pins are multiplexed between submodules using the same pin names for the inputs and outputs which are connected as shown in Table 15-36. 15.4 Block Diagram Figure 15-1 is a block diagram of the MIOS1.
MPC555
/ MPC556
MOTOROLA 15-4
USERS MANUAL
16-bit Counter Bus 22 (CB22) Channel and I/O Pins: 34 Pins

MDASM11 Double Action MDA14 MDA13 L C MMCSM22 Modulus Counter MDASM15 MDA15 Double Action MDA11
5xDASM
16-Bit Counter Bus 6 (CB6)
MDASM27 Double Action
MDA27
5xDASM
MDA12 MDA11 L C MMCSM6 Modulus Counter MDASM31 Double Action MDA31
MPWMSM0 PWM
MPWM0
Counter Clock
4xPWMSM
MPWMSM3 PWM MPWM3
Modular I/O Bus (MIOB) (To all Submodules)
MPWMSM16 PWM
MPWM16
4xPWMSM
MPWMSM19 PWM MCPSM Bus Interface Unit Submodule Interrupt Submodules MPIOSM32 16-bit Port I/O MPIO32B15 MPIO32B0 MPWM19
IMB3 Clock (FSYS)
IMB3
Figure 15-1 MIOS1 Block Diagram
MPC555
/ MPC556
MOTOROLA 15-5
USERS MANUAL

15.5 MIOS1 Bus System The internal bus system within the MIOS1 is called the modular I/O bus (MIOB). The MIOB makes communications possible between any submodule and the IMB3 bus master through the MBISM. The MIOB is divided into three dedicated buses: The read/write and control bus The request bus The counter bus set 15.5.1 Read/Write and Control Bus The read/write and control bus (RWCB) allows read and write data transfers to and from any I/O submodule through the MBISM. It includes signals for data and addresses as well as control signals. The control signals allow 16-bit simple synchronous single master accesses and supports fast or slow master accesses. 15.5.2 Request Bus The request bus (RQB) provides interrupt request signals along with I/O submodule identification and priority information to the MBISM. Note that some submodules do not generate interrupts and are therefore independent of the RQB. 15.5.3 Counter Bus Set The 16-bit counter bus set (CBS) is a set of two 16-bit counter buses. The CBS makes it possible to transfer information between submodules. Typically, counter submodules drive the CBS, while action submodules process the data on these buses. Note, however, that some submodules are self-contained and therefore independent of the counter bus set. 15.6 MIOS1 Programmers Model The address space of the MIOS1 consist of four Kbytes starting at the base address of the module. The MIOS1 base address is a multiple of the addressable range. The overall address map organization is shown in Figure 15-2. To find the base address of a given implementation, refer to 1.3 MPC555 / MPC556 Address Map. To find the submodule base address, refer to Table 15-36.
MPC555
/ MPC556
MOTOROLA 15-6
USERS MANUAL
MPWMSM0 MPWMSM1 MPWMSM2 MPWMSM3 Reserved MMCSM6 Reserved MDASM11 MDASM12 MDASM13 Base Address 0x30 6000 MDASM14 MDASM15 MPWMSM16 Channels MPWMSM17 MPWMSM18 Supervisor/ Unrestricted MPWMSM19 Reserved Reserved MMCSM22 Reserved 0x30 6800 0x30 6810 MDASM27 MBISM MCPSM MDASM28 MDASM29 MDASM30 MDASM31 Supervisor MPIOSM32 Reserved
0x30 6000 0x30 6008 0x30 6010 0x30 6018 0x30 6030
0x30 6058 0x30 6060 0x30 6068 0x30 6070 0x30 6078 0x30 6080 0x30 6088 0x30 6090 0x30 6098
0x30 60B0
0x30 60D8 0x30 60E0 0x30 60E8 0x30 60F0 0x30 60F8 0x30 6100
Submodules 15 to 0
MIOS1SR0 Reserved MIOS1ER0 MIOS1RPR0 Reserved MIOS1LVL0 Reserved
0x30 6C00 0x30 6C02 0x30 6C04 0x30 6C06
0x30 6C00 0x30 6C40 Supervisor
MIRSM0 MIRSM1
Reserved 0x30 6FFF
0x30 6C30
Submodules 31 to 16
MIOS1SR1 Reserved MIOS1ER1 MIOS1RPR1 Reserved MIOS1LVL1 Reserved
0x30 6C40 0x30 6C42
0x30 6C44
0x30 6C46
0x30 6C70
Figure 15-2 MIOS1 Memory Map

MPC555
/ MPC556
MOTOROLA 15-7
USERS MANUAL

If a supervisor privilege address space is accessed in user mode, the module returns a bus error. All MIOS1 unimplemented locations within the addressable range, return a logic 0 when accessed. In addition, the internal TEA (transfer error acknowledge) signal is asserted. All unused bits within MIOS1 registers return a 0 when accessed. 15.7 MIOS1 I/O Ports Each pin of each submodule can be used as an input, output, or I/O port: Table 15-1 MIOS1 I/O Ports
Submodule MPIOSM MMCSM MDASM MPWMSM
Number 16 2 1 1
Type I/O I I/O I/O
15.8 MIOS Bus Interface Submodule (MBISM) The MIOS bus interface submodule (MBISM) is used as an interface between the MIOB (modular I/O bus) and the IMB3. It allows the CPU to communicate with the MIOS1 submodules. 15.8.1 MIOS Bus Interface (MBISM) Registers Table 15-2 is the address map for the MBISM submodule. Table 15-2 MBISM Address Map
Address 0x30 6800 0x30 6802 0x30 6804 0x30 6806 Register MIOS1 Test and Pin Control Register (MIOS1TPCR) See Table 15-3 for bit descriptions. Reserved (MIOS1 Vector Register in some implementations) MIOS1 Module Version Number Register (MIOS1VNR) See Table 15-4 for bit descriptions. MIOS1 Module Control Register (MIOS1MCR) See Table 15-4 for bit descriptions.
0x30 6808 Reserved 0x30 680E
15.8.1.1 MIOS1 Test and Pin Control Register MIOS1TPCR Test and Pin Control Register
MSB 0 TEST RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 RESERVED 8 9 10 11 12 13
0x30 6800
14 VF LSB 15 VFLS
MPC555
/ MPC556
MOTOROLA 15-8
USERS MANUAL

This register is used for MIOS1 factory testing and selecting between the MIOS1 pin functions for the MPIO32B[0:3] and the developement support pin functions of VFLS[0:1] and VF[0-2]. Table 15-3 MIOS1TPCR Bit Descriptions
Bit(s) 0 1:13 Name TEST Reserved Pin multiplex. This bit is used to determine the usage of the MIOS1 pins. Refer to the pad-ring specification of the chip for details about the usage of this bit. This bit is set to 0 by reset. 0 = the concerned pins are dedicated to the MIOS1. 1 = alternate function Pin multiplex. This bit is used to determine the usage of the MIOS1 pins. Refer to the pad-ring specification of the chip for details about the usage of this bit. This bit is set to 0 by reset. 0 = the concerned pins are dedicated to the MIOS1. 1 = alternate function Description This bit is reserved for factory testing of the MIOS1. The test mode is disabled by reset.
14
VF
15
VFLS
15.8.1.2 MIOS1 Vector Register This register is used only in MCUs that use vectored interrupts. The MPC555 / MPC556 does not use this register. 15.8.1.3 MIOS1 Module and Version Number Register This read-only register contains the hard-coded values of the module and version number. MIOS1VNR MIOS1 Module/Version Number Register
MSB 0 1 2 3 MN 4 5 6 7 8 9 10 11 VN 12 13
0x30 6804
14 LSB 15
Table 15-4 MIOS1VNR Bit Descriptions

Bit(s) 0:7 8:15 Name MN VN Description Module number = 1 on the MPC555 / MPC556. The MPC555 / MPC556 implements the MIOS1 module. Version number
15.8.1.4 MIOS1 Module Configuration Register MIOS1MCR MIOS1 Module Configuration Register
MSB 0 STOP 0 1 0 0 2 FRZ 0 3 RST 0 0 4 5 6 7 8 SUPV 0 0 0 9 10 RESERVED 0 0 0 11 12 13 RESERVED 0 0
0x30 6806
14 LSB 15 RESERVED (IARB) 0 0 0
RESET:
MPC555
/ MPC556
MOTOROLA 15-9
USERS MANUAL

Table 15-5 MIOS1MCR Bit Descriptions
Bit(s) Name Description Stop enable. Setting the STOP bit activates the MIOB freeze signal regardless of the state of the IMB3 FREEZE signal. The MIOB freeze signal is further validated in some submodules with internal freeze enable bits in order for the submodule to be stopped. The MBISM continues to operate to allow the CPU access to the submodules registers. The MIOB freeze signal remains active until reset or until the STOP bit is written to zero by the CPU (via the IMB3). The STOP bit is cleared by reset. 0 = Enables MIOS1 operation. 1 = Selectively stops MIOS1 operation. Reserved Freeze enable. Setting the FRZ bit, activates the MIOB freeze signal only when the IMB3 FREEZE signal is active. The MIOB freeze signal is further validated in some submodules with internal freeze enable bits in order for the submodule to be frozen. The MBISM continues to operate to allow the CPU access to the submodules registers. The MIOB freeze signal remains active until the FRZ bit is written to zero or the IMB3 FREEZE signal is negated. The FRZ bit is cleared by reset. 0 = Ignores the FREEZE signal on the IMB3, allowing MIOS1 operation. 1 = Selectively stops MIOS1 operation when the FREEZE signal appears on the IMB3. Module reset. The RST bit always returns 0 when read and can be written to 1. When the RST bit is written to 1, the MBISM activates the reset signal on the MIOB. This completely stops the operation of the MIOS1 and resets all the values in the submodules registers that are affected by reset. This bit provides a way of resetting the complete MIOS1 module regardless of the reset state of the CPU. The RST bit is cleared by reset. 0 = Writing a 0 to RST has no effect. 1 = Reset the MIOS1 submodules Reserved Supervisor data space selector. The SUPV bit specifies whether the address space from 0x0000 to 0x07FF in the MIOS1 is accessed at the supervisor privilege level. When SUPV is cleared, these addresses are accessed at the Unrestricted privilege level. The SUPV bit is cleared by reset. 0 = Unrestricted data space. 1 = Supervisor data space. Reserved. In implementations that use hardware interrupt arbitration, bits 12:15 represent the IARB field.
STOP
FRZ
RST
4:7
SUPV
9:15
15.8.2 MBISM Interrupt Registers Table 15-6 shows the MBISM interrupt registers. Table 15-6 MBISM Interrupt Registers Address Map
Address 0x30 6C30 0x30 6C70 Register MIOS1 Interrupt Level Register 0 (MIOS1LVL0) See Table 15-7 for bit descriptions. MIOS1 Interrupt Level Register 1 (MIOS1LVL1) See Table 15-8 for bit descriptions.
15.8.2.1 MIOS1 Interrupt Level Register 0 (MIOS1LVL0) This register contains the interrupt level that applies to the submodules number 15 to zero.
MPC555
/ MPC556
MOTOROLA 15-10
USERS MANUAL

MIOS1LVL0 MIOS1 Interrupt Level Register 0
MSB 0 1 2 RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 4 5 6 LVL 7 8 TM 9 10 11 12 13
0x30 6C30
14 LSB 15
RESERVED
Table 15-7 MIOS1LVL0 Bit Descriptions

Bit(s) 0:4 5:7 8:9 LVL TM Name Reserved Interrupt request level. This field represents one of eight possible levels. Time multiplexing. This field determines the multiplexed time slot Reserved Description
10:15
15.8.2.2 MIOS1 Interrupt Level Register 1 (MIOS1LVL1) This register contains the interrupt level that applies to the submodules number 31 to 16. MIOS1LVL1 MIOS1 Interrupt Level 1 Register
MSB 0 1 2 RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 4 5 6 LVL 7 8 TM 9 10 11 12 13
0x30 6C70
14 LSB 15
RESERVED
Table 15-8 MIOS1LVL1 Bit Descriptions

Bit(s) 0:4 5:7 8:9 10:15 Name LVL TM Reserved Interrupt request level. This field represents one of eight possible levels. Time multiplexing. This field determines the multiplexed time slot. Reserved Description
15.8.3 Interrupt Control Section (ICS) The interrupt control section delivers the interrupt level to the CPU. The interrupt control section adapts the characteristics of the MIOB request bus to the characteristics of the interrupt structure of the IMB3. When at least one of the flags is set on an enabled level, the ICS receives a signal from the corresponding IRQ pending register. This signal is the result of a logical OR between all the bits of the IRQ pending register. The signal received from the IRQ pending register is associated with the interrupt level register within the ICS. This level is coded on five bits in this register: three bits represent one of eight levels and the two other represent the four time multiplex slots. Ac/ MPC556
MPC555
MOTOROLA 15-11
USERS MANUAL

cording to this level, the ICS sets the correct IRQ[7:0] lines with the correct ILBS[1:0] time multiplex lines on the peripheral bus. The CPU is then informed as to which of the thirty-two interrupt levels is requested. Based on the interrupt level requested, the software must determine which submodule requested the interrupt. The software may use a find-first-one type of instruction to determine, in the concerned MIRSM, which of the bits is set. The CPU can then serve the requested interrupt. 15.9 MIOS Counter Prescaler Submodule (MCPSM) The MIOS counter prescaler submodule (MCPSM) divides the MIOS1 clock (FSYS) to generate the counter clock. It is designed to provide all the submodules with the same division of the main MIOS1 clock (division of FSYS). It uses a 4-bit modulus counter. The clock signal is prescaled by loading the value of the clock prescaler register into the prescaler counter every time it overflows. This allows all prescaling factors between two and 16. Counting is enabled by asserting the PREN bit in the control register. The counter can be stopped at any time by negating this bit, thereby stopping all submodules using the output of the MCPSM (counter clock).
fSYS
CP0 Clock CP1 Prescaler Register CP2 CP3
Dec.
4-bit = 1? Decrementer
Counter Clock
Enable MCPSMSCR PREN
Load
Figure 15-3 MCPSM Block Diagram 15.9.1 MIOS Counter Prescaler Submodule (MCPSM) Registers Table 15-9 is the address map for the MCPSM submodule.
MPC555
/ MPC556
MOTOROLA 15-12
USERS MANUAL

Table 15-9 MCPSM Address Map
Address 0x30 6810 Reserved 0x30 6814 0x30 6816 MCPSM Status/Control Register (MCPSMSCR) See Table 15-10 for bit descriptions. Register
15.9.1.1 MCPSM Status/Control Register (MCPSMCSCR) This register contains status and control information for the MCPSM. MCPSMSCR MCPSM Status/Control Register 0x30 6816
9 10 11 12 13 PSL 0 0 0 0 0 0 0 0 14 LSB 15
MSB 0
PREN FREN RESET: 0 0 0 0 0 0
RESERVED 0 0
Table 15-10 MCPSMSCR Bit Descriptions

Bit(s) Name Description Prescaler enable. This active high read/write control bit enables the MCPSM counter. The PREN bit is cleared by reset. 0 = MCPSM counter disabled. 1 = MCPSM counter enabled. Freeze enable. This active high read/write control bit when set make possible a freeze of the MCPSM counter if the MIOB freeze line is activated. Note that this line is active when the MIOS1MCR STOP bit is set or when the MIOS1MCR FREN bit and the IMB3 FREEZE line are set. 1 FREN When the MCPSM is frozen, it stops counting. Then when the FREN bit is reset or when the freeze condition on the MIOB is negated, the counter restarts from where it was before being frozen. The FREN bit is cleared by reset. 0 = MCPSM counter not frozen. 1 = Selectively stops MIOS1 operation when the FREEZE signal appears on the IMB3. Reserved Clock prescaler. This 4-bit read/write data register stores the modulus value for loading into the clock prescaler. The new value is loaded into the counter on the next time the counter equals one or when disabled (PREN bit = 0). Divide ratios are as follows: 0000 = 16 0001 = No counter clock output 0010 = 2 0011 = 3 . . . 1110 = 14 1111 = 15
PREN
2:11
12:15
PSL
15.10 MIOS Modulus Counter Submodule (MMCSM) The MMCSM is a versatile counter submodule capable of performing complex counting and timing functions, including modulus counting, in a wide range of applications. The MMCSM may also be configured as an event counter, allowing the overflow flag to be set after a predefined number of events (internal clocks or external events), or
MPC555
/ MPC556
MOTOROLA 15-13
USERS MANUAL

as a time reference for other submodules. Note that the MMCSM can also operate as a free running counter by loading the modulus value of zero. The main components of the MMCSM are an 8-bit prescaler counter, an 8-bit prescaler register, a 16-bit up-counter register, a 16-bit modulus latch register, counter loading and interrupt flag generation logic. The contents of the modulus latch register is transferred to the counter under the following three conditions: 1. When an overflow occurs 2. When an appropriate transition occurs on the external load pin 3. When the program writes to the counter register. In this case, the value is first written into the modulus register and immediately transferred to the counter. Software can also write a value to the modulus register for later loading into the counter with one of the two first criteria. A software control register selects whether the clock input to the counter is the prescaler output or the corresponding input pin. The polarity of the external input pin is also programmable. Refer to Table 15-36 for the MMCSM relative I/O pin implementation.
MPC555
/ MPC556
MOTOROLA 15-14
USERS MANUAL
8-bit Clock Counter Clock Clock input pin (MDA11/MDA13) Edge Detect Clock Select Clock Enable Clock Prescaler
16-bit Counter Bus
Request Bus
Flag
MMCSMSCR
PINC
CP0 - CP7 8-bit Prescaler Modulus Register
CLS0
CLS1
FREN 16-bit Up-Counter Register
MMCSMCNT Load
Modulus Load Pin (MDA12/MDA14) Edge Detect
Load Control
Overflow
MMCSMSCR
PINL
EDGN
EDGP
MMCSMML 16-bit Modulus Latch Register
MIOB
Figure 15-4 MMCSM Block Diagram 15.10.1 MIOS Modulus Counter Submodule (MMCSM) Registers Each of the two MMCSM submodules in the MPC555 / MPC556 includes the register set shown in Table 15-11. Table 15-11 MMCSM Address Map
Address Register MMCSM6 0x30 6030 0x30 6032 MMCSM6 Up-Counter Register (MMCSMCNT) See Table 15-12 for bit descriptions. MMCSM6 Modulus Latch Register (MMCSMML) See Table 15-13 for bit descriptions. MMCSM6 Status/Control Register Duplicated (MMCSMSCRD) See 15.10.1.3 MMCSM Status/Control Register (Duplicated) for bit descriptions. MMCSM6 Status/Control Register (MMCSMSCR) MMCSM22 0x30 60B0 0x30 60B2 0x30 60B4 0x30 60B6 MMCSM Up-Counter Register (MMCSMCNT) MMCSM Modulus Latch Register (MMCSMML) MMCSM Status/Control Register Duplicated (MMCSMSCRD) MMCSM Status/Control Register (MMCSMSCR)
0x30 6034 0x30 6036
MPC555
/ MPC556
MOTOROLA 15-15
USERS MANUAL

15.10.1.1 MMCSM Up-Counter Register (MMCSMCNT) The MMCSMCNT register contains the 16-bit value of the up counter. Note that writing to MMCSMCNT simultaneously writes to MMCSMML. MMCSMCNT MMCSM Up-Counter Register
MSB 0 1 2 3 4 5 6 7 CNT RESET: U U U U U U U U U U U U U U U U 8 9 10 11 12 13
0x30 6030 0x30 60B0

14 LSB 15
Table 15-12 MMCSMCNT Bit Descriptions
Bit(s) 0:15
Name CNT
Description Counter value. These read/write data bits represent the 16-bit value of the up-counter. CNT contains the value that is driven onto the 16-bit counter bus.
15.10.1.2 MMCSM Modulus Latch Register (MMCSMML) The MMCSMML is a read/write register containing the 16-bit value of the up-counter. MMCSMML MMCSM Modulus Latch Register
MSB 0 1 2 3 4 5 6 7 ML RESET: U U U U U U U U U U U U U U U U 8 9 10 11 12 13
0x30 6032 0x30 60B2

14 LSB 15
Table 15-13 MMCSMML Bit Descriptions

Bit(s) Name Description Modulus latches. These bits are read/write data bits containing the 16-bit modulus value to be loaded into the up-counter. 0:15 ML The value loaded in this register must be the twos complement of the desired modulus count. The up-counter increments from this twos complement value up to 0xFFFF to get the correct number of steps before an overflow is generated to reload the modulus value into the upcounter. A value of 0x0000 should be used for a free-running counter.
15.10.1.3 MMCSM Status/Control Register (Duplicated) The MMCSMSCRD and the MMCSMSCR are the same registers accessed at two different addresses. Reading or writing to one of these two addresses has exactly the same effect. NOTE The user should not write directly to the address of the MMCSMSCRD. This registers address may be reserved for future use and should not be accessed by the software to assure future software compatibility.
MPC555
/ MPC556
MOTOROLA 15-16
USERS MANUAL

MMCSMSCRD MMCSM Status/Control Register (Duplicated)
MSB 0 PINC 1 PINL 2 3 4 5 CLS 6 7 8 9 10 11 CP 12 13
0x30 6034 0x30 60B4

14 LSB 15
FREN EDGN EDGP
RESET: 0 0 0 0 0 0 U U U U U U U U
15.10.1.4 MMCSM Status/Control Register (MMCSMSCR) This register contains both read-only status bits and read/write control bits. MMCSMSCR MMCSM Status/Control Register 0x30 6036 0x30 60B6
9 10 11 CP 12 13 14 LSB 15
MSB 0 PINC
1 PINL
5 CLS
FREN EDGN EDGP
RESET: 0 0 0 0 0 0 U U U U U U U U
Table 15-14 MMCSMSCR Bit Descriptions

Bit(s) 0 1 2 Name PINC PINL FREN Description Clock input pin status. This read-only status bit reflects the logic state of the clock input pin MMCnC (MDA11 or MDA13). Modulus load input pin status. This read-only status bit reflects the logic state of the modulus load pin MMCnL (MDA12 or MDA14). Freeze enable. This active high read/write control bit enables the MMCSM to recognize the MIOB freeze signal. Modulus load falling edge/rising edge sensitivity. These active high read/write control bits set falling-edge and rising edge sensitivity, respectively, for the MMCnL pin (MDA12 or MDA14). 00 = Disabled 01 = MMCSMCNT load on rising edges 10 = MMCSMCNT load on falling edges 11 = MMCSMCNT load on rising and falling edges Clock select. These read/write control bits select the clock source for the modulus counter. 00 = Disabled 01 = Falling edge of MMCnC (MDA11 or MDA13) pin 10 = Rising edge of MMCnC (MDA11 or MDA13) pin 11 = MMCSM clock prescaler Clock prescaler. This 8-bit read/write data register stores the twos complement of the desired modulus value for loading into the built-in 8-bit clock prescaler. The new value is loaded into the prescaler counter when the next counter overflow occurs or when the CLS bits are set to select the clock prescaler as the clock source.Table 15-15 gives the clock divide ratio according to the CP values
3:4
EDGN, EDGP
5:6
CLS
8:15
CP
MPC555
/ MPC556
MOTOROLA 15-17
USERS MANUAL

Table 15-15 MMCSMCR CP and MPWMSMSCR CP Values
Prescaler Value (CP in hex) FF FE FD FC FB FA F9 F8 ...... 02 01 00 MIOS Prescaler Clock Divided by 1 2 3 4 5 6 7 8 ........ 254 (2^8 -2) 255 (2^8 -1) 256 (2^8)
15.11 MIOS Double Action Submodule (MDASM) The MIOS double action submodule (MDASM) provides two consecutive 16-bit input captures or two consecutive 16-bit output compare functions that can occur automatically without software intervention. The input edge detector is programmable to trigger the capture function to occur on the desired edge. The output flip-flop is set by one of the output compares and is reset by the other one. In all modes except disable mode, an optional interrupt is available to the software. Software selection is provided to select which of the incoming 16-bit counter buses is used for the input capture or the output compare. The MDASM has six different software selectable modes: Disable mode Pulse width measurement Period measurement Input capture mode Single pulse generation Continuous pulse generation The MDASM has three data registers that are accessible to the software from the various modes. For some of the modes, two of the registers are cascaded together to provide double buffering. The value in one register is transferred to the other register automatically at the correct time so that the minimum pulse (measurement or generation) is just one 16-bit counter bus count. Refer to Table 15-36 for the MDASM relative I/O pin implementation.
MPC555
/ MPC556
MOTOROLA 15-18
USERS MANUAL
CBn CBn+1 CBn+2 CBn+3
4 X 16-bit Counter Buses
FORCA FORCB
Counter Bus Select
BSL1 BSL0
WOR
PIN
16-bit Comparator A
Output Flip-Flop
Output Buffer
I/O Pin
16-bit Register A
EDPOL
Edge Detect 16-bit Register B1 Register B 16-bit Register B2
FLAG
16-bit Comparator B
MODE0 MODE1 MODE2 MODE3

Control Register Bits
Request Bus MIOB
Figure 15-5 MDASM Block Diagram 15.11.1 MIOS Double Action Submodule (MDASM) Registers One set of registers is associated with each MDASM submodule. The base address of the particular submodule is shown in the table below.
MPC555
/ MPC556
MOTOROLA 15-19
USERS MANUAL

Table 15-16 MDASM Address Map
Address Register MDASM11 0x30 6058 MDASM11 Data A Register (MDASMAR) See 15.11.1.1 MDASM Data A Register for bit descriptions. MDASM11 Data B Register (MDASMBR) See 15.11.1.2 MDASM Data B Register (MDASMBR) for bit descriptions. MDASM11 Status/Control Register Duplicated (MDASMSCRD) See 15.11.1.3 MDASM Status/Control Register (Duplicated) for bit descriptions. MDASM11 Status/Control Register (MDASMSCR) See Table 15-17 for bit descriptions. MDASM12 0x30 6060 0x30 6062 0x30 6064 0x30 6066 0x30 6068 0x30 606A 0x30 606C 0x30 606E 0x30 6070 0x30 6072 0x30 6074 0x30 6076 0x30 6078 0x30 607A 0x30 607C 0x30 607E 0x30 60D8 0x30 60DA 0x30 60DE 0x30 60E0 0x30 60E2 0x30 60E4 0x30 60E6 0x30 60E8 MDASM12 Data A Register (MDASMAR) MDASM12 Data B Register (MDASMBR) MDASM12 Status/Control Register Duplicated (MDASMSCRD) MDASM12 Status/Control Register (MDASMSCR) MDASM13 MDASM13 Data A Register (MDASMAR) MDASM13 Data B Register (MDASMBR) MDASM13 Status/Control Register Duplicated (MDASMSCRD) MDASM13 Status/Control Register (MDASMSCR) MDASM14 MDASM14 Data A Register (MDASMAR) MDASM14 Data B Register (MDASMBR) MDASM14 Status/Control Register Duplicated (MDASMSCRD) MDASM14 Status/Control Register (MDASMSCR) MDASM15 MDASM15 Data A Register (MDASMAR) MDASM15 Data B Register (MDASMBR) MDASM15 Status/Control Register Duplicated (MDASMSCRD) MDASM15 Status/Control Register (MDASMSCR) MDASM27 MDASM27 Data A Register (MDASMAR) MDASM27 Data B Register (MDASMBR) MDASM27 Status/Control Register (MDASMSCR) MDASM28 MDASM28 Data A Register (MDASMAR) MDASM28 Data B Register (MDASMBR) MDASM28 Status/Control Register Duplicated (MDASMSCRD) MDASM28 Status/Control Register (MDASMSCR) MDASM29 MDASM29 Data A Register (MDASMAR)
0x30 605A
0x30 605C
0x30 605E
0x30 60DC MDASM27 Status/Control Register Duplicated (MDASMSCRD)
MPC555
/ MPC556
MOTOROLA 15-20
USERS MANUAL

Table 15-16 MDASM Address Map (Continued)
Address 0x30 60EA 0x30 60EC 0x30 60EE 0x30 60F0 0x30 60F2 0x30 60F4 0x30 60F6 0x30 60F8 Register MDASM29 Data B Register (MDASMBR) MDASM29 Status/Control Register Duplicated (MDASMSCRD) MDASM29 Status/Control Register (MDASMSCR) MDASM30 MDASM30 Data A Register (MDASMAR) MDASM30 Data B Register (MDASMBR) MDASM30 Status/Control Register Duplicated (MDASMSCRD) MDASM30 Status/Control Register (MDASMSCR) MDASM31 MDASM31 Data A Register (MDASMAR) MDASM31 Data B Register (MDASMBR) MDASM31 Status/Control Register Duplicated (MDASMSCRD) MDASM31 Status/Control Register (MDASMSCR) 0x30 60FA 0x30 60FC 0x30 60FE
15.11.1.1 MDASM Data A Register MDASMAR is the data register associated with channel A. Its use varies with the mode of operation: In the DIS mode, MDASMAR can be accessed to prepare a value for a subsequent mode selection In the IPWM mode, MDASMAR contains the captured value corresponding to the trailing edge of the measured pulse In the IPM and IC modes, MDASMAR contains the captured value corresponding to the most recently detected dedicated edge (rising or falling edge) In the OCB and OCAB modes, MDASMAR is loaded with the value corresponding to the leading edge of the pulse to be generated. Writing to MDASMAR in the OCB and OCAB modes also enables the corresponding channel A comparator until the next successful comparison. In the OPWM mode, MDASMAR is loaded with the value corresponding to the leading edge of the PWM pulse to be generated MDASMAR MDASM Data A Register
MSB 0 1 2 3 4 5 6 7 AR RESET: U U U U U U U U U U U U U U U U 8 9 10 11 12
0x30 6058*
13 14 LSB 15
* Refer to Table 15-16 for a complete list of all the base addresses for the MDASM registers.
15.11.1.2 MDASM Data B Register (MDASMBR) MDASMBR is the data register associated with channel B. Its use varies with the mode of operation. Depending on the mode selected, software access is to register B1 or register B2.
MPC555
/ MPC556
MOTOROLA 15-21
USERS MANUAL

In the DIS mode, MDASMBR can be accessed to prepare a value for a subsequent mode selection. In this mode, register B1 is accessed in order to prepare a value for the OPWM mode. Unused register B2 is hidden and cannot be read, but is written with the same value when register B1 is written. In the IPWM mode, MDASMBR contains the captured value corresponding to the leading edge of the measured pulse. In this mode, register B2 is accessed; buffer register B1 is hidden and cannot be accessed. In the IPM and IC modes, MDASMBR contains the captured value corresponding to the most recently detected period edge (rising or falling edge). In this mode, register B2 is accessed; buffer register B1 is hidden and cannot be accessed. In the OCB and OCAB modes, MDASMBR is loaded with the value corresponding to the trailing edge of the pulse to be generated. Writing to MDASMBR in the OCB and OCAB modes also enables the corresponding channel B comparator until the next successful comparison. In this mode, register B2 is accessed; buffer register B1 is hidden and cannot be accessed. In the OPWM mode, MDASMBR is loaded with the value corresponding to the trailing edge of the PWM pulse to be generated. In this mode, register B1 is accessed; buffer register B2 is hidden and cannot be accessed. MDASMBR MDASM Data B Register
MSB 0 1 2 3 4 5 6 7 BR RESET: U U U U U U U U U U U U U U U U 8 9 10 11 12
0x30 605A*
13 14 LSB 15
15.11.1.3 MDASM Status/Control Register (Duplicated) The MDASMSCRD and the MDASMSCR are the same registers accessed at two different addresses. Reading or writing to either of these two addresses has exactly the same effect. NOTE The user should not write directly to the address of the MDASMSCRD. This registers address may be reserved for future use and should not be accessed by the software to assure future software compatibility. MDASMSCRD MDASM Status/Control Register (Duplicated)
MSB 0 PIN 1 WOR 2 FREN 3 0 4 EDPOL 5 6 7 8 9 BSL 10 11 0 12
0x30 605C*
13 MOD 14 LSB 15
FORC FORC A B
RESERVED
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MPC555
/ MPC556
MOTOROLA 15-22
USERS MANUAL

15.11.1.4 MDASM Status/Control Register The status/control register contains a read-only bit reflecting the status of the MDASM pin as well as read/write bits related to its control and configuration. MDASMSCR MDASM Status/Control Register
MSB 0 PIN 1 WOR 2 FREN 3 0 4 EDPOL 5 6 7 8 9 BSL 10 11 0 12
0x30 605E*
13 MOD 14 LSB 15
FORC FORC A B
RESERVED
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 15-17 MDASMSCR Bit Descriptions

Bit(s) 0 Name PIN Description Pin input status. The pin input status bit reflects the status of the corresponding pin. Wired-OR. In the DIS, IPWM, IPM and IC modes, the WOR bit is not used; reading this bit returns the value that was previously written. In the OCB, OCAB and OPWM modes, the WOR bit selects whether the output buffer is configured for open-drain or totem-pole operation. 0 = Output buffer is totem-pole. 1 = Output buffer is open-drain. Freeze enable. This active high read/write control bit enables the MDASM to recognize the MIOB freeze signal. 0 = The MDASM is not frozen even if the MIOB freeze line is active. 1 = The MDASM is frozen if the MIOB freeze line is active. 0 Polarity. In the DIS mode, this bit is not used; reading it returns the last value written. In the IPWM mode, this bit is used to select the capture edge sensitivity of channels A and B. 0 = Channel A captures on a rising edge. Channel B captures on a falling edge. 1 = Channel A captures on a falling edge. Channel B captures on a rising edge. In the IPM and IC modes, the EDPOL bit is used to select the input capture edge sensitivity of channel A. 0 = Channel A captures on a rising edge. 1 = Channel A captures on a falling edge. In the OCB, OCAB and OPWM modes, the EDPOL bit is used to select the voltage level on the output pin. 0 = The output flip-flop logic level appears on the output pin: a compare on channel A sets the output pin, a compare on channel B resets the output pin. 1 = The complement of the output flip-flop logic level appears on the output pin: a compare on channel A resets the output pin; a compare on channel B sets the output pin. Force A. In the OCB, OCAB and OPWM modes, the FORCA bit allows the software to force the output flip-flop to behave as if a successful comparison had occurred on channel A (except that the FLAG line is not activated). Writing a one to FORCA sets the output flip-flop; writing a zero to it has no effect. In the DIS, IPWM, IPM and IC modes, the FORCA bit is not used and writing to it has no effect. FORCA is cleared by reset and is always read as zero. Writing a one to both FORCA and FORCB simultaneously resets the output flip-flop.
WOR
FREN
EDPOL
FORCA
MPC555
/ MPC556
MOTOROLA 15-23
USERS MANUAL

Table 15-17 MDASMSCR Bit Descriptions (Continued)
Bit(s) Name Description Force B. In the OCB, OCAB and OPWM modes, the FORCB bit allows the software to force the output flip-flop to behave as if a successful comparison had occurred on channel B (except that the FLAG line is not activated). Writing a one to FORCB resets the output flip-flop; writing a zero to it has no effect. In the DIS, IPWM, IPM and IC modes, the FORCB bit is not used and writing to it has no effect. FORCB is cleared by reset and is always read as zero. Writing a one to both FORCA and FORCB simultaneously resets the output flip-flop. 7:8 Reserved Bus select.These bits are used to select which of the four possible 16-bit counter bus passing nearby is used by the MDASM. Refer to Table 15-36 to see how the MDASM is connected to the 16-bit counter buses in the MIOS1. NOTE: In the MPC555 / MPC556, only 0b00 (CB6) and 0b01 (CB22) are implemented. 0 Mode select. These four mode select bits select the mode of operation of the MDASM. To avoid spurious interrupts, it is recommended that MDASM interrupts are disabled before changing the operating mode. It is also imperative to go through the disable mode before changing the operating mode. See Table 15-18 for details.
FORCB
9:10
BSL
11
12:15
MOD
Table 15-18 MDASM Mode Selects

MDASM Control Register Bits MOD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits of Resolution 16 16 16 16 16 16 15 14 13 12 11 9 7 Counter Bus Bits Ignored 0 0,1 0-2 0-3 0-4 0-6 0-8 MDASM Mode of Operation DIS Disabled IPWM Input pulse width measurement IPM Input period measurement IC Input capture OCB Output compare, flag on B compare OCAB Output compare, flag on A and B compare Reserved Reserved OPWM Output pulse width modulation OPWM Output pulse width modulation OPWM Output pulse width modulation OPWM Output pulse width modulation OPWM Output pulse width modulation OPWM Output pulse width modulation OPWM Output pulse width modulation OPWM Output pulse width modulation
MPC555
/ MPC556
MOTOROLA 15-24
USERS MANUAL

15.12 MIOS Pulse Width Modulation Submodule (MPWMSM) The purpose of the MIOS pulse width modulation submodule (MPWMSM) is to create a variable pulse width output signal at a wide range of frequencies, independent of other MIOS1 output signals. The MPWMSM includes its own 8-bit prescaler and counter and, thus, does not use the MIOS1 16-bit counter buses. The MPWMSM pulse width can vary from 0.0% to 100.0%, with up to 16 bits of resolution. The finest output resolution is the MCU IMB clock time divided by two (for a FSYS of 40.0 MHz, the finest output pulse width resolution is 50 ns). With the full sixteen bits of resolution and the overall prescaler divide ratio varying from divide-by-2 to divide-by-4096, the period of the PWM output can range from 3.28 ms to 6.7 s (assuming a fSYS of 40 MHz). By reducing the counting value, the output signal period can be reduced. The period can be as fast as 205 s (4.882 KHz) with twelve bits of resolution, as fast as 12.8 s (78.125 KHz) with eight bits of resolution and as fast as 3.2 s (312.500 KHz) with six bits of resolution (still assuming a fSYS of 40 MHz and a first stage prescaler divide-by-2 clock selection). Refer to Table 15-36 for the MPWMSM relative I/O pin implementation.
PS0 - PS7
Counter Clock
8- bit Prescaler (NCOUNT)
FREN EN TRSP
16-bit Down Counter MPWMC = 0x0001 16-bit <= Comparator
EN
POL
PIN
DDR
Output Flip-Flop
Output Buffer
Output Logic Output Pin
LOAD
Pulse Width Register PWMB2
Next Period Register MPWMA
PWMB Next Pulse Width Register MPWMB1 FLAG
Request Bus
MIOB
Figure 15-6 MPWMSM Block Diagram
MPC555
/ MPC556
MOTOROLA 15-25
USERS MANUAL

15.12.1 MIOS Pulse Width Modulation Submodule (MPWMSM) Registers One set of registers is associated with each MPWMSM submodule. The base address is given in the table below. Table 15-19 MPWMSM Address Map
Address Register MPWMSM0 0x30 6000 0x30 6002 0x30 6004 MPWMSM0 Period Register (MPWMSMPERR) See Table 15-20 for bit descriptions. MPWMSM0 Pulse Register (MPWMSMPULR) See Table 15-21 for bit descriptions. MPWMSM0 Count Register (MPWMSMCNTR) See Table 15-22 for bit descriptions. MPWMSM0 Status/Control Register (MPWMSMSCR) See Table 15-23 for bit descriptions. MPWMSM1 0x30 6008 0x30 600A 0x30 600C 0x30 600E 0x30 6010 0x30 6012 0x30 6014 0x30 6016 0x30 6018 0x30 601A 0x30 601C 0x30 601E 0x30 6080 0x30 6082 0x30 6084 0x30 6086 0x30 6088 0x30 608A 0x30 608C 0x30 608E 0x30 6090 0x30 6092 0x30 6094 0x30 6096 MPWMSM1 Period Register (MPWMSMPERR) MPWMSM1 Pulse Register (MPWMSMPULR) MPWMSM1 Count Register (MPWMSMCNTR) MPWMSM1 Status/Control Register (MPWMSMSCR) MPWMSM2 MPWMSM2 Period Register (MPWMSMPERR) MPWMSM2 Pulse Register (MPWMSMPULR) MPWMSM2 Count Register (MPWMSMCNTR) MPWMSM2 Status/Control Register (MPWMSMSCR) MPWMSM3 MPWMSM3 Period Register (MPWMSMPERR) MPWMSM3 Pulse Register (MPWMSMPULR) MPWMSM3 Count Register (MPWMSMCNTR) MPWMSM3 Status/Control Register (MPWMSMSCR) MPWMSM16 MPWMSM16 Period Register (MPWMSMPERR) MPWMSM16 Pulse Register (MPWMSMPULR) MPWMSM16 Count Register (MPWMSMCNTR) MPWMSM16 Status/Control Register (MPWMSMSCR) MPWMSM17 MPWMSM17 Period Register (MPWMSMPERR) MPWMSM17 Pulse Register (MPWMSMPULR) MPWMSM17 Count Register (MPWMSMCNTR) MPWMSM17 Status/Control Register (MPWMSMSCR) MPWMSM18 MPWMSM18 Period Register (MPWMSMPERR) MPWMSM18 Pulse Register (MPWMSMPULR) MPWMSM18 Count Register (MPWMSMCNTR) MPWMSM18 Status/Control Register (MPWMSMSCR)
0x30 6006
MPC555
/ MPC556
MOTOROLA 15-26
USERS MANUAL

Table 15-19 MPWMSM Address Map (Continued)
Address 0x30 6098 0x30 609A 0x30 609C 0x30 609E Register MPWMSM19 MPWMSM19 Period Register (MPWMSMPERR) MPWMSM19 Pulse Register (MPWMSMPULR) MPWMSM19 Count Register (MPWMSMCNTR) MPWMSM19 Status/Control Register (MPWMSMSCR)
15.12.1.1 MPWMSM Period Register (MPWMSMPERR) The period register contains the binary value corresponding to the period to be generated.
MPWMSMPERR MPWMSM Period Register

MSB 0 1 2 3 4 5 6 7 PER RESET: U U U U U U U U U U U U U U 8 9 10 11 12
0x30 6000*
13 14 LSB 15
* Refer to Table 15-19 for a complete list of all the base addresses for the MPWMSM registers.
Table 15-20 MPWMSMPERR Bit Descriptions

Bit(s) 0:15 Name PER Description Period. These bits contain the binary value corresponding to the period to be generated.
15.12.1.2 MPWMSM Pulse Width Register (MPWMSMPULR) This register contains the binary value of the pulse width to be generated. MPWMSMPULR MPWMSM Pulse Width Register
MSB 0 1 2 3 4 5 6 7 PUL RESET: U U U U U U U U U U U U U U U U 8 9 10 11 12
0x30 6002*
13 14 LSB 15
Table 15-21 MPWMSMPULR Bit Descriptions

Bit(s) 0:15 Name PUL Description Pulse width. These bits contain the binary value of the pulse width to be generated.
MPC555
/ MPC556
MOTOROLA 15-27
USERS MANUAL

15.12.1.3 MPWMSM Counter Register (MPWMSMCNTR) This register reflects the actual value of the MPWMSM counter. MPWMSMCNTR MPWMSM Counter Register
MSB 0 1 2 3 4 5 6 7 CNT RESET: U U U U U U U U U U U U U U U U 8 9 10 11 12
0x30 6004*
13 14 LSB 15
* Refer to Table 15-19 for a complete list of all the base addresses for the MPWMSM registers. A write to the MPWMSMCNTR register also writes the same value to MPWMSMPERR.
Table 15-22 MPWMSMCNTR Bit Descriptions
Bit(s) 0:15
Name CNT
Description Counter. These bits reflect the actual value of the MPWMSM counter.
15.12.1.4 MPWMSM Status/Control Register(MPWMSMCR) This register contains read-only status bits and read/write control bits. MPWMSMSCR MPWMSM Status/Control Register
MSB 0 PIN 1 DDR 2 3 4 POL 5 EN 6 7 8 9 10 11 CP 12
0x30 6006*
13 14 LSB 15
FREN TRSP
RESERVED
RESET: 0 0 0 0 0 0 0 U U U U U U U U
MPC555
/ MPC556
MOTOROLA 15-28
USERS MANUAL

Table 15-23 MPWMSMSCR Bit Descriptions
Bit(s) 0 Name PIN Description Pin input status. The PIN bit reflects the state present on the MPWMSM pin. The software can thus monitor the signal on the pin. The PIN bit is a read-only bit. Writing to the PIN bit has no effect. Data direction register. The DDR bit indicates the direction for the pin when the PWM function is not used (disable mode). Note that when the PWM function is used, the DDR bit has no effect. 1 DDR Table 15-24 lists the different uses for the polarity (POL) bit, the enable (EN) bit and the data direction register (DDR) bit. 0 = Pin is an input. 1 = Pin is an output. Freeze enable. This active high read/write control bit enables the MPWMSM to recognize the freeze signal on the MIOB. 0 = MPWMSM not frozen even if the MIOB freeze line is active. 1 = MPWMSM frozen if the MIOB freeze line is active. Transparent mode. The TRSP bit indicates that the MPWMSM double buffers are transparent: when the software writes to either the MPWMA or MPWMB1 register the value written is immediately transferred to respectively the counter or register MPWMB2. 0 = Transparent mode de-activated. 1 = Transparent mode activated. Output polarity control. The POL bit works in conjunction with the EN bit and controls whether the MPWMSM drives the pin with the true or the inverted value of the output flip-flop Table 15-24 lists the different uses for the polarity (POL) bit, the enable (EN) bit and the data direction register (DDR) bit. Enable PWM signal generation. The EN bit defines whether the MPWMSM generates a PWM signal or is used as an I/O channel: 5 EN Table 15-24 lists the different uses for the polarity (POL) bit, the enable (EN) bit and the data direction register (DDR) bit. 0 = PWM generation disabled (pin can be used as I/O). 1 = PWM generation enabled (pin is output only). Reserved Clock Prescaler. This 8-bit read/write register stores the twos complement of the desired modulus value for loading into the built-in 8-bit clock prescaler. The value loaded defines the divide ratio for the signal that clocks the MPWMSM period counter. Table 15-15 gives the clock divide ratio according to the CP values.
FREN
TRSP
POL
6:7
8:15
CP
Table 15-24 PWMSM Output Pin Polarity Selection

Control Bits POL 0 0 0 1 1 1 EN 0 0 1 0 0 1 DDR 0 1 0 1 Pin Direction (I/O) I O O I O O Pin State Input Always Low High Pulse Input Always High Low Pulse Periodic Edge Falling Edge Rising Edge Variable Edge Rising Edge Falling Edge Optional Interrupt On Falling Edge Rising Edge
MPC555
/ MPC556
MOTOROLA 15-29
USERS MANUAL

15.13 MIOS 16-bit Parallel Port I/O Submodule (MPIOSM) An MIOS 16-bit parallel port I/O submodule (MPIOSM) can handle up to 16 input/output pins. Its control register is composed of two 16-bit registers: the data register (DR) and the data direction register (DDR). Each pin of the MPIOSM may be programmed as an input or an output under software control. The direction of a pin is determined by the state of the corresponding bit in the DDR.
DATA DIRECTION REGISTER
MIOB
DATA REGISTER Output Driver
I/O PIN
Input
Figure 15-7 MPIOSM One-Bit Block Diagram Refer to Table 15-36 for the MPIOSM relative I/O pin implementation. 15.13.1 MIOS 16-bit Parallel Port I/O Submodule (MPIOSM) Registers One set of registers is associated with the MPIOSM submodule. The base addresses of the submodules are given in the table below. Table 15-25 MPIOSM Address Map
Address 0x30 6100 0x30 6102 0x30 6104 0x30 6106 Register MPIOSM Data Register (MPIOSMDR) See Table 15-26 for bit descriptions. MPIOSM Data Direction Register (MPIOSMDDR) See Table 15-27 for bit descriptions. Reserved Reserved
15.13.1.1 MPIOSM Data Register (MPIOSMDR) This read/write register defines the value to be driven to the pad in output mode, for each implemented I/O pin of the MPIOSM.
MPC555
/ MPC556
MOTOROLA 15-30
USERS MANUAL

MPIOSMDR MPIOSM Data Register
MSB 0 D15 1 D14 2 D13 3 D12 4 D11 5 D10 6 D9 7 D8 8 D7 9 D6 10 D5 11 D4 12 D3 13 D2
0x30 6100
14 D1 LSB 15 D0
RESET: U U U U U U U U U U U U U U U U
Table 15-26 MPIOSMDR Bit Descriptions

Bit(s) Name Description Data BITS. These bits are read/write data bits that define the value to be driven to the pad in output mode for each implemented I/O pin of the MPIOSM. While in output mode, a read returns the value of the pad. Note that, when little-endian bit ordering is used, bit 0 corresponds to D15 and bit 15 corresponds to D0.
0:15
D[15:0]
NOTE D[0:4] controls the signals MPIO32B[0:4]. These functions are shared on the MPC555 / MPC556 pins VF[0:2]/MPIO32B[0:2] VFLS[0:1]/MPIO32B[3:4] and can be configured as the alternate function (VF[0:2] and VFLS[0:1]). See 15.8.1.1 MIOS1 Test and Pin Control Register. 15.13.1.2 MPIOSM Data Direction Register (MPIOSMDDR) This read/write register defines the data direction for each implemented I/O pin of the MPIOSM. MPIOSMDDR MPIOSM Data Direction Register
MSB 0 1 2 3 4 5 6 7 8 9 10 DDR5 11 12 13
0x30 6102
14 LSB 15
DDR1 DDR1 DDR1 DDR1 DDR1 DDR10 DDR9 DDR8 DDR7 DDR6 RESET: 0 0 0 0 0 0 0 0 0 0
DDR4 DDR3 DDR2 DDR1 DDR0
Table 15-27 MPIOSMDDR Bit Descriptions

Bit(s) Name Description Data direction. These bits are read/write data bits that define the data direction status for each implemented I/O pin of the MPIOSM. Note that, when little-endian bit ordering is used, bit 0 corDDR[15:0] responds to D15 and bit 15 corresponds to D0. 0 = Corresponding pin is input. 1 = Corresponding pin is output.
0:15
15.14 MIOS1 Interrupts The MIOS1 and its submodules are capable of generating interrupts to be transmitted to the CPU via the IMB3. Inside the MIOS1, all the information required for requesting and servicing the interrupts are treated in two different blocks: The interrupt control section (ICS)
MPC555
/ MPC556
MOTOROLA 15-31
USERS MANUAL

The MIOS interrupt request submodules (MIRSM). The MIOS interrupt request submodule gathers service request flags from each group of up to 16 submodules and transfers those requests to the MIOS1 interrupt control section (ICS). Figure 15-8 shows a block diagram of the interrupt architecture.
Submodule 13
Submodule 2
(Flags) Status Register
Enable Register Level n Request IRQ Pend. Register Acknowledge IRQ Level Register
RQSM #0
RQSM #1 Submodules 16 to 23 Interrupt Control Section MBISM IMB3
Figure 15-8 MIOS Interrupt Structure 15.14.1 MIOS Interrupt Request Submodule (MIRSM) Each submodule that is capable of generating an interrupt can assert a flag line when an event occurs. In the MIOS1 configuration, there are eighteen flag lines and two MIRSMs are needed.
MPC555
/ MPC556
MOTOROLA 15-32
USERS MANUAL

Within the MIOS1, each MIRSM includes: One 16-bit status register (for the flags) One 16-bit enable register One 16-bit IRQ pending register One bit position in each of the above registers is associated with one submodule. Note that if a submodule in a group of 16 cannot generate interrupts, then its corresponding flag bit in the status register is inactive and reads as zero. When an event occurs in a submodule that activates a flag line, the corresponding flag bit in the status register is set. The status register is read/write, but a flag bit can be reset only if it has previously been read as a one. Writing a one to a flag bit has no effect. When the software intends to clear only one flag bit within a status register, the software must write an 16-bit value of all ones except for a zero in the bit position to be cleared. The enable register is initialized by the software to indicate whether each interrupt request is enabled for the level defined in the ICS. Each bit in the IRQ pending register is the result of a logical AND between the corresponding bits in the status and in the enable registers. If a flag bit is set and the level enable bit is also set, then the IRQ pending bit is set and the information is transferred to the interrupt control section that is in charge of sending the corresponding level to the CPU. The IRQ pending register is read only. NOTE When the enable bit is not set for a particular submodule, the corresponding status register bit is still set when the corresponding flag is set. This allows the traditional software approach of polling the flag bits to see which ones are set. The status register makes flag polling easy, since up to sixteen flag bits are contained in one register. The submodule number of an interrupting source defines the corresponding MIRSM number and the bit position in the status registers. To find the MIRSM number and bit position of an interrupting source, divide the interrupting submodule number by 16. The integer result of the division gives the MIRSM number. The remainder of the division gives the bit position. Refer to 15.14.2 MIOS Interrupt Request Submodule 0 (MIRSM0) Registers and to 15.14.3 MIOS Interrupt Request Submodule 1 (MIRSM1) Registers for details about the registers in the MIRSM. 15.14.2 MIOS Interrupt Request Submodule 0 (MIRSM0) Registers Table 15-28 shows the registers associated with the MIRSM0 submodule.
MPC555
/ MPC556
MOTOROLA 15-33
USERS MANUAL

Table 15-28 MIRSM0 Address Map
Address 0x30 6C00 0x30 6C02 0x30 6C04 0x30 6C06 Register MIRSM0 Interrupt Status Register (MIOS1SR0) See Table 15-29 for bit descriptions. Reserved MIRSM0 Interrupt Enable Register (MIOS1ER0) See Table 15-30 for bit descriptions. MIRSM0 Request Pending Register (MIOS1RPR0) See Table 15-31 for bit descriptions.
15.14.2.1 MIRSM0 Interrupt Status Register (MIOS1SR0) This register contains flag bits that are set when the associated submodule generates an interrupt. Each bit corresponds to a submodule. When an event occurs in a submodule that activates a flag line, the corresponding flag bit in the status register is set. The status register is read/write, but a flag bit can be reset only if it has previously been read as a one. Writing a one to a flag bit has no effect. When the software intends to clear only one flag bit within a status register, the software must write an 16-bit value of all ones except for a zero in the bit position to be cleared. MIOS1SR0 RQSM0 Interrupt Status Register
MSB 0 1 2 3 4 5 6 7 8 9 FLG6 10 11 12 FLG3 13 FLG2
0x30 6C00
14 FLG1 LSB 15 FLG0
FLG15 FLG14 FLG13 FLG12 FLG11 RESET: U U U U U 0
RESERVED
RESERVED
Table 15-29 MIOS1SR0 Bit Descriptions

Bit(s) 0 1 2 3 4 5:8 9 10:11 12 13 14 15 Name FLG15 FLG14 FLG13 FLG12 FLG11 FLG6 FLG3 FLG2 FLG1 FLG0 MDASM15 flag bit MDASM14 flag bit MDASM13 flag bit MDASM12 flag bit MDASM11 flag bit Reserved MMCSM6 flag bit Reserved MPWMSM3 flag bit MPWMSM2 flag bit MPWMSM1 flag bit MPWMSM0 flag bit Description
MPC555
/ MPC556
MOTOROLA 15-34
USERS MANUAL

15.14.2.2 MIRSM0 Interrupt Enable Register (MIOS1ER0) This read/write register contains interrupt enable bits. Each bit corresponds to a submodule. MIOS1ER0 MIRSM0 Interrupt Enable Register
MSB 0 EN15 1 EN14 2 EN13 3 EN12 4 EN11 5 6 7 8 9 EN6 10 11 12 EN3 13 EN2
0x30 6C04
14 EN1 LSB 15 EN0
RESERVED
RESERVED
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 15-30 MIOS1ER0 Bit Descriptions
Bit(s) 0 1 2 3 4 5:8 9 10:11 12 13 14 15
Name EN15 EN14 EN13 EN12 EN11 EN6 EN3 EN2 EN1 EN0
Description MDASM15 interrupt enable bit MDASM14 interrupt enable bit MDASM13 interrupt enable bit MDASM12 interrupt enable bit MDASM11 interrupt enable bit Reserved MMCSM6 interrupt enable bit Reserved MPWMSM3 interrupt enable bit MPWMSM2 interrupt enable bit MPWMSM1 interrupt enable bit MPWMSM0 interrupt enable bit
15.14.2.3 MIRSM0 Request Pending Register (MIOS1RPR0) This read-only register contains interrupt pending bits. Each bit corresponds to a submodule. A bit that is set indicates that the associated submodule set its flag and that the corresponding enable bit was set. MIOS1RPR0 MIRSM0 Request Pending Register
MSB 0 1 2 3 4 5 6 7 8 9 IRP6 0 0 10 11 12 IRP3 0 13 IRP2 0 IRP15 IRP14 IRP13 IRP12 IRP11 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 RESERVED RESERVED
0x30 6C06
14 IRP1 LSB 15 IRP0
MPC555
/ MPC556
MOTOROLA 15-35
USERS MANUAL

Table 15-31 MIOS1RPR0 Bit Descriptions
Bit(s) 0 1 2 3 4 5:8 9 10:11 12 13 Name IRP15 IRP14 IRP13 IRP12 IRP11 IRP6 IRP3 IRP2 IRP1 IRP0 Description MDASM15 IRQ pending bit MDASM14 IRQ pending bit MDASM13 IRQ pending bit MDASM12 IRQ pending bit MDASM11 IRQ pending bit Reserved MMCSM6 IRQ pending bit Reserved MPWMSM3 IRQ pending bit MPWMSM2 IRQ pending bit MPWMSM1 IRQ pending bit MPWMSM0 IRQ pending bit
14 15
15.14.3 MIOS Interrupt Request Submodule 1 (MIRSM1) Registers Table 15-32 shows the base addresses of the registers associated with the MIRSM1 submodule. Table 15-32 MIRSM1 Address Map
Address 0x30 6C40 0x30 6C42 0x30 6C44 0x30 6C46 Register MIRSM1 Interrupt Status Register (MIOS1SR1) See Table 15-33 for bit descriptions. Reserved MIRSM1 Interrupt Enable Register (MIOS1ER1) See Table 15-34 for bit descriptions. MIRSM1 Request Pending Register (MIOS1PR1) See Table 15-35 for bit descriptions.
15.14.3.1 MIRSM1 Interrupt Status Register (MIOS1SR1) This register contains flag bits that are set when the associated submodule generates an interrupt. Each bit corresponds to a submodule. MIOS1SR1 MIRSM1 Interrupt Status Register
MSB 0 1 2 3 4 5 6 7 8 9 FLG22 10 11 12 13
0x30 6C40
14 LSB 15
FLG31 FLG30 FLG29 FLG28 FLG27 RESET: U U U U U 0
RESERVED
RESERVED
FLG19 FLG18 FLG17 FLG16
MPC555
/ MPC556
MOTOROLA 15-36
USERS MANUAL

Table 15-33 MIOS1SR1 Bit Descriptions
Bit(s) 0 1 2 3 4 5:8 9 10:11 12 13 Name FLG31 FLG30 FLG29 FLG28 FLG27 FLG22 FLG19 FLG18 FLG17 FLG16 MDASM31 flag bit MDASM30 flag bit MDASM29 flag bit MDASM28 flag bit MDASM27 flag bit Reserved MMCSM22 flag bit Reserved MPWMSM19 flag bit MPWMSM18 flag bit MPWMSM17 flag bit MPWMSM16 flag bit Description
14 15
15.14.3.2 MIRSM1 Interrupt Enable Register (MIOS1ER1) This read/write register contains interrupt enable bits. Each bit corresponds to a submodule. MIOS1ER1 Interrupt Enable Register
MSB 0 EN31 0 1 2 3 4 EN27 0 0 5 6 7 8 9 EN22 0 0 10 11 12 EN19 0 13 EN18 0 EN30 EN129 EN28 0 0 0 RESERVED 0 0 RESERVED 0 0
0x30 6C44
14 EN17 0 LSB 15 EN16 0
RESET:
Table 15-34 MIOS1ER1 Bit Descriptions

Bit(s) 0 1 2 3 4 5:8 9 10:11 12 13 14 15 Name EN31 EN30 EN29 EN28 EN27 EN22 EN19 EN18 EN17 EN16 Description MDASM31 interrupt enable bit MDASM30 interrupt enable bit MDASM29 interrupt enable bit MDASM28 interrupt enable bit MDASM27 interrupt enable bit Reserved MMCSM22 interrupt enable bit Reserved MPWMSM19 interrupt enable bit MPWMSM18 interrupt enable bit MPWMSM17 interrupt enable bit MPWMSM16 interrupt enable bit
15.14.3.3 MIRSM1 Request Pending Register (MIOS1RPR1) This read-only register contains interrupt pending bits. Each bit corresponds to a submodule. A bit that is set indicates that the associated submodule set its flag and that the corresponding enable bit was set.
MPC555
/ MPC556
MOTOROLA 15-37
USERS MANUAL

MIOS1RPR1 MIRSM1 Request Pending Register
MSB 0 1 2 3 4 5 6 7 8 9 IRP22 10 11 12 13
0x30 6C46
14 LSB 15
IRP31 IRP30 IRP29 IRP28 IRP27 RESET: 0 0 0 0 0 0
RESERVED
RESERVED
IRP19 IRP18 IRP17 IRP16
Table 15-35 MIOS1RPR1 Bit Descriptions

Bit(s) 0 1 2 Name IRP31 IRP30 IRP29 IRP28 IRP27 IRP22 IRP19 IRP18 IRP17 IRP16 Description MDASM31 IRQ pending bit MDASM30 IRQ pending bit MDASM29 IRQ pending bit MDASM28 IRQ pending bit MDASM27 IRQ pending bit Reserved MMCSM22 IRQ pending bit Reserved MPWMSM19 IRQ pending bit MPWMSM18 IRQ pending bit MPWMSM17 IRQ pending bit MPWMSM16 IRQ pending bit
3 4 5:8 9 10:11 12 13 14 15
15.15 MIOS1 Function Examples The versatility of the MIOS1 timer architecture is based on multiple counters and capture/compare channel units interconnected on 16-bit counter buses. This section includes some typical application examples to show how the submodules can be interconnected to form timing functions. The diagrams used to illustrate these examples show only the blocks utilized for that function. To illustrate the timing range of the MIOS1 in different applications, many of the following paragraphs include time intervals quoted in microseconds and seconds. The assumptions used are that fSYS is at 40 MHz with minimum overall prescaling (50 ns cycle) and with the maximum overall prescaling (32 s cycle). For other fSYS clock cycle rates and prescaler choices, the times mentioned in these paragraphs scale appropriately. 15.15.1 MIOS1 Input Double Edge Pulse Width Measurement To measure the width of an input pulse, the MIOS double action submodule (MDASM) has two capture registers so that only one interrupt is needed after the second edge. The software can read both edge samples and subtract them to get the pulse width. The leading edge sample is double latched so that the software has the time of one full period of the input signal to read the samples to be sure that nothing is lost. Depending on the prescaler divide ratio, pulse width from 50 ns to 6.7 s can be measured. Note that a software option is provided to also generate an interrupt after the first edge.
MPC555
/ MPC556
MOTOROLA 15-38
USERS MANUAL

In the example shown in Figure 15-9, a counter submodule is used as the time-base for a MDASM configured in the input pulse width measurement mode. When the leading edge (programmed for being either rising or falling) of the input signal occurs, the state of the 16-bit counter bus is saved in register B1. When the trailing edge occurs, the 16-bit counter bus is latched into register A and the content of register B1 is transferred to register B2. This operation leaves register B1 free for the next leading edge to occur on the next clock cycle. When enabled, an interrupt is provided after the trailing edge, to notify the software that pulse width measurement data is available for a new pulse. After the trailing edge, the software has one cycle time of the input signal to obtain the values for each edge. When software attention is not needed for every pulse, the interrupt can be disabled. The software can read registers A and B2 coherently (using a 32-bit read instruction) at any time, to get the latest edge measurements. The software work is less than half that needed with a timer that requires the software to read one edge and save the value and then wait for the second edge.
MIOS Modulus Counter Submodule Two 16-bit Counter Buses
MIOS Double Action Submodule in IPWM mode (MOD3-MOD0 = 0b0001)
Input Pin 16-bit Register A Bus Select Edge Detect
From Prescaler or Pin
Clock Select
16-bit Up-Counter 16-bit Register B1 Input Capture Interrupt on Trailing Edge
16-bit Register B2 Submodule Bus
Figure 15-9 MIOS1 Example: Double Capture Pulse Width Measurement
MPC555
/ MPC556
MOTOROLA 15-39
USERS MANUAL

15.15.2 MIOS1 Input Double Edge Period Measurement Two samples are available to the software from an MIOS double action submodule for period measurement. The software can read the previous and the current edge samples and subtract them. As with pulse width measurement, the software can be sure not to miss samples by ensuring that the interrupt response time is faster than the fastest input period. Alternately, when the software is just interested in the latest period measurement, one 32-bit coherent read instruction can get both the current and the previous samples. Depending on the prescaler divide ratio, period times can be measured from 50 ns to 6.7 s. Figure 15-10 shows a counter submodule and a DASM combination as an example of period measurement. The software designates whether the rising or falling edge of the input signal is to be used for the measurements. When the edge is detected, the state of the 16-bit counter bus is stored in register A and the content of register B1 is transferred to register B2. After register B2 is safely latched, the content of register A is transferred to register B1. This procedure gives the software coherent current and previous samples in registers A and B2 at all times. An interrupt is available for the cases where the software needs to be aware of each new sample. Note that a software option is provided to also generate an interrupt after the first edge.
MIOS Modulus Counter Submodule
MIOS Double Action Submodule in IPM mode (MOD3-MOD0 = 0b0010)
Input Bus Select 16-bit Register A Pin
Edge Detect
Clock Select
16-bit Up-Counter
Two 16-bit Counter Buses
16-bit Register B1
Input Capture Interrupt on Designated Edge
Figure 15-10 MIOS1 Example: Double Capture Period Measurement
MPC555
/ MPC556
MOTOROLA 15-40
USERS MANUAL

15.15.3 MIOS1 Double Edge Single Output Pulse Generation Software can initialize the MIOS1 to generate both the rising and the falling edge of an output pulse. With a MDASM, pulses as narrow as 50 ns can be generated since software action is not needed between the edges. Pulses as long as 2.1 s can be generated. When an interrupt is desired, it can be selected to occur on every edge or only after the second edge. Figure 15-11 shows how a counter submodule and a MDASM can be used to generate both edges of a single output pulse. The software puts the compare value for one edge in register A and the other one in register B2. The MDASM automatically creates both edges and the pulse can be selected by software to be a high-going or a low-going. After the trailing edge, the MDASM stops to await further commands from the software. Note that a single edge output can be generated by writing to only one register.
MIOS Modulus Counter Submodule Two 16-bit Counter Buses
MIOS Double Action Submodule in OCB mode (MOD3 - MOD0 = 0b0100)
16-bit Register A
Output Pin
16-bit Compare A Bus Select 16-bit Compare B Output Flip-Flop
Clock Select
16-bit Up-Counter
Output Compare Interrupt on Trailing Edge
Figure 15-11 MIOS1 Example: Double Edge Output Compare
MPC555
/ MPC556
MOTOROLA 15-41
USERS MANUAL

15.15.4 MIOS1 Output Pulse Width Modulation With MDASM Output waveforms can be generated with any duty cycle without software involvement. The software sets up a MDASM with the compare times for the rising and falling edges and they are automatically repeated. The software does not need to respond to interrupts to generate continuous pulses. The frequency may be selected as the frequency of a free-running counter time-base, times a binary multiplier selected in the MDASM. Multiple PWM outputs can be created from multiple MDASMs and share one counter submodule, provided that the frequencies of all of the output signals are a binary multiple of the time-base and that the counter submodule is operating in a free-running mode. Each MDASM has a software selectable dont care on high-order bits of the time-base comparison so that the frequency of one output can be a binary multiple of another signal. Masking the time-base serves to multiply the frequency of the timebase by a binary number to form the frequency of the output waveform. The duty cycle can vary from one cycle to 64-Kbyte cycles. The frequency can range from 0.48 Hz to 156 KHz, though the resolution decreases at the higher frequencies to as low as seven bits. The generation of output square wave signals is of course the special case where the high and low times are equal. When an MMCSM is used to drive the time-base, the modulus value is the period of the output PWM signal. Figure 15-12 shows such an example. The polarity of the leading edge of an output waveform is programmable for a rising or a falling edge. The software selects the period of the output signal by programming the MMCSM with a modulus value. The leading edge compare value is written into register A by software and the trailing edge time is written into register B1. When the leading edge value is reached, the content of register B1 is transferred to register B2, to form the next trailing edge value. Subsequent changes to the output pulse width are made by writing a new time into register B1. Updates to the pulse width are always synchronized to the leading edge of the waveform. It is typical to use the pulse width modulation mode of the MDASM without interrupts, although an interrupt can be enabled to occur on the leading edge. When the output is an unchanging repetitive waveform, the MDASM continuously generates the signal without any software intervention. When the software needs to change the pulse width, a new trailing edge time is written to the MDASM. The output is changed on the next full pulse. When the software needs to change the output at a regular rate, such as an acceleration curve, the leading edge interrupt gives the software one period time to update the new trailing edge time.
MPC555
/ MPC556
MOTOROLA 15-42
USERS MANUAL
MIOS Modulus Counter Submodule
MIOS Double Action Submodule in OCAB mode (MOD3 MOD0 = 0b0101)
16-bit Register A Output Pin 16-bit Compare A
Clock Select
16-bit Up-Counter Load Bus Select 16-bit Compare B Modulus Register Two 16-bit Counter Buses Output Compare Interrupt on Leading Edge Output Flip-Flop
Modulus Control
16-bit Register B2
Figure 15-12 MIOS1 Example: Pulse Width Modulation Output 15.15.5 MIOS1 Input Pulse Accumulation Counting the number of pulses on an input signal is another capability of the MIOS1. Pulse accumulation uses an MMCSM. Since the counters in the counter submodules are software accessible, pulse accumulation does not require the use of an action submodule. The pulse accumulation can operate continuously, interrupting only on binary overflow of the 16-bit counter. When an MMCSM is used, an interrupt can instead be created when the pulse accumulation reaches a preprogrammed value. To do that, the twos complement of the value is put in the modulus register and the interrupt occurs when the counter overflows. 15.16 MIOS1 Configuration The complete MIOS1 submodule and pin configuration is shown in Table 15-36.
MPC555
/ MPC556
MOTOROLA 15-43
USERS MANUAL
Table 15-36 MIOS1 Configuration

connected to: Submodule type Submodule Number CBA CBB CBC CBD RQSM Number RQSM Bit Position Base Address Pin Function Input Pin Name Output Pin Name Alternate Pin Function
BSL=00 BSL=01 BSL=10 BSL=11 MPWMSM MPWMSM MPWMSM MPWMSM Reserved MMCSM 0 1 2 3 4-5 6 CB6 0 6 0x30 6030 Clock In Load In Reserved MDASM MDASM MDASM MDASM MDASM MPWMSM MPWMSM MPWMSM MPWMSM Reserved MMCSM 7-10 11 12 13 14 15 16 17 18 19 20-21 22 CB22 1 6 0x30 60B0 Clock In Load In Reserved MDASM MDASM MDASM MDASM MDASM MPIOSM 23-26 27 28 29 30 31 32 CB6 CB6 CB6 CB6 CB6 CB22 CB22 CB22 CB22 CB22 1 1 1 1 1 11 12 13 14 15 0x30 60D8 0x30 60E0 0x30 60E8 0x30 60F0 0x30 60F8 0x30 6100 Channel I/O Channel I/O Channel I/O Channel I/O Channel I/O GP I/O
1
0 0 0 0
0 1 2 3
0x30 6000 0x30 6008 0x30 6010 0x30 6018
PWM, I/O PWM, I/O PWM, I/O PWM, I/O
MPWM0 MPWM1 MPWM2 MPWM3
MPWM0 MPWM1 MPWM2 MPWM3
MDA11 MDA12
CB6 CB6 CB6 CB6 CB6
CB22 CB22 CB22 CB22 CB22
0 0 0 0 0 1 1 1 1
11 12 13 14 15 0 1 2 3
0x30 6058 0x30 6060 0x30 6068 0x30 6070 0x30 6078 0x30 6080 0x30 6088 0x30 6090 0x30 6098
Channel I/O Channel I/O Channel I/O Channel I/O Channel I/O PWM, I/O PWM, I/O PWM, I/O PWM, I/O
MDA11 MDA12 MDA13 MDA14 MDA15 MPWM16 MPWM17 MPWM18 MPWM19
MDA11 MDA12 MDA13 MDA14 MDA15 MPWM16 MPWM17 MPWM18 MPWM19
MDA13 MDA14
MDA27 MDA28 MDA29 MDA30 MDA31 MPIO32B0 MPIO32B1 MPIO32B2 MPIO32B3 MPIO32B4 MPIO32B5 MPIO32B6 MPIO32B7 MPIO32B8 MPIO32B9
MDA27 MDA28 MDA29 MDA30 MDA31 MPIO32B0 MPIO32B1 MPIO32B2 MPIO32B3 MPIO32B4 MPIO32B5 MPIO32B6 MPIO32B7 MPIO32B8 MPIO32B9 VF0 VF1 VF2 VFLS0 VFLS1
GP I/O GP I/O GP I/O GP I/O GP I/O GP I/O GP I/O GP I/O GP I/O
MPC555
/ MPC556
MOTOROLA 15-44
USERS MANUAL

Table 15-36 MIOS1 Configuration (Continued)
connected to: Submodule type Submodule Number CBA CBB CBC CBD RQSM Number RQSM Bit Position Base Address Pin Function Input Pin Name Output Pin Name Alternate Pin Function
BSL=00 BSL=01 BSL=10 BSL=11 GP I/O GP I/O GP I/O GP I/O GP I/O GP I/O Reserved 33-255 256 257 258 259 384-391 392-399 400-511 0x30 6C00 0x30 6C40 0x30 6810 0x30 6800 MPIO32B10 MPIO32B11 MPIO32B12 MPIO32B13 MPIO32B14 MPIO32B15 MPIO32B10 MPIO32B11 MPIO32B12 MPIO32B13 MPIO32B14 MPIO32B15
MBISM Reserved MCPSM Reserved RQSM0 RQSM1 Reserved
NOTES: 1. GP = General purpose.
MPC555
/ MPC556
MOTOROLA 15-45
USERS MANUAL
MPC555
/ MPC556
MOTOROLA 15-46
USERS MANUAL
SECTION 16 CAN 2.0B CONTROLLER MODULE

The MPC555 / MPC556 contains two CAN 2.0B controller modules (TouCAN). Each TouCAN is a communication controller that implements the controller area network (CAN) protocol, an asynchronous communications protocol used in automotive and industrial control systems. It is a high speed (1 Mbit/sec), short distance, priority based protocol that can run over a variety of mediums (for example, fiber optic cable or an unshielded twisted pair of wires). The TouCAN supports both the standard and extended identifier (ID) message formats specified in the CAN protocol specification, revision 2.0, part B. Each TouCAN module contains 16 message buffers, which are used for transmit and receive functions. It also contains message filters, which are used to qualify the received message IDs when comparing them to the receive buffer identifiers. Figure 16-1 shows a block diagram of a TouCAN module.
16Rx/Tx Message Buffers
Transmitter Control Receiver
CNTX0 CNTX11 CNRX0 CNRX11
Slave Bus Interface Unit
IMB 1. In the MPC555 / MPC556, the CNTX1 and CNRX1 signals are not available.
Figure 16-1 TouCAN Block Diagram 16.1 Features Each TouCAN module provides these features: Full implementation of CAN protocol specification, version 2.0 A/B Standard data and remote frames (up to 109 bits long)
MPC555 / MPC556 USERS MANUAL CAN 2.0B CONTROLLER MODULE MOTOROLA 16-1

Extended data and remote frames (up to 127 bits long) 0 to 8 bytes data length Programmable bit rate up to 1 Mbit/sec 16 RX/TX message buffers of 0-8 bytes data length Content-related addressing No read/write semaphores required Three programmable mask registers: global (for message buffers zero through 13), special for message buffer 14, and special for message buffer 15 Programmable transmit-first scheme: lowest ID or lowest buffer number Time stamp, based on 16-bit free-running timer Global network time, synchronized by a specific message Programmable I/O modes Maskable interrupts Independent of the transmission medium (external transceiver is assumed) Open network architecture Multimaster concept High immunity to EMI Short latency time for high-priority messages Low power sleep mode with programmable wakeup on bus activity Outputs have open drain drivers Can be used to implement recommended practices SAE J1939 and SAE J2284 Can also be used to implement popular industrial automation standards such as DeviceNet and Smart Distributed System Motorola IMB-family modular architecture 16.2 External Pins The TouCAN module interface to the CAN bus consists of four pins: CANTX0 and CANTX1, which transmit serial data, and CANRX0 and CANRX1, which receive serial In the MPC555 / MPC556, the CNTX1 and CNRX1 signals are not available. NOTE In the MPC555 / MPC556, the CNTX1 and CNRX1 signals are not available.
MPC555
/ MPC556
CAN 2.0B CONTROLLER MODULE
MOTOROLA 16-2
USERS MANUAL
CAN STATION 1
CAN STATION 2
CAN STATION n
CAN SYSTEM
CAN CONTROLLER (TouCAN)

CNTX0 CNTX11 CNRX0 CNRX11
TRANSCEIVER
1. In the MPC555, the CNTX1 and CNRX1 signals are not available.
Figure 16-2 Typical CAN Network Each CAN station is connected physically to the CAN bus through a transceiver. The transceiver provides the transmit drive, waveshaping, and receive/compare functions required for communicating on the CAN bus. It can also provide protection against damage to the TouCAN caused by a defective CAN bus or a defective CAN station. 16.3 TouCAN Architecture The TouCAN module uses a flexible design that allows each of its 16 message buffers to be designated either a transmit (Tx) buffer or a receive (Rx) buffer. In addition, to reduce the CPU overhead required for message handling, each message buffer is assigned an interrupt flag bit to indicate that the transmission or reception completed successfully. 16.3.1 TX/RX Message Buffer Structure Figure 16-3 displays the extended (29-bit) ID message buffer structure. Figure 16-4 displays the standard (11-bit) ID message buffer structure.
MPC555
/ MPC556
MOTOROLA 16-3
USERS MANUAL
MSB 0 0x0 0x2 0x4 0x6 0x8 0xA 0xC 0xE DATA BYTE 0 DATA BYTE 2 DATA BYTE 4 DATA BYTE 6 RESERVED
1
LSB 7 8 CODE SRR ID[14-0] DATA BYTE 1 DATA BYTE 3 DATA BYTE 5 DATA BYTE 7 IDE 11 12 LENGTH ID[17-15] 15 CONTROL/STATUS ID_HIGH RTR ID_LOW
TIME STAMP ID[28-18]
NOTES: 1. The reading of a reserved location in memory may cause an RCPU exception.
Figure 16-3 Extended ID Message Buffer Structure
MSB 0 0x0 0x2 0x4 0x6 0x8 0xA $C 0xE TIME STAMP ID[28:18] DATA BYTE 0 DATA BYTE 2 DATA BYTE 4 DATA BYTE 6 RESERVED1 7 8 CODE RTR 0 16-BIT TIME STAMP DATA BYTE 1 DATA BYTE 3 DATA BYTE 5 DATA BYTE 7 11 12 LENGTH 0 0
LSB 15 CONTROL/STATUS 0 ID_HIGH ID_LOW
NOTES: 1. The reading of a reserved location in memory may cause an RCPU exception.
Figure 16-4 Standard ID Message Buffer Structure 16.3.1.1 Common Fields for Extended and Standard Format Frames Table 16-1 describes the message buffer fields that are common to both extended and standard identifier format frames.
MPC555
/ MPC556
MOTOROLA 16-4
USERS MANUAL

Table 16-1 Common Extended/Standard Format Frames
Field Time Stamp Code Rx Length Description Contains a copy of the high byte of the free running timer, which is captured at the beginning of the identifier field of the frame on the CAN bus. Refer to Table 16-2 and Table 16-3. Length (in bytes) of the Rx data stored in offset 0x6 through 0xD of the buffer.This field is written by the TouCAN module, copied from the DLC (data length code) field of the received frame. Length (in bytes) of the data to be transmitted, located in offset 0x6 through 0xD of the buffer. This field is written by the CPU and is used as the DLC field value. If RTR (remote transmission request) = 1, the frame is a remote frame and will be transmitted without data field, regardless of the value in Tx length. This field can store up to eight data bytes for a frame. For Rx frames, the data is stored as it is received from the bus. For Tx frames, the CPU provides the data to be transmitted within the frame. The CPU controls access to this word entry field (16 bits).
Tx Length
Data
Reserved
Table 16-2 Message Buffer Codes for Receive Buffers

Rx Code Before Rx New Frame 0b0000 0b0100 0b0010 0b0110 Description NOT ACTIVE message buffer is not active. EMPTY message buffer is active and empty. FULL message buffer is full. OVERRUN second frame was received into a full buffer before the CPU read the first one. BUSY message buffer is now being filled with a new receive frame. This condition will be cleared within 20 cycles. 0b0110 0b0010 0b0110 Rx Code After Rx New Frame 0b0010 Comment If a CPU read occurs before the new frame, new receive code is 0010. An empty buffer was filled (XY was 10). A full/overrun buffer was filled (Y was 1).
0b0XY11
NOTES: 1. For Tx message buffers, upon read, the BUSY bit should be ignored.
Table 16-3 Message Buffer Codes for Transmit Buffers

RTR X 0 1 0 0 Initial Tx Code 0b1000 0b1100 0b1100 0b10101 0b1110 Description Message buffer not ready for transmit. Data frame to be transmitted once, unconditionally. Remote frame to be transmitted once, and message buffer becomes an RX message buffer for data frames. Data frame to be transmitted only as a response to a remote frame, always. Data frame to be transmitted only once, unconditionally, and then only as a response to remote frame, always. Code After Successful Transmission 0b1000 0b0100 0b1010 0b1010
NOTES: 1. When a matching remote request frame is detected, the code for such a message buffer is changed to be 1110.
MPC555
/ MPC556
MOTOROLA 16-5
USERS MANUAL

16.3.1.2 Fields for Extended Format Frames Table 16-4 describes the message buffer fields used only for extended identifier format frames. Table 16-4 Extended Format Frames
Field Description Contains the 14 most significant bits of the extended identifier, located in the ID HIGH word of the ID[28:18]/[17:15] message buffer. Substitute Contains a fixed recessive bit, used only in extended format. Should be set to one by the user for Remote Request Tx buffers. It will be stored as received on the CAN bus for Rx buffers. (SRR) ID Extended (IDE) If extended format frame is used, this field should be set to one. If zero, standard format frame should be used. Bits [14:0] of the extended identifier, located in the ID LOW word of the message buffer. This bit is located in the least significant bit of the ID LOW word of the message buffer; 0 = Data Frame, 1 = Remote Frame.
ID[14:0] Remote Transmission Request (RTR)
16.3.1.3 Fields for Standard Format Frames Table 16-5 describes the message buffer fields used only for standard identifier format frames. Table 16-5 Standard Format Frames
Field 16-bit Time Stamp Description The ID LOW word, which is not needed for standard format, is used in a standard format buffer to store the 16-bit value of the free-running timer which is captured at the beginning of the identifier field of the frame on the CAN bus. Contains bits [28:18] of the identifier, located in the ID HIGH word of the message buffer. The four least significant bits in this register (corresponding to the IDE bit and ID[17:15] for an extended identifier message) must all be written as logic zeros to ensure proper operation of the TouCAN. This bit is located in the ID HIGH word of the message buffer; 0 = data frame, 1 = remote frame. If the TouCAN transmits this bit as a one and receives it as a zero, an arbitration loss is indicated. If the TouCAN transmits this bit as a zero and is receives it as a one, a bit error is indicated. If the TouCAN transmits a value and receives a matching response, a successful bit transmission is indicated.
ID[28:18]
RTR
RTR/SRR Bit Treatment
16.3.1.4 Serial Message Buffers To allow double buffering of messages, the TouCAN has two shadow buffers called serial message buffers. The TouCAN uses these two buffers for buffering both received messages and messages to be transmitted. Only one serial message buffer is active at a time, and its function depends upon the operation of the TouCAN at that time. At no time does the user have access to or visibility of these two buffers.
MPC555
/ MPC556
MOTOROLA 16-6
USERS MANUAL

16.3.1.5 Message Buffer Activation/Deactivation Mechanism Each message buffer must be activated once the user configures it for the desired operation. A buffer is activated by writing the appropriate code to the control/status word for that buffer. Once the buffer is activated, it will begin participating in the normal transmit and receive processes. A buffer is deactivated by writing the appropriate deactivation code to the control/status word for that buffer. A buffer is typically deactivated when the user desires to reconfigure the buffer (for example to change the buffers function from Rx to Tx or Tx to Rx). The buffer should also be deactivated before changing a receive buffers message identifier or before loading a new message to be transmitted into a transmit buffer.
For more details on activation and deactivation of message buffers and the effects on message buffer operation, refer to 16.4 TouCAN Operation. 16.3.1.6 Message Buffer Lock/Release/Busy Mechanism In addition to the activation/deactivation mechanism, the TouCAN also uses a lock/release/busy mechanism to ensure data coherency during the receive process. The mechanism includes a lock status for each message buffer and uses the two serial message buffers to facilitate frame transfers within the TouCAN. Reading the control/status word of a receive message buffer triggers the lock for that buffer. While locked, a received message cannot be transferred into that buffer from one of the serial message buffers. If a message transfer between the message buffer and a serial message buffer is in progress when the control/status word is read, the BUSY status is indicated in the code field, and the lock is not activated. The user can release the lock on a message buffer in one of two ways. Reading the control/status word of another message buffer locks that buffer, releasing the previously locked buffer. A global release can also be performed on any locked message buffer by reading the free-running timer. Once a lock is released, any message transfers between a serial message buffer and a message buffer that were delayed due to that buffer being locked will take place. For more details on the message buffer locking mechanism, and the effects on message buffer operation, refer to 16.4 TouCAN Operation. 16.3.2 Receive Mask Registers The receive mask registers are used as acceptance masks for received frame IDs. The following masks are defined: A global mask, used for receive buffers 0-13 Two separate masks for buffers 14 and 15 The value of the mask registers should not be changed during normal operation. If the mask register data is changed after the masked identifier of a received message is
MPC555
/ MPC556
MOTOROLA 16-7
USERS MANUAL

matched to a locked message buffer, that message will be transferred into that message buffer once it is unlocked, regardless of whether that messages masked identifier still matches the receive buffer identifier. Table 16-6 shows mask bit values. Table 16-6 Receive Mask Register Bit Values
Mask Bit 0 1 Values The corresponding incoming ID bit is dont care The corresponding ID bit is checked against the incoming ID bit to see if a match exists
Table 16-7 shows mask examples for normal and extended messages. Refer to 16.7 Programmers Model for more information on Rx mask registers.
Table 16-7 Mask Examples for Normal/Extended Messages

Message Buffer (MB) /Mask MB2 MB3 MB4 MB5 MB14 RX Global Mask Base ID ID[28:18] 11111111000 11111111000 00000011111 00000011101 11111111000 11111111110 11111111001 11111111001 RX Message In 11111111001 01111111000 01111111000 RX 14 Mask RX Message In 01111111111 10111111000 01111111000 1 1 1 0 1 0 1 IDE 0 1 0 1 1 Extended ID ID[17:0] 010101010101010101 010101010101010101 010101010101010101 111111100000000001 010101010101010101 010101010101010100 010101010101010101 111111100000000000 010101010101010101 010101010101010101 Match 31 22 3 4 5 6 147
NOTES: 1. Match for extended format (MB3). 2. Match for standard format (MB2). 3. No match for MB3 because of ID0. 4. No match for MB2 because of ID28. 5. No match for MB3 because of ID28, match for MB14. 6. No match for MB14 because of ID27. 7. Match for MB14.
16.3.3 Bit Timing The TouCAN module uses three 8-bit registers to set up the bit timing parameters required by the CAN protocol. Control registers one and two (CANCTRL1, CANCTRL2) contain the PROPSEG, PSEG1, PSEG2, and the RJW fields which allow the user to configure the bit timing parameters. The prescaler divide register (PRESDIV) allows the user to select the ratio used to derive the S-clock from the IMB clock. The time
MPC555
/ MPC556
MOTOROLA 16-8
USERS MANUAL

quanta clock operates at the S-clock frequency. Table 16-8 provides examples of IMB clock, CAN bit rate, and S-clock bit timing parameters. Refer to 16.7 Programmers Model for more information on the bit timing registers. Table 16-8 Example IMB Clock, CAN Bit Rate and S-Clock Frequencies
IMB Clock Frequency (MHz) 25 20 16 25 20 CAN Bit Rate (MHz) 1 1 1 0.125 0.125 0.125 Possible S-Clock Frequency (MHz) 25 10, 20 8, 16 1, 1.25, 2.5 1, 2, 2.5 1, 2 Possible Number of Time Quanta/Bit 25 10, 20 8, 16 8,10, 20 8, 16, 20 8,16 PRESDIV Value + 1 1 2, 1 2, 1 25, 20,10 20, 10, 8 16, 8
16
16.3.3.1 Configuring the TouCAN Bit Timing The following considerations must be observed when programming bit timing functions. If the programmed PRESDIV value results in a single IMB clock per one time quantum, then the PSEG2 field in CANCTRL2 register must not be programmed to zero. If the programmed PRESDIV value results in a single IMB clock per one time quantum, then the information processing time (IPT) equals three time quanta; otherwise it equals two time quanta. If PSEG2 equals two, then the TouCAN transmits one time quantum late relative to the scheduled sync segment. If the prescaler and bit timing control fields are programmed to values that result in fewer than 10 IMB clock periods per CAN bit time and the CAN bus loading is 100%, then any time the rising edge of a start-of-frame (SOF) symbol transmitted by another node occurs during the third bit of the intermission between messages, the TouCAN may not be able to prepare a message buffer for transmission in time to begin its own transmission and arbitrate against the message which transmitted the early SOF. The TouCAN bit time must be programmed to be greater than or equal to nine IMB clocks, or correct operation is not guaranteed. 16.3.4 Error Counters The TouCAN has two error counters, the transmit (Tx) error counter and the receive (Rx) error counter. Refer to 16.7 Programmers Model for more information on error counters.The rules for increasing and decreasing these counters are described in the CAN protocol, and are fully implemented in the TouCAN. Each counter has the following features: 8-bit up/down-counter Increment by eight (Rx error counter also increments by one) Decrement by one Avoid decrement when equal to zero
MPC555
/ MPC556
MOTOROLA 16-9
USERS MANUAL

Rx error counter reset to a value between 119 and 127 inclusive, when the TouCAN transitions from error passive to error active Following reset, both counters reset to zero Detect values for error passive, bus off and error active transitions Cascade usage of Tx error counter with an additional internal counter to detect the 128 occurrences of 11 consecutive recessive bits necessary to transition from bus off into error active. Both counters are read-only (except in test/freeze/halt modes). The TouCAN responds to any bus state as described in the CAN protocol, transmitting an error active or error passive flag, delaying its transmission start time (error passive) and avoiding any influence on the bus when in the bus off state. The following are the basic rules for TouCAN bus state transitions:
If the value of the Tx error counter or Rx error counter increments to a value greater than or equal to 128, the fault confinement state (FCS[1:0]) field in the error status register is updated to reflect an error passive state. If the TouCAN is in an error passive state, and either the Tx error counter or Rx error counter decrements to a value less than or equal to 127 while the other error counter already satisfies this condition, the FCS[1:0] field in the error status register is updated to reflect an error active state. If the value of the Tx error counter increases to a value greater than 255, the FCS[1:0] field in the error status register is updated to reflect a bus off state, and an interrupt may be issued. The value of the Tx error counter is reset to zero. If the TouCAN is in the bus off state, the Tx error counter and an additional internal counter are cascaded to count 128 occurrences of 11 consecutive recessive bits on the bus. To do this, the Tx error counter is first reset to zero, and then the internal counter begins counting consecutive recessive bits. Each time the internal counter counts 11 consecutive recessive bits, the Tx error counter is incremented by one and the internal counter is reset to zero. When the Tx error counter reaches the value of 128, the FCS[1:0] field in the error status register is updated to be error active, and both error counters are reset to zero. Any time a dominant bit is detected following a stream of less than 11 consecutive recessive bits, the internal counter resets itself to zero but does not affect the Tx error counter value. If only one node is operating in a system, the Tx error counter is incremented with each message it attempts to transmit, due to the resulting acknowledgment errors. However, acknowledgment errors never cause the TouCAN to change from the error passive state to the bus off state. If the Rx error counter increments to a value greater than 127, it stops incrementing, even if more errors are detected while being a receiver. After the next successful message reception, the counter is reset to a value between 119 and 127, to enable a return to the error active state. 16.3.5 Time Stamp The value of the free-running 16-bit timer is sampled at the beginning of the identifier field on the CAN bus. For a message being received, the time stamp is stored in the time stamp entry of the receive message buffer at the time the message is written into
MPC555
/ MPC556
MOTOROLA 16-10
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that buffer. For a message being transmitted, the time stamp entry is written into the transmit message buffer once the transmission has completed successfully. The free-running timer can optionally be reset upon the reception of a frame into message buffer 0. This feature allows network time synchronization to be performed. 16.4 TouCAN Operation The basic operation of the TouCAN can be divided into three areas: Reset and initialization of the module Transmit message handling Receive message handling Example sequences for performing each of these processes is given in the following paragraphs. 16.4.1 TouCAN Reset The TouCAN can be reset in two ways: Hard reset, using one of the IMB3 reset lines Soft reset, using the SOFTRST bit in the module configuration register Following the negation of reset, the TouCAN is not synchronized with the CAN bus, and the HALT, FRZ, and FRZACK bits in the module configuration register are set. In this state, the TouCAN does not initiate frame transmissions or receive any frames from the CAN bus. The contents of the message buffers are not changed following reset. Any configuration change or initialization requires that the TouCAN be frozen by either the assertion of the HALT bit in the module configuration register or by reset. 16.4.2 TouCAN Initialization Initialization of the TouCAN includes the initial configuration of the message buffers and configuration of the CAN communication parameters following a reset, as well as any reconfiguration which may be required during operation. The following is a general initialization sequence for the TouCAN: 1. Initialize all operation modes a. Initialize the transmit and receive pin modes in control register 0 (CANCTRL0) b. Initialize the bit timing parameters PROPSEG, PSEGS1, PSEG2, and RJW in control registers 1 and 2 (CANCTRL[1:2]) c. Select the S-clock rate by programming the PRESDIV register d. Select the internal arbitration mode (LBUF bit in CANCTRL1) 2. Initialize message buffers / MPC556
MPC555
MOTOROLA 16-11
USERS MANUAL

a. The control/status word of all message buffers must be written either as an active or inactive message buffer. b. All other entries in each message buffer should be initialized as required 3. Initialize mask registers for acceptance mask as needed 4. Initialize TouCAN interrupt handler a. Initialize the interrupt configuration register (CANICR) with a specific request level b. Set the required mask bits in the IMASK register (for all message buffer interrupts), in CANCTRL0 (for bus off and error interrupts), and in CANMCR for the WAKE interrupt 5. Negate the HALT bit in the module configuration register
a. At this point, the TouCAN attempts to synchronize with the CAN bus NOTE In both the transmit and receive processes, the first action in preparing a message buffer must be to deactivate the buffer by setting its code field to the proper value. This step is mandatory to ensure data coherency. 16.4.3 Transmit Process The transmit process includes preparation of a message buffer for transmission, as well as the internal steps performed by the TouCAN to decide which message to transmit. For the user, this involves loading the message and ID to be transmitted into a message buffer and then activating that buffer as an active transmit buffer. Once this is done, the TouCAN performs all additional steps necessary to transmit the message onto the CAN bus. The user should prepare or change a message buffer for transmission by executing the following steps. 1. Write the control/status word to hold the transmit buffer inactive (code = 0b1000) 2. Write the ID_HIGH and ID_LOW words 3. Write the data bytes 4. Write the control/status word (active Tx code, Tx length) NOTE Steps one and four are mandatory to ensure data coherency. Once an active transmit code is written to a transmit message buffer, that buffer begins participating in an internal arbitration process as soon as the receiver senses that the CAN bus is free, or at the inter-frame space. If there are multiple messages awaiting transmission, this internal arbitration process selects the message buffer from which the next frame is transmitted.
MPC555
/ MPC556
MOTOROLA 16-12
USERS MANUAL

When this process is over and a message buffer is selected for transmission, the frame from that message buffer is transferred to the serial message buffer for transmission. The TouCAN transmits no more than eight data bytes, even if the transmit length contains a value greater than eight. At the end of a successful transmission, the value of the free-running timer (which was captured at the beginning of the identifier field on the CAN bus), is written into the time stamp field in the message buffer. The code field in the control/status word of the message buffer is updated and a status flag is set in the IFLAG register. 16.4.3.1 Transmit Message Buffer Deactivation Any write access to the control/status word of a transmit message buffer during the process of selecting a message buffer for transmission immediately deactivates that message buffer, removing it from the transmission process. If the user deactivates a transmit message buffer while a message is being transferred from it to a serial message buffer, the message is not transmitted. If the user deactivates the transmit message buffer after the message is transferred to the serial message buffer, the message is transmitted, but no interrupt is requested, and the transmit code is not updated. If a message buffer containing the lowest ID is deactivated while that message is undergoing the internal arbitration process to determine which message should be sent, then that message may not be transmitted. 16.4.3.2 Reception of Transmitted Frames The TouCAN receives a frame it has transmitted if an empty message buffer with a matching identifier exists. 16.4.4 Receive Process During the receive process, the following events occur: The user configures the message buffers for reception The TouCAN transfers received messages from the serial message buffers to the receive message buffers with matching IDs The user retrieves these messages The user should prepare or change a message buffer for frame reception by executing the following steps. 1. Write the control/status word to hold the receive buffer inactive (code = 0b0000) 2. Write the ID_HIGH and ID_LOW words 3. Write the control/status word to mark the receive message buffer as active and empty NOTE Steps one and three are mandatory for data coherency.
MPC555
/ MPC556
MOTOROLA 16-13
USERS MANUAL

Once these steps are performed, the message buffer functions as an active receive buffer and participates in the internal matching process, which takes place every time the TouCAN receives an error-free frame. In this process, all active receive buffers compare their ID value to the newly received one. If a match is detected, the following actions occur: 1. The frame is transferred to the first (lowest entry) matching receive message buffer 2. The value of the free-running timer (captured at the beginning of the identifier field on the CAN bus) is written into the time stamp field in the message buffer 3. The ID field, data field, and RX length field are stored 4. The code field is updated 5. The status flag is set in the IFLAG register The user should read a received frame from its message buffer in the following order: 1. Control/status word (mandatory, as it activates the internal lock for this buffer) 2. ID (optional, since it is needed only if a mask was used) 3. Data field word(s) 4. Free-running timer (optional, as it releases the internal lock) If the free running timer is not read, that message buffer remains locked until the read process starts for another message buffer. Only a single message buffer is locked at a time. When a received message is read, the only mandatory read operation is that of the control/status word. This ensures data coherency. If the BUSY bit is set in the message buffer code, the CPU should defer accessing that buffer until this bit is negated. Refer to Table 16-2. NOTE The user should check the status of a message buffer by reading the status flag in the IFLAG register and not by reading the control/status word code field for that message buffer. This prevents the buffer from being locked inadvertently. Because the received identifier field is always stored in the matching receive message buffer, the contents of the identifier field in a receive message buffer may change if one or more of the ID bits are masked. 16.4.4.1 Receive Message Buffer Deactivation Any write access to the control/status word of a receive message buffer during the process of selecting a message buffer for reception immediately deactivates that message buffer, removing it from the reception process. If a receive message buffer is deactivated while a message is being transferred into it, the transfer is halted and no interrupt is requested. If this occurs, that receive message buffer may contain mixed data from two different frames.
MPC555
/ MPC556
MOTOROLA 16-14
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Data must never be written into a receive message buffer. If this occurs while a message is being transferred from a serial message buffer, the control/status word will reflect a full or overrun condition, but no interrupt is requested. 16.4.4.2 Locking and Releasing Message Buffers The lock/release/busy mechanism is designed to guarantee data coherency during the receive process. The following examples demonstrate how the the lock/release/busy mechanism affects TouCAN operation. 1. Reading a control/status word of a message buffer triggers a lock for that message buffer. A new received message frame which matches the message buffer cannot be written into this message buffer while it is locked. 2. To release a locked message buffer, the CPU either locks another message buffer by reading its control/status word or globally releases any locked message buffer by reading the free-running timer. 3. If a receive frame with a matching ID is received during the time the message buffer is locked, the receive frame is not immediately transferred into that message buffer, but remains in the serial message buffer. There is no indication when this occurs. 4. When a locked message buffer is released, if a frame with a matching identifier exists within the serial message buffer, then this frame is transferred to the matching message buffer. 5. If two or more receive frames with matching IDs are received while a message buffer with a matching ID is locked, the last received frame with that ID is kept within the serial message buffer, while all preceding ones are lost. There is no indication when this occurs. 6. If the user reads the control/status word of a receive message buffer while a frame is being transferred from a serial message buffer, the BUSY code is indicated. The user should wait until this code is cleared before continuing to read from the message buffer to ensure data coherency. In this situation, the read of the control/status word does not lock the message buffer. Polling the control/status word of a receive message buffer can lock it, preventing a message from being transferred into that buffer. If the control/status word of a receive message buffer is read, it should be followed by a read of the control/status word of another buffer, or by a read of the free-running timer, to ensure that the locked buffer is unlocked. 16.4.5 Remote Frames The remote frame is a message frame that is transmitted to request a data frame. The TouCAN can be configured to transmit a data frame automatically in response to a remote frame, or to transmit a remote frame and then wait for the responding data frame to be received. To transmit a remote frame, the user initializes a message buffer as a transmit message buffer with the RTR bit set to one. Once this remote frame is transmitted successfully, the transmit message buffer automatically becomes a receive message buffer, with the same ID as the remote frame that was transmitted.
MPC555
/ MPC556
MOTOROLA 16-15
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When the TouCAN receives a remote frame, it compares the remote frame ID to the IDs of all transmit message buffers programmed with a code of 1010. If there is an exact matching ID, the data frame in that message buffer is transmitted. If the RTR bit in the matching transmit message buffer is set, the TouCAN transmits a remote frame as a response. A received remote frame is not stored in a receive message buffer. It is only used to trigger the automatic transmission of a frame in response. The mask registers are not used in remote frame ID matching. All ID bits (except RTR) of the incoming received frame must match for the remote frame to trigger a response transmission. 16.4.6 Overload Frames The TouCAN does not initiate overload frame transmissions unless it detects the following conditions on the CAN bus: A dominant bit in the first or second bit of intermission A dominant bit in the seventh (last) bit of the end-of-frame (EOF) field in receive frames A dominant bit in the eighth (last) bit of the error frame delimiter or overload frame delimiter 16.5 Special Operating Modes The TouCAN module has three special operating modes: Debug mode Low-power stop mode Auto power save mode 16.5.1 Debug Mode Debug mode is entered when the FRZ1 bit in CANMCR is set and one of the following events occurs: The HALT bit in the CANMCR is set; or The IMB3 FREEZE line is asserted Once entry into debug mode is requested, the TouCAN waits until an intermission or idle condition exists on the CAN bus, or until the TouCAN enters the error passive or bus off state. Once one of these conditions exists, the TouCAN waits for the completion of all internal activity. Once this happens, the following events occur: The TouCAN stops transmitting or receiving frames The prescaler is disabled, thus halting all CAN bus communication The TouCAN ignores its Rx pins and drives its Tx pins as recessive The TouCAN loses synchronization with the CAN bus and the NOTRDY and FRZACK bits in CANMCR are set The CPU is allowed to read and write the error counter registers
MPC555
/ MPC556
MOTOROLA 16-16
USERS MANUAL

After engaging one of the mechanisms to place the TouCAN in debug mode, the user must wait for the FRZACK bit to be set before accessing any other registers in the TouCAN; otherwise unpredictable operation may occur. To exit debug mode, the IMB FREEZE line must be negated or the HALT bit in CANMCR must be cleared. Once debug mode is exited, the TouCAN resynchronizes with the CAN bus by waiting for 11 consecutive recessive bits before beginning to participate in CAN bus communication. 16.5.2 Low-Power Stop Mode Before entering low-power stop mode, the TouCAN waits for the CAN bus to be in an idle state, or for the third bit of intermission to be recessive. The TouCAN then waits for the completion of all internal activity (except in the CAN bus interface) to be complete. Then the following events occur: The TouCAN shuts down its clocks, stopping most internal circuits, thus achieving maximum power savings The bus interface unit continues to operate, allowing the CPU to access the module configuration register The TouCAN ignores its Rx pins and drives its Tx pins as recessive The TouCAN loses synchronization with the CAN bus, and the STOPACK and NOTRDY bits in the module configuration register are set To exit low-power stop mode: Reset the TouCAN either by asserting one of the IMB3 reset lines or by asserting the SOFTRST bit CANMCR. Clear the STOP bit in CANMCR. The TouCAN module can optionally exit low-power stop mode via the self wake mechanism. If the SELFWAKE bit in CANMCR was set at the time the TouCAN entered stop mode, then upon detection of a recessive to dominant transition on the CAN bus, the TouCAN clears the STOP bit in CANMCR and its clocks begin running. When the TouCAN is in low-power stop mode, a recessive to dominant transition on the CAN bus causes the WAKEINT bit in the error and status register (ESTAT) to be set. This event generates an interrupt if the WAKEMSK bit in CANMCR is set. Consider the following notes regarding low-power stop mode: When the self wake mechanism is activated, the TouCAN tries to receive the frame that woke it up. (It assumes that the dominant bit detected is a start-offrame bit.) It will not arbitrate for the CAN bus at this time. If the STOP bit is set while the TouCAN is in the bus off state, then the TouCAN enters low-power stop mode and stops counting recessive bit times. The count continues when STOP is cleared. To place the TouCAN in low-power stop mode with the self wake mechanism engaged, write to CANMCR with both STOP and SELFWAKE set, and then wait
MPC555
/ MPC556
MOTOROLA 16-17
USERS MANUAL

for the TouCAN to set the STOPACK bit. To take the TouCAN out of low-power stop mode when the self wake mechanism is enabled, write to CANMCR with both STOP and SELFWAKE clear, and then wait for the TouCAN to clear the STOPACK bit. The SELFWAKE bit should not be set after the TouCAN has already entered lowpower stop mode. If both STOP and SELFWAKE are set and a recessive to dominant edge immediately occurs on the CAN bus, the TouCAN may never set the STOPACK bit, and the STOP bit will be cleared. To prevent old frames from being sent when the TouCAN awakes from low-power stop mode via the self wake mechanism, disable all transmit sources, including transmit buffers configured for remote request responses, before placing the TouCAN in low-power stop mode. If the TouCAN is in debug mode when the STOP bit is set, the TouCAN assumes that debug mode should be exited. As a result, it tries to synchronize with the CAN bus, and only then does it await the conditions required for entry into low-power stop mode. Unlike other modules, the TouCAN does not come out of reset in low-power stop mode. The basic TouCAN initialization procedure should be executed before placing the module in low-power stop mode. (Refer to 16.4.2 TouCAN Initialization.) If the TouCAN is in low-power stop mode with the self wake mechanism engaged and is operating with a single IMB clock per time quantum, there can be extreme cases in which TouCAN wake-up on recessive to dominant edge may not conform to the CAN protocol. TouCAN synchronization is shifted one time quantum from the wake-up event. This shift lasts until the next recessive-to-dominant edge, which resynchronizes the TouCAN to be in conformance with the CAN protocol. The same holds true when the TouCAN is in auto power save mode and awakens on a recessive to dominant edge. 16.5.3 Auto Power Save Mode Auto power save mode enables normal operation with optimized power savings. Once the auto power save (APS) bit in CANMCR is set, the TouCAN looks for a set of conditions in which there is no need for the clocks to be running. If these conditions are met, the TouCAN stops its clocks, thus saving power. The following conditions activate auto power save mode. No Rx/Tx frame in progress No transfer of Rx/Tx frames to and from a serial message buffer, and no Tx frame awaiting transmission in any message buffer No CPU access to the TouCAN module The TouCAN is not in debug mode, low-power stop mode, or the bus off state While its clocks are stopped, if the TouCAN senses that any one of the aforementioned conditions is no longer true, it restarts its clocks. The TouCAN then continues to monitor these conditions and stops or restarts its clocks accordingly.
MPC555
/ MPC556
MOTOROLA 16-18
USERS MANUAL

16.6 Interrupts The TouCAN can generate one interrupt level on the IMB. This level is programmed into the priority level bits in the interrupt configuration register (CANICR). This value determines which interrupt signal is driven onto the bus when an interrupt is requested. Each one of the 16 message buffers can be an interrupt source, if its corresponding IMASK bit is set. There is no distinction between transmit and receive interrupts for a particular buffer. Each of the buffers is assigned a bit in the IFLAG register. An IFLAG bit is set when the corresponding buffer completes a successful transmission/reception. An IFLAG bit is cleared when the CPU reads IFLAG while the associated bit is set, and then writes it back as zero (and no new event of the same type occurs between the read and the write actions).
The other three interrupt sources (bus off, error and wake up) act in the same way, and have flag bits located in the error and status register (ESTAT). The bus off and error interrupt mask bits (BOFFMSK and ERRMSK) are located in CANCTRL0, and the wake up interrupt mask bit (WAKEMSK) is located in the module configuration register. Refer to 16.7 Programmers Model for more information on these registers. The TouCAN module is capable of generating one of the 32 possible interrupt levels on the IMB3. The 32 interrupt levels are time multiplexed on the IMB3 IRQ[0:7] lines. All interrupt sources place their asserted level on a time multiplexed bus during four different time slots, with eight levels communicated per slot. The ILBS[0:1] signals indicate which group of eight are being driven on the interrupt request lines. Table 16-9 Interrupt Levels
ILBS[0:1] 00 01 10 11 Levels 0:7 8:15 16:23 24:31
The level that the TouCAN will drive onto IRQ[7:0] is programmed in the three interrupt request level (IRL) bits located in the interrupt configuration register. The two ILBS bits in the ICR register determine on which slot the TouCAN should drive its interrupt signal. Under the control of ILBS, each interrupt request level is driven during the time multiplexed bus during one of four different time slots, with eight levels communicated per time slot. No hardware priority is assigned to interrupts. Furthermore, if more than one source on a module requests an interrupt at the same level, the system software must assign a priority to each source requesting at that level. Figure 16-5 displays the interrupt levels on IRQ with ILBS.
MPC555
/ MPC556
MOTOROLA 16-19
USERS MANUAL
IMB3 CLOCK
ILBS [1:0]
00
01
10
11
00
01
10
11
IMB3 IRQ [7:0]
IRQ 7:0
IRQ 15:8
IRQ 23:16
IRQ 31:24
IRQ 7:0
Figure 16-5 Interrupt levels on IRQ with ILBS
16.7 Programmers Model Table 16-10 shows the TouCAN address map. The lowercase x appended to each register name represents A or B for the TouCAN_A or TouCAN_B module, respectively. Refer to 1.3 MPC555 / MPC556 Address Map to locate each TouCAN module in the MPC555 / MPC556 address map. The column labeled Access indicates the privilege level at which the CPU must be operating to access the register. A designation of S indicates that supervisor mode is required. A designation of S/U indicates that the register can be programmed for either supervisor mode access or unrestricted access. The address space for each TouCAN module is split, with 128 bytes starting at the base address, and an extra 256 bytes starting at the base address +128. The upper 256 are fully used for the message buffer structures. Of the lower 128 bytes, some are not used. Registers with bits marked as reserved should always be written as logic 0. Typically, the TouCAN control registers are programmed during system initialization, before the TouCAN becomes synchronized with the CAN bus. The configuration registers can be changed after synchronization by halting the TouCAN module. This is done by setting the HALT bit in the TouCAN module configuration register (CANMCR). The TouCAN responds by asserting the CANMCR NOTRDY bit. Additionally, the control registers can be modified while the MCU is in background debug mode. NOTE The TouCAN has no hard-wired protection against invalid bit/field programming within its registers. Specifically, no protection is provided if the programming does not meet CAN protocol requirements.
MPC555
/ MPC556
MOTOROLA 16-20
USERS MANUAL

Table 16-10 TouCAN Register Map
Access S S S Offset 0x30 7080, 0x30 7480 0x30 7082, 0x30 7482 0x30 7084, 0x30 7484 0x30 7086, 0x30 7486 MSB 0 LSB 15
TouCAN Module Configuration Register (TCNMCR_x) See Table 16-11 for bit descriptions. TouCAN Test Register (CANTCR_x) TouCAN Interrupt Register (CANICR_x) Control Register 0 (CANCTRL0_x) See Table 16-13 and Table 16-16 for bit descriptions. Control and Prescaler Divider Register (PRESDIV_x) See Table 16-17 and Table 16-18 for bit descriptions.
S/U
Control Register 1 (CANCTRL1_x)
S/U
0x30 7088, 0x30 7488 0x30 708A, 0x30 748A 0x30 708C, 0x30 748C 0x30 708E, 0x30 748E 0x30 7090, 0x30 7490 0x30 7092, 0x30 7492 0x30 7094, 0x30 7494 0x30 7096, 0x30 7496 0x30 7098, 0x30 7498 0x30 709A, 0x30 749A 0x30 709C, 0x30 749C 0x30 709E, 0x30 749E 0x30 70A0, 0x30 74A0 0x30 70A2, 0x30 74A2 0x30 70A4, 0x30 74A4 0x30 70A6, 0x30 74A6
Control Register 2 (CTRL2_x)
S/U
Free-Running Timer Register (TIMER_x) See Table 16-19 for bit descriptions.
Reserved
S/U S/U S/U S/U S/U S/U
Receive Global Mask High (RXGMSKHI_x) See Table 16-20 for bit descriptions. Receive Global Mask Low (RXGMSKLO_x) See Table 16-20 for bit descriptions. Receive Buffer 14 Mask High (RX14MSKHI_x) See 16.7.10 Receive Buffer 14 Mask Registers for bit descriptions. Receive Buffer 14 Mask Low (RX14MSKLO_x) See 16.7.10 Receive Buffer 14 Mask Registers for bit descriptions. Receive Buffer 15 FMask High (RX15MSKHI_x) See 16.7.11 Receive Buffer 15 Mask Registers for bit descriptions. Receive Buffer 15 Mask Low (RX15MSKLO_x) See 16.7.11 Receive Buffer 15 Mask Registers for bit descriptions.
Reserved
S/U S/U S/U
Error and Status Register (ESTAT_x) See Table 16-21 for bit descriptions. Interrupt Masks (IMASK_x) See Table 16-24 for bit descriptions. Interrupt Flags (IFLAG_x) See Table 16-25 for bit descriptions. Receive Error Counter (RXECTR_x) See Table 16-26 for bit descriptions.
S/U
Transmit Error Counter (TXECTR_x)
MPC555
/ MPC556
MOTOROLA 16-21
USERS MANUAL

Table 16-10 TouCAN Register Map (Continued)
Access Offset 0x30 7100 0x30 710F(A) 0x30 7500 0x30 750F(B) 0x30 7110 0x30 711F(A) 0x30 7510 0x30 751F(B) 0x30 7120 0x30 712F(A) 0x30 7520 0x30 752F(B) 0x30 7130 0x30 713F(A) 0x30 7530 0x30 753F(B) 0x30 7140 0x30 714F(A) 0x30 7540 0x30 754F(B) 0x30 7150 0x30 715F(A) 0x30 7550 0x30 755F(B) 0x30 7160 0x30 716F(A) 0x30 7560 0x30 756F(B) 0x307170 0x30717F(A) 0x30 7570 0x30 757F(B) 0x30 7180 0x30 718F(A) 0x30 7580 0x30 758F(B) 0x30 7190 0x30 719F(A) 0x30 7590 0x30 759F(B) 0x30 71A0 0x30 71AF(A) 0x30 75A0 0x30 75AF(B) 0x30 71B0 0x30 71BF(A) 0x30 75B0 0x30 75BF(B) 0x30 71C0 0x30 71CF(A) 0x30 75C0 0x30 75CF(B) 0x30 71D0 0x30 71DF(A) 0x30 75D0 0x30 75DF(B) MSB 0 LSB 15
S/U
MBUFF01 TouCAN_A Message Buffer 0. See Table 16-3 and Table 16-4 for message buffer definitions. MBUFF11 TouCAN_A Message Buffer 1. See Table 16-3 and Table 16-4 for message buffer definitions. MBUFF21 TouCAN_A Message Buffer 2. See Table 16-3 and Table 16-4 for message buffer definitions. MBUFF31 TouCAN_A Message Buffer 3. See Table 16-3 and Table 16-4 for message buffer definitions. MBUFF41 TouCAN_A Message Buffer 4. See Table 16-3 and Table 16-4 for message buffer definitions. MBUFF51 TouCAN_A Message Buffer 5. See Table 16-3 and Table 16-4 for message buffer definitions. MBUFF61 TouCAN_A Message Buffer 6. See Table 16-3 and Table 16-4 for message buffer definitions. MBUFF71 TouCAN_A Message Buffer 7. See Table 16-3 and Table 16-4 for message buffer definitions. MBUFF81 TouCAN_A Message Buffer 8. See Table 16-3 and Table 16-4 for message buffer definitions. MBUFF91 TouCAN_A Message Buffer 9. See Table 16-3 and Table 16-4 for message buffer definitions. MBUFF101 TouCAN_A Message Buffer 10. See Table 16-3 and Table 16-4 for message buffer definitions. MBUFF111 TouCAN_A Message Buffer 11. See Table 16-3 and Table 16-4 for message buffer definitions. MBUFF121 TouCAN_A Message Buffer 12. See Table 16-3 and Table 16-4 for message buffer definitions. MBUFF131 TouCAN_A Message Buffer 13. See Table 16-3 and Table 16-4 for message buffer definitions.
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
MPC555
/ MPC556
MOTOROLA 16-22
USERS MANUAL

Table 16-10 TouCAN Register Map (Continued)
Access Offset 0x30 71E0 0x30 71EF(A) 0x30 75E0 0x30 75EF(B) 0x30 71F0 0x30 71FF(A) 0x30 75F0 0x30 75FF(B) MSB 0 LSB 15
S/U
MBUFF141 TouCAN_A Message Buffer 14. See Table 16-3 and Table 16-4 for message buffer definitions. MBUFF151 TouCAN_A Message Buffer 15. See Table 16-3 and Table 16-4 for message buffer definitions.
S/U
NOTES: 1. The last word of each of the the MBUFF arrays (address 0x....E) is reserved and may cause a RCPU exception if read.
, 0x30 7100, 0x30 7500, 0x30 7C00
Control/Status ID High ID Low 8-Byte Data Field Message Buffer 0
0x30 7102, 0x30 7502, 0x30 7C02 0x307104, 0x307504 , 0x30 7C04 0x30 7106, 0x30 7506 , 0x30 7C06 0x30 710C, 0x30 750C, 0x30 7C0C 0x30710E, 0x30750E , 0x30 7C0E 0x30 7110, 0x30 7510, 0x30 7C10
Reserved Message Buffer 1
0x30 7120, 0x30 7520, 0x30 7C20 Message Buffer 2
0x30 71FF, 0x30 75FF, 0x30 7CFF
Message Buffer 15
Figure 16-6 TouCAN Message Buffer Memory Map
MPC555
/ MPC556
MOTOROLA 16-23
USERS MANUAL

16.7.1 TouCAN Module Configuration Register TCNMCR TouCAN Module Configuration Register
MSB 0 STOP 1 FRZ 2 NOT USED 3 HALT 4 NOT RDY 5 6 7 FRZ ACK 8 SUPV 9 SELF WAKE 10 APS 11 STOP ACK 12 13
0x30 7080 0x30 7480

14 LSB 15
WAKE SOFT MSK RST
RESERVED
RESET: 0 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0
MPC555
/ MPC556
MOTOROLA 16-24
USERS MANUAL

Table 16-11 TCNMCR Bit Descriptions
Bit(s) Name Description Low-power stop mode enable. The STOP bit may only be set by the CPU. It may be cleared either by the CPU or by the TouCAN, if the SELFWAKE bit is set. 0 = Enable TouCAN clocks 1 = Disable TouCAN clocks FREEZE assertion response. When FRZ = 1, the TouCAN can enter debug mode when the IMB3 FREEZE line is asserted or the HALT bit is set. Clearing this bit field causes the TouCAN to exit debug mode. Refer to 16.5.1 Debug Mode for more information. 0 = TouCAN ignores the IMB3 FREEZE signal and the HALT bit in the module configuration register. 1 = TouCAN module enabled to enter debug mode. Reserved Halt TouCAN S-Clock. Setting the HALT bit has the same effect as assertion of the IMB3 FREEZE signal on the TouCAN without requiring that FREEZE be asserted. This bit is set to one after reset. It should be cleared after initializing the message buffers and control registers. TouCAN message buffer receive and transmit functions are inactive until this bit is cleared. When HALT is set, write access to certain registers and bits that are normally read-only is allowed. 0 = The TouCAN operates normally 1 = TouCAN enters debug mode if FRZ = 1 TouCAN not ready. This bit indicates that the TouCAN is either in low-power stop mode or debug mode. This bit is read-only and is set only when the TouCAN enters low-power stop mode or debug mode. It is cleared once the TouCAN exits either mode, either by synchronization to the CAN bus or by the self wake mechanism. 0 = TouCAN has exited low-power stop mode or debug mode. 1 = TouCAN is in low-power stop mode or debug mode. Wakeup interrupt mask. The WAKEMSK bit enables wake-up interrupt requests. 0 = Wake up interrupt is disabled 1 = Wake up interrupt is enabled Soft reset. When this bit is asserted, the TouCAN resets its internal state machines (sequencer, error counters, error flags, and timer) and the host interface registers (CANMCR, CANICR, CANTCR, IMASK, and IFLAG). The configuration registers that control the interface with the CAN bus are not changed (CANCTRL[0:2] and PRESDIV). Message buffers and receive message masks are also not changed. This allows SOFTRST to be used as a debug feature while the system is running. 6 SOFTRST Setting SOFTRST also clears the STOP bit in CANMCR. After setting SOFTRST, allow one complete bus cycle to elapse for the internal TouCAN circuitry to completely reset before executing another access to CANMCR. The TouCAN clears this bit once the internal reset cycle is completed. 0 = Soft reset cycle completed 1 = Soft reset cycle initiated TouCAN disable. When the TouCAN enters debug mode, it sets the FRZACK bit. This bit should be polled to determine if the TouCAN has entered debug mode. When debug mode is exited, this bit is negated once the TouCAN prescaler is enabled. This is a read-only bit. 0 = The TouCAN has exited debug mode and the prescaler is enabled 1 = The TouCAN has entered debug mode, and the prescaler is disabled Supervisor/user data space. The SUPV bit places the TouCAN registers in either supervisor or user data space. 0 = Registers with access controlled by the SUPV bit are accessible in either user or supervisor privilege mode 1 = Registers with access controlled by the SUPV bit are restricted to supervisor mode
STOP
FRZ
HALT
NOTRDY
WAKEMSK
FRZACK
SUPV
MPC555
/ MPC556
MOTOROLA 16-25
USERS MANUAL

Table 16-11 TCNMCR Bit Descriptions (Continued)
Bit(s) Name Description Self wake enable. This bit allows the TouCAN to wake up when bus activity is detected after the STOP bit is set. If this bit is set when the TouCAN enters low-power stop mode, the TouCAN will monitor the bus for a recessive to dominant transition. If a recessive to dominant transition is detected, the TouCAN immediately clears the STOP bit and restarts its clocks. 9 SELFWAKE If a write to CANMCR with SELFWAKE set occurs at the same time a recessive-to-dominant edge appears on the CAN bus, the bit will not be set, and the module clocks will not stop. The user should verify that this bit has been set by reading CANMCR. Refer to 16.5.2 LowPower Stop Mode for more information on entry into and exit from low-power stop mode. 0 = Self wake disabled 1 = Self wake enabled Auto power save. The APS bit allows the TouCAN to automatically shut off its clocks to save power when it has no process to execute, and to automatically restart these clocks when it has a task to execute without any CPU intervention. 0 = Auto power save mode disabled; clocks run normally 1 = Auto power save mode enabled; clocks stop and restart as needed Stop acknowledge. When the TouCAN is placed in low-power stop mode and shuts down its clocks, it sets the STOPACK bit. This bit should be polled to determine if the TouCAN has entered low-power stop mode. When the TouCAN exits low-power stop mode, the STOPACK bit is cleared once the TouCANs clocks are running. 0 = The TouCAN is not in low-power stop mode and its clocks are running 1 = The TouCAN has entered low-power stop mode and its clocks are stopped Reserved
10
APS
11
STOPACK
12:15
16.7.2 TouCAN Test Configuration Register CANTCR TouCAN Test Configuration Register This register is used for factory test only. 16.7.3 TouCAN Interrupt Configuration Register CANICR TouCAN Interrupt Configuration Register
MSB 0 1 2 RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 3 4 5 6 IRL 7 8 ILBS 9 10 11 12 13
0x30 7082, 0x30 7482
0x30 7084 0x30 7484

14 LSB 15
RESERVED
MPC555
/ MPC556
MOTOROLA 16-26
USERS MANUAL

Table 16-12 CANICR Bit Descriptions
Bit(s) 0:4 5:7 Name IRL Reserved Interrupt request level. When the TouCAN generates an interrupt request, this field determines which of the interrupt request signals is asserted. Interrupt level byte select. This field selects one of four time-multiplexed slots during which the interrupt request is asserted. The ILBS and IRL fields together select one of 32 effective interrupt levels. 00 = Levels 0 to7 01 = Levels 8 to 15 10 = Levels 16 to 23 11 = Levels 24 to 31 Reserved Description
8:9
ILBS
10:15
16.7.4 Control Register 0 CANCTRL0 Control Register 0

MSB 0 BOFF MSK 1 ERR MSK 2 3 4 5 6 7 8 9 10 11 12 13
0x30 7086 0x30 7486

14 LSB 15
RESERVED
RXMOD
TXMODE
CANCTRL1
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 16-13 CANCTRL0 Bit Descriptions

Bit(s) 0 Name BOFFMSK Description Bus off interrupt mask. The BOFF MASK bit provides a mask for the bus off interrupt. 0 = Bus off interrupt disabled 1 = Bus off interrupt enabled Error interrupt mask. The ERRMSK bit provides a mask for the error interrupt. 0 = Error interrupt disabled 1 = Error interrupt enabled Receive pin configuration control. These bits control the configuration of the CANRX0 and CANRX1 pins. Refer to the Table 16-14. Transmit pin configuration control. This bit field controls the configuration of the CANTX0 and CANTX1 pins. Refer to Table 16-15. See Table 16-16.
1 2:3 4:5 6:7 8:15
ERRMSK RXMODE TXMODE CANCTRL1
MPC555
/ MPC556
MOTOROLA 16-27
USERS MANUAL

Table 16-14 RX MODE[1:0] Configuration
Pin RX1 0 CNRX11 1 X CNRX0 X 1 A logic one on the CNRX0 pin is interpreted as a dominant bit; a logic zeroon the CNRX0 pin is interpreted as a recessive bit X 0 RX0 X Receive Pin Configuration A logic zero on the CNRX1 pin is interpreted as a dominant bit; a logic one on the CNRX1 pin is interpreted as a recessive bit A logic one on the CNRX1 pin is interpreted as a dominant bit; a logic zero on the CNRX1 pin is interpreted as a recessive bit A logic zero on the CNRX0 pin is interpreted as a dominant bit; a logic one on the CNRX0 pin is interpreted as a recessive bit
NOTES: 1. The CNRX1 signal is not available on the MPC555 / MPC556.
Table 16-15 Transmit Pin Configuration

TXMODE[1:0] 00 01 1X Transmit Pin Configuration Full CMOS1; positive polarity (CNTX0 = 0, CNTX12 = 1 is a dominant level)2 Full CMOS; negative polarity (CNTX0 = 1, CNTX12 = 0 is a dominant level) Open drain3; positive polarity
NOTES: 1. Full CMOS drive indicates that both dominant and recessive levels are driven by the chip. 2. The CNTX1 signal is not available on the MPC555 / MPC556. 3. Open drain drive indicates that only a dominant level is driven by the chip. During a recessive level, the CNTX0 and CNTX1 pins are disabled (three stated), and the electrical level is achieved by external pull-up/pull-down devices. The assertion of both Tx mode bits causes the polarity inversion to be cancelled (open drain mode forces the polarity to be positive).

MSB 0 1 2 3 4 5 6 7 8 SAMP 9 Reserved 10 11 12 0D 13
0x30 7086 0x30 7486

14 PROPSE LSB 15
CANCTRL0 RESET: 0 0 0 0 0 0 0 0
TSYNC LBUF
MPC555
/ MPC556
MOTOROLA 16-28
USERS MANUAL

Bit(s) 0:7 Name CANCTRL0 See Table 16-13 Sampling mode. The SAMP bit determines whether the TouCAN module will sample each received bit one time or three times to determine its value. 0 = One sample, taken at the end of phase buffer segment one, is used to determine the value of the received bit. 1 = Three samples are used to determine the value of the received bit. The samples are taken at the normal sample point and at the two preceding periods of the S-clock. Reserved Timer synchronize mode. The TSYNC bit enables the mechanism that resets the free-running timer each time a message is received in message buffer zero. This feature provides the means to synchronize multiple TouCAN stations with a special SYNC message (global network time). 0 = Timer synchronization disabled. 1 = Timer synchronization enabled. Note: there can be a bit clock skew of four to five counts between different TouCAN modules that are using this feature on the same network. 11 12 LBUF Lowest buffer transmitted first. The LBUF bit defines the transmit-first scheme. 0 = Message buffer with lowest ID is transmitted first. 1 = Lowest numbered buffer is transmitted first. Reserved Propagation segment time. PROPSEG defines the length of the propagation segment in the bit time. The valid programmed values are zero to seven. The propagation segment time is calculated as follows: 13:15 PROPSEG Propagation Segment Time = (PROPSEG + 1) Time Quanta where 1 Time Quantum = 1 Serial Clock (S-Clock) Period Description
SAMP
10
TSYNC
16.7.6 Prescaler Divide Register PRESDIV Prescaler Divide Register

MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13
0x30 7088 0x30 7488

14 LSB 15
PRESDIV RESET: 0 0 0 0 0 0 0 0 0 0 0
CANCTRL2
MPC555
/ MPC556
MOTOROLA 16-29
USERS MANUAL

Table 16-17 PRESDIV Bit Descriptions
Bit(s) Name Description Prescaler divide factor. PRESDIV determines the ratio between the IMB clock frequency and the serial clock (S-clock). The S-clock is determined by the following calculation:
0:7
PRESDIV
f SYS S-clock = ----------------------------------PRESDIV + 1
The reset value of PRESDIV is 0x00, which forces the S-clock to default to the same frequency as the IMB clock. The valid programmed values are 0 through 255. 8:15 CANCTRL2 See Table 16-18.

MSB 0 1 2 3 4 5 6 7 8 RJW 9 10 11 PSEG 12 13
0x30 7088 0x30 7488

14 PSEG2 LSB 15
PRESDIV RESET: 0 0 0 0 0 0 0 0 0

Bit(s) 0:7 Name PRESDIV See Table 16-17. Resynchronization jump width. The RJW field defines the maximum number of time quanta a bit time may be changed during resynchronization. The valid programmed values are zero through three. The resynchronization jump width is calculated as follows: Resynchronizaton Jump Width = (RJW + 1) Time Quanta PSEG1[2:0] Phase buffer segment 1. The PSEG1 field defines the length of phase buffer segment one in the bit time. The valid programmed values are zero through seven. 10:12 PSEG1 The length of phase buffer segment 1 is calculated as follows: Phase Buffer Segment 1 = (PSEG1 + 1) Time Quanta PSEG2 Phase Buffer Segment 2. The PSEG2 field defines the length of phase buffer segment two in the bit time. The valid programmed values are zero through seven. 13:15 PSEG2 The length of phase buffer segment two is calculated as follows: Phase Buffer Segment 2 = (PSEG2 + 1) Time Quanta Description
8:9
RJW
MPC555
/ MPC556
MOTOROLA 16-30
USERS MANUAL

16.7.8 Free Running Timer TIMER Free Running Timer Register
MSB 0 1 2 3 4 5 6 7 8 TIMER RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 10 11 12
0x30 708A 0x30 748A

13 14 LSB 15
Table 16-19 TIMER Bit Descriptions

Bit(s) Name Description The free running timer counter can be read and written by the CPU. The timer starts from zero after reset, counts linearly to 0xFFFF, and wraps around. The timer is clocked by the TouCAN bit-clock. During a message, it increments by one for each bit that is received or transmitted. When there is no message on the bus, it increments at the nominal bit rate. The timer value is captured at the beginning of the identifier field of any frame on the CAN bus. The captured value is written into the time stamp entry in a message buffer after a successful reception or transmission of a message.
0:15
TIMER
16.7.9 Receive Global Mask Registers RXGMSKHI Receive Global Mask Register High RXGMSKLO Receive Global Mask Register Low
MSB 0 1 2 3 4 5 6 7 8 9 10
0x30 7090, 0x30 7490 0x30 7092, 0x30 7492

11 0 12 1 13 14 15
MID28 MID27 MID26 MID25 MID24 MID23 MID22 MID21 MID20 MID19 MID18 RESET: 1 16 1 17 1 18 1 19 1 20 1 21 MID9 1 22 MID8 1 23 MID7 1 24 MID6 1 25 MID5 1 26 MID4
MID17 MID16 MID15
0 27 MID3
1 28 MID2
1 29 MID1
1 30 MID0
1 LSB 31 0
MID14 MID13 MID12 MID11 MID10 RESET: 1 1 1 1 1
MPC555
/ MPC556
MOTOROLA 16-31
USERS MANUAL

Table 16-20 RXGMSKHI, RXGMSKLO Bit Descriptions
Bit(s) Name Description The receive global mask registers use four bytes. The mask bits are applied to all receiveidentifiers, excluding receive-buffers 14 and 15, which have their own specific mask registers. Base ID mask bits MID[28:18] are used to mask standard or extended format frames. Extended ID bits MID[17:0] are used to mask only extended format frames. 0:31 MIDx The RTR/SRR bit of a received frame is never compared to the corresponding bit in the message buffer ID field. However, remote request frames (RTR = 1) once received, are never stored into the message buffers. RTR mask bit locations in the mask registers (bits 20 and zero) are always zero, regardless of any write to these bits. The IDE bit of a received frame is always compared to determine if the message contains a standard or extended identifier. Its location in the mask registers (bit 19) is always one, regardless of any write to this bit.
16.7.10 Receive Buffer 14 Mask Registers RX14MSKHI Receive Buffer 14 Mask Register High 0x30 7094, 0x30 7494 RX14MSKLO Receive Buffer 14 Mask Register Low 0x30 7096, 0x30 7496 The receive buffer 14 mask registers have the same structure as the receive global mask registers and are used to mask buffer 14. 16.7.11 Receive Buffer 15 Mask Registers RX15MSKHI Receive Buffer 15 Mask Register High 0x30 7098, 0x30 7498 RX15MSKLO Receive Buffer 15 Mask Register Low 0x30 709A, 0x30 749A The receive buffer 15 mask registers have the same structure as the receive global mask registers and are used to mask buffer 15. 16.7.12 Error and Status Register ESTAT Error and Status Register
MSB 0 1 2 ACK ERR 3 CRC ERR 4 FORM ERR 5 STUFF ERR 6 7 8 9 TX/RX 10 11 FCS 12 0 13 BOFF INT
0x30 70A0 0x30 74A0

14 ERR INT LSB 15 WAKE INT
BITERR RESET: 0 0
TX RX IDLE WARN WARN
This register reflects various error conditions, general status, and has the enable bits for three of the TouCAN interrupt sources. The reported error conditions are those which have occurred since the last time the register was read. A read clears these bits to zero.
MPC555
/ MPC556
MOTOROLA 16-32
USERS MANUAL

Table 16-21 ESTAT Bit Descriptions
Bit(s) Name Description Transmit bit error. The BITERR[1:0] field is used to indicate when a transmit bit error occurs. Refer to Table 16-22. 0:1 BITERR NOTE: The transmit bit error field is not modified during the arbitration field or the ACK slot bit time of a message, or by a transmitter that detects dominant bits while sending a passive error frame. Acknowledge error. The ACKERR bit indicates whether an acknowledgment has been correctly received for a transmitted message. 0 = No ACK error was detected since the last read of this register 1 = An ACK error was detected since the last read of this register Cyclic redundancy check error. The CRCERR bit indicates whether or not the CRC of the last transmitted or received message was valid. 0 = No CRC error was detected since the last read of this register 1 = A CRC error was detected since the last read of this register Message format error. The FORMERR bit indicates whether or not the message format of the last transmitted or received message was correct. 0 = No format error was detected since the last read of this register 1 = A format error was detected since the last read of this register Bit stuff error. The STUFFERR bit indicates whether or not the bit stuffing that occurred in the last transmitted or received message was correct. 0 = No bit stuffing error was detected since the last read of this register 1 = A bit stuffing error was detected since the last read of this register Transmit error status flag. The TXWARN status flag reflects the status of the TouCAN transmit error counter. 0 = Transmit error counter < 96 1 = Transmit error counter 96 Receiver error status flag. The RXWARN status flag reflects the status of the TouCAN receive error counter. 0 = Receive error counter < 96 1 = Receive error counter 96 Idle status. The IDLE bit indicates when there is activity on the CAN bus. 0 = The CAN bus is not idle 1 = The CAN bus is idle Transmit/receive status. The TX/RX bit indicates when the TouCAN module is transmitting or receiving a message. TX/RX has no meaning when IDLE = 1. 0 = The TouCAN is receiving a message if IDLE = 0 1 = The TouCAN is transmitting a message if IDLE = 0 Fault confinement state. The FCS[1:0] field describes the state of the TouCAN. Refer to Table 16-23. 10:11 FCS If the SOFTRST bit in CANMCR is asserted while the TouCAN is in the bus off state, the error and status register is reset, including FCS[1:0]. However, as soon as the TouCAN exits reset, FCS[1:0] bits will again reflect the bus off state. Refer to16.3.4 Error Counters for more information on entry into and exit from the various fault confinement states. Reserved Bus off interrupt. The BOFFINT bit is used to request an interrupt when the TouCAN enters the bus off state. 0 = No bus off interrupt requested 1 = When the TouCAN state changes to bus off, this bit is set, and if the BOFFMSK bit in CANCTRL0 is set, an interrupt request is generated. This interrupt is not requested after reset.
ACKERR
CRCERR
FORMERR
STUFERR
TXWARN
RXWARN
IDLE
TX/RX
12
13
BOFFINT
MPC555
/ MPC556
MOTOROLA 16-33
USERS MANUAL

Table 16-21 ESTAT Bit Descriptions (Continued)
Bit(s) Name Description Error Interrupt. The ERRINT bit is used to request an interrupt when the TouCAN detects a transmit or receive error. 0 = No error interrupt request 1 = If an event which causes one of the error bits in the error and status register to be set occurs, the error interrupt bit is set. If the ERRMSK bit in CANCTRL0 is set, an interrupt request is generated. To clear this bit, first read it as a one, then write as a zero. Writing a one has no effect. Wake interrupt. The WAKEINT bit indicates that bus activity has been detected while the TouCAN module is in low-power stop mode. 0 = No wake interrupt requested 1 = When the TouCAN is in low-power stop mode and a recessive to dominant transition is detected on the CAN bus, this bit is set. If the WAKEMSK bit is set in CANMCR, an interrupt request is generated.
14
ERRINT
15
WAKEINT
Table 16-22 Transmit Bit Error Status

BITERR[1:0] 00 01 10 11 No transmit bit error At least one bit sent as dominant was received as recessive At least one bit sent as recessive was received as dominant Not used Bit Error Status
Table 16-23 Fault Confinement State Encoding

FCS[1:0] 00 01 1X Bus State Error active Error passive Bus off
16.7.13 Interrupt Mask Register IMASK Interrupt Mask Register

MSB 0 1 2 3 4 5 6 7 8 9 10
0x30 70A2, 0x30 74A2

11 12 13 14 LSB 15
IMASKH RESET: 0 0 0 0 0 0 0 0 0 0 0
IMASKL
Table 16-24 IMASK Bit Descriptions

Bit(s) Name Description IMASK contains two 8-bit fields, IMASKH and IMASKL. IMASK can be accessed with a 16bit read or write, and IMASKH and IMASKL can be accessed with byte reads or writes. 0:7, 8:15 IMASKH, IMASKL IMASK contains one interrupt mask bit per buffer. It allows the CPU to designate which buffers will generate interrupts after successful transmission/reception. Setting a bit in IMASK enables interrupt requests for the corresponding message buffer. NOTE: Bit 15 (LSB) corresponds to message buffer 0. Bit 0 (MSB) corresponds to mesage buffer 15.
MPC555
/ MPC556
MOTOROLA 16-34
USERS MANUAL

16.7.14 Interrupt Flag Register IFLAG Interrupt Flag Register
MSB 0 1 2 3 4 5 6 7 8 9 10 11 12
0x30 70A4 0x30 74A4

13 14 LSB 15
IFLAGH RESET: 0 0 0 0 0 0 0 0 0 0 0
IFLAGL
Table 16-25 IFLAG Bit Descriptions

Bit(s) Name Description IFLAG contains two 8-bit fields, IFLAGH and IFLAGL. IFLAG can be accessed with a 16-bit read or write, and IFLAGH and IFLAGL can be accessed with byte reads or writes. IFLAG contains one interrupt flag bit per buffer. Each successful transmission/reception sets the corresponding IFLAG bit and, if the corresponding IMASK bit is set, an interrupt request will be generated. To clear an interrupt flag, first read the flag as a one, and then write it as a zero. Should a new flag setting event occur between the time that the CPU reads the flag as a one and writes the flag as a zero, the flag is not cleared. This register can be written to zeros only. NOTE: Bit 15 (LSB) corresponds to message buffer 0. Bit 0 (MSB) corresponds to mesage buffer 15.
0:7, 8:15
IFLAGH, IFLAGL
16.7.15 Error Counters RXECTR Receive Error Counter TXECTR Transmit Error Counter
MSB 0 1 2 3 4 5 6 7 8 9 10
0x30 70A6, 0x30 74A6

11 12 13 14 LSB 15
RXECTR RESET: 0 0 0 0 0 0 0 0 0 0 0
TXECTR
Table 16-26 RXECTR, TXECTR Bit Descriptions

Bit(s) 0:7, 8:15 Name RXECTR, TXECTR Description Both counters are read only, except when the TouCAN is in test or debug mode.
MPC555
/ MPC556
MOTOROLA 16-35
USERS MANUAL
MPC555
/ MPC556
MOTOROLA 16-36
USERS MANUAL
SECTION 17 TIME PROCESSOR UNIT 3

The time processor unit 3 (TPU3), an enhanced version of the original TPU, is an intelligent, semi-autonomous microcontroller designed for timing control. The TPU3 is fully compatible to the TPU2. Operating simultaneously with the CPU, the two TPU3 modules process micro-instructions, schedules and processes real-time hardware events, performs input and output, and accesses shared data without CPU intervention. Consequently, for each timer event, the CPU setup and service times are minimized or eliminated.
The MPC555 / MPC556 contains two independent TPU3s. Figure 17-1 is a simplified block diagram of a single TPU3.
HOST INTERFACE
CONTROL
SCHEDULER
SERVICE REQUESTS
TIMER CHANNELS
CHANNEL 0 CHANNEL SYSTEM CONFIGURATION TCR1 T2CLK PIN TCR2 PINS MICROENGINE CHANNEL CONTROL CHANNEL 1
IMB3
DEVELOPMENT SUPPORT AND TEST
DATA
CONTROL STORE
CONTROL AND DATA
PARAMETER RAM DATA
EXECUTION UNIT
CHANNEL 15
Figure 17-1 TPU3 Block Diagram 17.1 Overview The TPU3 can be viewed as a special-purpose microcomputer that performs a programmable series of two operations, match and capture. Each occurrence of either operation is called an event. A programmed series of events is called a function. TPU functions replace software functions that would require CPU interrupt service.
TIME PROCESSOR UNIT 3
MOTOROLA 17-1

The microcode ROM TPU3 functions that are available in the MPC555 / MPC556 are described in APPENDIX D TPU ROM FUNCTIONS. 17.2 TPU3 Components The TPU3 consists of two 16-bit time bases, 16 independent timer channels, a task scheduler, a microengine, and a host interface. In addition, a dual-ported parameter RAM is used to pass parameters between the module and the CPU. 17.2.1 Time Bases Two 16-bit counters provide reference time bases for all output compare and input capture events. Prescalers for both time bases are controlled by the CPU via bit fields in the TPU3 module configuration register (TPUMCR) and TPU module configuration register two (TPUMCR2). Timer count registers TCR1 and TCR2 provide access to the current counter values. TCR1 and TCR2 can be read by TPU microcode but are not directly available to the CPU. The TCR1 clock is always derived from the IMB clock. The TCR2 clock can be derived from the IMB clock or from an external input via theT2CLK clock pin. The duration between active edges on the T2CLK clock pin must be at least nine IMB clocks. 17.2.2 Timer Channels The TPU3 has 16 independent channels, each connected to an MCU pin. The channels have identical hardware and are functionally equivalent in operation. Each channel consists of an event register and pin control logic. The event register contains a 16-bit capture register, a 16-bit compare/match register, and a 16-bit greater-than-orequal-to comparator. The direction of each pin, either output or input, is determined by the TPU microengine. Each channel can either use the same time base for match and capture, or can use one time base for match and the other for capture. 17.2.3 Scheduler When a service request is received, the scheduler determines which TPU3 channel is serviced by the microengine. A channel can request service for one of four reasons: for host service, for a link to another channel, for a match event, or for a capture event. The host system assigns each active channel one of three priorities: high, middle, or low. When multiple service requests are received simultaneously, a priority-scheduling mechanism grants service based on channel number and assigned priority. 17.2.4 Microengine The microengine is composed of a control store and an execution unit. Control-store ROM holds the microcode for each factory-masked time function. When assigned to a channel by the scheduler, the execution unit executes microcode for a function assigned to that channel by the CPU. Microcode can also be executed from the dual-port RAM (DPTRAM) module instead of the control store. The DPTRAM allows emulation and development of custom TPU microcode without the generation of a microcode ROM mask. Refer to 17.3.6 Emulation Support for more information.
MPC555
/ MPC556
MOTOROLA 17-2
USERS MANUAL

17.2.5 Host Interface The host interface registers allow communication between the CPU and the TPU3, both before and during execution of a time function. The registers are accessible from the IMB through the TPU3 bus interface unit. Refer to 17.4 Programming Model for register bit/field definitions and address mapping. 17.2.6 Parameter RAM Parameter RAM occupies 256 bytes at the top of the system address map. Channel parameters are organized as 128 16-bit words. Channels zero through 15 each have eight parameters. The parameter RAM address map in 17.4.18 TPU3 Parameter RAM shows how parameter words are organized in memory.
The CPU specifies function parameters by writing to the appropriate RAM address. The TPU3 reads the RAM to determine channel operation. The TPU3 can also store information to be read by the CPU in the parameter RAM. Detailed descriptions of the parameters required by each time function are beyond the scope of this manual. Refer to the TPU Reference Manual (TPURM/AD) and the Motorola TPU Literature Package (TPULITPAK/D) for more information. 17.3 TPU Operation All TPU3 functions are related to one of the two 16-bit time bases. Functions are synthesized by combining sequences of match events and capture events. Because the primitives are implemented in hardware, the TPU3 can determine precisely when a match or capture event occurs, and respond rapidly. An event register for each channel provides for simultaneous match/capture event occurrences on all channels. When a match or input capture event requiring service occurs, the affected channel generates a service request to the scheduler. The scheduler determines the priority of the request and assigns the channel to the microengine at the first available time. The microengine performs the function defined by the content of the control store or emulation RAM, using parameters from the parameter RAM. 17.3.1 Event Timing Match and capture events are handled by independent channel hardware. This provides an event accuracy of one time-base clock period, regardless of the number of channels that are active. An event normally causes a channel to request service. The time needed to respond to and service an event is determined by which channels and the number of channels requesting service, the relative priorities of the channels requesting service, and the microcode execution time of the active functions. Worstcase event service time (latency) determines TPU3 performance in a given application. Latency can be closely estimated. For more information, refer to the TPU Reference Manual (TPURM/AD). 17.3.2 Channel Orthogonality Most timer systems are limited by the fixed number of functions assigned to each pin. All TPU3 channels contain identical hardware and are functionally equivalent in operMPC555
/ MPC556
MOTOROLA 17-3
USERS MANUAL

ation, so that any channel can be configured to perform any time function. Any function can operate on the calling channel, and, under program control, on another channel determined by the program or by a parameter. The user controls the combination of time functions. 17.3.3 Interchannel Communication The autonomy of the TPU3 is enhanced by the ability of a channel to affect the operation of one or more other channels without CPU intervention. Interchannel communication can be accomplished by issuing a link service request to another channel, by controlling another channel directly, or by accessing the parameter RAM of another channel. 17.3.4 Programmable Channel Service Priority The TPU3 provides a programmable service priority level to each channel. Three priority levels are available. When more than one channel of a given priority requests service at the same time, arbitration is accomplished according to channel number. To prevent a single high-priority channel from permanently blocking other functions, other service requests of the same priority are performed in channel order after the lowestnumbered, highest-priority channel is serviced. 17.3.5 Coherency For data to be coherent, all available portions of the data must be identical in age, or must be logically related. As an example, consider a 32-bit counter value that is read and written as two 16-bit words. The 32-bit value is read-coherent only if both 16-bit portions are updated at the same time, and write-coherent only if both portions take effect at the same time. Parameter RAM hardware supports coherent access of two adjacent 16-bit parameters. The host CPU must use a long-word operation to guarantee coherency. 17.3.6 Emulation Support Although factory-programmed time functions can perform a wide variety of control tasks, they may not be ideal for all applications. The TPU3 provides emulation capability that allows the user to develop new time functions. Emulation mode is entered by setting the EMU bit in TPUMCR. In emulation mode, an auxiliary bus connection is made between the DPTRAM and the TPU3, and access to DPTRAM via the intermodule bus is disabled. A 9-bit address bus, a 32-bit data bus, and control lines transfer information between the modules. To ensure exact emulation, DPTFLASH module access timing remains consistent with access timing of the TPU microcode ROM control store. To support changing TPU application requirements, Motorola has established a TPU function library. The function library is a collection of TPU functions written for easy assembly in combination with each other or with custom functions. Refer to Motorola Programming Note Using the TPU Function Library and TPU Emulation Mode, (TPUPN00/D), for information about developing custom functions and accessing the
MPC555
/ MPC556
MOTOROLA 17-4
USERS MANUAL

TPU function library. Refer to the Motorola TPU Literature Package (TPULITPAK/D) for more information about specific functions. 17.3.7 TPU3 Interrupts Each of the TPU3 channels can generate an interrupt service request. Interrupts for each channel must be enabled by writing to the appropriate control bit in the channel interrupt enable register (CIER). The channel interrupt status register (CISR) contains one interrupt status flag per channel. Time functions set the flags. Setting a flag bit causes the TPU3 to make an interrupt service request if the corresponding channel interrupt enable bit is set. The TPU3 can generate one of 32 possible interrupt request levels on the IMB3. The value driven onto IRQ[7:0] represents the interrupt level programmed in the IRL field of the TPU interrupt configuration register (TICR). Under the control of the ILBS bits in the ICR, each interrupt request level is driven during the time multiplexed bus during one of four different time slots, with eight levels communicated per time slot. No hardware priority is assigned to interrupts. Furthermore, if more than one source on a module requests an interrupt at the same level, the system software must assign a priority to each source requesting at that level. Figure 17-2 displays the interrupt level scheme.
IMB3 CLOCK
ILBS[1:0]
00
01
10
11
00
01
10
11
IMB3 IRQ[7:0]
IRQ 7:0
IRQ 15:8
IRQ 23:16
IRQ 31:24
IRQ 7:0
Figure 17-2 TPU3 Interrupt Levels 17.3.8 Prescaler Control for TCR1 Timer count register 1 (TCR1) is clocked from the output of a prescaler. The following fields control TCR1: The PSCK and TCR1P fields in TPUMCR The DIV2 field in TPUMCR2 The EPSCKE and EPSCK fields in TPUMCR3. The rate at which TCR1 is incremented is determined as follows: The user selects either the standard prescaler (by clearing the enhanced prescaler enable bit, EPSCKE, in TPUMCR3) or the enhanced prescaler (by setting EPSCKE).
MPC555
/ MPC556
MOTOROLA 17-5
USERS MANUAL

If the standard prescaler is selected (EPSCKE = 0), the the PSCK bit determines whether the standard prescaler divides the IMB clock input by 32 (PSCK = 0) or four (PSCK = 1) If the enhanced prescaler is selected (EPSCKE = 1), the EPSCK bits select a value by which the IMB clock is divided. The lowest frequency for TCR1 clock is IMB clock divided by 64x8. The highest frequency for TCR1 clock is IMB clock divided by two (2x1). See Table 17-1. Table 17-1 Enhanced TCR1 Prescaler Divide Values
EPSCK Value
0x00 0x01 0x02 0x03 0x04, 0x05,...0x1d 0x1e 0x1f Divide IMB Clock By 2 4 6 8 10,12,...60 62 64
The output of either the standard prescaler or the enhanced prescaler is then divided by 1, 2, 4, or 8, depending on the value of the TCR1P field in the TPUMCR. Table 17-2 TCR1 Prescaler Values
TCR1P Value 0b00 0b01 0b10 0b11 Divide by 1 2 4 8
If the DIV2 bit is one, the TCR1 counter increments at a rate of the internal clock divided by two. If DIV2 is zero, the TCR1 increment rate is defined by the output of the TCR1 prescaler (which, in turn, takes as input the output of either the standard or enhanced prescaler). Figure 17-3 shows a diagram of the TCR1 prescaler control block.
MPC555
/ MPC556
MOTOROLA 17-6
USERS MANUAL
IMB Clock
Prescaler 32 / 4 Enhanced Prescaler 2,4,6,...64 PSCK MUX TCR1 PRESCALER 1,2,4,8 TCR1
EPSCKE
DIV2
Figure 17-3 TCR1 Prescaler Control 17.3.9 Prescaler Control for TCR2 Timer count register 2 (TCR2), like TCR1, is clocked from the output of a prescaler. The T2CG (TCR2 clock/gate control) bit and the T2CSL (TCR2 counter clock edge) bit in TPUMCR determine T2CR2 pin functions. Refer to Table 17-3. Table 17-3 TCR2 Counter Clock Source
T2CSL 0 0 1 1 T2CG 0 1 0 1 TCR2 Clock Rise transition T2CLK Gated IMB clock Fall transition T2CLK Rise & fall transition T2CLK
The function of the T2CG bit is shown in Figure 17-4. When T2CG is set, the external T2CLK pin functions as a gate of the DIV8 clock (the TPU3 IMB clock divided by eight). In this case, when the external TCR2 pin is low, the DIV8 clock is blocked, preventing it from incrementing TCR2. When the external TCR2 pin is high, TCR2 is incremented at the frequency of the DIV8 clock. When T2CG is cleared, an external clock from the TCR2 pin, which has been synchronized and fed through a digital filter, increments TCR2. The duration between active edges on the T2CLK clock pin must be at least nine IMB clocks. The TCR2PSCK2 bit in TPUMCR3 determines whether the clock source is divided by two before it is fed into the TCR2 prescaler. The TCR2 field in TPUMCR specifies the value of the prescaler: 1, 2, 4, or 8. Channels using TCR2 have the capability to re-
MPC555
/ MPC556
MOTOROLA 17-7
USERS MANUAL

solve down to the TPU3 IMB clock divided by eight. Figure 17-4 illustrates the TCR2 pre-divider and pre-scaler control.
TCR2 Pin CLOCK DIV8 MUX Control
Clock Source
Pre-divider Prescaler
TCR2 PRESCALER 1,2,4,8
TCR2
TCR2PSCK2
Figure 17-4 TCR2 Prescaler Control Table 17-4 is a summary of prescaler output (assuming a divide-by-one value for the pre-divider prescaler. Table 17-4 TCR2 Prescaler Control
TCR2 Value 0b00 0b01 0b10 0b11 Internal Clock Divide Ratio TCR2PSCK2 = 0 TCR2PSCK2 = 1 8 8 16 24 32 56 64 120 External Clock Divide Ratio TCR2PSCK2 = 0 TCR2PSCK2 = 1 1 1 2 3 4 7 8 15
17.4 Programming Model The TPU3 memory map contains three groups of registers: System configuration registers Channel control and status registers Development support and test verification registers All registers except the channel interrupt status register (CISR) must be read or written by means of half-word (16-bit) or word (32-bit) accesses. The address space of the TPU3 memory map occupies 512 bytes. Unused registers within the 512-byte address space return zeros when read. Table 17-5 shows the TPU3 address map.
MPC555
/ MPC556
MOTOROLA 17-8
USERS MANUAL

Table 17-5 TPU3 Register Map
MSB 0 Address 0x30 4000 0x30 4400 0x30 4002 0x30 4402 0x30 4004 0x30 4404 0x30 4006 0x30 4406 Register TPU3 Module Configuration Register (TPUMCR) See Table 17-6 for bit descriptions. TPU3 Test Configuration Register (TCR) Development Support Control Register (DSCR) See Table 17-7 for bit descriptions. Development Support Status Register (DSSR) See Table 17-8 for bit descriptions. TPU3 Interrupt Configuration Register (TICR) See Table 17-9 for bit descriptions. Channel Interrupt Enable Register (CIER) See Table 17-10 for bit descriptions. Channel Function Selection Register 0 (CFSR0) See Table 17-11 for bit descriptions. Channel Function Selection Register 1 (CFSR1) See Table 17-11 for bit descriptions. Channel Function Selection Register 2 (CFSR2) See Table 17-11 for bit descriptions. Channel Function Selection Register 3 (CFSR3) See Table 17-11 for bit descriptions. Host Sequence Register 0 (HSQR0) See Table 17-12 for bit descriptions. Host Sequence Register 1 (HSQR1) See Table 17-12 for bit descriptions. Host Service Request Register 0 (HSRR0) See Table 17-13 for bit descriptions. Host Service Request Register 1 (HSRR1) See Table 17-13 for bit descriptions. Channel Priority Register 0 (CPR0) See Table 17-14 for bit descriptions. Channel Priority Register 1 (CPR1) See Table 17-14 for bit descriptions. Channel Interrupt Status Register (CISR) See Table 17-16 for bit descriptions. Link Register (LR) Service Grant Latch Register (SGLR) Decoded Channel Number Register (DCNR) TPU Module Configuration Register 2 (TPUMCR2) See Table 17-17 for bit descriptions. TPU Module Configuration 3 (TPUMCR3) See Table 17-20 for bit descriptions. Internal Scan Data Register (ISDR) LSB 15
0x30 4008 0x30 4408 0x30 400A 0x30 440A 0x30 400C 0x30 440C 0x30 400E 0x30 440E 0x30 4010 0x30 4410 0x30 4012 0x30 4412 0x30 4014 0x30 4414 0x30 4016 0x30 4416 0x30 4018 0x30 4418 0x30 401A 0x30 441A 0x30 401C 0x30 441C 0x30 401E 0x30 441E 0x30 4020 0x30 4420 0x30 4022 0x30 4422 0x30 4024 0x30 4424 0x30 4026 0x30 4426 0x30 4028 0x30 4428 0x30 402A 0x30 442A 0x30 402C 0x30 442C
MPC555
/ MPC556
MOTOROLA 17-9
USERS MANUAL

Table 17-5 TPU3 Register Map (Continued)
MSB 0 Address 0x30 402E 0x30 442E 0x30 4100 0x30 410F 0x30 4500 0x30 450F 0x30 4110 0x30 411F 0x30 4510 0x30 451F 0x30 4120 0x30 412F 0x30 4520 0x30 452F 0x30 4130 0x30 413F 0x30 4530 0x30 453F Register Internal Scan Control Register (ISCR) Channel 0 Parameter Registers Channel 1 Parameter Registers Channel 2 Parameter Registers Channel 3 Parameter Registers Channel 4 Parameter Registers Channel 5 Parameter Registers Channel 6 Parameter Registers Channel 7 Parameter Registers Channel 8 Parameter Registers Channel 9 Parameter Registers
0x30 4140 0x30 414F 0x30 4540 0x30 454F 0x30 4150 0x30 415F 0x30 4550 0x30 455F 0x30 4160 0x30 416F 0x30 4560 0x30 456F 0x30 4170 0x30 417F 0x30 4570 0x30 457F 0x30 4180 0x30 418F 0x30 4580 0x30 458F 0x30 4190 0x30 419F 0x30 4590 0x30 459F
0x30 41A0 0x30 41AF Channel 10 Parameter Registers 0x30 45A0 0x30 45AF 0x30 41B0 0x30 41BF Channel 11 Parameter Registers 0x30 45B0 0x30 45BF 0x30 41C0 0x30 41CF Channel 12 Parameter Registers 0x30 45C0 0x30 45CF 0x30 41D0 0x30 41DF Channel 13 Parameter Registers 0x30 45D0 0x30 45DF 0x30 41E0 0x30 41EF Channel 14 Parameter Registers 0x30 45E0 0x30 45EF 0x30 41F0 0x30 41FF 0x30 45F0 0x30 45FF Channel 15 Parameter Registers
17.4.1 TPU Module Configuration Register TPUMCR TPU Module Configuration Register
MSB 0 STOP RESET: 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 2 3 4 5 EMU 6 T2CG 7 STF 8 9 10 TPU3 11 T2CSL 12 13 14
0x30 4000 0x30 4400

LSB 15
TCR1P
TCR2P
SUPV PSCK
RESERVED
MPC555
/ MPC556
MOTOROLA 17-10
USERS MANUAL

Table 17-6 TPUMCR Bit Descriptions
Bit(s) Name Description Low-power stop mode enable. If the STOP bit in TPUMCR is set, the TPU3 shuts down its internal clocks, shutting down the internal microengine. TCR1 and TCR2 cease to increment and retain the last value before the stop condition was entered. The TPU3 asserts the stop flag (STF) in TPUMCR to indicate that it has stopped. 0 = Enable TPU3 clocks 1 = Disable TPU3 clocks Timer count register 1 prescaler control. TCR1 is clocked from the output of a prescaler. The prescaler divides its input by 1, 2, 4, or 8. This is a write-once field unless the PWOD bit in TPUMCR3 is set. 00 = Divide by 1 01 = Divide by 2 10 = Divide by 4 11 = Divide by 8 Refer to 17.3.8 Prescaler Control for TCR1 for more information. Timer count register 2 prescaler control. TCR2 is clocked from the output of a prescaler. The prescaler divides this input by 1, 2, 4, or 8. This is a write-once field unless the PWOD bit in TPUMCR3 is set. 00 = Divide by 1 01 = Divide by 2 10 = Divide by 4 11 = Divide by 8 Refer to 17.3.9 Prescaler Control for TCR2 for more information. Emulation control. In emulation mode, the TPU3 executes microinstructions from DPTRAM exclusively. Access to the DPTRAM via the IMB3 is blocked, and the DPTRAM is dedicated for use by the TPU3. After reset, this bit can be written only once. 0 = TPU3 and DPTRAM operate normally 1 = TPU3 and DPTRAM operate in emulation mode TCR2 clock/gate control 0 = TCR2 pin used as clock source for TCR2 1 = TCR2 pin used as gate of DIV8 clock for TCR2 Refer to 17.3.9 Prescaler Control for TCR2 for more information. Stop flag. 0 = TPU3 is operating normally 1 = TPU3 is stopped (STOP bit has been set) Supervisor data space 0 = Assignable registers are accessible from user or supervisor privilege level 1 = Assignable registers are accessible from supervisor privilege level only Standard prescaler clock. Note that this bit has no effect if the extended prescaler is selected (EPSCKE = 1). 0 = fSYS 32 is input to TCR1 prescaler, if standard prescaler is selected 1 = fSYS 4 is input to TCR1 prescaler, if standard prescaler is selected TPU3 enable. The TPU3 enable bit provides compatibility with the TPU. If running TPU code on the TPU3, the microcode size should not be greater than two Kbytes and the TPU3 enable bit should be cleared to zero. The TPU3 enable bit is write-once after reset. The reset value is one, meaning that the TPU3 will operate in TPU3 mode. 0 = TPU mode; zero is the TPU reset value 1 = TPU3 mode; one is the TPU3 reset value NOTE: The programmer should not change this value unless necessary when developing custom TPU microcode. 11 12:15 T2CSL TCR2 counter clock edge. This bit and the T2CG control bit determine the clock source for TCR2. Refer to 17.3.9 Prescaler Control for TCR2 for details. Reserved. These bits are used for the IARB (interrupt arbitration ID) field in TPU3 implementations that use hardware interrupt arbitration.
STOP
1:2
TCR1P
3:4
TCR2P
EMU
T2CG
STF
SUPV
PSCK
10
TPU3
MPC555
/ MPC556
MOTOROLA 17-11
USERS MANUAL

17.4.2 TPU3 Test Configuration Register TCR TPU3 Test Configuration Register Used for factory test only. 17.4.3 Development Support Control Register DSCR Development Support Control Register
MSB 0 HOT4 1 2 3 4 5 BLC 6 CLKS 7 FRZ 8 9 CCL 10 BP 11 BC 12 BH 13 BL 14 BM
0x30 4002, 0x30 4402
0x30 4004 0x30 4404

LSB 15 BT
RESERVED
RESET: 0 0 0 0 0 0 0 0 0 0 0 0
MPC555
/ MPC556
MOTOROLA 17-12
USERS MANUAL

Table 17-7 DSCR Bit Descriptions
Bit(s) 0 1:4 5 Name HOT4 BLC Description Hang on T4 0 = Exit wait on T4 state caused by assertion of HOT4 1 = Enter wait on T4 state Reserved Branch latch control 0 = Latch conditions into branch condition register before exiting halted state 1 = Do not latch conditions into branch condition register before exiting the halted state or during the time-slot transition period Stop clocks (to TCRs) 0 = Do not stop TCRs 1 = Stop TCRs during the halted state FREEZE assertion response. The FRZ bits specify the TPU microengine response to the IMB3 FREEZE signal 00 = Ignore freeze 01 = Reserved 10 = Freeze at end of current microcycle 11 = Freeze at next time-slot boundary Channel conditions latch. CCL controls the latching of channel conditions (MRL and TDL) when the CHAN register is written. 0 = Only the pin state condition of the new channel is latched as a result of the write CHAN register microinstruction 1 = Pin state, MRL, and TDL conditions of the new channel are latched as a result of a write CHAN register microinstruction PC breakpoint enable 0 = Breakpoint not enabled 1 = Break if PC equals PC breakpoint register Channel breakpoint enable 0 = Breakpoint not enabled 1 = Break if CHAN register equals channel breakpoint register at beginning of state or when CHAN is changed through microcode Host service breakpoint enable 0 = Breakpoint not enabled 1 = Break if host service latch is asserted at beginning of state Link service breakpoint enable 0 = Breakpoint not enabled 1 = Break if link service latch is asserted at beginning of state MRL breakpoint enable 0 = Breakpoint not enabled 1 = Break if MRL is asserted at beginning of state TDL breakpoint enable 0 = Breakpoint not enabled 1 = Break if TDL is asserted at beginning of state
CLKS
7:8
FRZ
CCL
10
BP
11
BC
12
BH
13
BL
14
BM
15
BT
MPC555
/ MPC556
MOTOROLA 17-13
USERS MANUAL

17.4.4 Development Support Status Register DSSR Development Support Status Register
MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RESERVED
0x30 4006 0x30 4406

LSB 15
RESERVED RESET: 0 0 0 0 0 0 0 0
BKPT PCBK CHBK SRBK TPUF
Table 17-8 DSSR Bit Descriptions

Bit(s) Name BKPT Reserved Breakpoint asserted flag. If an internal breakpoint caused the TPU3 to enter the halted state, the TPU3 asserts the BKPT signal on the IMB and sets the BKPT flag. BKPT remains set until the TPU3 recognizes a breakpoint acknowledge cycle, or until the IMB FREEZE signal is asserted. PC breakpoint flag. PCBK is asserted if a breakpoint occurs because of a PC (microprogram counter) register match with the PC breakpoint register. PCBK is negated when the BKPT flag is cleared. Channel register breakpoint flag. CHBK is asserted if a breakpoint occurs because of a CHAN register match with the CHAN register breakpoint register. CHBK is negated when the BKPT flag is cleared. Service request breakpoint flag. SRBK is asserted if a breakpoint occurs because of any of the service request latches being asserted along with their corresponding enable flag in the development support control register. SRBK is negated when the BKPT flag is cleared. TPU3 FREEZE flag. TPUF is set whenever the TPU3 is in a halted state as a result of FREEZE being asserted. This flag is automatically negated when the TPU3 exits the halted state because of FREEZE being negated. Reserved Description
0:7 8
PCBK
10
CHBK
11
SRBK
12 13:15
TPUF
17.4.5 TPU3 Interrupt Configuration Register TICR TPU3 Interrupt Configuration Register
MSB 0 1 2 RESERVED RESET: 0 0 0 0 0 0 0 3 4 5 6 CIRL 7 8 ILBS 9 10 11 12 13 14
0x30 4008 0x30 4408

LSB 15
RESERVED
MPC555
/ MPC556
MOTOROLA 17-14
USERS MANUAL

Table 17-9 TICR Bit Descriptions
Bit(s) 0:4 5:7 Name CIRL Reserved Channel interrupt request level. This three-bit field specifies the interrupt request level for all channels. This field is used in conjunction with the ILBS field to determine the request level of TPU3 interrupts. Interrupt level byte select. This field and the CIRL field determine the level of TPU3 interrupt requests. 00 = IRQ[0:7] selected 01 = IRQ[8:15] selected 10 = IRQ[16:23] selected 11 = IRQ[24:31] selected Reserved. Note that bits 10:11 represent channel interrupt base vector (CIBV) bits in some TPU3 implementations. Description
8:9
ILBS
10:15
17.4.6 Channel Interrupt Enable Register The channel interrupt enable register (CIER) allows the CPU to enable or disable the ability of individual TPU3 channels to request interrupt service. Setting the appropriate bit in the register enables a channel to make an interrupt service request; clearing a bit disables the interrupt. CIER Channel Interrupt Enable Register
MSB 0 1 2 3 4 5 6 CH 9 7 CH 8 8 CH 7 9 CH 6 10 CH 5 11 CH 4 12 CH 3 13 CH 2 14 CH 1
0x30 400A 0x30 440A

LSB 15 CH 0
CH 15 CH 14 CH 13 CH 12 CH 11 CH 10 RESET: 0 0 0 0 0 0
Table 17-10 CIER Bit Descriptions

Bit(s) Name Channel interrupt enable/disable 0 = Channel interrupts disabled 1 = Channel interrupts enabled Note: The MSB (bit 0 in big-endian mode) represents CH15, and the LSB (bit 15 in big-endian mode) represents CH0. Description
0:15
CH[15:0]
17.4.7 Channel Function Select Registers Encoded 4-bit fields within the channel function select registers specify one of 16 time functions to be executed on the corresponding channel. Encodings for predefined functions will be provided in a subsequent draft of this document.
MPC555
/ MPC556
MOTOROLA 17-15
USERS MANUAL

CFSR0 Channel Function Select Register 0
MSB 0 1 CH 15 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 3 4 5 CH 14 6 7 8 9 10 CH 13 11 12 13 14
0x30 400C 0x30 440C

LSB 15
CH 12

MSB
0x30 400E 0x30 440E

LSB 9 CH 9 10 11 12 13 CH 8 14 15
1 CH 11
5 CH 10
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

MSB 0 1 CH 7 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 3 4 5 CH 6 6 7 8 9 CH 5 10 11 12 13
0x30 4010 0x30 4410

LSB 14 CH 4 15

MSB 0 1 CH 3 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 3 4 5 CH 2 6 7 8 9 CH 1 10 11 12 13
0x30 4012 0x30 4412

LSB 14 CH 0 15
Table 17-11 CFSRx Bit Descriptions

Name CH[15:0] Description Encoded time function for each channel. Encoded four-bit fields in the channel function select registers specify one of 16 time functions to be executed on the corresponding channel.
17.4.8 Host Sequence Registers The host sequence field selects the mode of operation for the time function selected on a given channel. The meaning of the host sequence bits depends on the time function specified. Meanings of host sequence bits and host service request bits for predefined time functions will be provided in a subsequent draft of this document.
MPC555
/ MPC556
MOTOROLA 17-16
USERS MANUAL

HSQR0 Host Sequence Register 0
MSB 0 CH 15 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 CH 14 3 4 CH 13 5 6 CH 12 7 8 CH 11 9 10 11 12 CH 9 13 14 CH 8
0x30 4014 0x30 4414

LSB 15
CH 10
HSQR1 Host Sequence Register 1

MSB
0x30 4016 0x30 4416

LSB 7 8 CH 3 9 10 CH 2 11 12 CH 1 13 14 CH 0 15
0 CH 7
2 CH 6
4 CH 5
6 CH 4
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 17-12 HSQRx Bit Descriptions

Name CH[15:0] Description Encoded host sequence. The host sequence field selects the mode of operation for the time function selected on a given channel. The meaning of the host sequence bits depends on the time function specified.
17.4.9 Host Service Request Registers The host service request field selects the type of host service request for the time function selected on a given channel. The meaning of the host service request bits is determined by time function microcode. Refer to the TPU Reference Manual (TPURM/ AD) and the Motorola TPU Literature Package (TPULITPAK/D) for more information. HSRR0 Host Service Request Register 0
0x30 4018 0x30 4418

LSB 15
CH 10
MPC555
/ MPC556
MOTOROLA 17-17
USERS MANUAL

HSRR1 Host Service Request Register 1
MSB 0 CH 7 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 CH 6 3 4 CH 5 5 6 CH 4 7 8 CH 3 9 10 CH 2 11 12 CH 1 13 14 CH 0
0x30 401A 0x30 441A

LSB 15
Table 17-13 HSSRx Bit Descriptions

Name Description Encoded type of host service. The host service request field selects the type of host service request for the time function selected on a given channel. The meaning of the host service request bits depends on the time function specified. CH[15:0] A host service request field cleared to 0b00 signals the host that service is completed by the microengine on that channel. The host can request service on a channel by writing the corresponding host service request field to one of three non-zero states. The CPU must monitor the host service request register until the TPU3 clears the service request to 0b00 before any parameters are changed or a new service request is issued to the channel.
17.4.10 Channel Priority Registers The channel priority registers (CPR1, CPR2) assign one of three priority levels to a channel or disable the channel. CPR0 Channel Priority Register 0
0x30 401C 0x30 441C

LSB 15
CH 10
CPR1 Channel Priority Register 1

MSB 0 CH 7 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 CH 6 3 4 CH 5 5 6 CH 4 7 8 CH 3 9 10 CH 2 11 12 CH 1 13
0x30 401E 0x30 441E

LSB 14 CH 0 15
Table 17-14 CPRx Bit Descriptions

Name CH[15:0] Description Encoded channel priority levels. Table 17-15 indicates the number of time slots guaranteed for each channel priority encoding.
MPC555
/ MPC556
MOTOROLA 17-18
USERS MANUAL

Table 17-15 Channel Priorities
CHx[1:0] 00 01 10 11 Service Disabled Low Middle High Guaranteed Time Slots 1 out of 7 2 out of 7 4 out of 7
17.4.11 Channel Interrupt Status Register The channel interrupt status register (CISR) contains one interrupt status flag per channel. Time functions specify via microcode when an interrupt flag is set. Setting a flag causes the TPU3 to make an interrupt service request if the corresponding CIER bit is set. To clear a status flag, read CISR, then write a zero to the appropriate bit. CISR is the only TPU3 register that can be accessed on a byte basis. CISR Channel Interrupt Status Register
MSB 0 1 2 3 4 5 6 CH 9 7 CH 8 8 CH 7 9 CH 6 10 CH 5 11 CH 4 12 CH 3 13 CH 2 14 CH 1
0x30 4020 0x30 4420

LSB 15 CH 0
CH 15 CH 14 CH 13 CH 12 CH 11 CH 10 RESET: 0 0 0 0 0 0
Table 17-16 CISR Bit Descriptions

Bit(s) 0:15 Name CH[15:0] Channel interrupt status 0 = Channel interrupt not asserted 1 = Channel interrupt asserted Description
17.4.12 Link Register LR Link Register Used for factory test only. 17.4.13 Service Grant Latch Register SGLR Service Grant Latch Register Used for factory test only. 17.4.14 Decoded Channel Number Register DCNR Decoded Channel Number Register Used for factory test only. 0x30 4026, 0x30 4426 0x30 4024, 0x30 4424 0x30 4022, 0x30 4422
MPC555
/ MPC556
MOTOROLA 17-19
USERS MANUAL

17.4.15 TPU3 Module Configuration Register 2 TPUMCR2 TPU Module Configuration Register 2
MSB 0 1 2 3 RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 5 6 7 DIV2 8 SOFT RST 9 10 11 12 FPSCK 13 14 T2CF
0x30 4028 0x30 4428

LSB 15 DTPU
ETBANK
Table 17-17 TPUMCR2 Bit Descriptions
Bit(s) 0:6
Name Reserved
Description Divide by 2 control. When asserted, the DIV2 bit, along with the TCR1P bit and the PSCK bit in the TPUMCR, determines the rate of the TCR1 counter in the TPU3. If set, the TCR1 counter increments at a rate of two IMB clocks. If negated, TCR1 increments at the rate determined by control bits in the TCR1P and PSCK fields. 0 = TCR1 increments at rate determined by control bits in the TCR1P and PSCK fields of the TPUMCR register 1 = Causes TCR1 counter to increment at a rate of the IMB clock divided by two
DIV2
Soft reset. The TPU3 performs an internal reset when both the SOFT RST bit in the TPUMCR2 and the STOP bit in TPUMCR are set. The CPU must write zero to the SOFT RST bit to bring the TPU3 out of reset. The SOFT RST bit must be asserted for at least nine clocks. SOFT RST 0 = Normal operation 1 = Puts TPU3 in reset until bit is cleared NOTE: Do not attempt to access any other TPU3 registers when this bit is asserted. When this bit is asserted, it is the only accessible bit in the register. Entry table bank select. This field determines the bank where the microcoded entry table is situated. After reset, this field is 0b00. This control bit field is write once after reset. ETBANK is used when the microcode contains entry tables not located in the default bank 0. To execute the ROM functions on this MCU, ETBANK[1:0] must be 0b0. Refer to Table 17-18. NOTE: This field should not be modified by the programmer unless necessary because of custom microcode.
9:10
ETBANK
11:13
FPSCK
Filter prescaler clock. The filter prescaler clock control bit field determines the ratio between IMB clock frequency and minimum detectable pulses. The reset value of these bits is zero, defining the filter clock as four IMB clocks. Refer to Table 17-19. T2CLK pin filter control. When asserted, the T2CLK input pin is filtered with the same filter clock that is supplied to the channels. This control bit is write once after reset. 0 = Uses fixed four-clock filter 1 = T2CLK input pin filtered with same filter clock that is supplied to the channels Disable TPU3 pins. When the disable TPU3 control pin is asserted, pin TP15 is configured as an input disable pin. When the TP15 pin value is zero, all TPU3 output pins are three-stated, regardless of the pins function. The input is not synchronized. This control bit is write once after reset. 0 = TP15 functions as normal TPU3 channel 1 = TP15 pin configured as output disable pin. When TP15 pin is low, all TPU3 output pins are in a high-impedance state, regardless of the pin function.
14
T2CF
15
DTPU
MPC555
/ MPC556
MOTOROLA 17-20
USERS MANUAL

Table 17-18 Entry Table Bank Location
ETBANK 00 01 10 11 Bank 0 1 2 3
Table 17-19 IMB Clock Frequency/Minimum Guaranteed Detected Pulse

Filter Control FPSCK 000 001 010 011 100 101 110 111 Divide By 4 8 16 32 64 128 256 512 20 MHz 200 ns 400 ns 800 ns 1.6 s 3.2 s 6.4 s 12.8 s 25.6 s 33 MHz 121 ns 242 ns 485 ns 970 ns 1.94 s 3.88 s 7.76 s 15.51 s 40 MHz 100 ns 200 ns 400 ns 800 ns 1.60 s 3.20 s 6.40 s 12.80 s
17.4.16 TPU Module Configuration Register 3 TPUMCR3 TPU Module Configuration Register 3
MSB 0 1 2 3 RESERVED RESET: 0 0 0 0 0 0 0 4 5 6 7 PWOD 8 TCR2 PCK2 9 10 11 12 13 EPSCK 14
0x30 402A 0x30 442A

LSB 15
EPReSCKE served
Table 17-20 TPUMCR3 Bit Descriptions

Bit(s) 0:6 Name Reserved Prescaler write-once disable bit. The PWOD bit does not lock the EPSCK field and the EPSCKE bit. 0 = Prescaler fields in MCR are write-once 1 = Prescaler fields in MCR can be written anytime Description
PWOD
TCR2 prescaler 2 TCR2PSC 0 = Prescaler clock source is divided by one. K2 1 = Prescaler clock is divided. See divider definitions in Table 17-4. EPSCKE Enhanced pre-scaler enable 0 = Disable enhanced prescaler (use standard prescaler) 1 = Enable enhanced prescaler. IMB clock will be divided by the value in EPSCK field.
MPC555
/ MPC556
MOTOROLA 17-21
USERS MANUAL

Table 17-20 TPUMCR3 Bit Descriptions (Continued)
Bit(s) 10 11:15 Name EPSCK Reserved Enhanced prescaler value that will be loaded into the enhanced prescaler counter. Prescaler value = (EPSCK + 1) x 2. Refer to 17.3.8 Prescaler Control for TCR1 for details. Description
17.4.17 TPU3 Test Registers The following TPU3 registers are used for factory test only: Internal scan data register (ISDR, address offset 0x30 402C, 0x30 442C) Internal scan control register (ISCR, address offset 0x30 402E, 0x30 442E) 17.4.18 TPU3 Parameter RAM The channel parameter registers are organized as one hundred 16-bit words of RAM. Channels 0 to 15 have eight parameters. The parameter registers constitute a shared work space for communication between the CPU and the TPU3. The TPU3 can only access data in the parameter RAM. Refer to Table 17-21. Table 17-21 Parameter RAM Address Offset Map1
Channel Number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 0 100 500 110 510 120 520 130 530 140 540 150 550 160 560 170 570 180 580 190 590 1A0 5A0 1B0 5B0 1C0 5C0 1D0 5D0 1 102 502 112 512 122 522 132 532 142 542 152 552 162 562 172 572 182 582 192 592 1A2 5A2 1B2 5B2 1C2 5C2 1D2 5D2 2 104 504 114 514 124 524 134 534 144 544 154 554 164 564 174 574 184 585 194 594 1A4 5A4 1B4 5B4 1C4 5C4 1D4 5D4 Parameter 3 106 506 116 516 126 526 136 536 146 546 156 556 166 566 176 576 186 586 196 596 1A6 5A6 1B6 5B6 1C6 5C6 1D6 5D6 4 108 508 118 518 128 528 138 538 148 548 158 558 168 568 178 578 188 588 198 598 1A8 5A8 1B8 5B8 1C8 5C8 1D8 5D8 5 10A 50A 11A 51A 12A 52A 13A 53A 14A 54A 15A 55A 16A 56A 17A 57A 18A 58A 19A 59A 1AA 5AA 1BA 5BA 1CA 5CA 1DA 5DA 6 10C 50C 11C 51C 12C 52C 13C 53C 14C 54C 15C 55C 16C 56C 17C 57C 18C 58C 19C 59C 1AC 5AC 1BC 5BC 1CC 5CC 1DC 5DC 7 10E 50E 11E 51E 12E 52E 13E 53E 14E 54C 15E 55E 16E 56E 17E 57E 18E 58E 19E 59E 1AE 5AE 1BE 5BE 1CE 5CE 1DE 5DE
MPC555
/ MPC556
MOTOROLA 17-22
USERS MANUAL

Table 17-21 Parameter RAM Address Offset Map1
Channel Number 14 15 0 1E0 5E0 1F0 5F0 1 1E2 5E2 1F2 5F2 2 1E4 5E4 1F4 5F4 Parameter 3 1E6 5E6 1F6 5F6 4 1E8 5E8 1F8 5F8 5 1EA 5EA 1FA 5FA 6 1EC 5EC 1FC 5FC 7 1EE 5EE 1FE 5FE
NOTES: 1. These addresses should be added to 0x30 4000 to derive the complete parameter address.
17.5 Time Functions Descriptions of the MPC555 / MPC556 pre-programmed time functions are shown in APPENDIX D TPU ROM FUNCTIONS.
MPC555
/ MPC556
MOTOROLA 17-23
USERS MANUAL
MPC555
/ MPC556
MOTOROLA 17-24
USERS MANUAL
SECTION 18 DUAL-PORT TPU RAM (DPTRAM)

The dual-port RAM module with TPU microcode storage support (DPTRAM) consists of a control register block and a 6-Kbyte array of static RAM, which can be used either as a microcode storage for TPU or as a general-purpose memory. The DPTRAM module acts as a common memory on the IMB3 and allows the transfer of data to the two TPU3 modules. Therefore, the DPTRAM interface includes an IMB3 bus interface and two TPU3 interfaces. When the RAM is being used in microcode mode, the array is only accessible to the TPU3 via a separate local bus, and not via the IMB3. The dual-port TPU3 RAM (DPTRAM) is intended to serve as fast, two-clock access, general-purpose RAM memory for the MCU. When used as general-purpose RAM, this module is accessed via the MCUs internal bus. The DPTRAM module is powered by VDDL in normal operation. The entire array may be used as standby RAM if standby power is supplied via the VDDSRAM pin of the MCU. VDDSRAM must be supplied by an external source. The DPTRAM may also be used as the microcode control store for up to two TPU3 modules when placed in a special emulation mode. In this mode the DPTRAM array may only be accessed by either or both of the TPU3 units simultaneously via separate emulation buses, and not via the IMB3. The DPTRAM contains a multiple input signature calculator (MISC) in order to provide RAM data corruption checking. The MISC reads each RAM address and generates a 32-bit data-dependent signature. This signature can then be checked by the host. The DPTRAM supports soft defects detection (SDD). NOTE The RCPU can not perform instruction fetches from any module on the IMB (including the DPTRAM). Only data accesses are permitted. 18.1 Features Six Kbytes of static RAM Only accessible by the CPU if neither TPU3 is in emulation mode Low-power stop operation Entered by setting the STOP bit in the DPTMCR Applies only to IMB3 accesses and not to accesses from either TPU3 interface TPU microcode mode The DPTRAM array acts as a microcode storage for the TPU module. This provides a means executing TPU code out of DPTRAM instead of programming it in the TPU ROM.
MPC555 / MPC556 USERS MANUAL DUAL-PORT TPU RAM (DPTRAM) MOTOROLA 18-1

Includes built in check logic which scans the array contents and calculates the RAM signature IMB3 bus interface Two TPU3 interface units Bytes, half-word or word accessible 18.2 DPTRAM Configuration and Block Diagram
TPU
TPU
Local Bus
IMB3
IMB3
RAM
RAM
Local Bus
TPU
TPU
RAM Mode
TPU Microcode Mode
Figure 18-1 DPTRAM Configuration 18.3 Programming Model The DPTRAM module consists of two separately addressable sections. The first is a set of memory-mapped control and status registers used for configuration (DPTMCR, RAMBAR, MISRH, MISRL, MISCNT) and testing (DPTTCR) of the DPTRAM array. The second section is the array itself. All DPTRAM module control and status registers are located in supervisor data space. User reads or writes of these will result in a bus error. When the TPU3 is using the RAM array for microcode control store, none of these control registers have any effect on the operation of the RAM array. All addresses within the 64-byte control block will respond when accessed properly. Unimplemented addresses will return zeros for read accesses. Likewise, unimplemented bits within registers will return zero when read and will not be affected by write operations. Table 18-1 shows the DPTRAM control and status registers. The addresses shown are offsets from the base address for the module. Refer to 1.3 MPC555 / MPC556 Ad-
MPC555
/ MPC556
DUAL-PORT TPU RAM (DPTRAM)
MOTOROLA 18-2
USERS MANUAL

dress Map to locate the DPTRAM control block in the MPC555 / MPC556 address map. Table 18-1 DPTRAM Register Map
R/W Access Supv R/W Test Supv R/W Address 0x30 0000 0x30 0002 0x30 0004 Register DPT RAM Module Configuration Register (DPTRMCR) See Table 18-2 for bit descriptions. Test Configuration Register (DPTTCR) RAM Base Address Register (RAMBAR) See Table 18-3 for bit descriptions. Multiple Input Signature Register High (MISRH) See 18.3.4 MISR High (MISRH) and MISR Low (MISRL) for bit descriptions. Multiple Input Signature Register Low (MISRL) See 18.3.4 MISR High (MISRH) and MISR Low (MISRL) for bit descriptions. Multiple Input Signature Counter (MISCNT) See 18.3.5 MISC Counter (MISCNT) for bit descriptions. Reset Value 0x0100 0x0000 0x0001
Supv Read Only
0x30 0006
0x0000
Supv Read Only
0x30 0008
0x0000 Last memory address
Supv Read Only
0x30 000A
The DPTRAM array occupies the 6-Kbyte block. In the MPC555 / MPC556, the array must be located at the address 0x30 2000. Refer to Figure 1-3 and Figure 18-2.
0x30 2000
DPTRAM Array (6 Kbytes) 0x30 37FF
Figure 18-2 DPTRAM Memory Map 18.3.1 DPTRAM Module Configuration Register (DPTMCR) This register defines the basic configuration of the DPTRAM module. The DPTMCR contains bits to configure the DPT RAM module for stop operation and for proper access rights to the array. The register also contains the MISC control bits.
MPC555
/ MPC556
MOTOROLA 18-3
USERS MANUAL

DPTMCR DPT Module Configuration Register
MSB 0 STOP RESET: 0 0 0 1 0 0 0 0 0 0 0 0 1 2 3 4 5 MISF 6 MISEN 7 RASP 8 9 10 11 12
0x30 0000
13 14 LSB 15
NOT USED
Reserved
Table 18-2 DPTMCR Bit Descriptions

Bit(s) Name Low power stop (sleep) mode 0 = DPTRAM clocks running 1 = DPTRAM clocks shut down Description
STOP
Only the STOP bit in the DPTMCR may be accessed while the STOP bit is asserted. Accesses to other DPTRAM registers may result in unpredictable behavior. Note also that the STOP bit should be set and cleared independently of the other control bits in this register to guarantee proper operation. Changing the state of other bits while changing the state of the STOP bit may result in unpredictable behavior. Refer to 18.4.4 Stop Operation for more information. Reserved Multiple input signature flag. MISF is readable at any time. This flag bit should be polled by the host to determine if the MISC has completed reading the RAM. If MISF is set, the host should read the MISRH and MISRL registers to obtain the RAM signature. 0 = First signature not ready 1 = MISC has read entire RAM. Signature is latched in MISRH and MISRL and is ready to be read. Multiple input signature enable. MISEN is readable and writable at any time. The MISC will only operate when this bit is set and the MPC555 / MPC556 is in TPU3 emulation mode. When enabled, the MISC will continuously cycle through the RAM addresses, reading each and adding the contents to the MISR. In order to save power, the MISC can be disabled by clearing the MISEN bit. 0 = MISC disabled 1 = MISC enabled Ram area supervisor/user program/data. The RAM array may be placed in supervisor or unrestricted Space. When placed in supervisor space, (RASP = 1), only a supervisor may access the array. If a supervisor program is accessing the array, normal read/write operation will occur. If a user program is attempting to access the array, the access will be ignored and the address may be decoded externally. 0 = Both supervisor and user access to RAM allowed 1 = Supervisor access only to RAM allowed Reserved
1:4
MISF
MISEN
RASP
8:15
18.3.2 DPTRAM Test Register RAMTST Test Register RAMTST is used only during factory testing of the MCU. 0x30 0002
MPC555
/ MPC556
MOTOROLA 18-4
USERS MANUAL

18.3.3 Ram Base Address Register (RAMBAR) The RAMBAR register is used to specify the 16 MSBs of the starting DPT RAM array location in the memory map. In the MPC555 / MPC556, this register must be programed to the value 0xFFA0. This register can be written only once after a reset. This prevents runaway software from inadvertently re-mapping the array. Since the locking mechanism is triggered by the first write after reset, the base address of the array should be written in a single operation. Writing only one half of the register will prevent the other half from being written. Soft reset has no effect on this register.
RAMBAR RAM Array Base Address Register

MSB 0 A8 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 A9 2 A10 3 A11 4 A12 5 A13 6 A14 7 A15 8 A16 9 A17 10 A18 11 12
0x30 0004
13 14 LSB 15 RAMDS
Reserved
Table 18-3 RAMBAR Bit Descriptions

Bit(s) Name Description RAM array base address. These bits specify the 11 high-order bits (address lines ADDR[8:18] in little-endian notation) of the 24-bit base address of the RAM array. This allows the array to be placed on a 8-Kbyte boundary anywhere in the memory map. It is the users responsibility not to overlap the RAM array memory map with other modules on the chip. On the MPC555 / MPC556 the value 0xFFA0 must be used. Reserved. (Bits 11:12 represent A[19:20] in DPTRAM implementations that require them. RAM disabled. RAMDS is a read-only status bit. The RAM array is disabled after a master reset since the RAMBAR register may be incorrect. When the array is disabled, it will not respond to any addresses on the IMB3. Access to the RAM control register block is not affected when the array is disabled. RAMDS is cleared by the DPTRAM module when a base address is written to the array address field of RAMBAR. RAMDS = 0: RAM enabled RAMDS = 1: RAM disabled
0:10
A[8:18]
11:14
15
RAMDS
18.3.4 MISR High (MISRH) and MISR Low (MISRL) The MISRH and MISRL together contain the 32-bit RAM signature calculated by the MISC. These registers are read-only and should be read by the host when the MISF bit in the MCR is set. Note that the naming of the D[31:0] bits represents little-endian bit encoding. Exiting TPU3 emulation mode results in the reset of both MISRH and MISRL MISRH Multiple Input Signature Register High
MSB 0 1 2 3 4 5 6 7 8 9 10 11 12
0x30 0006
13 14 LSB 15
MPC555
/ MPC556
MOTOROLA 18-5
USERS MANUAL

MISRH Multiple Input Signature Register High
D31 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19
0x30 0006
D18 D17 D16
MISRL Multiple Input Signature Register Low

MSB 0 D15 RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D14 2 D13 3 D12 4 D11 5 D10 6 D9 7 D8 8 D7 9 D6 10 D5 11 D4 12 D3
0x30 0008
13 D2 14 D1 LSB 15 D0
18.3.5 MISC Counter (MISCNT) The MISCNT contains the address of the current MISC memory access. This registers is read-only. Note that the naming of the A[31:0] bits represents little-endian bit encoding. Exiting TPU3 emulation mode or clearing the MISEN bit in the DPTMCR results in the reset of this register. MISCNT MISC Counter
MSB 0 1 2 3 A12 4 A11 5 A10 6 A9 7 A8 8 A7 9 A6 10 A5 11 A4 12 A3 13 A2
0x30 000A
14 A1 LSB 15 A0
RESERVED RESET:
Last Memory Address
18.4 Operation The DPTRAM module has several modes of operation. The following sections describe DPTRAM operation in each of these modes. 18.4.1 Normal Operation In normal operation, the DPTRAM is powered by VDDL and may be accessed via the IMB3 by a bus master. Read or write accesses of 8, 16, or 32 bits are supported. In normal operation, neither TPU3 accesses the array, nor do they have any effect on the operation of the DPTRAM module. 18.4.2 Standby Operation The DPTRAM array uses a separate power supply VDDSRAM to maintain the contents of the DPTRAM array during a power-down phase. When the RAM array is powered by the VDDSRAM pin of the MCU, access to the RAM array is blocked. Data read from the RAM array during this condition cannot be guaranteed. Data written to the DPTRAM may be corrupted if switching occurs during a write operation.
MPC555
/ MPC556
MOTOROLA 18-6
USERS MANUAL

In order to guarantee valid DPTRAM data during power-down, external low voltage inhibit circuitry (external to the MCU) must be designed to force the RESET pin of the MCU into the active state before VDDL drops below its normal limit. This is necessary to inhibit spurious writes to the DPTRAM during power-down. 18.4.3 Reset Operation When a synchronous reset occurs, a bus master is allowed to complete the current access. Thus a write bus cycle (byte or half word) that is in progress when a synchronous reset occurs will be completed without error. Once a write already in progress has been completed, further writes to the RAM array are inhibited. NOTE A word (32-bit) write will be completed coherently only if the reset occurs during the second (16-bit) write bus cycle. If reset occurs during the first write bus cycle, only the first half word will be written to the RAM array and the second write will not be allowed to occur. In this case, the word data contained in the DPTRAM will not be coherent. The first half word will contain the most significant half of the new word information and the second half word will contain the least significant half of the old word information. If a reset is generated by an asynchronous reset such as the loss of clocks or software watchdog time-out, the contents of the RAM array are not guaranteed. (Refer to SECTION 7 RESET for a description of MPC555 / MPC556 reset sources, operation, control, and status.) Reset will also reconfigure some of the fields and bits in the DPTRAM control registers to their default reset state. See the description of the control registers to determine the effect of reset on these registers. 18.4.4 Stop Operation Setting the STOP control bit in the DPTMCR causes the module to enter its lowest power-consuming state. The DPTMCR can still be written to allow the STOP control bit to be cleared. In stop mode, the DPTRAM array cannot be read or written. All data in the array is retained. The BIU continues to operate to allow the CPU to access the STOP bit in the DPTMCR. The system clock remains stopped until the STOP bit is cleared or the DPTRAM module is reset. The STOP bit is initialized to logical zero during reset. Only the STOP bit in the DPTMCR can be accessed while the STOP bit is asserted. Accesses to other DPTRAM registers may result in unpredictable behavior. Note also that the STOP bit should be set and cleared independently of the other control bits in this register to guarantee proper operation. Changing the state of other bits while changing the state of the STOP bit may result in unpredictable behavior.
MPC555
/ MPC556
MOTOROLA 18-7
USERS MANUAL

Switching to VDDSRAM occurs if VDDL drops below its specified value when the RAM module is in stop mode. The DPTRAM will not enter stop mode if either or both of the TP1EMM or TP2EMM signals are asserted, indicating TPU3 emulation mode. 18.4.5 Freeze Operation The FREEZE line on the IMB3 has no effect on the DPTRAM module. When the freeze line is set, the DPTRAM module will operate in its current mode of operation. If the DPTRAM module is not disabled, (RAMDS = 0), it may be accessed via the IMB3. If the DPTRAM array is being used by the TPU in emulation mode, the DPTRAM will still be able to be accessed by the TPU microengine.
18.4.6 TPU3 Emulation Mode Operation To emulate TPU3 time functions, the user stores the microinstructions required for all time functions to be used, in the RAM array. This must be done with the DPTRAM in its normal operating mode and accessible from the IMB3. After the time functions are stored in the array, the user places one or both of the TPU3 units in emulation mode. The RAM array is then controlled by the TPU3 units and disconnected from the IMB3. To use the DPTRAM for microcode accesses, set the EMU bit in the corresponding TPU3 module configuration register. Through the auxiliary buses, the TPU3 units can access word instructions simultaneously at a rate of up to 40 MHz. When the RAM array is being used by either or both of the TPU3 units, all accesses via the IMB3 are disabled. The control registers have no effect on the RAM array. Accesses to the array are ignored, allowing an external RAM to replace the function of the general-purpose RAM array. The contents of the RAM are validated using a multiple input signature calculator (MISC). MISC reads of the RAM are performed only when the MPC555 / MPC556 is in emulation mode and the MISC is enabled (MISEN = 1 in the DPTMCR). Refer to 17.3.6 Emulation Support for more information in TPU3 and DPTRAM operation in emulation mode. 18.5 Multiple Input Signature Calculator (MISC) The integrity of the RAM data is ensured through the use of a MISC. The RAM data is read in reverse address order and a unique 32-bit signature is generated based on the output of these reads. MISC reads are performed when one of the TPU3 modules does not request back-to-back accesses to the RAM provided that the MISEN bit in the DPTMCR is set. The MISC generates the DPTRAM signature based on the following polynomial: 2 22 31 G(x) = 1 + x + x + x + x / MPC556
MPC555
MOTOROLA 18-8
USERS MANUAL

After the entire RAM has been read and a signature has been calculated, the MISC sets the MISF bit in the DPTMCR. The host should poll this bit and enter a handling routine when the bit is found to be set. The signature should be then read from the MISRH and MISRL registers and the host determines if it matches the predetermined signature. The MISRH and MISRL registers are updated each time the MISC completes reading the entire RAM regardless of whether or not the previous signature has been read or not. This ensures that the host reads the most recently generated signature. The MISC can be disabled by clearing the MISEN bit in the DPTMCR. Note that the reset state of the MPC555 / MPC556 MISEN is disabled.
MPC555
/ MPC556
MOTOROLA 18-9
USERS MANUAL
MPC555
/ MPC556
MOTOROLA 18-10
USERS MANUAL
SECTION 19 CDR MoneT FLASH EEPROM

19.1 Introduction The two CDR MoneT flash EEPROM modules (CMF) serve as electrically programmable and erasable non-volatile memory (NVM) to store system program and data. The modules are designed to be used with the unified bus (U-bus). The CMF arrays use Motorolas one-transistor (MoneT) bit cell technology. The MPC555 / MPC556s total 448-Kbytes of flash EEPROM non-volatile memory are distributed between two CMF EEPROM modules: a 256-Kbyte array and a 192-Kbyte array. The erase block size is 32 Kbytes. Each CMF EEPROM module is arranged into two major sections. The first section is the flash EEPROM array used to store system program and data. The second section is the bus interface unit (BIU) that controls access and operation of the array through a standard U-bus interface and the external signals EPEE (external program or erase enable) and VPP (supply program or erase power). Each CMF EEPROM module array is divided into blocks to allow for independent erase, access state, and protection from program and erase for each block. Information is transferred to the CMF EEPROM through the U-bus a word (32 bits), half-word (16 bits), or byte at a time. The BIU accesses 32 bytes of information in the array at a time. These bytes are copied into a read-page buffer aligned to the low order addresses, ADDR[27:31]. Each CMF module contains two non-overlapping page buffers. The first page buffer is associated with array blocks zero to three. The second page is associated with array blocks four to seven (for CMF Module A), or blocks four to five (for CMF Module B). Read access time for data in the page buffers (on-page read) is one system clock. The read access time for a new page of data (off-page read) is two system clocks. To prevent the BIU from accessing an unnecessary page from the array, the CMF EEPROM monitors the U-bus address to determine whether the required information is in one of the two current pages and whether the access is valid for the module. Burst accesses are not supported by the CMF EEPROM. In normal operation, write accesses to the CMF array are not recognized. The CMF EEPROM module requires an external program or erase voltage (VPP) to program or erase the array or any of its control register shadow bits. Special hardware interlocks and the external signal EPEE protect the array from accidental enabling of program and erase operation. The program and erase algorithms are implemented by a series of writes to the CMF EEPROM registers and are under software control.
CDR MoneT FLASH EEPROM
MOTOROLA 19-1

Up to eight unique 64-byte pages are programmed simultaneously in eight separate array blocks of each of the two CMF modules. Each of the pages being programmed simultaneously is located at the same block offset address, ADDR[17:25]. Erasing is performed on one or more of the selected block(s) simultaneously. 19.1.1 MPC555 / MPC556 CMF Features Motorolas one-transistor (MoneT) bit cell Reset configuration stored in special FLASH NVM locations Array sizes of 256 Kbytes and 192 Kbytes Arrays distributed in 32-Kbyte blocks Erase by block(s) Block protection for program and erase operations Block access state control Select between supervisor and supervisor/user spaces Select between data and instruction/data spaces 32-bit word length Page mode read Retains two separate pages per CMF module Page size of 32 bytes (eight words) Off-page read access time of two system clocks On-page read access time of one system clock Supports U-bus pipelined accesses to a pipe depth of two Program up to 512 bytes at a time per CMF module Program up to eight unique 64-byte pages of data in eight separate blocks simultaneously (CMF Module A) Program up to six unique 64-byte pages of data in six separate blocks simultaneously (CMF Module B) Program CMF Module A and CMF Module B at the same time Pages located at the same offset address Self-timed program and erase pulses Internal pulse width timing control generates pulses from 4.00 s to 2.73 s using system clock frequencies from 8.0 MHz to 40.0 MHz Censored access mode with a user bypass for uncensored access per CMF module External 4.75 to 5.25-V VPP program and erase power supply External program or erase enable signal (EPEE) CMF arrays are hardware mapped to the first 512 Kbytes of the 4-Mbyte internal address space of the U-bus Supports external emulation 19.1.2 Glossary of Terms for the CMF EEPROM Array block 32-Kbyte contiguous block of information. Each array block may be erased independently. BIU Bus interface unit controls access and operation of the CMF array through a standard U-bus interface. Cleared censorship CENSOR[0:1] = 00. The CMF EEPROM can change to
MPC555
/ MPC556
MOTOROLA 19-2
USERS MANUAL

either no censorship or information censorship without modifying the CMF array contents. Cleared censorship will prevent CMF array accesses when the device is censored and ACCESS = 0. Erase interlock write A write to any CMF array address after initializing the erase sequence. Erase margin read Special off-page read of the CMF array where the CMF EEPROM hardware adjusts the reference of the sense amplifier to check for correct erase operation. All CMF array off-page read accesses between the erase interlock write and clearing the SES bit are erase margin reads. Information censorship CENSOR[0:1] = 11. Requires an erase of the CMF EEPROM to change CENSOR[0:1]. Information censorship will prevent CMF array accesses when the device is censored and ACCESS = 0. Information stored in the CMF array is made invalid while clearing CENSOR[0:1]. Initialize program/erase sequence The write to the high voltage control register that changes the SES bit from a zero to a one. MoneT The CMF EEPROMs FLASH bit cell. No censorship CENSOR[0:1] = 10 or 01, The CMF EEPROM can change to information censorship without modifying the CMF array contents. No censorship allows all CMF array accesses. Off-page read Array read operation that requires two clocks and updates a page buffer. On-page read Array read operation that accesses information in one of the read page buffers and requires one clock. Over-programmed By exceeding the specified programming time and/or voltage a CMF bit may be over-programmed. This bit will cause erased bits on the same column in the same array block to read as programmed. Programming write A word write to a CMF array address to transfer information into a program page buffer. The CMF EEPROM accepts programming writes from after initializing the program sequence until the EHV bit is changed from a zero to a one. Program margin read Special off-page read of the CMF array where the CMF EEPROM hardware adjusts the reference of the sense amplifier to check for correct program operation. All CMF array off-page read accesses between the first programming write and clearing the SES bit are program margin reads. Program page buffer 64 bytes of information used to program the CMF array. This information is aligned to a 64-byte boundary within the CMF array block. Each CMF module has one program page buffer for each array block. Read page buffer 32-byte block of information that is read from the CMF array. This information is aligned to a 32-byte boundary within the CMF array. Each CMF module has two read page buffers. Shadow information An extra row (256 bytes) of the CMF array used to provide reset configuration information. This row may be accessed by setting the SIE bit in the module configuration register and accessing the CMF array. The shadow information is always in the lowest array block of the CMF array.
MPC555
/ MPC556
MOTOROLA 19-3
USERS MANUAL

19.2 Programming Model The CMF EEPROM Module consists of two addressed sections. The first is the 32byte control registers used to configure, program, erase and test the CMF EEPROM array while, the second is the array. Figure 19-1 shows the part of the MPC555 / MPC556 memory map involving the CMF arrays and control registers. Refer to 1.3 MPC555 / MPC556 Address Map for the complete memory map.
0x00 0000 CMF Flash 448 Kbytes 0x2F C000 USIU Control Registers 1 Kbyte 0x2F C800 0x2F C840 0x2F C880 Reserved for SIU 0x 2F BFFF 0x 2F C000 0x 2F FFFF U SI U & F lash Control 16 Kbytes
0x06 FFFF
0x08 0000
FLASH Module A (64 bytes) Reserved for Flash (2.6 Mbytes 16 Kbytes) FLASH Module B (64 bytes)
Figure 19-1 CMF Array and Control Register Addressing 19.2.1 CMF EEPROM Control Registers The control registers are used to control CMF EEPROM module operation. They reside in supervisor data space. On master reset the registers are loaded with default reset information. Some of the registers are special CMF NVM registers which retain their state when power is removed from the CMF EEPROM. These special FLASH NVM registers are identified in the individual register field and control bit descriptions. The CMF EEPROM control registers are accessible for read or write operation at all times while the device is powered up except during master reset, soft reset or erase interlock write. The access time of a CMF register is one system clock for both read and write accesses. Accesses to reserved registers will cause the BIU to generate a data error exception.
MPC555
/ MPC556
MOTOROLA 19-4
USERS MANUAL

Table 19-1 is a programming model for each set of CMF EEPROM control registers. The address offset is from the start of the control register block for each CMF module. (See Figure 19-1.) Table 19-1 CMF Register Programmers Model
MSB 0 LSB 31
Address 0x2F C800 0x2F C840 0x2F C804 0x2F C844
Register
Control Registers (Located in Supervisor Data Space) CMF Module Configuration Register (CMFMCR) See Table 19-2 for bit descriptions. CMF EEPROM Test Register (CMFTST) See Table 19-3 for bit descriptions. High Voltage Control Register (CMFCTL) See Table 19-6 for bit descriptions. Reserved CMF Flash Array 0x00 0000 0x03 FFFF 0x04 0000 0x06 FFFF CMF_A RAM Array CMF_B RAM Array
0x2F C808 0x2F C848 0x2F C80C 0x2F C81C 0x2F C84C 0x2F C85C
19.2.1.1 CMF EEPROM Configuration Register (CMFMCR) The CMF EEPROM module configuration register is used to control the operation of the CMF EEPROM array and BIU. Two bits (the Censor bits) of the CMFMCR bits are special FLASH NVM registers. The factory default state of the Censor bits is either 0b01 or 0b10. CMFMCR CMF EEPROM Configuration Register
MSB 0 LOCK 1 0 2 0 3 FIC 4 SIE 5 ACCESS 6 7 8 9 10 11 12
0x2F C800 0x2F C840

13 14 15
CENSOR1
SUPV[0:7]
RESET: 1 0 0 0 0 0 1 1 1 1 1 1 1 1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
DATA[0:7] RESET: 0 0 0 0 0 0 0 0 1 1 1
PROTECT[0:7]
1. The reset state of bits 6:7 are defined by special FLASH NVM registers. The factory default state is either 0b01 or 0b10.
MPC555
/ MPC556
MOTOROLA 19-5
USERS MANUAL

Table 19-2 CMFMCR Bit Descriptions
Bit(s) Name Description Lock control. When the LOCK control bit is cleared, the following bits are locked: FIC, SUPV[0:7], DATA[0:7] and PROTECT[0:7]. Writes to these bits will have no effect. 0 LOCK In normal operation, once the LOCK bit is cleared, the write-lock can only be disabled again by a master reset. The LOCK bit is writable if the device is in background debug mode and CSC = 0. 0 = Write-locked registers are protected 1 = Write-lock is disabled (reset state) Warning: If the lock protection mechanism is enabled (LOCK = 0) before the PROTECT[0:7] bits are cleared, the device must use background debug mode to program or erase the CMF array. 1:2 Reserved Force information censorship for access development. Refer to 19.8 Censored and Non-Censored Accesses for details. 3 FIC
The FIC bit is write protected by the LOCK. If FIC = 1 it cannot be cleared except by a hard reset. 0 = Normal CMF censorship operation 1 = Forces the CMF into information censorship mode, unless ACCESS = 1 Shadow information enable. Refer to 19.3 Shadow Information for details. The SIE bit is write protected by the SES bit for programming operation. Writes have no effect if (SES = 1 and PE = 0). The SIE bit can be read whenever the registers are enabled. 0 = Normal array access 1 = Disables normal array access and selects the shadow information Enable uncensored access. Refer to 19.8 Censored and Non-Censored Accesses for details. Writes to this bit have no effect when CSC = 1. This bit can be set only when the MCU is in uncensored mode. 0 = Censored CMF array access allowed only if the CMF censorship is no censorship, (FIC = 0 and CENSOR[0] CENSOR[1]) 1 = Allows all CMF array access. Censor accesses. The value of these bits is determined by the state of two NVM bits in two special NVM fuses. Refer to 19.8 Censored and Non-Censored Accesses for details.
SIE
ACCESS
6:7
The default reset state of CENSOR is user defined by the FLASH NVM register bits. 00 = Cleared censorship, CMF array access allowed only if device is in uncensored mode or CENSOR ACCESS = 1 01 = No censorship, All CMF array accesses allowed 10 = No censorship, All CMF array accesses allowed 11 = Information censorship, CMF array access allowed only if device is in uncensored mode or ACCESS = 1 Supervisor space. Each array block can be mapped into supervisor or unrestricted address space. When an array block is mapped into supervisor address space, only supervisor accesses are allowed. A user access to a location in supervisor address space will result in a data error exception. When an array block is mapped into unrestricted address space, both supervisor and SUPV[0:7] user accesses are allowed. The SUPV[0:7] bits are write protected by the LOCK and CSC bits. Writes will have no effect if LOCK=0 or CSC=1. 0 = Array block M is placed in unrestricted address space 1 = Array block M is placed in supervisor address space (reset value)
8:15
MPC555
/ MPC556
MOTOROLA 19-6
USERS MANUAL

Table 19-2 CMFMCR Bit Descriptions (Continued)
Bit(s) Name Description Data space. Each array block can be mapped into data or both data and Instruction address space. When an array block is mapped into data address space (DATA[M] = 1) only data accesses are allowed. An instruction access to a location in data address space will result in a data error exception. When an array block is mapped into both data and instruction address space DATA[0:7] (DATA[M] = 0), both data and instruction accesses are allowed. The DATA[0:7] bits are write protected by the LOCK and CSC bits. Writes have no effect if LOCK = 0 or CSC = 1. 0 = Array block M is placed in both data and instruction address spaces (reset value) 1 = Array block M is placed in data address space Block protect. Each array block of the CMF EEPROM can be protected from program and erase operation by setting PROTECT[M] = 1. The CMF BIU will perform all programming and erase interlocks except the program and erase voltages will not be applied to MoneT locations within the protected array block(s).
16:23
24:31
PROTECT Writes to PROTECT[0:7] have no effect if LOCK = 0 or CSC = 1 or SES = 1. [0:7] 0 = Array block M is unprotected 1 = Array block M is protected (default value) Warning: If a CMF EEPROM enables the lock protection mechanism (LOCK = 0) before PROTECT is cleared, the device must use background debug mode to program or erase the CMF EEPROM.
19.2.1.2 CMF EEPROM Test Register (CMFTST) The CMF EEPROM test register (CMFTST) is used to control the test operation of the CMF array. Only six bits [20:23, 25:26] are readable or writeable in normal operation. CMFTST CMF EEPROM Test Register
MSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13
0x2F C804 0x2F C844

14 15
RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LSB 31
NVR1
PAWS
RESERVE STE1,2 D
GDB1
RESERVED
NOTES: 1. The NVR, STE, and GDB bits are not accessible in all revisions of the MPC555 / MPC556 (2K02A mask sets and earlier). 2. The STE bit should always be programmed as a 0.
MPC555
/ MPC556
MOTOROLA 19-7
USERS MANUAL

Table 19-3 CMFTST Bit Descriptions
Bit(s) 0:19 Name Reserved Negative voltage range. This bit switches between the low and high voltage range of the negative charge pump in programming and erasing the CMF Flash module when GDB = 0b1. This bit is writeable when HVS = 0b0. 0 = High Range (more negative) 1 = Low Range Program amplitude/width modulation select. The PAWS bits, in conjunction with the NVR and GDB bits can be used to select the programming voltage applied to the drain or gate of the EEPROM bitcell. These bits should be left set to 0b000, unless advised by Motorola. For information about PAWS programming modes, see Table 19-4 and Table 19-5. Reserved This bit is reserved for Motorola factory testing and should always be programmed to 0b0. 0 = Normal Operation 1 = Factory test mode use only. This setting could disturb contents of flash. Gate/drain bias select. This bit works in conjunction with the PAWS bits to select between positive and negative ramped voltages for programing and erasing. This bit is writeable when SES = 0b0. 0 = Positive voltage ramp selected on the bitcell drain. 1 = Negative voltage ramp selected on the bitcell gate. Reserved Description
20
NVR
21:23
PAWS [0:2] STE
24
25
26
GDB
27:31
Table 19-4 CMF Programming Algorithm (v6 and Later)

No. of Pulses 4 4 4 4 20 20 20 max. 48,000 Pulse Width 256 s 256 s 256 s 256 s 50 s 50 s 50 s 50 s NVR 1 1 1 1 0 0 0 0 PAWs 100 101 110 111 100 101 110 111 GDB 1 1 1 1 1 1 1 1 PAWs Mode Mode 4NL Mode 5NL Mode 6NL Mode 7NL Mode 4NL Mode 5NL Mode 6NL Mode 7NL Negative gate ramp (high range) Negative gate ramp (low range) Description
MPC555
/ MPC556
MOTOROLA 19-8
USERS MANUAL

Table 19-5 CMF Erase Algorithm (v6)
No. of Pulses 1 1 1 1 1 1 1 20 Pulse Width 100 ms1 100 ms1 100 ms1 100 ms1 100 ms1 100 ms1 100 ms1 100 ms2 NVR 1 1 1 1 0 0 0 0 PAWs 100 101 110 111 100 101 110 111 GDB 1 1 1 1 1 1 1 1 PAWs Mode Mode 4NL Mode 5NL Negative gate ramp (low range) Mode 6NL Mode 7NL Mode 4NL Mode 5NL Negative gate ramp (high range) Mode 6NL Mode 7NL Description
NOTES: 1. No margin read after pulse. 2. Do margin read after each pulse.
19.2.1.3 CMF EEPROM High Voltage Control Register (CMFCTL) The CMF EEPROM high voltage control register is used to control the program and erase operations of the CMF EEPROM module and setting and clearing CENSOR[0:1] fuses. Refer to 19.7 Voltage Control for Programming and Erasing for more information on this register. CMFCTL CMF EEPROM High Voltage Control Register
MSB 0 HVS 1 0 2 3 SCLKR 4 5 0 6 7 8 0 9 10 11 12 CLKPM 13
0x2F C808 0x2F C848

14 15
CLKPE
PORESET/HRESET: 0 SRESET: U U U U U U U U U U U U U U U U 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20
21
22
23
24 0
25 CSC
26 EPEE
27 0
28 0
29 PE
30 SES
LSB 31 EHV
BLOCK[0:7] PORESET/HRESET: 0 SRESET: U U U U U U U U 0 0 0 0 0 0 0
MPC555
/ MPC556
MOTOROLA 19-9
USERS MANUAL

Table 19-6 CMFCTL Bit Descriptions
Bit(s) Name Description High voltage status. During a program or erase pulse this bit is set while the pulse is active or during recovery. The BIU does not acknowledge an access to an array location if HVS = 1. While HVS = 1, SES cannot be changed. This bit is read only; writes have no effect. 0 = Program or erase pulse is not applied to the CMF array or shadow information 1 = Program or erase pulse is applied to the CMF array or shadow information Reserved System clock range. These bits are write protected by the SES bit. Writes to CMFCTL do not change SCLKR[0:2] if SES = 1. The default reset state of SCLKR[0:2] = 000 for a clock scaling of 1. 000 = Clock scaling of 1 (Not for Customer use.) 001 = Clock scaling of 1 010 = Clock scaling of 3/2 011 = Clock scaling of 2 100 = Clock scaling of 3 101 = Clock scaling of 4 110 = Reserved 111 = Reserved Refer to 19.7.3 System Clock Scaling for instructions on selecting a clock scaling factor. 5 Reserved Clock period exponent. The CLKPE, CSC, and PE fields determine the value of the exponential clock multiplier, N. Refer to 19.7.4 Exponential Clock Multiplier for details. The CLKPE bits are write protected by the SES bit. Writes to CMFCTL will not change CLKPE if SES = 1.The default reset state of CLKPE is 00. Reserved Clock period multiple. This field determines the linear clock multiplier, M, according to the following equation: M = 1 + CLKPM[0:6] The CLKPM bits are write protected by the SES bit. Writes to CMFCTL will not change CLKPM if SES = 1. The reset state of CLKPM = 0, for a multiplier of 1. Refer to 19.7.5 Linear Clock Multiplier for more information. Block program and erase select. The CMF EEPROM array blocks that are selected to be programmed or erased are the blocks for which BLOCK[M] = 1. Bit 16 controls block 0 and bit 23 controls block 7. On the 192-Kbyte array (Flash Module B), blocks 6 and 7 are not available, but these bits need to be set when doing a clear censor operation. 16:23 BLOCK [0:7] Warning: The block bit must be set only for the blocks currently being programed. If the block bits are set for blocks that are not being programmed, the contents of the other blocks could be disturbed. The BLOCK[0:7] bits are write protected by the SES bit. Writes to CMFCTL will not change BLOCK[0:7] if SES = 1. BLOCK[0:7] default reset state is 0x00, not selected for program or erase. 0 = Array block M is not selected for program or erase 1 = Array block M is selected for program or erase 24 Reserved Censor set or clear. CSC configures the CMF EEPROM for setting or clearing the CENSOR bits. If CSC=1 then CENSOR is configured for setting if PE = 0 or clearing if PE = 1. For more information on setting or clearing the CENSOR bits see section 19.8.4 Setting and Clearing Censor. The CSC bit is write protected by the SES bit. Writes to CMFCTL will not change CSC if SES = 1. 0 = Configure for normal operation (default value) 1 = Configure to set or clear the CENSOR bits
HVS
2:4
SCLKR
6:7
CLKPE
9:15
CLKPM
25
CSC
MPC555
/ MPC556
MOTOROLA 19-10
USERS MANUAL

Table 19-6 CMFCTL Bit Descriptions (Continued)
Bit(s) Name Description EPEE pin status bit. The EPEE bit monitors the state of the external program/erase enable (EPEE) pin. EPEE has a digital filter that requires two consecutive samples to be equal before the output of the filter changes. The CMF samples EPEE when EHV is asserted and holds the EPEE state until EHV is negated. EPEE is a read-only bit; writes have no effect. 0 = High voltage operations are not possible 1 = High voltage operations are possible Refer to 19.9.1 EPEE Signal for more information. 27:28 Reserved Program or erase select. PE configures the CMF EEPROM for programming or erasing. When PE = 0, the array is configured for programming and if SES = 1 the SIE bit will be write locked. When PE = 1, the array is configured for erasing and SES will not write lock the SIE bit. The PE bit is write protected by the SES bit. Writes to CMFCTL will not change PE if SES = 1. 0 = Configure for program operation (default value) 1 = Configure for erase operation Start-end program or erase sequence. The SES bit is write protected by the HVS and EHV bits, unless the PAW bits are set to 0b1xx. Writes to CMFCTL will not change SES if HVS = 1 or EHV = 1. Refer to 19.7.7 Starting and Ending a Program or Erase Sequence for more information. 0 = CMF EEPROM not configured for program or erase operation 1 = Configure CMF EEPROM for program or erase operation Enable high voltage. EHV can be asserted only after the SES bit has been asserted and a valid programming write(s) or erase hardware interlock write has occurred. If an attempt is made to assert EHV when SES is negated, or if a valid programming write(s) or erase hardware interlock write has not occurred since SES was asserted, EHV will remain negated. 0 = Program or erase pulse disabled 1 = Program or erase pulse enabled
26
EPEE
29
PE
30
SES
31
EHV
19.2.2 CMF EEPROM Array Addressing The CMF EEPROM array is addressed when an internal access has been initialized and ADDR[10:13] matches the array hardware mapping address. The CMF array location selected is determined by ADDR[14:29] and the bytes are selected by ADDR[30:31] and internal SIZE[0:1] information. Table 19-6 and Table 19-7 show the internal mapping of the flash array. Information in the array is accessed in 32-byte pages. For each CMF module, two read page buffers are assigned to the low order addresses (ADDR[27:31]). The first page buffer is assigned to blocks zero to three; the second to blocks four to seven (for CMF Module A) or four to five (for CMF Module B). Access time for data in the read page buffers is one system clock; access time for an off-page read is two system clocks. To prevent the BIU from accessing an unnecessary page from the array, the CMF EEPROM monitors the U-bus address to determine whether the required information is within one of the two read page buffers and the access is valid for the module. This strategy allows the CMF EEPROM to have a twoclock read for an off-page access and one clock for an on-page access. The BIU does not recognize write accesses to the CMF array.
MPC555
/ MPC556
MOTOROLA 19-11
USERS MANUAL

Table 19-7 EEPROM Array Addressing
0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1
0000000
USIU Internal Mapping
Array Hardware Mapping
Block Address
Row Address
Column Address
Byte Addr
Table 19-8 CMF EEPROM Array Address Fields

Bit(s) 0:6 7:9 Field USIU Internal Mapping Description The seven high-order address bits of a CMF EEPROM array access (or any MPC555 / MPC556 internal access) must equal zero. These bits (programmed in the USIU internal memory map register) specify one of eight locations for the MPC555 / MPC556 internal memory map.
10:13
These bits determine the location of each array within the MPC555 / MPC556 internal Array Hardware memory map. Values are as follows: Mapping Flash module A = 0000 Flash Module B = 0001 Block Address Row Address These three bits specify one of eight 32-Kbyte blocks within CMF Module A (000 to 111), or one of six 32-Kbyte blocks within CMF Module B (000 to 101) These seven bits select one of 128 rows within the 32-Kbyte block.
14:16 17:23
24:29
These six bits select one of 64 (word-length) columns within the row. Note also the following: Column Address ADDR[24:26] select a 32-byte read page. ADDR[27:29] represent the read page word address. ADDR[24:25] select a 64-byte program page. ADDR[26:29] represent the program page word address. Byte Address Bits 30:31 select a byte within the column.
30:31
19.2.2.1 Read Page Buffers Each CMF array has two 32-byte read page buffers. The fully independent buffers are located in two separate read sections of the array. Each page buffer status and address are monitored in the BIU. The status of the read page buffers is made invalid by any of the following operations: Reset Programming write Erase interlock write Setting EHV Clearing SES Setting or clearing SIE Each access to the CMF EEPROM array determines whether the requested location is within the current pages. If the requested location is not within the read page buffers, the correct read page buffer is made invalid, and a new page of information is fetched from the array. The page buffer address is updated and status is made valid. If the requested location is within one of the current page buffers or has been fetched from the array, the selected bytes are transferred to the U-bus, completing the access. CMF EEPROM array accesses that make the page buffer(s) invalid (off-page reads) require two system clocks. CMF EEPROM array accesses that do not make the page buffer(s) / MPC556
MPC555
MOTOROLA 19-12
USERS MANUAL

invalid (on-page reads) require one system clock. Read buffer management is transparent to user software and is taken care of in hardware. 19.2.2.2 Program Page Buffers The CMF EEPROM modules A and B can program up to eight and six 64-byte pages at one time, respectively. Each program page buffer is located in one program section. All program page buffers within a CMF module share the same block offset address. The block offset address is extracted from the address of the first programming write. To select the CMF EEPROM array block that will be programmed, the program page buffers use the CMF EEPROM array configuration and BLOCK[0:7]. The array block that will be programmed is selected by the BLOCK bit that is set. If BLOCK[M] = 1 then program buffer[M] is active and array block[M] is selected for programming. Bits in the program page buffers select the non-program state if SES = 0. During a program margin read, the program buffers update bits to the non-program state for bits that correspond to array bits that the program margin read has determined are programmed.
MPC555
/ MPC556
MOTOROLA 19-13
USERS MANUAL

19.2.2.3 Array Configuration for CMF Module A
64-byte Program Page Buffer 7 3-2Kbyte Array Block 7 0x3 8000 0x3 FFFF
64-byte Program Page Buffer 6 32-Kbyte Array Block 6 0x3 0000 0x3 7FFF
32-byte Read Page Buffer 1 32-Kbyte Array Block 5 0x2 8000 0x2 FFFF
64-byte Program Page Buffer 4 64-byte Program Page Buffer 3 32-Kbyte Array Block 3 0x1 8000 0x1 FFFF
32-byte Read Page Buffer 0 32-Kbyte Array Block 1 0x0 8000 0x0 FFFF
64-byte Program Page Buffer 1 32-Kbyte Array Block 0 and Shadow Information 0x0 0000 0x0 7FFF1
64-byte Program Page Buffer 0 Bus Interface Unit (BIU)
1.If SIE=1, then the shadow row is enabled instead of the flash block. Shadow locations 0x00 to 0x03 are reserved for the Internal Flash Reset Configuration word. Shadow locations 0x04 to 0x0F are Reserved by Motorola for possible future use.
MPC555
/ MPC556
MOTOROLA 19-14
USERS MANUAL

19.2.2.4 Array Configuration for CMF Module B
64-byte Program Page Buffer 5 32-Kbyte Array Block 5 0x6 8000 0x6 FFFF
32-byte Read Page Buffer 1 32-Kbyte Array Block 4 0x6 0000 0x6 7FFF
64-byte Program Page Buffer 4 64-byte Program Page Buffer 3 32-Kbyte Array Block 3 0x5 8000 0x5 FFFF
64-byte Program Page Buffer 2
32-Kbyte Array Block 2 0x5 0000 0x5 7FFF 32-byte Read Page Buffer 0 32-Kbyte Array Block 1 0x4 8000 0x4 FFFF
64-byte Program Page Buffer 1 32-Kbyte Array Block 0 and Shadow Information 0x4 0000 0x4 7FFF1
64-byte Program Page Buffer 0 Bus Interface Unit (BIU) 1. If SIE=1, then the shadow row is enabled instead of the flash block. Locations 0x4 00000 to 0x4 000F of the shadow row are Reserved by Motorola for possible future use.
19.3 Shadow Information Programming the shadow information uses the same procedure as programming the array, except that there are only 256 bytes available in the shadow row. Before starting the program sequence SIE must equal one. The SIE bit is write protected by the SES bit for programming operation. Writes will have no effect if (SES = 1 and PE = 0). The SIE bit can be read whenever the registers are enabled. When SIE = 1, normal array accesses are disabled and the shadow information is enabled. When an array location is read using supervisor data in this mode, the shadow information is read from a location determined by the column, 32-byte read page select and read page word addresses (ADDR[24:29]) of the access. Accessing the CMF control block registers accesses the registers and not the shadow information. The read page buffer address monitor is reset whenever SIE is modified, making the next CMF array access an off-page access. The default reset state of SIE is normal array access (SIE = 0).
MPC555
/ MPC556
MOTOROLA 19-15
USERS MANUAL

NOTE When SIE = 1, only program page buffer zero can be programmed. All programming writes to the CMF will be directed to program page buffer 0 if SIE = 1. In addition, the other program page buffers cannot be accessed and will not apply any programming voltages to their CMF array blocks while programming the shadow information. 19.3.1 Address Range of Shadow Information The address range of the shadow information is the entire address range of the CMF EEPROM array but the high order array addresses, ADDR[14:23], are not used to encode the location. The first 16 bytes (ADDR[24:29] = 0x00 to 0x0F) of the 256 bytes of shadow locations are withheld by Motorola for the reset configuration word and future applications. The remaining 240 bytes are available as supervisor data. This is shown in Figure 19-2.
0x00 0x03 0x04 0x0F 0x10
Reset Configuration Word Reserved for Future Applications
General-Use MoneT Shadow Information

0xFF
Figure 19-2 Shadow Information 19.3.2 Reset Configuration Word (CMFCFIG) The CMF EEPROM reset configuration word is implemented in the first word (ADDR[24:29] = 0x00) of the special shadow locations. The reset configuration word along with the rest of the shadow information words is located in supervisor data address space. The purpose of the reset configuration word is to provide the system with an alternative internal source for the reset configuration. Note that with the exception of bit 20, the bits in the CMFCFIG are identical to those in the USIU hard reset configuration word. Refer to 7.5.2 Hard Reset Configuration Word for descriptions of these bits.
MPC555
/ MPC556
MOTOROLA 19-16
USERS MANUAL

CMFCFIG Hard Reset Configuration Word
MSB 0 EARB 1 IP 2 BDRV 3 BDIS 4 BPS 5 6 7 RESERVED 8 9 10 DBGC 11 12 13 14 15 Reserved
DBPC ATWC
EBDF
LSB 16 PRPM 17 SC 18 19 ETRE 20 FLEN 21

EN_ COMP
22
EXC_ COMP
23
24
25 Reserved
26
27
28
29 ISB
30
31 DME
During reset the HC bit (has configuration, bit 20) and the USIU configure the CMF EEPROM module to provide CMFCFIG. If HC = 0 and the USIU requests internal configuration during reset the reset configuration word will be provided by CMFCFIG. The default reset state of the CMFCFIG after an erase operation of the CMF module A block 0 is no configuration word available (HC = 1). 19.4 Array Read Operation The CMF EEPROM array is available for read operation under most conditions while the device is powered up. Reads of the array are not allowed under any of the following conditions: During master or soft reset ACCESS = 0 and CENSOR[0:1] = 11 or 00 While the CMF EEPROM is disabled During programming and erase operations, while the high voltage is applied to the array, the BIU does not acknowledge a CMF array read. At certain points, as defined in the program or erase sequence, reading the array results in a margin read. These margin reads return the status of the program or erase operation and not the data in the array. The type of CMF EEPROM array read is determined by comparing the address of the requested information with the address of the read page buffers. If the requested address is not within one of the read page buffers or if the read page buffer has been made invalid, an off-page read results. This read updates the read page buffer address of the selected array block, copies the information from the array into the read page buffer, and drives a word onto the data bus. The off-page read requires a minimum of two clocks, while margin off-page reads require additional clocks. If the address of the requested information is within the address ranges of either of the read page buffers, an on-page read is performed. This requires one clock to transfer information from the read page buffer onto the data bus. See section 19.2.2 CMF EEPROM Array Addressing for more information on array accesses.
MPC555
/ MPC556
MOTOROLA 19-17
USERS MANUAL

19.5 Programming the CMF Array To modify the charge stored in the isolated element of the CMF bit from a logic one state to a logic zero state, a programming operation is required. This programming operation applies the required voltages to change the charge state of the selected bits without changing the logic state of any other bits in the CMF array. The program operation cannot change the logic zero state to a logic one state; this must be done by the erase operation. Programming uses a set of program buffers of 64 bytes each to store the required data, an address offset buffer to store the starting address of the block(s) to be programmed and a block select buffer that stores information on which block(s) are to be programmed. Any number of the array blocks may be programmed at one time. WARNING Do not program any page more than once after a successful erase operation. While this will not physically damage the array it will cause an increased partial disturb time for the unselected bits on the row and columns that are not programmed. If this happens, a full erase of all blocks being programmed must be done before the CMF EEPROM can be used reliably. If block M of the CMF EEPROM is protected (PROTECT[M] = 1), it will not be programmed. Also, if EPEE = 0, no programming voltages will be applied to the array. Software should verify the state of EPEE prior to programming (programming will fail if EPEE = 0). The user should also insure that the programming voltage (5.0 0.25 volts) is applied to VPP. 19.5.1 Program Sequence The CMF EEPROM module requires a sequence of writes to the high voltage control register (CMFCTL) and to the programming page buffer(s) in order to enable the high voltage to the array or shadow information for program operation. See Table 19-4 for the programming algorithm bit settings. The required program sequence follows. 1. Write PROTECT[0:7] to disable protection on blocks to be programmed. 2. Write PAWS to 0b100, write NVR = 1, write GDB = 1. 3. Using 19.7.6 A Technique to Determine SCLKR, CLKPE, and CLKPM, program the following fields: Pulse width timing control fields for a program pulse BLOCK[0:7] to select the array blocks to be programmed PE = 0 in the CMFCTL register 4. Write SES = 1 in the CMFCTL register. NOTE Step 4 can be accomplished with the same write as that in step 3. It is listed as a separate step in the sequence for looping.
MPC555
/ MPC556
MOTOROLA 19-18
USERS MANUAL

5. Write to the 64-byte array locations to be programmed. This updates the programming page buffer(s) with the information to be programmed. The last write to a word within the program page buffer will be saved for programming. All accesses of the array after the first write are to the same block offset address (ADDR[17:25]) regardless of the address provided. Thus the locations accessed after the first programming write are limited to the page locations to be programmed. Off-page read accesses of the CMF array after the first programming write are program margin reads. (See section 19.5.2 Program Margin Reads.) To select the CMF EEPROM array block(s) to be programmed, the program page buffers use the CMF EEPROM array configuration and BLOCK[0:7]. Subsequent writes fill in the programming page buffers using the block address to select the program page buffer and the page word address (ADDR[26:29]) to select the word in the page buffer. 6. Write EHV = 1 in the CMFCTL register. NOTE If a program buffer word has not received a programming write no programming voltages will be applied to the drain of the corresponding word in the array. Also, at this point writes to the program page buffers are disabled until SES has been cleared and set. 7. Read the CMFCTL register until HVS = 0. 8. Write EHV = 0. 9. To verify the programming, read the words of the pages that are being programmed. These are program margin reads. (See 19.5.2 Program Margin Reads.) If any bit is a 1 after reading all of the locations that are being programmed, then another pulse needs to be applied to the these locations. If all the locations verify as programmed go to step 11. WARNING After a program pulse, read at least one location with ADDR[26] = 0 and one location with ADDR[26] = 1 on each programmed page. Failure to do so may result in the loss of information in the CMF EEPROM array. While this will not physically damage the array a full erase of all blocks being programmed must be done before the CMF EEPROM can be used reliably. For more information see 19.5.3 Over-Programming. To reduce the time for verification, read two locations in each program page that is being programmed after reading a non-programmed bit. The first location must be a location with ADDR[26] = 0, while the second must use ADDR[26] = 1. In addition, after a location has been fully verified (all bits are programmed) it is not necessary to verify the location again, since no further programming voltages will be applied to the drain of the corresponding bits. This will reduce the time required to program the array.
MPC555
/ MPC556
MOTOROLA 19-19
USERS MANUAL

10. If the margin read is successful, then write SES = 0 in the CMFCTL register, otherwise do the following: a. Write new pulse width parameters (if required per Table 19-4) - SCLKR, CLKPE, CLKPM. b. Write new values for PAWS, NVR, and GDB (if required per Table 19-4). c. Go back to step 6 to apply additional programming pulses. 11. If more information needs to be programmed, go back to step 2.
T3
S2
S3
T1 Reset S1
T2 T6 S4
T4
T7 T8 T9 S5 T5
Figure 19-3 Program State Diagram
MPC555
/ MPC556
MOTOROLA 19-20
USERS MANUAL

Table 19-9 Program Interlock State Descriptions
State Normal Operation: S1 Normal array reads and register accesses. The block protect information and pulse width timing control can be modified. S2 T2 Write PE = 0, SES = 1 Mode Next State Transition Requirement
S1
T1
Write SES = 0 or a master reset Hardware Interlock A successful write to any CMF array location. This programming write latches the selected word of data into the programming page buffer and the address is latched to select the location to be programmed. Once a bit has been written then it will remain in the program buffer until another write to the word or a write of SES = 0 or a program margin read determines that the state of the bit needs no further modification by the program operation. If the write is to a register no data will be stored in the program page buffers and the CMF will remain in state S2. Write SES = 0 or a master reset
First Program Hardware Interlock Write:
S2
Normal read operation still occurs. The array will accept programming writes. Accesses to the registers are normal register accesses. A write to CMFCTL can not change EHV at this time. If the write is to a register, no data is stored in the program page buffers, and the CMF remains in state S2.
S3
T3
Expanded Program Hardware Interlock Operation: Program margin reads will occur. Programming writes are accepted so that all program pages may be programmed. These writes may be to any CMF array location. The program page buffers will be updated using only the data, the lower address (ADDR[26:29]) and the block address. Accesses to the registers are normal register accesses. A write to CMFCTL can change EHV. If the write is to a register, no data is stored in the program page buffer. Program Operation: High voltage is applied to the array or shadow information to program the CMF bit cells. The pulse width timer is active if SCLKR[0:2] 0 and HVS can be polled to time the program pulse. No further programming writes are accepted. During programming the array does not respond to any access. Accesses to the registers are allowed. A write to CMFCTL can change EHV only.
S1
T6
S3
S4
T4
Write EHV = 1
S1
T7
Master reset
S4
S5
T5
Write EHV = 0, disable the internal memory map or a soft reset.
MPC555
/ MPC556
MOTOROLA 19-21
USERS MANUAL

Table 19-9 Program Interlock State Descriptions (Continued)
State Mode Program Margin Read Operation: These reads determines if the state of the bits on the selected page needs further modification by the program operation. Once a bit is fully programmed, the data stored in the program page is updated. No further programming occurs for that bit, and the value read is a 0. While it is not necessary to read all words on a page to determine if another program pulse needs to be applied, all pages being programmed must be read once after each program pulse. Next State S4 T8 Transition Requirement Write EHV = 1
S5
S1
T9
Write SES = 0 or a master reset.
19.5.2 Program Margin Reads The CMF EEPROM provides a program margin read with electrical margin for the program state. Program margin reads provide sufficient margin to assure specified data retention. The program margin read is enabled when SES = 1 and a programming write has occurred. To increase the access time of the program margin read, the offpage access time is four clocks instead of the usual two-clock off-page read access time. The program margin read and subsequent on-page program verify reads return a one for any bit that has not been completely programmed. Bits that the programming write left in the non-programmed state return zero when read. Bits that have completed programming return zero when read and update the data in the programming page buffer so that no further programming of those bits will occur. The program margin read occurs during the off-page read. A program margin read must be performed for all pages that are being programmed after each program pulse. Table 19-10 Results of Programming Margin Read
Current Data in the Program Page Buffer1 0 0 1 1 Current State of Bit Programmed (0) Erased (1) Programmed (0) Erased (1) Data Read During Margin Read2 0 1 0 0 New Data for the Program Page Buffer1 1 0 1 1
NOTES: 1. 0 = bit needs further programming 1 = bit does not need further programming 2. A 0 read during the margin read means that the bit does NOT need further programming. A 1 means the bit needs to be programmed further.
MPC555
/ MPC556
MOTOROLA 19-22
USERS MANUAL

CAUTION Failure to read each page that is being programmed after each program pulse may result in the loss of information in the CMF EEPROM array. While this will not physically damage the array a full erase of all blocks being programmed must be performed before the CMF EEPROM can be used reliably. For more information, see 19.5.3 OverProgramming. 19.5.3 Over-Programming Either of the following events results in an over-programmed state: Programming a CMF bit without a program margin read after each program pulse Exceeding the specified program times or voltages Once a CMF bit has been over-programmed, data in the array block (32 Kbytes) that is located in the same column is lost, since the over-programmed bit causes the entire column to appear programmed. To restore an array block with an over-programmed bit, the block must be erased. 19.6 Erasing CMF Array Blocks To modify the charge stored in the isolated element of the CMF bit from a logic zero state to a logic one state, an erase operation is required. The erase operation cannot change the logic one state to a logic zero state; this is accomplished by the program operation. In the CMF EEPROM, erase is a bulk operation that affects the stored charge of all the isolated elements in an array block. To make the CMF module block-erasable, the array is divided into blocks that are physically isolated from each other. Each of the array blocks may be erased in isolation or in any combination. The CMF array block size is fixed for all blocks in the module at 32 Kbytes. CMF module A consists of eight array blocks; CMF module B consists of six blocks. Array blocks of the CMF EEPROM that are protected (PROTECT[M] = 1) are not erased. In addition, if EPEE = 0 no erase voltages are applied to the array. The array blocks selected for erase operation are determined by BLOCK[0:7] and the array configuration. 19.6.1 Erase Sequence The CMF EEPROM module requires a sequence of writes to the high voltage control register (CMFCTL) and an erase interlock write in order to enable the high voltage to the array and shadow information for erase operation. See Table 19-5 for erase algorithm bit settings.The erase sequence follows. 1. Write PROTECT[0:7] to disable protect for the blocks to be erased. 2. Write PAWS to 0b100, NVR to 1, and GDB to 1. 3. Using 19.7.6 A Technique to Determine SCLKR, CLKPE, and CLKPM, write the pulse width timing control fields for an erase pulse, BLOCK[0:7] to select the blocks to be erased, PE = 1 and SES = 1 in the CMFCTL register. Set the initial
MPC555
/ MPC556
MOTOROLA 19-23
USERS MANUAL

pulse width bit settings per Table 19-5. Execute an erase interlock write to any CMF array location. Write EHV = 1 in the CMFCTL register. Read the CMFCTL register until HVS = 0. Write EHV = 0 in the CMFCTL register. To verify the erase operation, read all locations that are being erased, including the shadow information if the block containing it is erased. Off-page reads are erase margin reads that update the read page buffer. (See section 19.6.2 Erase Margin Reads.) If all the locations read as erased, go to step 9. NOTE Do not perform erase margin reads until reaching the condition PAWS=0b111, NVR=0 and GDB=1.
4. 5. 6. 7. 8.
9. To reduce the time used for erase margin reads, upon the first read of a zero, do the following: a. Write new pulse width parameters, SCLKR, CLKPE, and CLKPM (if required per Table 19-5). b. Write new PAWS value (if required per Table 19-5). c. Write new values for NVR and GDB (if required per Table 19-5). d. Go back to step 5 to apply additional erase pulses. NOTE After a location has been verified (all bits erased), it is not necessary to verify the location after subsequent erase pulses. 10. Write SES = 0 in the CMFCTL register.
MPC555
/ MPC556
MOTOROLA 19-24
USERS MANUAL
T3 S2 S3
T1 Reset S1
T2 T6 S4
T4
T7 T8 T5 S5
T9
Figure 19-4 Erase State Diagram
MPC555
/ MPC556
MOTOROLA 19-25
USERS MANUAL

Table 19-11 Erase Interlock State Descriptions
State Normal Operation: S1 Normal array reads and register accesses. The Block protect information and pulse width timing control can be modified. Erase Hardware Interlock Write: Normal read operation still occurs. The CMF accepts the erase hardware interlock write. This write may be to any CMF array location. Accesses to the registers are normal register accesses. A write to CMFCTL can not set EHV at this time. A write to the register is not an erase hardware interlock write, and the CMF remains in state S2. High Voltage Write Enable S3 Erase margin reads will occur. Accesses to the registers are normal register accesses. A write to CMFCTL can change EHV. Erase Operation: High voltage is applied to the array blocks to erase the CMF bit cells. The pulse width timer is active if SCLKR[0:2] 0, and HVS can be polled to time the erase pulse. During the erase operation, the array does not respond to any address. Accesses to the registers are allowed. A write to CMFCTL can change EHV only. Erase Margin Read Operation: These reads determine whether the state of the bits in the selected blocks needs further modification by the erase operation. Once a bit is fully erased it returns one when read. All words within the blocks being erased must be read to determine whether the erase operation is completed. S2 T2 Write PE = 1, SES = 1. Mode Next State Transition Requirement
S1
T1
Write SES = 0 or a master reset Hardware Interlock A successful write to any CMF array location is the erase interlock write. If the write is to a register the erase hardware interlock write has not been done and the CMF will remain in state S2. Write SES = 0 or a master reset Write EHV=1 Master reset
S2
S3
T3
S1 S4 S1
T6 T4 T7
S4
S5
T5
Write EHV = 0, disable the internal memory map or a soft reset
S4
T8
Write EHV = 1
S5
S1
T9
Write SES = 0 or a master reset
19.6.2 Erase Margin Reads The CMF EEPROM provides an erase margin read with electrical margin for the erase state. Erase margin reads provide sufficient margin to ensure specified data retention. The erase margin read is enabled when SES = 1 and the erase write has occurred. The erase margin read and subsequent on-page erase verify reads return a zero for any bit that has not been completely erased. Bits that have completed erasing return one when read. To increase the access time of the erase margin read, the off-page access time is 16 clocks instead of the usual two clock off-page read access time. The erase margin read occurs during an off-page read. All locations within the block(s) being erased must return one when read to determine that no more erase pulses are required. 19.6.3 Erasing Shadow Information Words The shadow information words are erased with CMF array block zero. To verify that the shadow information words are erased, the SIE bit in CMFMCR must be set to one
MPC555
/ MPC556
MOTOROLA 19-26
USERS MANUAL

during the erase margin read while the shadow information is read. For the erase operation to be completed, block zero must also be fully verified. NOTE Setting the SIE bit disables normal array access. SIE should be cleared after verifying the shadow information. 19.7 Voltage Control for Programming and Erasing Bits for controlling the voltage during programming and erasing are found in the CMFCTL register. 19.7.1 Pulse Status During a program or erase pulse, the HVS bit is set while the pulse is active or during recovery. The BIU does not acknowledge an access to an array location if HVS = 1. While HVS = 1, SES cannot be changed. The program or erase pulse becomes active by setting the EHV bit and is terminated by clearing EHV or by the pulse width timing control.
EHV HVS Pulse Width Recovery = 48 Scaled Clocks or 128 Clocks Recovery
Figure 19-5 Pulse Status Timing The recovery time is the time required for the CMF EEPROM to remove the program or erase voltage from the array or shadow information before switching to another mode of operation. The recovery time is determined by the system clock range (SCLKR[0:2]) and the PE bit. If SCLKR = 000, the recovery time is 128 clocks. Otherwise, the recovery time is 48 periods of the scaled clock. Once reset is completed HVS will indicate no program or erase pulse (HVS = 0). 19.7.2 Pulse Width Timing Equation To control the pulse widths for program and erase operations, the CMF EEPROM uses the system clock and the timing control in CMFCTL. The total pulse time is defined by the following pulse width equation:
MPC555
/ MPC556
MOTOROLA 19-27
USERS MANUAL

Pulse Width = System Clock Period R 2N M R = Clock Scaling N = 5 + CLKPE[0:1] + ((PE | CSC) 10) M = 1 + CLKPM[0:6] The following subsections explain how the values for R, N, and M are determined. 19.7.3 System Clock Scaling The first term of the pulse width timing equation is the clock scaling, R. The value of R is determined by the system clock range (SCLKR) field. SCLKR defines the pulse timers base clock using the system clock. Use Table 19-12 to set SCLKR based upon the system clock frequency. The system clock period is multiplied by the clock scaling value to generate a 83.3-ns to 125-ns scaled clock. This scaled clock is used to run the charge pump submodule and the next functional block of the timing control. Table 19-12 System Clock Range
SCLKR[0:2] System Clock Frequency (MHz) Minimum Maximum Not for customer use. Program and erase timing control not specified and pulse is not terminated by the timer control. Recovery time is specified to be 128 clocks. 8 12 18 24 36 12 18 24 36 40 Reserved by Motorola for future use Clock Scaling (R)
Where:
000 001 010 011 100 101 110 and 111
1 1 3/2 2 3 4
NOTE The minimum specified system clock frequency for performing program and erase operations is 8.0 MHz. The CMF EEPROM does not have any means to monitor the system clock frequency and will not prevent program or erase operation at frequencies below 8.0 MHz. Attempting to program or erase the CMF EEPROM at system clock frequencies lower than 8.0 MHz will not damage the device if the maximum pulse times and total times are not exceeded. While some bits in the CMF EEPROM array may change state if programmed or erased at system clock frequencies below 8.0 MHz, the full program or erase transition is not ensured. WARNING Never stop the U-bus clock or alter its frequency during a program or erase operation. Changing the clock frequency during a program or erase operation results in inaccurate pulse widths and variations in the charge pump output. This includes loss of system clock/PLL.
MPC555
/ MPC556
MOTOROLA 19-28
USERS MANUAL

19.7.4 Exponential Clock Multiplier The second term in the pulse width timing equation is the exponential clock multiplier, N. The program pulse number (pulse), clock period exponent (CLKPE), CSC, and PE define the exponent in the 2N multiply of the clock period. The exponent, N, is defined by the equation: N = 5 + CLKPE[0:1] + ((PE | CSC) 10) All of the exponents are shown in Table 19-12. Table 19-13 Clock Period Exponent and Pulse Width Range
Pulse Width Range for all System Clock Frequencies from 8.0 MHz to 40.0 MHz. PE | Exponent CLKPE[0:1] CSC (N) 8 Minimum Pulse Width 2N1.25E-7 00 0 01 10 11 00 1 01 10 11 5 6 7 8 15 16 17 18 4 s 8 s 16 s 32 s 4.096 ms 8.192 ms 16.384 ms 32.768 ms MHz1 10 2N1E-7 3.2 s 6.4 s 12.8 s 25.6 s 3.28 ms 6.55 ms 13.11 ms 26.21 ms MHz1 2N0.833E-7 2.7 s 5.3 s 10.7 s 21.3 s 2.73 ms 5.46 ms 10.92 ms 21.85 ms 12 MHz1 Maximum Pulse Width 8 MHz1 N1.25E-07 2 512 s 1.024 ms 2.048 ms 4.096 ms 524.29 ms 1.05 s 2.10 s 4.19 s 10 MHz1 2N1E-7 409.6 s 819.2 s 1.6384 ms 3.2768 ms 419.43 ms 838.86 ms 1.68 s 3.35 s 12 MHz1 N0.833E-7 2 341.3 s 682.7 s 1.365 ms 2.731 ms 349.5 ms 699.1 ms 1.398 s 2.796 s
NOTES: 1. CMF clock frequency after SCKLR scaling. Example: A 40 MHz system clock scaled by 4 (SCLKR[0:2] = 0b101) results in an equivalent CMF clock of 10 MHz.
19.7.5 Linear Clock Multiplier The third term of the pulse width timing equation is the linear clock multiplier, M. The clock period multiplier, CLKPM[0:6], defines a linear multiplier for the program or erase pulse. The multiplier, M, is defined by the equation: M = 1 + CLKPM[0:6] This allows for the program/erase pulse to be from one to 128 times the pulse set by the system clock period, SCLKR[0:2] and CLKPE[0:1]. The default reset state of CLKPM[0:6] = 000 0000 for a multiplier of one. 19.7.6 A Technique to Determine SCLKR, CLKPE, and CLKPM The following example determines the values of the SCLKR, CLKPE, and CLKPM fields for a 25.6 s program pulse, PE = 0, in a system with a 40 MHz system clock.
MPC555
/ MPC556
MOTOROLA 19-29
USERS MANUAL

In this example system clock frequency = 40 MHz; the system clock period is therefore 25 ns. 1. Determine SCLKR: From Table 19-12 a 40 MHz system clock uses SCLKR[0:2] = 0b101, R = 4. 2. Determine CLKPE: From Table 19-13 a 25.6 s program pulse, PE = 0, can be generated by exponents in the range of N = 5, 6, 7, or 8. While any of these values can be selected CLKPE[0:1] = 0b00, N = 5, will be used for the example. 3. Determine CLKPM: Using the selected values of N and R in the pulse width equation and solving for M yields M = 8. Therefore, CLKPM[0:6] = 0x7 (0b0000111). 4. Check the results: Pulse Width = System Clock Period R 2N M Using SCLKR[0:2] = 0b101, CLKPE[0:1] = 0b00, CLKPM[0:6] = 0b0000111 and PE = 0 at 40 MHz system clock. Pulse Width = 25 ns 4 25 8 = 25.6 s program pulse. 19.7.7 Starting and Ending a Program or Erase Sequence The SES bit is used to signal the start and end of a program or erase sequence. At the start of a program or erase sequence, SES is set (written to a one). This locks PROTECT[0:7], SCLKR[0:2], CLKPE[0:1], CLKPM[0:6], BLOCK[0:7], CSC and PE. If PE = 0 and SES = 1, SIE is write-locked. At this point the CMF EEPROM is ready to receive either the programming writes or the erase interlock write. NOTE The erase interlock write is a write to any CMF EEPROM array location after SES is set and PE = 1. If the PE bit is a zero, the CMF BIU accepts programming writes to the CMF array address for programming. The first programming write selects the program page offset address (ADDR[17:25]) to be programmed along with the data for the programming buffers at the location written. All programming writes after the first will update the program buffers using the lower address (ADDR[26:29]) and the block address (ADDR[14:16]) to select the program page buffers to receive the data. For further information see section 19.2.2.2 Program Page Buffers. After the data has been written to the program buffers the EHV bit is set (written to a one) to start the programming pulse and lock out further programming writes. If the PE bit = 1, the CMF BIU accepts writes to any CMF array address as an eraseinterlock write. An erase interlock write is required before the EHV bit can be set. At the end of the program or erase operation the SES bit must be cleared (written to a zero) to return to normal operation and release the program buffers, PROTECT[0:7], SCLKR[0:2], CLKPE[0:1], CLKPM[0:6], BLOCK[0:7], CSC and PE. The default reset state of SES is not configured for program or erase operation (SES = 0).
MPC555
/ MPC556
MOTOROLA 19-30
USERS MANUAL

19.7.8 Controlling the Program/Erase Voltage The external program or erase enable pin (EPEE) and EHV are used to control the application of the program or erase voltage to the CMF EEPROM module. High voltage operations to the CMF EEPROM array, special MoneT shadow locations or FLASH NVM registers can occur only if EHV = 1 and EPEE = 1. Only after the correct hardware and software interlocks have been applied to the CMF EEPROM can EHV be set. Once EHV is set SES cannot be changed and attempts to read the array will not be acknowledged. The default reset state of EHV disables program or erase pulses (EHV = 0). A master reset while EHV = 1 terminates the high voltage operation, and CMF generates the required sequence to disable the high voltage without damage to the high voltage circuits. A soft reset or disabling the internal memory map clears EHV, terminating the high voltage pulse. 19.8 Censored and Non-Censored Accesses The MPC555 / MPC556 always operates in one of two modes: censored or uncensored. 19.8.1 Uncensored Mode Uncensored mode provides no censorship. In uncensored mode the FIC, ACCESS, and CENSOR[0:1] bits are irrelevant. The MPC555 / MPC556 operates in uncensored mode unless a specific event occurs to place the device in censored mode. 19.8.2 Censored Mode The MPC555 / MPC556 enters censored mode in response to any of the following events: Booting from external memory Any CMF array access from an external master Entering background debug mode. The CMF EEPROM censorship mechanism provides several censorship levels. Four bits in CMFMCR are used to configure the CMF censorship level. These bits are listed in Table 19-14. Table 19-14 Censorship Control Bits
ACCESS FIC CENSOR[0:1] Enables a CMF EEPROM to bypass the censorship Overrides CENSOR[0:1] to force information censorship if ACCESS = 0 Determine the censorship level of the CMF
In censored mode, the ACCESS and CENSOR bits work together according to Table 19-15.
MPC555
/ MPC556
MOTOROLA 19-31
USERS MANUAL

Table 19-15 Levels of Censorship
ACCESS 0 0 0 1 CENSOR[0:1] 11 01 or 10 00 XX Description Information censorship, No CMF array accesses allowed No censorship, CMF array accesses allowed Cleared censorship, No CMF array accesses allowed No censorship, CMF array accesses allowed
There are two states of censorship: information censorship (CENSOR[0:1] = 11) and cleared censorship (CENSOR[0:1] = 00). In the information censorship state the entire CMF array must be erased to clear CENSOR[0:1]. In the cleared censorship or no censorship states the bits in CENSOR[0:1] may be set without modifying the information in the CMF array. When FIC=1, the CENSOR bits have no effect upon censorship.
While the device is in uncensored mode, ACCESS may be set to allow the device to enter censored mode and still access the CMF array. ACCESS may not be set while the device is in censored mode but may be cleared. The default reset state of ACCESS is zero, so that FIC and CENSOR[0:1] control the level of censorship to the CMF EEPROM array. All accesses to the CMF EEPROM array are allowed if ACCESS=1. If an access is attempted when the device is in censored mode and the following condition holds, the CMF EEPROM module disallows access to the array and signals a bus error: ((CENSOR[0] = CENSOR[1])|(FIC = 1)) AND (ACCESS = 0) If CENSOR[0:1] is in the no-censorship state, however (CENSOR[0]CENSOR[1]), the CMF EEPROM module recognizes accesses to its address space. When FIC = 1, the CENSOR bits have no effect upon censorship. If ((FIC = 1) and (ACCESS = 0)) the CMF is in information censorship mode. If ((FIC = 1) and (ACCESS = 1)), the CMF is in normal access mode. This arrangement aids in the development of custom techniques for controlling the ACCESS bit without setting CENSOR[0:1] to the information censorship state. Using FIC to force information censorship allows testing of the hardware and software for setting ACCESS without setting CENSOR[0:1] = 11. The default reset state of FIC is normal censorship operation (FIC = 0). 19.8.3 Device Modes and Censorship Status Table 19-16 summarizes the various combinations of censorship mode and states of the ACCESS, FIC, and CENSOR[0:1] bits. When booting from the internal flash, the default state is #8 unless BDM was entered, or a slave access to the MPC555 / MPC556 occurred. When any of these three conditions occur, then the state of CENSOR[0:1] determine whether the flash array can be accessed: 1. BDM is active 2. Accessing the MPC555 / MPC556 flash via a slave mode read 3. Booting from an external memory
MPC555
/ MPC556
MOTOROLA 19-32
USERS MANUAL

Table 19-16 CMF EEPROM Devices Modes and Censorship Status
Device Mode ACCESS FIC 0 01 or 10 #2 00, 01 or 10 #4 0 1 0 Censored 1 1 0 0 1 0 Uncensored 1 1
CENSOR[0:1]
00
11
11
00, 01, 10 or 11
CMF EEPROM Status #1 #2
#1
#3
#5
#6
#7
#8
#9
#10
#11
CMF array can not be accessed. ACCESS can not be changed. FIC can be set. CENSOR[0:1] can be set. CENSOR[0:1] can not be cleared. CMF array can be accessed. ACCESS can not be changed. FIC can be set. CENSOR[0:1] can be set. CENSOR[0:1] can be cleared. CMF array can not be accessed. ACCESS can not be changed. FIC can be set. CENSOR[0:1] can not be cleared. CMF array can not be accessed. ACCESS can not be changed. FIC can not be changed. CENSOR[0:1] can be set. CENSOR[0:1] can not be cleared. CMF array can not be accessed. ACCESS can not be changed. FIC can not be changed. CENSOR[0:1] can not be cleared. CMF array can be accessed. ACCESS can be cleared. FIC can be set. CENSOR[0:1] can be changed. CMF array can be accessed. ACCESS can be cleared. FIC can not be changed. CENSOR[0:1] can be changed. CMF array can be accessed. ACCESS can be changed. FIC can be set. CENSOR[0:1] can be changed. CMF array can be accessed. ACCESS can be changed. FIC can not be changed. CENSOR[0:1] can be changed. CMF array can be accessed. ACCESS can be changed. FIC can be set. CENSOR[0:1] can be changed. CMF array can be accessed. ACCESS can be changed. FIC can not be changed. CENSOR[0:1] can be changed.
#3 #4 #5 #6 #7 #8 #9 #10 #11
= Indicates that the CMF array can not be accessed.
The only way CENSOR[0:1] can be changed is by setting or clearing the FLASH NVM fuses. In the information censorship state, CENSOR[0:1] must be cleared to the cleared censorship state before CENSOR[0:1] can be put into the no-censorship state. CAUTION Clearing the CENSOR[0:1] bits causes the entire CMF array to be erased. 19.8.4 Setting and Clearing Censor The value of each bit in CENSOR[0:1] is determined by the state of two NVM bits in a special NVM fuse as shown in Table 19-17. These two NVM bits are not part of the main flash array. The NVM fuse is not writable but instead may be set or cleared. The two NVM bits in the NVM fuse are programmed and erased simultaneously to change
MPC555
/ MPC556
MOTOROLA 19-33
USERS MANUAL

the value of the NVM fuse. Reading CENSOR[0:1] while setting or clearing with the high voltage applied (CSC = 1 and EHV = 1) will return zeroes. Table 19-17 NVM Fuse States
NVM bit 0 Erased Programmed Erased Programmed NVM bit 1 Erased Erased Programmed Programmed NVM Fuse Bit Value Undefined Set (1) Cleared (0) Undefined
The set operation changes the state in an NVM fuse from a zero to a one by programming NVM bit 0 and erasing NVM bit 1 simultaneously in the NVM fuse. This set operation can be performed without changing the contents of the CMF array. To set one or both of the bits in CENSOR[0:1], 1. Using section 19.7.6 A Technique to Determine SCLKR, CLKPE, and CLKPM, write the pulse width timing control fields for an erase pulse, CSC = 1, PE = 0 and SES = 1 in the CMFCTL register. 2. Write a one to the CENSOR bit(s) to be set. 3. Write EHV = 1 in the CMFCTL register. This will apply the programming voltages to NVM bit 0 and the erase voltages to NVM bit 1 simultaneously. 4. Read the CMFCTL register until HVS = 0. 5. Write EHV = 0 in the CMFCTL register. 6. Read the CMFMCR CENSOR bit(s) that are being set. If any bit selected for set is a 0 go to step 3. 7. Write SES = 0 and CSC = 0. The clear operation changes the state in an NVM fuse from a one to a zero by erasing NVM bit 0 and programming NVM bit 1 simultaneously in the NVM fuse. This clear operation can be done only while erasing the entire CMF array and shadow information. To clear CENSOR[0:1], 1. Write PROTECT[0:7] = 0x00 to enable the entire array for erasure. 2. Using section 19.7.6 A Technique to Determine SCLKR, CLKPE, and CLKPM, write the pulse width timing control fields for an erase pulse, BLOCK[0:7] = 0xFF, CSC = 1, PE = 1 and SES = 1 in the CMFCTL register. 3. Perform an erase interlock write. 4. Write EHV = 1 in the CMFCTL register. This will apply the erase voltages to the entire CMF array and NVM bit 0 and the programming voltages to NVM bit 1 simultaneously. 5. Read the CMFCTL register until HVS = 0. 6. Write EHV = 0 in the CMFCTL register. 7. Read the entire CMF array and the shadow information words. If any bit equals zero, go to step 4. 8. Read CENSOR[0:1]. If CENSOR[0:1] 0 go to step 4. 9. Write SES = 0 and CSC = 0.
MPC555
/ MPC556
MOTOROLA 19-34
USERS MANUAL

19.8.5 Switching the CMF EEPROM Censorship There are three levels of censorship that CENSOR[0:1] can select: cleared censorship, no censorship (two states) and information censorship. These three levels, state values, transitions and level of censorship are shown in Figure 19-6.
Information Censorship
Data
CENSOR[0:1]=3
Data
T2
Data
T4
No Censorship
CENSOR[0:1]=1
Data
CENSOR[0:1]=2
T3
Data T1 T3
Cleared Censorship
Data
CENSOR[0:1]=0
Data
T3
Unknown
Figure 19-6 Censorship States and Transitions
MPC555
/ MPC556
MOTOROLA 19-35
USERS MANUAL

Figure 19-6 illustrates the following CENSOR[0:1] transitions: T1: Cleared censorship to no censorship Set CENSOR[0] or CENSOR[1]. T2: No censorship to information censorship Set CENSOR[0] and CENSOR[1]. T3: Information censorship, no censorship or unknown to cleared censorship clear CENSOR[0:1]. This is done only while the entire CMF array is erased. T4: Cleared censorship to information censorship Set both CENSOR[0] and CENSOR[1]. 19.9 Pin Descriptions The CMF modules use the following pins:
EPEE VPP VDDF VSSF 19.9.1 EPEE Signal The EPEE bit monitors the state of the external program/erase enable, EPEE pin. EPEE has a digital filter that requires two consecutive samples to be equal before the output of the filter changes. The CMF samples EPEE when EHV is asserted and holds the EPEE state until EHV is negated. This is shown in Figure 19-7.
EPEE Pins Digital Filter
EPEE Pin = 1 @ T2
Pin Filter Output = 0
EPEE Pin = 0 @ T2
EPEE Pin = 0 @ T2 EPEE Pin = 1 @ T2
EPEE Pin = 1 @ T2
In Out Latch EPEE
EPEE Pin = 0 @ T2
EHV
Figure 19-7 EPEE Digital Filter and Latch

MPC555
/ MPC556
MOTOROLA 19-36
USERS MANUAL

If EPEE = 1 when EHV is asserted, high voltage operations such as program or erase are enabled. If EPEE = 0 when EHV is asserted, high voltage operations are disabled. The EPEE pin uses a two-period clock synchronizer that switches the internal signal CMF_EPEE after two consecutive constant values of EPEE, as shown in Figure 198. At first the value of CMF_EPEE is unknown, as the prior information for the EPEE pin is not provided. One high or low clock of EPEE does not cause CMF_EPEE to switch.
Clock EPEE CMF_EPEE
Figure 19-8 CMF_EPEE Timing Diagram 19.9.2 FLASH Program/Erase Voltage Conditioning A voltage of at least (VDDL 0.35 V) must be applied at all times to the VPP pins or damage to the FLASH module can occur. FLASH modules can be damaged by power on and power off VPP transients. VPP must not rise to programming level while VDDL is below 1.0 volts, and must not fall below the minimum specified value while VDDL is applied. Figure 19-9 shows the VPP and VDDL operating envelope.
MPC555
/ MPC556
MOTOROLA 19-37
USERS MANUAL

Maximum Overshoot 6.0 V 100 ns Maximum
5.5 V 5.25 V
4.75 V
3.6 V
3.0 V 2.65 V VPP Envelope VDDL* Envelope Combined VPP and VDDL Suggested VPP Suggested VDDL
0.0 V -0.35 V
Power On
Normal
Program/Erase
Normal
Power Down
*This assumes that VDDL = VDDI = VDDF = VDDSYN.
Figure 19-9 VPP and VDDL Power Switching Use of an external circuit to condition VPP is recommended. Figure 19-10 shows a simple circuit that maintains required voltages and filters transients. VPP is pulled up to VDDL via Schottky diode D2, protecting VDDL from excessive reverse current. D2 also protects the FLASH from damage should the programming voltage go to zero. Programming power supply voltage must be adjusted to compensate for the forwardMPC555
/ MPC556
MOTOROLA 19-38
USERS MANUAL

bias drop across D1. Capacitor C1 filters transients, while R2 provides a discharge bleed path for C1. Allow for RC charge and discharge time constants when applying and removing power. When using this circuit, keep leakage from external devices connected to the VPP pin low, to minimize diode voltage drop.
PROGRAMMING VOLTAGE POWER SUPPLY*
D1 D2 VDDL VPP Pin
R2 22K
C1 0.1F
*The VPP voltage specification is the voltage at the VPP pin, not the input to diode D1.
Figure 19-10 VPP Conditioning Circuit 19.10 Reset Operation 19.10.1 Master Reset The MPC555 / MPC556 signals a master reset (both PORESET or HRESET) to the CMF EEPROM when a full reset is required. A master reset is the highest priority operation for the CMF EEPROM and will terminate all other operations. The CMF EEPROM module uses master reset to initialize all register bits to their reset values. If the CMF EEPROM is in program or erase operation (EHV = 1) and a master reset is generated, the module will perform the needed interlocks to disable the high voltage without damage to the high voltage circuits. Master reset will terminate any other mode of operation and force the CMF EEPROM BIU to a state ready to receive U-bus accesses within 10 clocks of the end of master reset. If the HC bit of the reset configuration word = 0 and the SIU requests internal configuration during reset, the CMF EEPROM will provide the reset configuration word to the device from CMFRC. 19.10.2 Soft Reset A soft reset forces the BIU into a state ready to receive U-bus accesses and clear the EHV bit. All other register bits remain unaltered by a soft reset.
MPC555
/ MPC556
MOTOROLA 19-39
USERS MANUAL

19.10.3 Emulation Operation The CMF EEPROM supports externally mapped access for emulation operation. When the SIU indicates an externally mapped access to the CMF EEPROM, the CMF does not respond to the address, even though it may be a valid CMF access. Refer to 10.6 Dual Mapping of the Internal Flash EEPROM Array for details. 19.11 Disabling the CMF Module The CMF EEPROM can be disabled when the internal memories are disabled. Disabling the internal memories is controlled by the FLEN bit (bit 20) in the USIU internal memory map register. The default reset enable/disable state of the internal memories is user defined with the reset configuration word bit 20.
CAUTION The reset configuration word from an erased CMF must be generated external to the CMF, i.e., from the default reset configuration word off the external reset configuration word. See 7.5 Reset Configuration. EHV is reset to 0 when the CMF is disabled and can not be set until the CMF is enabled, see section 19.7.8 Controlling the Program/Erase Voltage When disabled, the power used by the CMF is reduced. NOTE Although the program and erase operations can be suspended (EHV = 0) by disabling the internal memory, it is not recommended that program or erase be suspended in this manner.
MPC555
/ MPC556
MOTOROLA 19-40
USERS MANUAL
SECTION 20 STATIC RANDOM ACCESS MEMORY (SRAM)

The MPC555 / MPC556 contains two static random access memory (SRAM) modules: a 16-Kbyte module and a 10-Kbyte module. The SRAM modules provide the microcontroller unit (MCU) with fast (one cycle access), general-purpose memory. The SRAM can be read or written as either bytes, half words, or words. Each SRAM module is built with a series of 4-Kbyte blocks and occupies a continuous block of memory. For a RAM size array block of less than 4 Kbytes (e.g., the 2-Kbyte array in the 10-Kbyte SRAM module), the remaining 2 Kbytes are unimplemented and unusable. The SRAM modules are accessible to the CPU and other bus masters via the L-bus on the CPU chip. To improve access time, each SRAM module resides on a separate bus interface unit (BIU). Each BIU has its own module control register. 20.1 Features One-cycle access Byte, half-word, or word read/write accesses Individual protection control bits provided for 4-Kbyte block boundaries read only region data only region user/supervisor Two-cycle access for power savings Low power standby operation for data retention VDDI = 0, no read/writes to the SRAM; VDDSRAM = 3.3 V to retain data Supports pipelining 20.2 Block Diagram Figure 20-1 shows the major components of an SRAM module.
L-bus Power Gone SRAM Array (Maximum 16 Kbytes) BIU Keep-Alive Power
Figure 20-1 SRAM Block Diagram
STATIC RANDOM ACCESS MEMORY (SRAM)
MOTOROLA 20-1

20.3 Programming Model The SRAM modules consist of two separately addressable sections the array itself, and a set of registers used for configuration and testing of the SRAM array. The registers are located in the SRAM control register block, shown in Figure 20-2. See also Figure 1-3 for the entire MPC555 / MPC556 memory map.
MSB 0 0x38 0000 0x38 0004 SRAMTST_A 0x38 0008 SRAMMCR_B SRAM Control Registers SRAMMCR_A LSB 31
0x38 000C
SRAMTST_B
0x3F 8000 0x3F 8FFF 0x3F 9000 0x3F 97FF 0x3F 9800 0x3F 9FFF 0x3F A000 0x3F AFFF 0x3F B000 0x3F BFFF 0x3F C000 0x3F CFFF 0x3F D000 0x3F DFFF 0x3F E000 0x3F EFFF 0x3F F000 0x3F FFFF Sub Block 2 Sub Block 3 Sub Block 0 Sub Block 1 16 Kbytes SRAM Sub Block 1 Sub Block 2 Sub Block 3 10 Kbytes SRAM Sub Block 0 6 Kbytes Unused Sub Block 1
Figure 20-2 SRAM Memory Map The control block for each of the two SRAM modules contains one control register for configuring the array and one control register for use in testing. 20.3.1 SRAM Module Configuration Register (SRAMMCR) Each SRAM module configuration register contains bits for setting access rights to the array. Table 20-1 provides definitions for the bits.
MPC555
/ MPC556
MOTOROLA 20-2
USERS MANUAL

SRAMMCR SRAM Module Configuration Register
MSB 0 LCK 1 DIS 2 2CY 3 4 5 6 7 8 9 RESERVED 10 11 12 13
0x38 0000 0x38 0008

14 15
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
17
18
19
20 R0
21 D0
22 S0
23 R1
24 D1
25 S1
26 R2
27 D2
28 S2
29 R3
30 D3
LSB 31 S3
RESERVED RESET:
Table 20-1 SRAMMCR Bit Descriptions

Bit(s) 0 Name LCK Description Lock bit. This bit can be set only once and cleared only by reset. 0 = Writes to the SRAMMCR are accepted 1 = Writes to the SRAMMCR are ignored Module disable 0 = SRAM module is enabled 1 = SRAM module is disabled. Module can be subsequently re-enabled by software setting this bit or by reset. Attempts to read SRAM array when it is disabled result in internal TEA assertion. Two-cycle mode 0 = SRAM module is in single-cycle mode (normal operation) 1 = SRAM module is in two-cycle mode. In this mode, the first cycle is used for decoding the address, and the second cycle is used for accepting or providing data. This mode provides some power savings while keeping the memory active. Reserved
DIS
2CY
3:19 20, 23, 26, 29
Rx Read only. R0 controls the highest 4-Kbyte block (lowest address) of the SRAM array; (x = 0, 1, 2, 3) R3 controls the lowest block (highest address). 0 = 4-Kbyte block is readable and writable 1 = 4-Kbyte block is read only. Attempts to write to this space result in internal TEA assertion. Dx Data only. D0 controls the highest 4-Kbyte block (lowest address) of the SRAM array; D3 (x = 0, 1, 2, 3) controls the lowest block (highest address). 0 = 4-Kbyte block can contain data or instructions 1 = 4-Kbyte block contains data only. Attempts to load instructions from this space result in internal TEA assertion. Sx Supervisor only. S0 controls the highest 4-Kbyte block (lowest address) of the SRAM ar(x = 0, 1, 2, 3) ray; S3 controls the lowest block (highest address). 0 = 4-Kbyte block is placed in unrestricted space 1 = 4-Kbyte block is placed in supervisor space. Attempts to access this space from the user privilege level result in internal TEA assertion.
21, 24, 27, 30
22, 25, 28, 31
20.3.2 SRAM Test Register (SRAMTST) SRAMTST SRAM Test Register The SRAM test register is used for factory testing only.
MPC555
0x38 0004, 0x38 000C
/ MPC556
MOTOROLA 20-3
USERS MANUAL
MPC555
/ MPC556
MOTOROLA 20-4
USERS MANUAL
SECTION 21 DEVELOPMENT SUPPORT

21.1 Overview The visibility and controllability requirements of emulators and bus analyzers are in opposition to the trend of modern microcomputers and microprocessors where many bus cycles are directed to internal resources and are not visible externally. In order to enhance the development tool visibility and controllability, some of the development support functions are implemented in silicon. These functions include program flow tracking, internal watchpoint, breakpoint generation, and emulation while in debug mode. This section covers program flow tracking support, breakpoint/watchpoint support, development system interface support (debug mode) and software monitor debugger support. These features allow the user to efficiently debug systems based on the MPC555 / MPC556. 21.2 Program Flow Tracking The mechanism described below allows tracking of program instruction flow with almost no performance degradation. The information provided may be compressed and captured externally and then parsed by a post-processing program using the microarchitecture defined below. The program instructions flow is visible on the external bus when the MPC555 / MPC556 is programmed to operate in serial mode and show all fetch cycles on the external bus. This mode is selected by programming the ISCT_SER (instruction fetch show cycle control) field in the I-bus support control register (ICTRL), as shown in Table 21-21. In this mode, the processor is fetch serialized, and all internal fetch cycles appear on the external bus. Processor performance is, therefore, much lower than when working in regular mode. These features, together with the fact that most fetch cycles are performed internally (e.g., from the I-cache), increase performance but make it very difficult to provide the user with the real program trace. In order to reconstruct a program trace, the program code and the following additional information from the MCU are needed: A description of the last fetched instruction (stall, sequential, branch not taken, branch direct taken, branch indirect taken, exception taken) The addresses of the targets of all indirect flow change. Indirect flow changes include all branches using the link and count registers as the target address, all exceptions, and rfi, mtmsr and mtspr (to some registers) because they may cause a context switch.
MPC555 / MPC556 USERS MANUAL DEVELOPMENT SUPPORT MOTOROLA 21-1

The number of instructions canceled each clock Instructions are fetched sequentially until branches (direct or indirect) or exceptions appear in the program flow or some stall in execution causes the machine not to fetch the next address. Instructions may be architecturally executed, or they may be canceled in some stage of the machine pipeline. The following sections define how this information is generated and how it should be used to reconstruct the program trace. The issue of data compression that could reduce the amount of memory needed by the debug system is also mentioned. 21.2.1 Program Trace Cycle To allow visibility of the events happening in the machine a few dedicated pins are used and a special bus cycle attribute, program trace cycle, is defined.
The program trace cycle attribute is attached to all fetch cycles resulting from indirect flow changes. When program trace recording is needed, the user can make sure these cycles are visible on the external bus. The VSYNC indication, when asserted, forces all fetch cycles marked with the program trace cycle attribute to be visible on the external bus even if their data is found in one of the internal devices. To enable the external hardware to properly synchronize with the internal activity of the CPU, the assertion and negation of VSYNC forces the machine to synchronize. The first fetch after this synchronization is marked as a program trace cycle and is visible on the external bus. For more information on the activity of the external hardware during program trace refer to 21.2.4 The External Hardware. In order to keep the pin count of the chip as low as possible, VSYNC is not implemented as one of the chips external pins. It is asserted and negated using the serial interface implemented in the development port. For more information on this interface refer to 21.5 Development Port Forcing the CPU to show all fetch cycles marked with the program trace cycle attribute can be done either by asserting the VSYNC pin (as mentioned above) or by programming the fetch show cycle bits in the instruction support control register, ICTRL. For more information refer to 21.2.5 Instruction Fetch Show Cycle Control When the VSYNC indication is asserted, all fetch cycles marked with the program trace cycle attribute are made visible on the external bus. These cycles can generate regular bus cycles (address phase and data phase) when the instructions reside only in one of the external devices. Or, they can generate address-only cycles when the instructions reside in one of the internal devices (internal memory, etc.). When VSYNC is asserted, some performance degradation is expected due to the additional external bus cycles. However, since this performance degradation is expected to be very small, it is possible to program the machine to show all indirect flow changes. In this way, the machine will always perform the additional external bus cycles and maintain exactly the same behavior both when VSYNC is asserted and when it is negated. For more information refer to 21.7.6 I-Bus Support Control Register.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-2
USERS MANUAL

The status pins are divided into two groups and one special case listed below: 21.2.1.1 Instruction Queue Status Pins VF [0:2] Instruction queue status pins denote the type of the last fetched instruction or how many instructions were flushed from the instruction queue. These status pins are used for both functions because queue flushes only happen in clocks that there is no fetch type information to be reported. Possible instruction types are defined in Table 21-1. Table 21-1 VF Pins Instruction Encodings
VF[0:2] Instruction Type None Sequential Branch (direct or indirect) not taken VSYNC was asserted/negated and therefore the next instruction will be marked with the indirect change-of-flow attribute VF Next Clock Will Hold More instruction type information More instruction type information More instruction type information More instruction type information 000 001 010 011
100
Exception taken the target will be marked with the Queue flush information1 indirect change-of-flow attribute Branch indirect taken, rfi, mtmsr, isync and in some cases mtspr to CMPA-F, ICTRL, ECR, or DER 1 the target will be marked with the indirect change-of- Queue flush information flow attribute2 Branch direct taken Branch (direct or indirect) not taken Queue flush information1 Queue flush information1
101
110 111
NOTES: 1. Unless next clock VF=111. See below. 2. The sequential instructions listed here affect the machine in a manner similar to indirect branch instructions. Refer to 21.2.3 Sequential Instructions Marked as Indirect Branch.
Table 21-2 shows VF[0:2] encodings for instruction queue flush information.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-3
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Table 21-2 VF Pins Queue Flush Encodings
VF[0:2] 000 001 010 011 100 101 110 111 Queue Flush Information 0 instructions flushed from instruction queue 1 instruction flushed from instruction queue 2 instructions flushed from instruction queue 3 instructions flushed from instruction queue 4 instructions flushed from instruction queue 5 instructions flushed from instruction queue Reserved Instruction type information1
NOTES: 1. Refer to Table 21-1.
21.2.1.2 History Buffer Flushes Status Pins VFLS [0..1] The history buffer flushes status pins denote how many instructions are flushed from the history buffer this clock due to an exception.Table 21-3 shows VFLS encodings. Table 21-3 VFLS Pin Encodings
VFLS[0:1] 00 01 10 11 History Buffer Flush Information 0 instructions flushed from history queue 1 instruction flushed from history queue 2 instructions flushed from history queue Used for debug mode indication (FREEZE). Program trace external hardware should ignore this setting.
21.2.1.3 Queue Flush Information Special Case There is one special case when although queue flush information is expected on the VF pins, (according to the last value on the VF pins), regular instruction type information is reported. The only instruction type information that can appear in this case is VF = 111, branch (direct or indirect) NOT taken. Since the maximum queue flushes possible is five, it is easy to identify this special case. 21.2.2 Program Trace when in Debug Mode When entering debug mode an interrupt/exception taken is reported on the VF pins, (VF = 100) and a cycle marked with the program trace cycle is made visible externally. When the CPU is in debug mode, the VF pins equal 000 and the VFLS pins equal 11. For more information on debug mode refer to 21.4 Development System Interface If VSYNC is asserted/negated while the CPU is in debug mode, this information is reported as the first VF pins report when the CPU returns to regular mode. If VSYNC was not changed while in debug mode. the first VF pins report will be of an indirect branch taken (VF = 101), suitable for the rfi instruction that is being issued. In both
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-4
USERS MANUAL

cases the first instruction fetch after debug mode is marked with the program trace cycle attribute and therefore is visible externally. 21.2.3 Sequential Instructions Marked as Indirect Branch There are cases when non-branch (sequential) instructions may effect the machine in a manner similar to indirect branch instructions. These instructions include rfi, mtmsr, isync and mtspr to CMPA-F, ICTRL, ECR and DER. These instructions are marked by the CPU as indirect branch instructions (VF = 101) and the following instruction address is marked with the same program trace cycle attribute as if it were an indirect branch target. Therefore, when one of these special instructions is detected in the CPU, the address of the following instruction is visible externally. In this way the reconstructing software is able to evaluate correctly the effect of these instructions. 21.2.4 The External Hardware When program trace is needed, the external hardware needs to sample the status pins (VF and VFLS) each clock cycle and the address of all cycles marked with the program trace cycle attribute. Program trace can be used in various ways. Below are two examples of how program trace can be used: Back trace Back trace is useful when a record of the program trace before some event occurred is needed. An example of such an event is some system failure. In case back trace is needed the external hardware should start sampling the status pins (VF and VFLS) and the address of all cycles marked with the program trace cycle attribute immediately when reset is negated. If show cycles is programmed out of reset to show all, all cycles marked with program trace cycle attribute are visible on the external bus. VSYNC should be asserted sometime after reset and negated when the programmed event occurs. If no show is programmed for show cycles, make sure VSYNC is asserted before the Instruction show cycles programming is changed from show all. Note that in case the timing of the programmed event is unknown it is possible to use cyclic buffers. After VSYNC is negated the trace buffer will contain the program flow trace of the program executed before the programmed event occurred. Window trace Window trace is useful when a record of the program trace between two events is needed. In case window trace is needed the VSYNC pin should be asserted between these two events. After the VSYNC pin is negated the trace buffer will contain information describing the program trace of the program executed between the two events. 21.2.4.1 Synchronizing the Trace Window to the CPU Internal Events The assertion/negation of VSYNC is done using the serial interface implemented in the development port. In order to synchronize the assertion/negation of VSYNC to an inMPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-5
USERS MANUAL

ternal event of the CPU, it is possible to use the internal breakpoints together with debug mode. This method is available only when debug mode is enabled. For more information on debug mode refer to 21.4 Development System Interface The following is an example of steps that enable the user to synchronize the trace window to the CPU internal events: 1. Enter debug mode, either immediately out of reset or using the debug mode request 2. Program the hardware to break on the event that marks the start of the trace window using the control registers defined in 21.3 Watchpoints and Breakpoints Support 3. Enable debug mode entry for the programmed breakpoint in the debug enable register (DER). See 21.7.12 Debug Enable Register (DER)) 4. Return to the regular code run (see 21.4.1.6 Exiting Debug Mode) 5. The hardware generates a breakpoint when the programmed event is detected and the machine enters debug mode (see 21.4.1.2 Entering Debug Mode) 6. Program the hardware to break on the event that marks the end of the trace window 7. Assert VSYNC 8. Return to the regular code run. The first report on the VF pins is a VSYNC (VF = 011). 9. The external hardware starts sampling the program trace information upon the report on the VF pins of VSYNC 10. The hardware generates a breakpoint when the programmed event is detected and the machine enters debug mode 11. Negate VSYNC 12. Return to the regular code run (issue an rfi). The first report on the VF pins is a VSYNC (VF = 011) 13. The external hardware stops sampling the program trace information upon the report on the VF pins of VSYNC 21.2.4.2 Detecting the Trace Window Start Address When using back trace, latching the value of the status pins (VF and VFLS), and the address of the cycles marked as program trace cycle, should start immediately after the negation of reset. The start address is the first address in the program trace cycle buffer. When using window trace, latching the value of the status pins (VF and VFLS), and the address of the cycles marked as program trace cycle, should start immediately after the first VSYNC is reported on the VF pins. The start address of the trace window should be calculated according to first two VF pins reports. Assuming that VF1 and VF2 are the two first VF pins reports and T1 and T2 are the two addresses of the first two cycles marked with the program trace cycle attribute that were latched in the trace buffer, use the following table to calculate the trace window start address.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-6
USERS MANUAL

Table 21-4 Detecting the Trace Buffer Start Point
VF1 011 VSYNC 011 VSYNC 011 VSYNC VF2 001 sequential 110 branch direct taken 101 branch indirect taken Starting point T1 T1 - 4 + offset (T1 - 4) T2 Description VSYNC asserted followed by a sequential instruction. The start address is T1 VSYNC asserted followed by a taken direct branch. The start address is the target of the direct branch VSYNC asserted followed by a taken indirect branch. The start address is the target of the indirect branch
21.2.4.3 Detecting the Assertion/Negation of VSYNC Since the VF pins are used for reporting both instruction type information and queue flush information, the external hardware must take special care when trying to detect the assertion/negation of VSYNC. When VF = 011 it is a VSYNC assertion/negation report only if the previous VF pins value was one of the following values: 000, 001, or 010. 21.2.4.4 Detecting the Trace Window End Address The information on the status pins that describes the last fetched instruction and the last queue/history buffer flushes, changes every clock. Cycles marked as program trace cycle are generated on the external bus only when possible (when the SIU wins the arbitration over the external bus). Therefore, there is some delay between the information reported on the status pins that a cycle marked as program trace cycle will be performed on the external bus and the actual time that this cycle can be detected on the external bus. When VSYNC is negated by the user (through the serial interface of the development port), the CPU delays the report of the of the assertion/negation of VSYNC on the VF pins (VF = 011) until all addresses marked with the program trace cycle attribute were visible externally. Therefore, the external hardware should stop sampling the value of the status pins (VF and VFLS), and the address of the cycles marked as program trace cycle immediately after the VSYNC report on the VF pins. The last two instructions reported on the VF pins are not always valid. Therefore at the last stage of the reconstruction software, the last two instructions should be ignored. 21.2.4.5 Compress In order to store all the information generated on the pins during program trace (five bits per clock + 30 bits per show cycle) a large memory buffer may be needed. However, since this information includes events that were canceled, compression can be very effective. External hardware can be added to eliminate all canceled instructions and report only on branches (taken and not taken), indirect flow change, and the number of sequential instructions after the last flow change.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-7
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21.2.5 Instruction Fetch Show Cycle Control Instruction fetch show cycles are controlled by the bits in the ICTRL and the state of VSYNC. The following table defines the level of fetch show cycles generated by the CPU. For information on the fetch show cycles control bits refer to Table 21-5 Table 21-5 Fetch Show Cycles Control
VSYNC X X X 0 ISCTL Instruction Fetch Show Cycle Control Bits ISCTRL[ISCT_SER] x00 x01 x10 x11 x11 Show Cycles Generated All fetch cycles All change of flow (direct & indirect) All indirect change of flow No show cycles are performed All indirect change of flow
NOTE A cycle marked with the program trace cycle attribute is generated for any change in the VSYNC state (assertion or negation). 21.3 Watchpoints and Breakpoints Support Watchpoints, when detected, are reported to the external world on dedicated pins but do not change the timing and the flow of the machine. Breakpoints, when detected, force the machine to branch to the appropriate exception handler. The CPU supports internal watchpoints, internal breakpoints, and external breakpoints. Internal watchpoints are generated when a user programmable set of conditions are met. Internal breakpoints can be programmed to be generated either as an immediate result of the assertion of one of the internal watchpoints, or after an internal watchpoint is asserted for a user programmable times. Programming a certain internal watchpoint to generate an internal breakpoint can be done either in software, by setting the corresponding software trap enable bit, or on the fly using the serial interface implemented in the development port to set the corresponding development port trap enable bit. External breakpoints can be generated by any of the peripherals of the system, including those found on the MPC555 / MPC556 or externally, and also by an external development system. Peripherals found on the external bus use the serial interface of the development port to assert the external breakpoint. In the CPU, as in other RISC processors, saving/restoring machine state on the stack during exception handling, is done mostly in software. When the software is in the middle of saving/restoring machine state, the MSR[RI] bit is cleared. Exceptions that occur and that are handled by the CPU when the MSR[RI] bit is clear result in a non-restartable machine state. For more information refer to 3.15.4 Interrupts In general, breakpoints are recognized in the CPU is only when the MSR[RI] bit is set, which guarantees machine restartability after a breakpoint. In this working mode breakpoints are said to be masked. There are cases when it is desired to enable
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-8
USERS MANUAL

breakpoints even when the MSR[RI] bit is clear, with the possible risk of causing a nonrestartable machine state. Therefore internal breakpoints have also a programmable non-masked mode, and an external development system can also choose to assert a non-maskable external breakpoint. Watchpoints are not masked and therefore always reported on the external pins, regardless of the value of the MSR[RI] bit. The counters, although counting watchpoints, are part of the internal breakpoints logic and therefore are not decremented when the CPU is operating in the masked mode and the MSR[RI] bit is clear. The following figure illustrates the watchpoints and breakpoints support of the CPU.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-9
USERS MANUAL
MPC555
Internal Peripherals Maskable Breakpoint Non-maskable Breakpoint Development Port Trap Enable Bits Breakpoint to CPU X X Software trap Enable Bits (Non-masked Control Bit) MSR[RI] Watchpoints Counters X bit wise AND bit wise OR X To watchpoints pins
USERS MANUAL
Development System OR External Peripherals
/ MPC556
Development Port
LCTRL2
DEVELOPMENT SUPPORT
Figure 21-1 Watchpoints and Breakpoint Support in the CPU
MSR
Internal Watchpoints Logic
MOTOROLA
21-10

21.3.1 Internal Watchpoints and Breakpoints This section describes the internal breakpoints and watchpoints support of the CPU. For information on external breakpoints support refer to 21.4 Development System Interface Internal breakpoint and watchpoint support is based on eight comparators comparing information on instruction and load/store cycles, two counters, and two AND-OR logic structures. The comparators perform compare on the Instruction address (I-address), on the load/store address (L-address) and on the load/store data (L-data). The comparators are able to detect the following conditions: equal, not equal, greater than, less than (greater than or equal and less than or equal are easily obtained from these four conditions, for more information refer to 21.3.1.6 Generating Six Compare Types). Using the AND-OR logic structures in range and out of range detections (on address and on data) are supported. Using the counters, it is possible to program a breakpoint to be recognized after an event was detected a predefined number of times. The L-data comparators can operate on fix point data of load or store. When operating on fix point data the L-data comparators are able to perform compare on bytes, halfwords and words and can treat numbers either as signed or as unsigned values. The comparators generate match events. The match events enter the instruction AND-OR logic where the instruction watchpoints and breakpoint are generated. The instruction watchpoints, when asserted, may generate the instruction breakpoint. Two of them may decrement one of the counters. If one of the instruction watchpoints expires in a counter that is counting, the instruction breakpoint is asserted. The instruction watchpoints and the load/store match events (address and data) enter the load/store AND-OR logic where the load/store watchpoints and breakpoint are generated. The load/store watchpoints, when asserted, may generate the load/store breakpoint or they may decrement one of the counters. When a counter that is counting one of the load/store watchpoints expires, the load/store breakpoint is asserted. Watchpoints progress in the machine and are reported on retirement. Internal breakpoints progress in the machine until they reach the top of the history buffer when the machine branches to the breakpoint exception routine. In order to enable the user to use the breakpoint features without adding restrictions on the software, the address of the load/store cycle that generated the load/store breakpoint is not stored in the DAR (data address register), like other load/store type exceptions. In case of a load/store breakpoint, the address of the load/store cycle that generated the breakpoint is stored in an implementation-dependent register called the BAR (breakpoint address register). Key features of internal watchpoint and breakpoint support are: Four I-address comparators (each supports equal, not equal, greater than, less than) Two L-address comparators (each supports equal, not equal, greater than, less
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-11
USERS MANUAL

than) including least significant bits masking according to the size of the bus cycle for the byte and half-word working modes. Refer to 21.3.1.2 Byte and Half-Word Working Modes Two L-data comparators (each supports equal, not equal, greater than, less than) including byte, half-word and word operating modes and four byte mask bits for each comparator. Can be used for fix point data. Match is detected only on the valid part of the data bus (according to the cycles size and the two address least significant bits). No internal breakpoint/watchpoint matching support for unaligned words and halfwords The L-data comparators can be programmed to treat fix point numbers as signed values or as unsigned values Combine comparator pairs to detect in and out of range conditions (including either signed or unsigned values on the L-data) A programmable AND-OR logic structure between the four instruction comparators results with five outputs, four instruction watchpoints and one instruction breakpoint A programmable AND-OR logic structure between the four instruction watchpoints and the four load/store comparators results with three outputs, two load/ store watchpoints and one load/store breakpoint Five watchpoint pins, three for the instruction and two for the load/store Two dedicated 16-bit down counters. Each can be programmed to count either an instruction watchpoint or an load/store watchpoint. Only architecturally executed events are counted, (count up is performed in case of recovery). On the fly trap enable programming of the different internal breakpoints using the serial interface of the development port (refer to 21.5 Development Port). Software control is also available. Watchpoints do not change the timing of the machine Internal breakpoints and watchpoints are detected on the instruction during instruction fetch Internal breakpoints and watchpoints are detected on the load/store during load/ store bus cycles Both instruction and load/store breakpoints and watchpoints are handled and reported on retirement. Breakpoints and watchpoints on recovered instructions (as a result of exceptions, interrupts or miss prediction) are not reported and do not change the timing of the machine. Instructions with instruction breakpoints are not executed. The machine branches to the breakpoint exception routine BEFORE it executes the instruction. Instructions with load/store breakpoints are executed. The machine branches to the breakpoint exception routine AFTER it executes the instruction. The address of the access is placed in the BAR (breakpoint address register). Load/store multiple and string instructions with load/store breakpoints first finish execution (all of it) and then the machine branches to the breakpoint exception routine. Load/store data compare is done on the load/store, AFTER swap in store accesses and BEFORE swap in load accesses (as the data appears on the bus). Internal breakpoints may operate either in masked mode or in non-masked mode.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-12
USERS MANUAL

Both go to x and continue working modes are supported for the instruction breakpoints. 21.3.1.1 Restrictions There are cases when the same watchpoint can be detected more than once during the execution of a single instruction, e.g. a load/store watchpoint is detected on more than one transfer when executing a load/store multiple/string or a load/store watchpoint is detected on more than one byte when working in byte mode. In all these cases only one watchpoint of the same type is reported for a single instruction. Similarly, only one watchpoint of the same type can be counted in the counters for a single instruction. Since watchpoint events are reported upon the retirement of the instruction that caused the event, and more than one instruction can retire from the machine in one clock, consequent events may be reported in the same clock. Moreover the same event, if detected on more than one instruction (e.g., tight loops, range detection), in some cases will be reported only once. Note that the internal counters count correctly in these cases. Do not put a breakpoint on an mtspr ICTRL instruction. When a breakpoint is set on an mtspr ICTRL Rx instruction and the value of bit 28 (IFM) is one, the result will be unpredictable. A breakpoint can be taken or not on the instruction and the value of the IFM bit can be either zero or one. Also, do not put a breakpoint on an mtspr ICTRL Rx instruction when Rx contains one in bit 28. 21.3.1.2 Byte and Half-Word Working Modes The CPU watchpoints and breakpoints support enables the user to detect matches on bytes and half-words even when accessed using a load/store instruction of larger data widths, for example when loading a table of bytes using a series of load word instructions. In order to use this feature, the user needs to program the byte mask for each of the L-data comparators and to write the needed match value to the correct half-word of the data comparator when working in half-word mode and to the correct bytes of the data comparator when working in byte mode. Since bytes and half-words can be accessed using a larger data width instruction, it is impossible for the user to predict the exact value of the L-address lines when the requested byte/half-word is accessed, (e.g., if the matched byte is byte two of the word and it is accessed using a load word instruction), the L-address value will be of the word (byte zero). Therefore, the CPU masks the two least-significant bits of the L-address comparators whenever a word access is performed and the least-significant bit whenever a half-word access is performed. Address range is supported only when aligned according to the access size. (See examples)
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-13
USERS MANUAL

21.3.1.3 Examples A fully supported scenario: Looking for: Data size: Byte Address: 0x00000003 Data value: greater than 0x07 and less than 0x0c Programming options: One L-address comparator = 0x00000003 and program for equal One L-data comparator = 0x00000007 and program for greater than One L-data comparator = 0x0000000c and program for less than Both byte masks = 0xe Both L-data comparators program to byte mode Result: The event will be correctly detected regardless of the load/store instruction the compiler chooses for this access A fully supported scenario: Looking for: Data size: half-word Address: greater than 0x00000000 and less than 0x0000000c Data value: greater than 0x4e204e20 and less than 0x9c409c40 Programming option: One L-address comparator = 0x00000000 and program for greater than One L-address comparator = 0x0000000c and program for less than One L-data comparator = 0x4e204e20 and program for greater than One L-data comparator = 0x9c409c40 and program for less than Both byte masks = 0x0 Both L-data comparators program to half-word mode Result: The event will be correctly detected as long as the compiler does not use a load/store instruction with data size of byte. A partially supported scenario: Looking for: Data size: half-word Address: greater than or equal 0x00000002 and less than 0x0000000e Data value: greater than 0x4e204e20 and less than 0x9c409c40 Programming option: One L-address comparator = 0x00000001 and program for greater than One L-address comparator = 0x0000000e and program for less than One L-data comparator = 0x4e204e20 and program for greater than One L-data comparator = 0x9c409c40 and program for less than Both byte masks = 0x0 Both L-data comparators program to half-word mode or to word mode Result: The event will be correctly detected if the compiler chooses a load/store instruction with data size of half-word. If the compiler chooses load/store instructions with data size greater than half-word (word, multiple), there might be some false detections. These can be ignored only by the software that handles the breakpoints. The following figure illustrates this partially supported scenario.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-14
USERS MANUAL
Possible false detect on these half-words when using word/multiple
0x00000000 0x00000004 0x00000008 0x0000000C 0x00000010
Figure 21-2 Partially Supported Watchpoint/Breakpoint Example
21.3.1.4 Context Dependent Filter The CPU can be programmed to either recognize internal breakpoints only when the recoverable interrupt bit in the MSR is set (masked mode) or it can be programmed to always recognize internal breakpoints (non-masked mode). When the CPU is programmed to recognize internal breakpoints only when MSRRI = 1, it is possible to debug all parts of the code except when the machine status save/ restore registers (SRR0 and SRR1), DAR (data address register) and DSISR (data storage interrupt status register) are busy and, therefore, MSRRI = 0, (in the prologues and epilogues of interrupt/exception handlers). When the CPU is programmed always to recognize internal breakpoints, it is possible to debug all parts of the code. However, if an internal breakpoint is recognized when MSRRI = 0 (SRR0 and SRR1 are busy), the machine enters into a non-restartable state. For more information refer to 3.15.4 Interrupts When working in the masked mode, all internal breakpoints detected when MSRRI = 0 are lost. Watchpoints detected in this case are not counted by the debug counters. Watchpoints detected are always reported on the external pins, regardless of the value of the MSRRI bit. Out of reset, the CPU is in masked mode. Programming the CPU to be in non-masked mode is done by setting the BRKNOMSK bit in the LCTRL2 register. Refer to 21.7.8 L-Bus Support Control Register 2 The BRKNOMSK bit controls all internal breakpoints (I-breakpoints and L-breakpoints). 21.3.1.5 Ignore First Match In order to facilitate the debugger utilities continue and go from x, the ignore first match option is supported for instruction breakpoints. When an instruction breakpoint is first enabled (as a result of the first write to the instruction support control register or as a result of the assertion of the MSRRI bit when operating in the masked mode), the first instruction will not cause an instruction breakpoint if the ignore first match (IFM) bit in the instruction support control register (ICTRL) is set (used for continue).
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-15
USERS MANUAL

When the IFM bit is clear, every matched instruction can cause an instruction breakpoint (used for go from x). This bit is set by the software and cleared by the hardware after the first instruction breakpoint match is ignored. Load/store breakpoints and all counter generated breakpoints (instruction and load/store) are not affected by this mode. 21.3.1.6 Generating Six Compare Types Using the four compare types mentioned above (equal, not equal, greater than, less than) it is possible to generate also two more compare types: greater than or equal and less than or equal. Generating the greater than or equal compare type can be done by using the greater than compare type and programming the comparator to the needed value minus 1. Generating the less than or equal compare type can be done by using the less than compare type and programming the comparator to the needed value plus 1. This method does not work for the following boundary cases: Less than or equal of the largest unsigned number (1111...1) Greater than or equal of the smallest unsigned number (0000...0) Less than or equal of the maximum positive number when in signed mode (0111...1) Greater than or equal of the maximum negative number when in signed mode (1000...) These boundary cases need no special support because they all mean always true and can be programmed using the ignore option of the load/store watchpoint programming (refer to 21.3 Watchpoints and Breakpoints Support). 21.3.2 Instruction Support There are four instruction address comparators A,B,C, and D. Each is 30 bits long, generating two output signals: equal and less than. These signals are used to generate one of the following four events: equal, not equal, greater than, less than. The instruction watchpoints and breakpoint are generated using these events and according to user programming. Note that using the OR option enables out of range detect.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-16
USERS MANUAL

Table 21-6 Instruction Watchpoints Programming Options
Name IWP0 IWP1 IWP2 IWP3 Description First instruction watchpoint Second instruction watchpoint Third instruction watchpoint Fourth instruction watchpoint Programming options Comparator A Comparators (A&B) Comparator B Comparator (A | B) Comparator C Comparators (C&D) Comparator D Comparator (C | D)
Compare Type Comparator A eq lt Compare Type Logic
Control Bits
Comparator B eq lt Compare Type Logic A B Events Generator (A&B) (A | B) C D (C&D) (C | D) I-Breakpoint I-Watchpoint 3 AND-OR Logic I-Watchpoint 1 I-Watchpoint 2 I-Watchpoint 0
Comparator C eq lt Compare Type Logic
Comparator D eq lt Compare Type Logic
Figure 21-3 Instruction Support General Structure 21.3.2.1 Load/Store Support There are two load/store address comparators E, and F. Each compares the 32 address bits and the cycles attributes (read/write). The two least-significant bits are
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-17
USERS MANUAL

masked (ignored) whenever a word is accessed and the least-significant bit is masked whenever a half-word is accessed. (For more information refer to 21.3.1.2 Byte and Half-Word Working Modes). Each comparator generates two output signals: equal and less than. These signals are used to generate one of the following four events (one from each comparator): equal, not equal, greater than, less than. There are two load/store data comparators (comparators G,H) each is 32 bits wide and can be programmed to treat numbers either as signed values or as unsigned values. Each data comparator operates as four independent byte comparators. Each byte comparator has a mask bit and generates two output signals: equal and less than, if the mask bit is not set. Therefore, each 32 bit comparator has eight output signals. These signals are used to generate the equal and less than signals according to the compare size programmed by the user (byte, half-word, word). When operating in byte mode all signals are significant, when operating in half-word mode only four signals from each 32 bit comparator are significant. When operating in word mode only two signals from each 32 bit comparator are significant. From the new equal and less than signals and according to the compare type programmed by the user one of the following four match events are generated: equal, not equal, greater than, less than. Therefore, from the two 32-bit comparators eight match indications are generated: Gmatch[0:3], Hmatch[0:3]. According to the lower bits of the address and the size of the cycle, only match indications that were detected on bytes that have valid information are validated, the rest are negated. Note that if the cycle executed has a smaller size than the compare size (e.g., a byte access when the compare size is word or half-word) no match indication will be asserted. Using the match indication signals four load/store data events are generated in the following way. Table 21-7 Load/Store Data Events
Event Name G H (G&H) (G | H) Event Function1 (Gmatch0 | Gmatch1 | Gmatch2 | Gmatch3) (Hmatch0 | Hmatch1 | Hmatch2 | Hmatch3) ((Gmatch0 & Hmatch0) | (Gmatch1 & Hmatch1) | (Gmatch2 & Hmatch2) | (Gmatch3 & Hmatch3)) ((Gmatch0 | Hmatch0) | (Gmatch1 | Hmatch1) | (Gmatch2 | Hmatch2) | (Gmatch3 | Hmatch3))
NOTES: 1. & denotes a logical AND, | denotes a logical OR
The four load/store data events together with the match events of the load/store address comparators and the instruction watchpoints are used to generate the load/store watchpoints and breakpoint according to the users programming.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-18
USERS MANUAL

Table 21-8 Load/Store Watchpoints Programming Options
Name Description Instruction Events Programming Options IWP0, IWP1, IWP2, IWP3, ignore instruction events IWP0, IWP1, IWP2, IWP3, ignore instruction events L-address Events Programming Options Comparator E Comparator F Comparators (E&F) Comparators (E | F) ignore L-addr events Comparator E Comparator F Comparators (E&F) Comparators (E | F) ignore I-addr events L-data Events Programming Options Comparator G Comparator H Comparators (G&H) Comparators (G | H) ignore L-data events Comparator G Comparator H Comparators (G&H) Comparators (G | H) ignore L-data events
LWP0
First Load/store watchpoint
LWP1
Second Load/store watchpoint
Note that when programming the load/store watchpoints to ignore L-addr events and L-data events, it does not reduce the load/store watchpoints detection logic to be instruction watchpoint detection logic since the instruction must be a load/store instruction for the load/store watchpoint event to trigger.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-19
USERS MANUAL
MPC555
Data Cycle Size Comparator E lt Compare Type Type Logic Valid 3 Valid 2 Valid 1 Valid 0 Compare Size Compare Type eq lt eq Comparator F Compare Size add(30:31) Type Logic eq Size Logic lt eq lt eq lt lt eq Compare Type Logic Byte Qualifier Logic Instruction Watchpoints Control bits Events Generator (E | F) (E&F) F E G L-watchpoint 0 H (G&H) L-breakpoint (G | H) AND-OR Logic L-watchpoint 1 Events Generator eq Size Logic lt eq lt eq lt Compare Type Logic lt eq Byte Qualifier Logic
USERS MANUAL
/ MPC556
Byte Mask
comparator G eq Byte 0 lt eq Byte 1 lt eq Byte 2 lt eq Byte 3 lt
DEVELOPMENT SUPPORT
Figure 21-4 Load/Store Support General Structure
Byte Mask
Comparator H eq Byte 0 lt eq Byte 1 lt eq Byte 2 lt eq Byte 3 lt
MOTOROLA
21-20

21.3.3 Watchpoint Counters There are two 16-bit watchpoint counters. Each counter is able to count one of the instruction watchpoints or one of the load/store watchpoints. Both generate the corresponding breakpoint when they reach ZERO. When working in the masked mode, the counters do not count watchpoints detected when MSRRI = 0. See 21.3.1.4 Context Dependent Filter The counters value when counting watchpoints programmed on the actual instructions that alter the counters, are not predictable. Reading values from the counters when they are active, must be synchronized by inserting a sync instruction before the actual read is performed.
NOTE When programmed to count instruction watchpoints, the last instruction which decrements the counter to ZERO is treated like any other instruction breakpoint in the sense that it is not executed and the machine branches to the breakpoint exception routine BEFORE it executes this instruction. As a side effect of this behavior, the value of the counter inside the breakpoint exception routine equals ONE and not ZERO as might be expected. When programmed to count load/store watchpoints, the last instruction which decrements the counter to ZERO is treated like any other load/store breakpoint in the sense that it is executed and the machine branches to the breakpoint exception routine AFTER it executes this instruction. Therefore, the value of the counter inside the breakpoint exception routine equals ZERO. 21.3.3.1 Trap Enable Programming The trap enable bits can be programmed by regular software (only if MSRPR = 0) using THE mtspr instruction or on the fly using the special development port interface. For more information refer to section 21.5.6.5 Development Port Serial Communications Trap Enable Mode. The value used by the breakpoints generation logic is the bit wise OR of the software trap enable bits, (the bits written using the mtspr) and the development port trap enable bits (the bits serially shifted using the development port). All bits, the software trap enable bits and the development port trap enable bits, can be read from ICTRL and the LCTRL2 using mfspr. For the exact bits placement refer to 21.7.6 I-Bus Support Control Register and to 21.7.8 L-Bus Support Control Register 2 21.4 Development System Interface When debugging an existing system, it is sometimes desirable to be able to do so without the need to insert any changes in the existing system. In some cases it is not de-
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-21
USERS MANUAL

sired, or even impossible, to add load to the lines connected to the existing system. The development system interface of the CPU supports such a configuration. The development system interface of the CPU uses a dedicated serial port (the development port) and, therefore, does not need any of the regular system interfaces. Controlling the activity of the system from the development port is done when the CPU is in the debug mode. The development port is a relatively economical interface (three pins) that allows the development system to operate in a lower frequency than the frequency of the CPU. Note that it is also possible to debug the CPU using monitor debugger software, for more information refer to 21.6 Software Monitor Debugger Support. Debug mode is a state where the CPU fetches all instructions from the development port. In addition, when in debug mode, data can be read from the development port and written to the development port. This allows memory and registers to be read and modified by a development tool (emulator) connected to the development port. For protection purposes, two possible working modes are defined: debug mode enable and debug mode disable. These working modes are selected only during reset. For more information refer to 21.4.1.1 Debug Mode Enable vs. Debug Mode Disable The user can work in debug mode starting from reset or the CPU can be programmed to enter debug mode as a result of a predefined list of events. These events include all possible interrupts and exceptions in the CPU system, including the internal breakpoints, together with two levels of development port requests (masked and nonmasked) and one peripheral breakpoint request that can be generated by any one of the peripherals of the system (including internal and external modules). Each event can be programmed either to be treated as a regular interrupt that causes the machine to branch to its interrupt vector, or to be treated as a special interrupt that causes debug mode entry. When in debug mode an rfi instruction will return the machine to its regular work mode. The relationship between the debug mode logic to the rest of the CPU chip is shown in the following figure.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-22
USERS MANUAL
CPU Core ECR DER 32
SIU/ EBI
EXT BUS
Internal Bus
32 VFLS, FRZ
Development Port Control Logic DPIR
BKPT, TE, VSYNC
TECR
DPDR
Development Port Support Logic
35 DSCK DSDI Development Port Shift Register
DSDO
Figure 21-5 Functional Diagram of MPC555 / MPC556 Debug Mode Support The development port provides a full duplex serial interface for communications between the internal development support logic of the CPU and an external development tool. The development port can operate in two working modes: the trap enable mode and the debug mode. The trap enable mode is used in order to shift into the CPU internal development support logic the following control signals: 1. Instruction trap enable bits, used for on the fly programming of the instruction breakpoint 2. Load/store trap enable bits, used for on the fly programming of the load/store breakpoint 3. Non-maskable breakpoint, used to assert the non-maskable external breakpoint 4. Maskable breakpoint, used to assert the maskable external breakpoint 5. VSYNC, used to assert and negate VSYNC
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-23
USERS MANUAL

In debug mode the development port controls also the debug mode features of the CPU. For more information 21.5 Development Port 21.4.1 Debug Mode Support The debug mode of the CPU provides the development system with the following basic functions: Gives an ability to control the execution of the processor and maintain control on it under all circumstances. The development port is able to force the CPU to enter to the debug mode even when external interrupts are disabled. It is possible to enter debug mode immediately out of reset thus allowing the user even to debug a ROM-less system. The user can selectively define, using an enable register, the events that will cause the machine to enter into the debug mode. When in debug mode the user can detect the reason upon which the machine entered debug mode by reading a cause register. Entering into the debug mode in all regular cases is restartable in the sense that the user is able to continue to run his regular program from the location where it entered the debug mode. When in debug mode all instructions are fetched from the development port but load/store accesses are performed on the real system memory. Data Register of the development port is accessed using mtspr and mfspr instructions via special load/store cycles. (This feature together with the last one enables easy memory dump & load). Upon entering debug mode, the processor gets into the privileged state (MSRPR = 0). This allows execution of any instruction, and access to any storage location. An OR signal of all exception cause register (ECR) bits (ECR_OR) enables the development port to detect pending events while already in debug mode. An example is the ability of the development port to detect a debug mode access to a non existing memory space. The following figure illustrates the debug mode logic implemented in the CPU.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-24
USERS MANUAL
5 Decoder
Event
Exception Cause Register (ECR)
Event valid
Debug Enable Register (DER)
rfi
reset
set Q
freeze
ECR_OR debug mode enable
internal debug mode signal
Figure 21-6 Debug Mode Logic
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-25
USERS MANUAL

21.4.1.1 Debug Mode Enable vs. Debug Mode Disable For protection purposes two possible working modes are defined: debug mode enable and debug mode disable. These working modes are selected only during reset. Debug mode is enabled by asserting the DSCK pin during reset. The state of this pin is sampled three clocks before the negation of SRESET. NOTE Since SRESET negation is done by an external pull up resistor any reference here to SRESET negation time refers to the time the MPC555 / MPC556 releases SRESET. If the actual negation is slow due to large resistor, set up time for the debug port signals should be set accordingly.
If the DSCK pin is sampled negated, debug mode is disabled until a subsequent reset when the DSCK pin is sampled in the asserted state. When debug mode is disabled the internal watchpoint/breakpoint hardware will still be operational and may be used by a software monitor program for debugging purposes. When working in debug mode disable, all development support registers (see list in Table 21-14) are accessible to the supervisor code (MSRPR = 0) and can be used by a monitor debugger software. However, the processor never enters debug mode and, therefore, the exception cause register (ECR) and the debug enable register (DER) are used only for asserting and negating the freeze signal. For more information on the software monitor debugger support refer to 21.6 Software Monitor Debugger Support. When working in debug mode enable, all development support registers are accessible only when the CPU is in debug mode. Therefore, even supervisor code that may be still under debug cannot prevent the CPU from entering debug mode. The development system has full control of all development support features of the CPU through the development port. Refer to Table 21-16 21.4.1.2 Entering Debug Mode Entering debug mode can be a result of a number of events. All events have a programmable enable bit so the user can selectively decide which events result in debug mode entry and which in regular interrupt handling. Entering debug mode is also possible immediately out of reset, thus allowing the user to debug even a ROM-less system. Using this feature is possible by special programming of the development port during reset. If the DSCK pin continues to be asserted following SRESET negation (after enabling debug mode) the processor will take a breakpoint exception and go directly to debug mode instead of fetching the reset vector. To avoid entering debug mode following reset, the DSCK pin must be negated no later than seven clock cycles after SRESET negates. In this case, the processor will jump to the reset vector and begin normal execution. When entering debug mode immediately after reset, bit 31 (development port interrupt) of the exception cause register (ECR) is set.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-26
USERS MANUAL
11
12
13
14
15
16
17
SRESET
Figure 21-7 Debug Mode Reset Configuration When debug mode is disabled all events result in regular interrupt handling.
MPC555
/ MPC556
CLK OUT
DEVELOPMENT SUPPORT
DSCK
DSCK asserts high while SRESET asserted to enable debug mode operation.
DSCK asserts high following SRESET negation to enable debug mode immediately.
10
MOTOROLA 21-27
USERS MANUAL

The internal freeze signal is asserted whenever an enabled event occurs, regardless if debug mode is enabled or disabled. The internal freeze signal is connected to all relevant internal modules. These modules can be programmed to stop all operations in response to the assertion of the freeze signal. Refer to 21.6.1 Freeze Indication. The freeze indication is negated when exiting debug mode. Refer to 21.4.1.6 Exiting Debug Mode The following list contains the events that can cause the CPU to enter debug mode. Each event results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. The reset values of the enable bits let the user, in most cases, to use of the debug mode features without the need to program the debug enable register (DER). For more information refer to 21.7.12 Debug Enable Register (DER).
NMI exception as a result of the assertion of the IRQ0_B pin. For more information refer to 3.15.4.1 System Reset Interrupt Check stop. Refer to 21.4.1.3 The Check Stop State and Debug Mode Machine check exception Implementation specific instruction protection error Implementation specific data protection error External interrupt, recognized when MSREE = 1 Alignment interrupt Program interrupt Floating point unavailable exception Floating point assist exception Decrementer exception, recognized when MSREE = 1 System call exception Trace, asserted when in single trace mode or when in branch trace mode (refer to 3.15.4.10 Trace Interrupt) Implementation dependent software emulation exception Instruction breakpoint, when breakpoints are masked (BRKNOMSK bit in the LCTRL2 is clear) recognized only when MSRRI = 1, when breakpoints are not masked (BRKNOMSK bit in the LCTRL2 is set) always recognized Load/store breakpoint, when breakpoints are masked (BRKNOMSK bit in the LCTRL2 is cleared) recognized only when MSRRI = 1, when breakpoints are not masked (BRKNOMSK bit in the LCTRL2 is set) always recognized Peripherals breakpoint, from the development port, internal and external modules. are recognized only when MSRRI = 1. Development port non-maskable interrupt, as a result of a debug station request. Useful in some catastrophic events like an endless loop when MSRRI = 0. As a result of this event the machine may enter a non-restartable state, for more information refer to 3.15.4 Interrupts.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-28
USERS MANUAL

The processor enters into the debug mode state when at least one of the bits in the exception cause register (ECR) is set, the corresponding bit in the debug enable register (DER) is enabled and debug mode is enabled. When debug mode is enabled and an enabled event occurs, the processor waits until its pipeline is empty and then starts fetching the next instructions from the development port. For information on the exact value of machine status save/restore registers (SRR0 and SRR1) refer to 3.15.4 Interrupts When the processor is in debug mode the freeze indication is asserted thus allowing any peripheral that is programmed to do so to stop. The fact that the CPU is in debug mode is also broadcast to the external world using the value b11 on the VFLS pins. NOTE The freeze signal can be asserted by software when debug mode is disabled. The development port should read the value of the exception cause register (ECR) in order to get the cause of the debug mode entry. Reading the exception cause register (ECR) clears all its bits. 21.4.1.3 The Check Stop State and Debug Mode The CPU enters the check stop state if the machine check interrupt is disabled (MSRME = 0) and a machine check interrupt is detected. However, if a machine check interrupt is detected when MSRME = 0, debug mode is enabled and the check stop enable bit in the debug enable register (DER) is set, the CPU enters debug mode rather then the check stop state. The different actions taken by the CPU when a machine check interrupt is detected are shown in the following table. Table 21-9 The Check Stop State and Debug Mode
MSRME 0 1 0 0 1 1 Debug Mode Enable 0 0 1 1 1 1 CHSTPE1 X X 0 1 X X MCIE2 X X X X 0 1 Action Performed by the CPU when Detecting a Machine Check Interrupt Enter the check stop state Branch to the machine check interrupt Enter the check stop state Enter Debug Mode Branch to the machine check interrupt Enter Debug Mode Exception Cause Register (ECR) Value 0x20000000 0x10000000 0x20000000 0x20000000 0x10000000 0x10000000
NOTES: 1. Check stop enable bit in the debug enable register (DER) 2. Machine check interrupt enable bit in the debug enable register (DER)
21.4.1.4 Saving Machine State upon Entering Debug Mode If entering debug mode was as a result of any load/store type exception, and therefore the DAR (data address register) and DSISR (data storage interrupt status register)
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-29
USERS MANUAL

have some significant value, these two registers must be saved before any other operation is performed. Failing to save these registers may result in loss of their value in case of another load/store type exception inside the development software. Since exceptions are treated differently when in debug mode (refer to 21.4.1.5 Running in Debug Mode), there is no need to save machine status save/restore zero register (SRR0) and machine status save/restore one register (SRR1). 21.4.1.5 Running in Debug Mode When running in debug mode all fetch cycles access the development port regardless of the actual address of the cycle. All load/store cycles access the real memory system according to the cycles address. The data register of the development port is mapped as a special control register therefore it is accessed using mtspr and mfspr instructions via special load/store cycles (refer to 21.7.13 Development Port Data Register (DPDR)). Exceptions are treated differently when running in debug mode. When already in debug mode, upon recognition of an exception, the exception cause register (ECR) is updated according to the event that caused the exception, a special error indication (ECR_OR) is asserted for one clock cycle to report to the development port that an exception occurred and execution continues in debug mode without any change in SRR0 and SRR1. ECR_OR is asserted before the next fetch occurs to allow the development system to detect the excepting instruction. Not all exceptions are recognized when in debug mode. Breakpoints and watchpoints are not generated by the hardware when in debug mode (regardless of the value of MSRRI). Upon entering debug mode MSREE is cleared by the hardware thus forcing the hardware to ignore external and decrementer interrupts. Setting the MSREE bit while in debug mode, (by the debug software), is strictly forbidden. The reason for this restriction is that the external interrupt event is a level signal, and since the CPU only reports exceptions while in debug mode but do not treat them, the CPU does not clear the MSREE bit and, therefore, this event, if enabled, is recognized again every clock cycle. When the ECR_OR signal is asserted the development station should investigate the exception cause register (ECR) in order to find out the event that caused the exception. Since the values in SRR0 and SRR1 do not change if an exception is recognized while already in debug mode, they only change once when entering debug mode, saving them when entering debug mode is not necessary. 21.4.1.6 Exiting Debug Mode The rfi instruction is used to exit from debug mode in order to return to the normal processor operation and to negate the freeze indication. The development system may monitor the freeze status to make sure the MPC555 / MPC556 is out of debug mode. It is the responsibility of the software to read the exception cause register (ECR) before
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-30
USERS MANUAL

performing the rfi. Failing to do so will force the CPU to immediately re-enter to debug mode and to re-assert the freeze indication in case an asserted bit in the interrupt cause register (ECR) has a corresponding enable bit set in the debug enable register (DER). 21.5 Development Port The development port provides a full duplex serial interface for communications between the internal development support logic including debug mode and an external development tool. The relationship of the development support logic to the rest of the CPU chip is shown in Figure 21-5. The development port support logic is shown as a separate block for clarity. It is implemented as part of the SIU module.
21.5.1 Development Port Pins The following development port pin functions are provided: 1. Development serial clock (DSCK) 2. Development serial data in (DSDI) 3. Development serial data out (DSDO) 21.5.2 Development Serial Clock The development serial clock (DSCK) is used to shift data into and out of the development port shift register. At the same time, the new most significant bit of the shift register is presented at the DSDO pin. In all further discussions references to the DSCK signal imply the internal synchronized value of the clock. The DSCK input must be driven either high or low at all times and not allowed to float. A typical target environment would pull this input low with a resistor. The clock may be implemented as a free running clock or as gated clock. As discussed in section 21.5.6.5 Development Port Serial Communications Trap Enable Mode and section 21.5.6.8 Development Port Serial Communications Debug Mode, the shifting of data is controlled by ready and start signals so the clock does not need to be gated with the serial transmissions. The DSCK pin is also used at reset to enable debug mode and immediately following reset to optionally cause immediate entry into debug mode following reset. 21.5.3 Development Serial Data In Data to be transferred into the development port shift register is presented at the development serial data in (DSDI) pin by external logic. To be sure that the correct value is used internally. When driven asynchronous (synchronous) with the system clock, the data presented to DSDI must be stable a setup time before the rising edge of DSCK (CLKOUT) and a hold time after the rising edge of DSCK (CLKOUT).
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-31
USERS MANUAL

The DSDI pin is also used at reset to control the overall chip configuration mode and to determine the development port clock mode. See section 21.5.6.4 Development Port Serial Communications Clock Mode Selection for more information. 21.5.4 Development Serial Data Out The debug mode logic shifts data out of the development port shift register using the development serial data out (DSDO) pin. All transitions on DSDO are synchronous with DSCK or CLKOUT depending on the clock mode. Data will be valid a setup time before the rising edge of the clock and will remain valid a hold time after the rising edge of the clock. Refer to Table 21-12 for DSDO data meaning.
21.5.5 Freeze Signal The freeze indication means that the processor is in debug mode (i.e., normal processor execution of user code is frozen). On the MPC555 / MPC556, the freeze state can be indicated by three different pins. The FRZ signal is generated synchronously with the system clock. This indication may be used to halt any off-chip device while in debug mode as well as a handshake means between the debug tool and the debug port. The internal freeze status can also be monitored through status in the data shifted out of the debug port. 21.5.5.1 SGPIO6/FRZ/PTR Pin The SGPIO6/FRZ/PTR pin powers up as the PTR function and its function is controlled by the GPC bits in the SIUMCR. 21.5.5.2 IWP[0:1]/VFLS[0:1] Pins The IWP[0:1]/VFLS[0:1] pins power up as the VFLS[0:1] function and their function can be changed via the DBGC bits in the SIUMCR (see 6.13.1.1 SIU Module Configuration Register). They can also be set via the reset configuration word (See 7.5.2 Hard Reset Configuration Word). The FRZ state is indicated by the value b11 on the VFLS[0:1] pins. 21.5.5.3 VFLS[0:1]_MPIO32B[3:4] Pins The VFLS[0:1]_MPIO32B[3:4] Pins power up as the MPIO32B[3:4] function and their function can be changed via the VFLS bit in the MIOS1TPCR register (see section 15.15.1.1). The FRZ state is indicated by the value b11 on the VFLS[0:1] pins. 21.5.6 Development Port Registers The development port consists logically of the three registers: development port instruction register (DPIR), development port data register (DPDR), and trap enable control register (TECR). These registers are physically implemented as two registers, development port shift register and trap enable control register. The development port shift register acts as both the DPIR and DPDR depending on the operation being per-
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-32
USERS MANUAL

formed. It is also used as a temporary holding register for data to be stored into the TECR. These registers are discussed below in more detail. 21.5.6.1 Development Port Shift Register The development port shift register is a 35-bit shift register. Instructions and data are shifted into it serially from DSDI using DSCK (or CLKOUT depending on the debug port clock mode, refer to 21.5.6.4 Development Port Serial Communications Clock Mode Selection) as the shift clock. These instructions or data are then transferred in parallel to the CPU, the trap enable control register (TECR). When the processor enters debug mode it fetches instructions from the DPIR which causes an access to the development port shift register. These instructions are serially loaded into the shift register from DSDI using DSCK (or CLKOUT) as the shift clock. In a similar way, data is transferred to the CPU by moving it into the shift register which the processor reads as the result of executing a move from special purpose register DPDR instruction. Data is also parallel-loaded into the development port shift register from the CPU by executing a move to special purpose register DPDR instruction. It is then shifted out serially to DSDO using DSCK (or CLKOUT) as the shift clock. 21.5.6.2 Trap Enable Control Register The trap enable control register is a 9-bit register that is loaded from the development port shift register. The contents of the control register are used to drive the six trap enable signals, the two breakpoint signals, and the VSYNC signal to the CPU. The transfer data to trap enable control register commands will cause the appropriate bits to be transferred to the control register. The trap enable control register is not accessed by the CPU, but instead supplies signals to the CPU. The trap enable bits, VSYNC bit, and the breakpoint bits of this register are loaded from the development port shift register as the result of trap enable mode transmissions. The trap enable bits are reflected in ICTRL and LCTRL2 special registers. See 21.7.6 I-Bus Support Control Register and 21.7.8 L-Bus Support Control Register 2. 21.5.6.3 Development Port Registers Decode The development port shift register is selected when the CPU accesses DPIR or DPDR. Accesses to these two special purpose registers occur in debug mode and appear on the internal bus as an address and the assertion of an address attribute signal indicating that a special purpose register is being accessed. The DPIR register is read by the CPU to fetch all instructions when in debug mode and the DPDR register is read and written to transfer data between the CPU and external development tools. The DPIR and DPDR are pseudo registers. Decoding either of these registers will cause the development port shift register to be accessed. The debug mode logic knows whether the CPU is fetching instructions or reading or writing data. If what the CPU is expecting and what the register receives from the serial port do not match (instruction instead of data) the mismatch is used to signal a sequence error to the external development tool.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-33
USERS MANUAL

21.5.6.4 Development Port Serial Communications Clock Mode Selection All of the serial transmissions are clock transmissions and are therefore synchronous communications. However, the transmission clock may be either synchronous or asynchronous with the system clock (CLKOUT). The development port allows the user to select two methods for clocking the serial transmissions. The first method allows the transmission to occur without being externally synchronized with CLKOUT, in this mode a serial clock DSCK must be supplied to the MPC555 / MPC556. The other communication method requires a data to be externally synchronized with CLKOUT. The first clock mode is called asynchronous clock since the input clock (DSCK) is asynchronous with CLKOUT. To be sure that data on DSDI is sampled correctly, transitions on DSDI must occur a setup time ahead and a hold time after the rising edge of DSCK. This clock mode allows communications with the port from a development tool which does not have access to the CLKOUT signal or where the CLKOUT signal has been delayed or skewed. Refer to the timing diagram in Figure 21-8 The second clock mode is called synchronous self clock. It does not require an input clock. Instead the port is timed by the system clock. The DSDI input is required to meet setup and hold time requirements with respect to CLKOUT rising edge. The data rate for this mode is always the same as the system clock. Refer to the timing diagram in Figure 21-9. The selection of clock or self clock mode is made at reset. The state of the DSDI input is latched eight clocks after SRESET negates. If it is latched low, asynchronous clock mode is enabled. If it is latched high then synchronous self clock mode is enabled. Since DSDI is used to select the development port clocking scheme, it is necessary to prevent any transitions on DSDI during this time from being recognized as the start of a serial transmission. The port will not begin scanning for the start bit of a serial transmission until 16 clocks after the negation of SRESET. If DSDI is asserted 16 clocks after SRESET negation, the port will wait until DSDI is negated to begin scanning for the start bit.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-34
USERS MANUAL
MPC555
START MODE CNTRL DI<0> DI <N-2> DI <N-1> DI <N> READY S<0> S<1> DO<0> DO <N-2> DO <N-1> DO <N> Debug Port detects the start bit on DSDI and follows the ready bit with two status bits and 7 or 32 output data bits. Development Tool drives the start bit on DSDI (after detecting ready bit on DSDO when in debug mode). The start bit is immediately followed by a mode bit and a control bit and then 7 or 32 input data bits. Debug Port drives ready bit onto DSDO when ready for a new transmission. NOTE: DSCK and DSDI transitions are not required to be synchronous with CLKOUT.
USERS MANUAL
/ MPC556
DSCK
DSDI
DEVELOPMENT SUPPORT
Figure 21-8 Asynchronous Clock Serial Communications
DSDO
MOTOROLA
21-35
MPC555
1 START MODE CNTRL DI<0> DI<1> DI DI DI DI< <N-3> <N-2> <N-1> DI <N> READY S<0> S<1> DO<0> DO<1> DO DO DO <N-3> <N-2> <N-1> DO <N>
USERS MANUAL
Debug Port detects the start bit on DSDI and follows the ready bit with two status bits and 7 or 32 output data bits. Development Tool drives the start bit on DSDI (after detecting ready bit on DSDO when in debug mode). The start bit is immediately followed by a mode bit and a control bit and then 7 or 32 input data bits. Debug Port drives ready bit onto DSDO when CPU starts a read of DPIR or DPDR.
/ MPC556
CLK OUT
DSDI
DEVELOPMENT SUPPORT
Figure 21-9 Synchronous Self Clock Serial Communication
DSDO
MOTOROLA
21-36
MPC555
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
USERS MANUAL
/ MPC556
CLK OUT
SRESET
DSDI
DEVELOPMENT SUPPORT
CLKEN
Figure 21-10 Enabling Clock Mode Following Reset
DSDI negates following SRESET negation to enable clocked mode.
Internal clock enable signal asserts 8 clocks after SRESET negation if DSDI is negated. This enables clocked mode.
First Start bit detected after DSDI negation (self clocked mode)
MOTOROLA
21-37

21.5.6.5 Development Port Serial Communications Trap Enable Mode When in not in debug mode the development port starts communications by setting DSDO (the MSB of the 35-bit development port shift register) low to indicate that all activity related to the previous transmission are complete and that a new transmission may begin. The start of a serial transmission from an external development tool to the development port is signaled by a start bit. A mode bit in the transmission defines the transmission as either a trap enable mode transmission or a debug mode transmission. If the mode bit is set the transmission will only be 10 bits long and only seven data bits will be shifted into the shift register. These seven bits will be latched into the TECR. A control bit determines whether the data is latched into the trap enable and VSYNC bits of the TECR or into the breakpoints bits of the TECR. 21.5.6.6 Serial Data into Development Port Trap Enable Mode The development port shift register is 35 bits wide but trap enable mode transmissions only use the start/ready bit, a mode/status bit, a control/status bit, and the seven least significant data bits. The encoding of data shifted into the development port shift register (through the DSDI pin) is shown in Table 21-10 and Table 21-11 below: Table 21-10 Trap Enable Data Shifted into Development Port Shift Register
1st Start Mode Control 2nd 3rd 4th 1st 2nd VSYNC Function Transfer Data to Trap Enable Control Register - - - - - - Instruction- - - - - Watchpoint Trap Enables 1 1 0 0 = disabled; 1 = enabled - - Data- -
Table 21-11 Debug Port Command Shifted Into Development Port Shift Register
Start Mode Control Extended Opcode x 0 1 1 1 1 1 x x x 0 1 x x 0 1 x 0 1 x x Major Opcode 00000 00001 00010 00011 00011 00011 11111 11111 11111 11111 NOP Hard Reset request Soft Reset request Reserved End Download procedure Start Download procedure Negate Maskable breakpoint. Assert Maskable breakpoint. Negate Non Maskable breakpoint. Assert Non Maskable breakpoint. Function
00100... 11110 Reserved
The watchpoint trap enables and VSYNC functions are described in section 21.3 Watchpoints and Breakpoints Support and section 21.2 Program Flow Tracking.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-38
USERS MANUAL

The debug port command function allows the development tool to either assert or negate breakpoint requests, reset the processor, activate or deactivate the fast download procedure. 21.5.6.7 Serial Data Out of Development Port Trap Enable Mode In trap enable mode the only response out of the development port is sequencing error. Data that can come out of the development port is shown in Table 21-12. Valid data from CPU and CPU interrupt status cannot occur in trap enable mode. Table 21-12 Status / Data Shifted Out of Development Port Shift Register
Data Ready (0) (0) (0) (0) Status [0:1] 0 0 1 1 0 1 0 1 Freeze status1 Download Procedure in progress2 Bit 0 Bit 1 Bits 2:31 or 2:6 (Depending on Input Mode) Data 1s 1s 1s Function Valid Data from CPU Sequencing Error CPU Interrupt Null
NOTES: 1. The Freeze status is set to (1) when the CPU is in debug mode and to (0) otherwise. 2. The Download Procedure in progress status is asserted (0) when Debug port in the Download procedure and is negated (1) otherwise.
When not in debug mode the sequencing error encoding indicates that the transmission from the external development tool was a debug mode transmission. When a sequencing error occurs the development port will ignore the data shifted in while the sequencing error was shifting out. It will be treated as a NOP function. Finally, the null output encoding is used to indicate that the previous transmission did not have any associated errors. When not in debug mode, ready will be asserted at the end of each transmission. If debug mode is not enabled and transmission errors can be guaranteed not to occur, the status output is not needed. 21.5.6.8 Development Port Serial Communications Debug Mode When in debug mode the development port starts communications by setting DSDO low to indicate that the CPU is trying to read an instruction from DPIR or data from DPDR. When the CPU writes data to the port to be shifted out the ready bit is not set. The port waits for the CPU to read the next instruction before asserting ready. This allows duplex operation of the serial port while allowing the port to control all transmissions from the external development tool. After detecting this ready status the external development tool begins the transmission to the development port with a start bit (logic high) on the DSDI pin.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-39
USERS MANUAL

21.5.6.9 Serial Data Into Development Port In debug mode the 35 bits of the development port shift register are interpreted as a start/ready bit, a mode/status bit, a control/status bit, and 32 bits of data. All instructions and data for the CPU are transmitted with the mode bit cleared indicating a 32bit data field. The encoding of data shifted into the development port shift register (through the DSDI pin) is shown below in Table 21-13
.
Table 21-13 Debug Instructions / Data Shifted Into Development Port Shift Register
Start 1 Mode 0 0 Control 0 1 enable1 Instruction / Data (32 Bits) Bits 0:6 Bits 7:31 CPU Instruction CPU Data Function Transfer Instruction to CPU Transfer Data to CPU Transfer data to Trap Enable Control Register Negate breakpoint requests to the CPU. nop
Trap
Not exist
1 1
1 1
1 1
0011111 0
Not exist Not exist
NOTES: 1. Refer to Table 21-10
Data values in the last two functions other than those specified are reserved. All transmissions from the debug port on DSDO begin with a 0 or ready bit. This indicates that the CPU is trying to read an instruction or data from the port. The external development tool must wait until it sees DSDO go low to begin sending the next transmission. The control bit differentiates between instructions and data and allows the development port to detect that an instruction was entered when the CPU was expecting data and vice versa. If this occurs a sequence error indication is shifted out in the next serial transmission. The trap enable function allows the development tool to transfer data to the trap enable control register. The debug port command function allows the development tool to either negate breakpoint requests, reset the processor, activate or deactivate the fast down load procedure. The NOP function provides a null operation for use when there is data or a response to be shifted out of the data register and the appropriate next instruction or command will be determined by the value of the response or data shifted out.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-40
USERS MANUAL

21.5.6.10 Serial Data Out of Development Port The encoding of data shifted out of the development port shift register in debug mode (through the DSDO pin) is the same as for trap enable mode and is shown in Table 21-12. Valid data encoding is used when data has been transferred from the CPU to the development port shift register. This is the result of an instruction to move the contents of a general purpose register to the debug port data register (DPDR). The valid data encoding has the highest priority of all status outputs and will be reported even if an interrupt occurs at the same time. Since it is not possible for a sequencing error to occur and also have valid data there is no priority conflict with the sequencing error status. Also, any interrupt that is recognized at the same time that there is valid data is not related to the execution of an instruction. Therefore, a valid data status will be output and the interrupt status will be saved for the next transmission. The sequencing error encoding indicates that the inputs from the external development tool are not what the development port and/or the CPU was expecting. Two cases could cause this error: 1. The processor was trying to read instructions and there was data shifted into the development port, or 2. The processor was trying to read data and there was instruction shifted into the development port. The port will terminate the read cycle with a bus error. This bus error will cause the CPU to signal that an interrupt (exception) occurred. Since a status of sequencing error has a higher priority than exception, the port will report the sequencing error first, and the CPU interrupt on the next transmission. The development port will ignore the command, instruction, or data shifted in while the sequencing error or CPU interrupt is shifted out. The next transmission after all error status is reported to the port should be a new instruction, trap enable or command (possibly the one that was in progress when the sequencing error occurred). The interrupt-occurred encoding is used to indicate that the CPU encountered an interrupt during the execution of the previous instruction in debug mode. Interrupts may occur as the result of instruction execution (such as unimplemented opcode or arithmetic error), because of a memory access fault, or from an unmasked external interrupt. When an interrupt occurs the development port will ignore the command, instruction, or data shifted in while the interrupt encoding was shifting out. The next transmission to the port should be a new instruction, trap enable or debug port command. Finally, the null encoding is used to indicate that no data has been transferred from the CPU to the development port shift register. 21.5.6.11 Fast Download Procedure The download procedure is used to download a block of data from the debug tool into system memory. This procedure can be accomplished by repeating the following sequence of transactions from the development tool to the debug port for the number of data words to be down loaded:
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-41
USERS MANUAL
INIT:Save RX, RY RY <- Memory Block address- 4 repeat:mfsprRX, DPDR DATA word to be moved to memory stwuRX, 0x4(RY) until here
Restore RX,RY
Figure 21-11 Download Procedure Code Example For large blocks of data this sequence may take significant time to complete. The fast download procedure of the debug port may be used to reduce this time. This time reduction is achieved by eliminating the need to transfer the instructions in the loop to the debug port. The only transactions needed are those required to transfer the data to be placed in system memory. Figure 21-12 and Figure 21-13 illustrate the time benefit of the fast download procedure.
External Transaction Internal Activity
MFSPR
DATA
STWU
Figure 21-12 Slow Download Procedure Loop
External Transaction Internal Activity
DATA
Figure 21-13 Fast Download Procedure Loop
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-42
USERS MANUAL

The sequence of the instructions used in the fast download procedure is the one illustrated in Figure 21-11 with RX = r31 and RY = r30. This sequence is repeated infinitely until the end download procedure command is issued to the debug port. Note that, the internal general purpose register 31 is used for temporary storage data value. Before beginning the fast download procedure by the start download procedure command, The value of the first memory block address, 4, must be written to the general purpose register 30. To end a download procedure, an end download procedure command should be issued to the debug port, and then, additional DATA transaction should be sent by the development tool. This data word will NOT be placed into the system memory, but it is needed to stop the procedure gracefully.
21.6 Software Monitor Debugger Support When in debug mode disable, a software monitor debugger can make use of all of the development support features defined in the CPU. When debug mode is disabled all events result in regular interrupt handling, i.e. the processor resumes execution in the corresponding interrupt handler. The exception cause register (ECR) and the debug enable register (DER) only influence the assertion and negation of the freeze signal. 21.6.1 Freeze Indication The internal freeze signal is connected to all relevant internal modules. These modules can be programmed to stop all operations in response to the assertion of the freeze signal. In order to enable a software monitor debugger to broadcast the fact that the debug software is now executed, it is possible to assert and negate the internal freeze signal also when debug mode is disabled. The assertion and negation of the freeze signal when in debug mode disable is controlled by the exception cause register (ECR) and the debug enable register (DER) as described in Figure 21-6. In order to assert the freeze signal the software needs to program the relevant bits in the debug enable register (DER). In order to negate the freeze line the software needs to read the exception cause register (ECR) in order to clear it and perform an rfi instruction. If the exception cause register (ECR) is not cleared before the rfi is performed the freeze signal is not negated. Therefore it is possible to nest inside a software monitor debugger without affecting the value of the freeze line although rfi may be performed a few times. Only before the last rfi the software needs to clear the exception cause register (ECR). The above mechanism enables the software to accurately control the assertion and the negation of the freeze signal. 21.7 Development Support Registers Table 21-14 lists the registers used for development support. The registers are accessed with the mtspr and mfspr instructions. / MPC556
MPC555
DEVELOPMENT SUPPORT
MOTOROLA 21-43
USERS MANUAL

Table 21-14 Development Support Programming Model
SPR Number (Decimal) 144 145 146 147 148 Name Comparator A Value Register (CMPA) See Table 21-17 for bit descriptions. Comparator B Value Register (CMPB) See Table 21-17 for bit descriptions. Comparator C Value Register (CMPC) See Table 21-17 for bit descriptions. Comparator D Value Register (CMPD) See Table 21-17 for bit descriptions. Exception Cause Register (ECR) See Table 21-27 for bit descriptions. Debug Enable Register (DER) See Table 21-28 for bit descriptions. Breakpoint Counter A Value and Control Register (COUNTA) See Table 21-25 for bit descriptions. Breakpoint Counter B Value and Control Register (COUNTB) See Table 21-26 for bit descriptions. Comparator E Value Register (CMPE) See Table 21-18 for bit descriptions. Comparator F Value Register (CMPF) See Table 21-18 for bit descriptions. Comparator G Value Register (CMPG) See Table 21-20 for bit descriptions. Comparator H Value Register (CMPH) See Table 21-20 for bit descriptions. L-Bus Support Control Register 1 (LCTRL1) See Table 21-23 for bit descriptions. L-Bus Support Control Register 2 (LCTRL2) See Table 21-24 for bit descriptions. I-Bus Support Control Register (ICTRL) See Table 21-21 for bit descriptions. Breakpoint Address Register (BAR) See Table 21-19 for bit descriptions. Development Port Data Register (DPDR) See 21.7.13 Development Port Data Register (DPDR) for bit descriptions.
149 150 151 152 153 154 155 156 157 158 159
630
21.7.1 Register Protection Table 21-15 and Table 21-16 summarize protection features of development support registers during read and write accesses, respectively.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-44
USERS MANUAL

Table 21-15 Development Support Registers Read Access Protection
MSR[PR] Debug Mode Enable 0 In Debug Mode Result Read is performed. ECR is cleared when read. Reading DPDR yields indeterminate data. Read is performed. ECR is not cleared when read. Reading DPDR yields indeterminate data. Read is performed. ECR is cleared when read. Program exception is generated. Read is not performed. ECR is not cleared when read.
Table 21-16 Development Support Registers Write Access Protection

MSR[PR] Debug Mode Enable 0 In Debug Mode Write is performed. Write to ECR is ignored. Writing to DPDR is ignored. Write is not performed. Writing to DPDR is ignored. Write is performed. Write to ECR is ignored. Write is not performed. Program exception is generated. Result
0 0 1
1 1 X
0 1 X
21.7.2 Comparator AD Value Registers (CMPACMPD) CMPACMPD Comparator AD Value Register

0 1 2 3 4 5 6 7 8 9 10 11 CMPAD RESET: UNAFFECTED
SPR 144 SPR 147

12 13 14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CMPAD RESET: UNAFFECTED
RESERVED
Table 21-17 CMPA-CMPD Bit Descriptions

Bits 0:29 30:31 Mnemonic CMPAD Address bits to be compared Reserved Description
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-45
USERS MANUAL

These registers are unaffected by reset. 21.7.3 Comparator EF Value Registers CMPECMPF Comparator EF Value Registers
0 1 2 3 4 5 6 7 8 9 CMPEF RESET: UNAFFECTED
SPR 152, 153
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Table 21-18 CMPE-CMPF Bit Descriptions

Bits Mnemonic CMPV Address bits to be compared Description
0:31
These registers are unaffected by reset. 21.7.4 Breakpoint Address Register (BAR) BAR Breakpoint Address Register
0 1 2 3 4 5 6 7 8 9 CMPEF RESET: UNAFFECTED
SPR 159
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Table 21-19 BAR Bit Descriptions

Bits 0:31 Mnemonic BARV[0:31] Description The address of the load/store cycle that generated the breakpoint
21.7.5 Comparator GH Value Registers (CMPGCMPH) CMPGCMPH Comparator GH Value Registers

0 1 2 3 4 5 6 7 8 9 CMPGH RESET: UNAFFECTED
SPR 154, 155
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Table 21-20 CMPG-CMPH Bit Descriptions

Bits 0:31 Mnemonic CMPGH Data bits to be compared Description
These registers are unaffected by reset.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-46
USERS MANUAL

21.7.6 I-Bus Support Control Register ICTRL I-Bus Support Control Register
0 1 CTA RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 3 4 CTB 5 6 7 CTC 8 9 10 CTD 11 12 IWP0 13
SPR 158
14 IWP1 15
16 IWP2
17
18 IWP3
19
20
21
22
23
24
25 DIWP 1 EN
26 DIWP 2 EN
27 DIWP 3 EN
28 IIFM
29
30 ISCT_SER*
31
SIWP0 SIWP1 SIWP2 SIWP3 DIWP0 EN EN EN EN EN
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
*Changing the instruction show cycle programming starts to take effect only from the second instruction after the actual mtspr to ICTRL.
If the processor aborts a fetch of the target of a direct branch (due to an exception), the target is not always visible on the external pins. Program trace is not affected by this phenomenon.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-47
USERS MANUAL

Table 21-21 ICTRL Bit Descriptions
Bits 0:2 3:5 6:8 9:11 12:13 Mnemonic CTA CTB CTC CTD IWP0 Description Compare type of comparator A Compare type of comparator B Compare type of comparator C Compare type of comparator D I-bus 1st watchpoint programming Function 0xx = not active (reset value) 100 = equal 101 = less than 110 = greater than 111 = not equal 0x = not active (reset value) 10 = match from comparator A 11 = match from comparators (A&B)
14:15
W1
0x = not active (reset value) I-bus 2nd watchpoint programming 10 = match from comparator B 11 = match from comparators (A | B) I-bus 3rd watchpoint programming 0x = not active (reset value) 10 = match from comparator C 11 = match from comparators (C&D) 0x = not active (reset value) 10 = match from comparator D 11 = match from comparators (C | D)
16:17
IWP2
18:19 20 21 22 23
IWP3 SIWP0EN SIWP1EN SIWP2EN SIWP3EN
I-bus 4th watchpoint programming Software trap enable selection of the 1st I-bus watchpoint Software trap enable selection of the 2nd I-bus watchpoint Software trap enable selection of the 3rd I-bus watchpoint Software trap enable selection of the 4th I-bus watchpoint Development port trap enable selection of the 1st I-bus watchpoint (read only bit) Development port trap enable selection of the 2nd I-bus watchpoint (read only bit) Development port trap enable selection of the 3rd I-bus watchpoint (read only bit) Development port trap enable selection of the 4th I-bus watchpoint (read only bit) Ignore first match, only for I-bus breakpoints
0 = trap disabled (reset value) 1 = trap enabled
24
DIWP0EN
25
DIWP1EN
0 = trap disabled (reset value) 1 = trap enabled
26
DIWP2EN
27
DIWP3EN
28
IIFM
0 = Do not ignore first match, used for go to x (reset value) 1 = Ignore first match (used for continue) These bits control serialization and instruction fetch show cycles. See Table 21-5 for the bit definitions. NOTE: Changing the instruction show cycle programming starts to take effect only from the second instruction after the actual mtspr to ICTRL.
29:31
ISCT_SER
Instruction fetch show cycle and RCPU serialize control
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-48
USERS MANUAL

Table 21-22 ISCT_SER Bit Descriptions
Serialize (SER) Instruction Fetch Show Cycle) Control (ISCTL) 00 01 10 11 00 01 10 11
Functions Selected
0 0 0 0 1
RCPU is fully serialized and show cycle will be performed for all fetched instructions (reset value) RCPU is fully serialized and show cycle will be performed for all changes in the program flow RCPU is fully serialized and show cycle will be performed for all indirect changes in the program flow RCPU is fully serialized and no show cycles will be performed for fetched instructions Illegal. This mode should not be selected. RCPU is not serialized (normal mode) and show cycle will be performed for all changes in the program flow RCPU is not serialized (normal mode) and show cycle will be performed for all indirect changes in the program flow RCPU is not serialized (normal mode) and no show cycles will be performed for fetched instructions
1 1 1
21.7.7 L-Bus Support Control Register 1 LCTRL1 L-Bus Support Control Register 1
0 1 CTE RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 3 4 CTF 5 6 7 CTG 8 9 10 CTH 11 12 13 CRWE
SPR 156
14 15 CRWF
16 CSG
17
18 CSH
19
20
21
22
23
24
25
26
27
28
29
30
31
SUSG SUSH
CGBMSK
CHBMSK
UNUSED
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-49
USERS MANUAL

Table 21-23 LCTRL1 Bit Descriptions
Bits 0:2 3:5 6:8 9:11 12:13 14:15 16:17 Mnemonic CTE CTF CTG CTH CRWE CRWF CSG Description Compare type, comparator E Compare type, comparator F Compare type, comparator G Compare type, comparator H Select match on read/write of comparator E Select match on read/write of comparator F Compare size, comparator G Function 0xx = not active (reset value) 100 = equal 101 = less than 110 = greater than 111 = not equal 0X = dont care (reset value) 10 = match on read 11 = match on write 00 = reserved 01 = word 10 = half word 11 = byte (Must be programmed to word for floating point compares) 0 = unsigned 1 = signed (Must be programmed to signed for floating point compares)
18:19
CSH
Compare size, comparator H
20 21 22:25
SUSG SUSH CGBMSK
Signed/unsigned operating mode for comparator G Signed/unsigned operating mode for comparator H Byte mask for 1st L-data comparator
26:29 30:31
CHBMSK
0000 = all bytes are not masked 0001 = the last byte of the word is masked . Byte mask for 2nd L-data compara- . . tor 1111 = all bytes are masked
Reserved
LCTRL1 is cleared following reset. 21.7.8 L-Bus Support Control Register 2 LCTRL2 L-Bus Support Control Register 2
0 LW0EN RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 LW0IA 2 3 LW0 IADC 4 5 6 LW0 LADC 7 8 9 10 11 12 13 LW1 IADC LW0 LW1EN LDDC
SPR 157
14 15
LW0LA
LW0LD
LW1IA
LW1LA
16 LW1 LADC
17
18
19
20
21
22
23
24 RESERVED
25
26
27
28
29
30
31
LW1LD
LW1 BRK LDDC NOMSK
DLW0 DLW1 SLW0 SLW1 EN EN EN EN
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-50
USERS MANUAL

Table 21-24 LCTRL2 Bit Descriptions
Bits 0 Mnemonic LW0EN Description 1st L-bus watchpoint enable bit 1st L-bus watchpoint I-addr watchpoint selection 1st L-bus watchpoint care/dont care I-addr events 1st L-bus watchpoint L-addr events selection 1st L-bus watchpoint care/dont care L-addr events 1st L-bus watchpoint L-data events selection 1st L-bus watchpoint care/dont care L-data events 2nd L-bus watchpoint enable bit 2nd L-bus watchpoint I-addr watchpoint selection 2nd L-bus watchpoint care/dont care I-addr events 2nd L-bus watchpoint L-addr events selection 2nd L-bus watchpoint care/dont care L-addr events 2nd L-bus watchpoint L-data events selection 2nd L-bus watchpoint care/dont care L-data events Internal breakpoints non-mask bit Reserved Function 0 = watchpoint not enabled (reset value) 1 = watchpoint enabled 00 = first I-bus watchpoint 01 = second I-bus watchpoint 10 = third I-bus watchpoint 11 = fourth I-bus watchpoint 0 = Dont care 1 = Care 00 = match from comparator E 01 = match from comparator F 10 = match from comparators (E&F) 11 = match from comparators (E | F) 0 = Dont care 1 = Care 00 = match from comparator G 01 = match from comparator H 10 = match from comparators (G&H) 11 = match from comparators (G | H) 0 = Dont care 1 = Care 0 = watchpoint not enabled (reset value) 1 = watchpoint enabled 00 = first I-bus watchpoint 01 = second I-bus watchpoint 10 = third I-bus watchpoint 11 = fourth I-bus watchpoint 0 = Dont care 1 = Care 00 = match from comparator E 01 = match from comparator F 10 = match from comparators (E&F) 11 = match from comparators (E | F) 0 = Dont care 1 = Care 00 = match from comparator G 01 = match from comparator H 10 = match from comparators (G&H) 11 = match from comparator (G | H) 0 = Dont care 1 = Care 0 = masked mode; breakpoints are recognized only when MSR[RI]=1 (reset value) 1 = non-masked mode; breakpoints are always recognized
1:2
LW0IA
LW0IADC
4:5
LW0LA
LW0LADC
7:8
LW0LD
9 10
LW0LDDC LW1EN
11:12
LW1IA
13
LW1IADC
14:15
LW1LA
16
LW1LADC
17:18
LW1LD
19
LW1LDDC
20 21:27
BRKNOMSK
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-51
USERS MANUAL

Table 21-24 LCTRL2 Bit Descriptions (Continued)
Bits Mnemonic Description Development port trap enable selection of the 1st L-bus watchpoint (read only bit) Development port trap enable selection of the 2nd L-bus watchpoint (read only bit) Software trap enable selection of the 1st L-bus watchpoint Software trap enable selection of the 2nd L-bus watchpoint 0 = trap disabled (reset value) 1 = trap enabled Function
28
DLW0EN
29
DLW1EN
30 31
SLW0EN SLW1EN
LCTRL2 is cleared following reset.
For each watchpoint, three control register fields (LWxIA, LWxLA, LWxLD) must be programmed. For a watchpoint to be asserted, all three conditions must be detected. 21.7.9 Breakpoint Counter A Value and Control Register COUNTA Breakpoint Counter A Value and Control Register
0 1 2 3 4 5 6 7 CNTV RESET: UNAFFECTED 8 9 10 11 12 13
SPR 150
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RESERVED RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CNTC
Table 21-25 Breakpoint Counter A Value and Control Register (COUNTA)

Bit(s) 0:15 16:29 Name CNTV Counter preset value Reserved Counter source select 00 = not active (reset value) 01 = I-bus first watchpoint 10 =L-bus first watchpoint 11 = Reserved Description
30:31
CNTC
COUNTA[16:31] are cleared following reset; COUNTA[0:15] are unaffected by reset.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-52
USERS MANUAL

21.7.10 Breakpoint Counter B Value and Control Register COUNTB Breakpoint Counter B Value and Control Register
0 1 2 3 4 5 6 7 CNTV RESET: UNAFFECTED 8 9 10 11 12 13
SPR 151
14 15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RESERVED RESET:
CNTC
Table 21-26 Breakpoint Counter B Value and Control Register (COUNTB)

Bit(s) 0:15 16:29 Name CNTV Counter preset value Reserved Counter source select 00 = not active (reset value) 01 = I-bus second watchpoint 10 = L-bus second watchpoint 11 = Reserved COUNTB[16:31] are cleared following reset; COUNTB[0:15] are unaffected by reset. Description
30:31
CNTC
21.7.11 Exception Cause Register (ECR) The ECR indicates the cause of entry into debug mode. All bits are set by the hardware and cleared when the register is read when debug mode is disabled, or if the processor is in debug mode. Attempts to write to this register are ignored. When the hardware sets a bit in this register, debug mode is entered only if debug mode is enabled and the corresponding mask bit in the DER is set. All bits are cleared to zero following reset.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-53
USERS MANUAL

ECR Exception Cause Register
0 0 1 RST 2 CHST P 3 MCE 4 5 6 EXTI 7 ALE 8 PRE 9 10 11 12 13 SYSE FPUV DECE E
SPR 148
14 TR 15 FPAS E
RESERVED
RESERVED
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 0
17 SEE
18 RESERV ED
19 ITLBER
20 RESERV ED
21 DTLBER
22
23
24
25
26
27
28 LBRK
29 IBRK
30 EBRK D
31 DPI
RESERVED
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 21-27 ECR Bit Descriptions

Bit(s) 0 1 2 3 4:5 6 7 8 9 10 11:12 13 14 15 16 17 18 19 20 21 22:27 Name RST CHSTP MCE EXTI ALE PRE FPUVE DECE SYSE TR FPASE SEE ITLBER DTLBER Reserved Reset interrupt bit. This bit is set when the system reset pin is asserted. Checkstop bit. Set when the processor enters checkstop state. Machine check interrupt bit. Set when a machine check exception (other than one caused by a data storage or instruction storage error) is asserted. Reserved External interrupt bit. Set when the external interrupt is asserted. Alignment exception bit. Set when the alignment exception is asserted. Program exception bit. Set when the program exception is asserted. Floating point unavailable exception bit. Set when the program exception is asserted. Decrementer exception bit. Set when the decrementer exception is asserted. Reserved System call exception bit. Set when the system call exception is asserted. Trace exception bit. Set when in single-step mode or when in branch trace mode. Floating point assist exception bit. Set when the floating point assist exception occurs. Reserved Software emulation exception. Set when the software emulation exception is asserted. Reserved Implementation specific instruction protection error This bit is set as a result of an instruction protection error. Results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. Reserved Implementation specific data protection error This bit is set as a result of an data protection error. Results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. Reserved Description
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-54
USERS MANUAL

Table 21-27 ECR Bit Descriptions (Continued)
Bit(s) 28 Name LBRK Description L-bus breakpoint exception bit. This bit is set as a result of the assertion of a load/store breakpoint. Results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. I-bus breakpoint exception bit. This bit is set as a result of the assertion of an Instruction breakpoint. Results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. External breakpoint exception bit. Set when an external breakpoint is asserted (by an on-chip IMB or L-bus module, or by an external device or development system through the development port). This bit is set as a result of the assertion of an external breakpoint. Results in debug mode entry if debug mode is enabled and the corresponding enable bit is set. Development port interrupt bit. Set by the development port as a result of a debug station nonmaskable request or when debug mode is entered immediately out of reset.
29
IBRK
30
EBRK
31
DPI
21.7.12 Debug Enable Register (DER) This register enables the user to selectively mask the events that may cause the processor to enter into debug mode. DER Debug Enable Register
0 0 1 RSTE 2 3 4 5 6 7 8 9 FPUVEE 10 DECEE 11 12 13 SYSEE CHST MCEE PE
SPR 149
14 TRE 15 FPAS E
RESERVED
EXTIE ALEE PREE
RESERVED
RESET: 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 DPIE
REREREITLDTLSERV SEEE SERV SERV BERE BERE ED ED ED RESET: 0 0 0 0 0 0 0 0
RESERVED
LBRK EBRK IBRKE E E
Table 21-28 DER Bit Descriptions

Bit(s) 0:1 1 Name RSTE Reserved Reset enable 0 = Debug entry is disabled (reset value) 1 = Debug entry is enabled Checkstop enable bit 0 = Debug mode entry disabled 1 = Debug mode entry enabled (reset value) Machine check exception enable bit 0 = Debug mode entry disabled (reset value) 1 = Debug mode entry enabled Reserved Description
CHSTPE
3 4:5
MCEE
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-55
USERS MANUAL

Table 21-28 DER Bit Descriptions (Continued)
Bit(s) 6 Name EXTIE Description External interrupt enable bit 0 = Debug mode entry disabled (reset value) 1 = Debug mode entry enabled Alignment exception enable bit 0 = Debug mode entry disabled (reset value) 1 = Debug mode entry enabled Program exception enable bit 0 = Debug mode entry disabled (reset value) 1 = Debug mode entry enabled Floating point unavailable exception enable bit 0 = Debug mode entry disabled (reset value) 1 = Debug mode entry enabled Decrementer exception enable bit 0 = Debug mode entry disabled (reset value) 1 = Debug mode entry enabled Reserved System call exception enable bit 0 = Debug mode entry disabled (reset value) 1 = Debug mode entry enabled Trace exception enable bit 0 = Debug mode entry disabled 1 = Debug mode entry enabled (reset value) Floating point assist exception enable bit. 0 = Debug mode entry disabled (reset value) 1 = Debug mode entry enabled Reserved Software emulation exception enable bit 0 = Debug mode entry disabled (reset value) 1 = Debug mode entry enabled Reserved Implementation specific instruction protection error enable bit. 0 = Debug mode entry disabled (reset value) 1 = Debug mode entry enabled Reserved Implementation specific data protection error enable bit. 0 = Debug mode entry disabled (reset value) 1 = Debug mode entry enabled Reserved Load/store breakpoint enable bit. 0 = Debug mode entry disabled 1 = Debug mode entry enabled (reset value) Instruction breakpoint interrupt enable bit. 0 = Debug mode entry disabled 1 = Debug mode entry enabled (reset value) External breakpoint interrupt enable bit (development port, internal or external modules). 0 = Debug mode entry disabled 1 = Debug mode entry enabled (reset value) Development port interrupt enable bit 0 = Debug mode entry disabled 1 = Debug mode entry enabled (reset value)
ALEE
PREE
FPUVEE
10 11:12 13
DECEE SYSEE
14
TRE
15 16 17 18 19 20 21 22:27 28
FPASEE SEEE ITLBERE DTLBERE LBRKE
29
IBRKE
30
EBRKE
31
DPIE
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-56
USERS MANUAL

21.7.13 Development Port Data Register (DPDR) This 32-bit special purpose register physically resides in the development port logic. It is used for data interchange between the core and the development system. An access to this register is initiated using mtspr and mfspr (SPR 630) and implemented using a special bus cycle on the internal bus.
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-57
USERS MANUAL
MPC555
/ MPC556
DEVELOPMENT SUPPORT
MOTOROLA 21-58
USERS MANUAL
SECTION 22 IEEE 1149.1-COMPLIANT INTERFACE (JTAG)

The MPC555 / MPC556 includes dedicated user-accessible test logic that is fully compatible with the IEEE 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture. Problems associated with testing high-density circuit boards have led to development of this standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The MPC555 / MPC556 supports circuit-board test strategies based on this standard.
This section is intended to be used with the supporting IEEE 1149.1-1990 standard. The scope of this description includes those items required by the standard to be defined and, in certain cases, provides additional information specific to the implementation. For internal details and applications of the standard, refer to the IEEE 1149.11990 document. An overview of the JTAG pins on the MPC555 / MPC556 is shown in Figure 22-1.
bsc bsc
bsc
bsc
bsc bsc bsc
TDI TCK TMS JCOMP TDO TAP
MPC555 / MPC556
TRST
bsc bsc bsc bsc
Figure 22-1 JTAG Pins Boundary scan cells (BSC) are placed at the digital boundary of the chip (normally the package pins). The boundary scan cells are chained together to form a boundary scan register (BSR). The data is serially shifted in through the serial port (TDI) and serially shifted out through the output port (TDO). 22.1 JTAG Interface Block Diagram A block diagram of the MPC555 / MPC556 implementation of the IEEE 1149.1-1990 test logic is shown in Figure 22-2.
IEEE 1149.1-COMPLIANT INTERFACE (JTAG)
MOTOROLA 22-1
Boundary scan register TDI Bypass M U X
Instruction apply & decode register
4-bit Instruction register
M U X
TDO
JCOMP
TMS TCK
TAP CONTROLLER TRST
Figure 22-2 Test Logic Block Diagram 22.2 JTAG Signal Descriptions The MPC555 / MPC556 has five dedicated JTAG pins, which are described in Table 22-1. The TDI and TDO scan ports are used to scan instructions as well as data into the various scan registers for JTAG operations. The scan operation is controlled by the test access port (TAP) controller, which in turn is controlled by the TMS input sequence. To enable JTAG on reset for board test, bit 11 (DGPC select JTAG pins) and bit 16 (PRPM peripheral mode enable) of the reset configuration word should be held high during the rising edge of reset (see 7.5.2 Hard Reset Configuration Word). These need to be configurable on the user board to allow JTAG test of a board. To allow normal operation of the board these bits need to be low in the reset configuration word.
MPC555
/ MPC556
MOTOROLA 22-2
USERS MANUAL

Table 22-1 JTAG Interface Pin Descriptions
Signal Name TDI Input/ Output (I/O) Input Internal Pull-Up/ Pull-Down Provided Pull-up Description Test data input pin. Sampled on the rising edge of TCK. Has a pull-up resistor. Test data output pin. Actively driven during the Shift-IR and ShiftDR controller states. Changes on the falling edge of TCK. Can be placed in high-impedance state. Test mode select pin. Sampled on the rising edge of TCK to sequence the test controllers state machine. Has a pull-up resistor. Test clock input to synchronize the test logic. Has a pull-down resistor. TAP controller asynchronous reset. Provides initialization of the TAP controller and other logic as required by the standard. Has a pull-up resistor.
TDO
Output
None
TMS
Input
Pull-up
TCK
Input
Pull-down
TRST
Input
Pull-up
22.3 Operating Frequency The TCK frequency must be between 5 MHz and 10 MHz. This pin is internally driven to a low value when disconnected. 22.4 TAP Controller TRST is used to reset the TAP controller asynchronously. The TRST pin ensures that the JTAG logic does not interfere with the normal operation of the chip. This pin is optional in the JTAG specification. The TAP controller changes state either on the rising edge of TCK or when TRST is asserted. The TDO signal remains in a high-impedance state except during the Shift-DR or ShiftIR controller states. During these controller states, TDO is updated on the falling edge of TCK. The TAP controller states are designed to meet the IEEE 1149.1 standard. Refer to Figure 22-3.
MPC555
/ MPC556
MOTOROLA 22-3
USERS MANUAL
TEST LOGIC RESET 1 0 1 1 1
RUN-TEST/IDLE 0
SELECT-DR_SCAN 0 1 1 CAPTURE-DR 1 0
SELECT-IR_SCAN 0 1 CAPTURE-IR
0 SHIFT-IR 0 1 0
SHIFT-DR 1
EXIT1-DR 0
EXIT1-IR
0 PAUSE-IR 0 0 0
PAUSE-DR 1 0
1 EXIT2-IR 1
EXIT2-DR 1
UPDATE-DR 1 0 1
UPDATE-IR 0
Figure 22-3 TAP Controller State Machine 22.5 Instruction Register The MPC555 / MPC556 JTAG implementation includes the public instructions (EXTEST, SAMPLE/PRELOAD, and BYPASS), and also supports the CLAMP instruction. One additional public instruction (HI-Z) provides the capability for disabling all device output drivers. The MPC555 / MPC556 includes a 4-bit instruction register without parity consisting of a shift register with four parallel outputs. Data is transferred from the shift register to the parallel outputs during the update-IR controller state. The four bits are used to decode the five unique instructions listed in Table 22-2.
MPC555
/ MPC556
MOTOROLA 22-4
USERS MANUAL
Table 22-2 Instruction Decoding

Code B3 0 0 0 0 0 B2 0 0 X 1 1 B1 0 0 1 0 0 B0 0 1 X 0 1 Instruction EXTEST SAMPLE/PRELOAD BYPASS HI-Z CLAMP and BYPASS
The parallel output of the instruction register is reset to all ones in the test-logic-reset controller state. Note that this preset state is equivalent to the BYPASS instruction. During the capture-IR controller state, the parallel inputs to the instruction shift register are loaded with the CLAMP command code. 22.5.1 EXTEST The external test (EXTEST) instruction selects the 346-bit boundary scan register. EXTEST also asserts internal reset for the MPC555 / MPC556 system logic to force a predictable beginning internal state while performing external boundary scan operations. By using the TAP, the register is capable of scanning user-defined values into the output buffers, capturing values presented to input pins and controlling the output drive of three-state output or bi-directional pins. For more details on the function and use of EXTEST, refer to the scan chain document. 22.5.2 SAMPLE/PRELOAD The SAMPLE/PRELOAD instruction initializes the boundary scan register output cells prior to selection of EXTEST. This initialization ensures that known data will appear on the outputs when entering the EXTEST instruction. The SAMPLE/PRELOAD instruction also provides a means to obtain a snapshot of system data and control signals. NOTE Since there is no internal synchronization between the scan chain clock (TCK) and the system clock (CLKOUT), the user must provide some form of external synchronization to achieve meaningful results. 22.5.3 BYPASS The BYPASS instruction selects the single-bit bypass register as shown in Figure 224. This creates a shift register path from TDI to the bypass register and, finally, to TDO, circumventing the 463-bit boundary scan register. This instruction is used to enhance test efficiency when a component other than the MPC555 / MPC556 becomes the device under test.
MPC555
/ MPC556
MOTOROLA 22-5
USERS MANUAL
SHIFT DR 0 FROM TDI
G1 1 1 D C TO TDO
MUX
CLOCK DR
Figure 22-4 Bypass Register
When the bypass register is selected by the current instruction, the shift register stage is set to a logic zero on the rising edge of TCK in the capture-DR controller state. Therefore, the first bit to be shifted out after selecting the bypass register will always be a logic zero. 22.5.4 CLAMP The CLAMP instruction selects the single-bit bypass register as shown in Figure 224, and the state of all signals driven from system output pins is completely defined by the data previously shifted into the boundary scan register (e.g., using the SAMPLE/ PRELOAD instruction). 22.5.5 HI-Z The HI-Z instruction is provided as a manufacturers optional public instruction to prevent having to backdrive the output pins during circuit-board testing. When HI-Z is invoked, all output drivers, including the two-state drivers, are turned off (i.e., high impedance). The instruction selects the bypass register. 22.6 Restrictions The MPC555 / MPC556 provides flexible control of external signals using the boundary scan register and EXTEST or CLAMP instructions. As a result, the circuit board test environment must be designed to avoid signal contention which may result in device destruction. 22.7 Low-Power Stop Mode The MPC555 / MPC556 features a low-power stop mode. The interaction of the scan chain interface with low-power stop mode is as follows: 1. The TAP controller must be in the test-logic-reset state to either enter or remain in the low-power stop mode. Leaving the TAP controller in the test-logic-reset state negates the ability to achieve low-power, but does not otherwise affect device functionality. / MPC556
MPC555
MOTOROLA 22-6
USERS MANUAL

2. The TCK input is not blocked in low-power stop mode. To consume minimal power, the TCK input should be externally connected to VDD or ground, although TCK pin is internally connected to ground. 3. The TMS, TDI and TRST pins include on-chip pullup resistors. In low-power stop mode, these three pins should remain either unconnected or connected to VDD to achieve minimal power consumption. NOTE For proper reset of the scan chain test logic, the best approach is to assert TRST at power on reset (PORESET). 22.8 Non-IEEE 1149.1-1990 Operation In non-IEEE 1149.1-1990 operation, the IEEE 1149.1-1990 test logic must be kept transparent to the system logic by forcing and holding the TAP controller into the testlogic-reset controller state. There are two methods of forcing and holding the controller to this state. The first is to assert the TRST signal, forcing the TAP into the testlogic-reset controller state. The second is to provide at least five TCK pulses with TMS held high. The best approach is to connect a pull down resistor to TRST, or to connect it to PORESET with a resistor. If bounday scan is required, the JTAG controller should drive TRST to the negated state (1 value) following PORESET. 22.9 Boundary Scan Register The MPC555 / MPC556 scan chain implementation has a 346-bit boundary scan register. This register contains bits for all device signal and clock pins and associated control signals. The XTAL, EXTAL and XFC pins are associated with analog signals and are not included in the boundary scan register. An IEEE-1149.1 compliant boundary scan register has been included on the MPC555 / MPC556. This 346-bit boundary scan register can be connected between TDI and TDO when EXTEST or SAMPLE/PRELOAD instructions are selected. This register is used for capturing signal pin data on the input pins, forcing fixed values on the output signal pins, and selecting the direction and drive characteristics (a logic value or high impedance) of the bidirectional and three-state signal pins. Figure 22-5 through Figure 22-8 depict the various cell types.
MPC555
/ MPC556
MOTOROLA 22-7
USERS MANUAL
1- EXTEST | CLAMP 0- OTHERWIZE G1 DATA FROM SYSTEM LOGIC 1 MUX 1
SHIFT DR
TO NEXT CELL
TO OUTPUT BUFFER
G1 1 Mux 1
D C D C
FROM LAST CELL
CLOCK DR
UPDATE DR
Figure 22-5 Output Pin Cell (O.pin)
TO NEXT CELL
DATA TO SYSTEM LOGIC
INPUT PIN
G1 D C MUX 1 1
CLOCK DR
FROM LAST CELL
SHIFT DR
Figure 22-6 Observe-Only Input Pin Cell (I.Obs)
MPC555
/ MPC556
MOTOROLA 22-8
USERS MANUAL

)
1- EXTEST | CLAMP 0- OTHERWISE G1 OUTPUT CONTROL FROM SYSTEM LOGIC 1 MUX 1
SHIFT DR
TO NEXT CELL
TO OUTPUT BUFFER
G1 1 MUX 1
D C D C
FROM LAST CELL
CLOCK DR
UPDATE DR
Figure 22-7 Output Control Cell (IO.CTL)
FROM LAST CELL OUTPUT ENABLE FROM SYSTEM LOGIC
I/O.CTL
OUTPUT DATA
O.Pin
En
I/O PIN
INPUT DATA I.Obs
TO NEXT CELL
TO NEXT PIN PAIR
Figure 22-8 General Arrangement of Bidirectional Pin Cells The key to using the boundary scan register is knowing the boundary scan bit order and the pins that are associated with them. Below in Table 22-3 is the bit order starting
MPC555
/ MPC556
MOTOROLA 22-9
USERS MANUAL

from the TDI input and going to the TDO output. This table uses the long pin names of the MPC555 / MPC556. See Table 2-6 for a translation of the long names to the short names found on the pinout information in Figure 2-2. The first column in the table defines the bits ordinal position in the boundary scan register. The shift register cell nearest TDI (i.e., first to be shifted in) is defined as bit 1; the last bit to be shifted in is 345. The second column references one of the three MPC555 / MPC556 cell types depicted in Figure 22-5 through Figure 22-8, which describe the cell structure for each type. The third column lists the pin name for all pin-related cells or defines the name of bidirectional control register bits. The fourth column lists the pin type. The last column indicates the associated boundary scan register control bit for bi-directional output pins.
Bi-directional pins include two scan cells for data (IO.Cell) as depicted in Figure 22-8. These bits are controlled by the cell shown in Figure 22-7. The value of the control bit controls the output function of the bidirectional pin. One or more bidirectional data cells can be serially connected to a control cell.
Table 22-3 Boundary Scan Bit Definition

Bit Cell Type i.obs o.pin IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN Pin/Cell Name b_cnrx0 b_cntx0 b_tpuch0 g251.ctl b_tpuch1 g252.ctl b_tpuch2 g253.ctl b_tpuch3 g254.ctl b_tpuch4 g255.ctl b_tpuch5 g256.ctl b_tpuch6 g257.ctl b_tpuch7 Pin Type i o io io io io io io io io Output CTL Cell g251.ctl g252.ctl g253.ctl g254.ctl g255.ctl g256.ctl g257.ctl g258.ctl
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MPC555
/ MPC556
MOTOROLA 22-10
USERS MANUAL

Table 22-3 Boundary Scan Bit Definition (Continued)
Bit Cell Type IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl Pin/Cell Name g258.ctl b_tpuch8 g259.ctl b_tpuch9 g260.ctl b_tpuch10 g261.ctl b_tpuch11 g262.ctl b_tpuch12 g263.ctl b_tpuch13 g264.ctl b_tpuch14 g265.ctl b_tpuch15 g266.ctl b_t2clk g267.ctl a_t2clk g268.ctl a_tpuch0 g269.ctl a_tpuch1 g302.ctl a_tpuch2 g303.ctl a_tpuch3 g304.ctl a_tpuch4 g305.ctl Pin Type io io io io io io io io io io io io io io io Output CTL Cell g259.ctl g260.ctl g261.ctl g262.ctl g263.ctl g264.ctl g265.ctl g266.ctl g267.ctl g268.ctl g269.ctl g302.ctl g303.ctl g304.ctl g305.ctl
17 18 19 20 21 22 23
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
MPC555
/ MPC556
MOTOROLA 22-11
USERS MANUAL

Bit Cell Type IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl i.obs i.obs i.obs i.obs i.obs i.obs IO.PIN IO.ctl IO.PIN Pin/Cell Name a_tpuch5 g306.ctl a_tpuch6 g307.ctl a_tpuch7 g308.ctl a_tpuch8 g309.ctl a_tpuch9 g310.ctl a_tpuch10 g311.ctl a_tpuch11 g312.ctl a_tpuch12 g313.ctl a_tpuch13 g314.ctl a_tpuch14 g315.ctl a_tpuch15 g316.ctl a_an0_anw_pqb0 a_an1_anx_pqb1 a_an2_any_pqb2 a_an3_anz_pqb3 a_an48_pqb4 a_an49_pqb5 a_an50_pqb6 g333.ctl a_an51_pqb7 Pin Type io io io io io io io io io io io i i i i i i io io Output CTL Cell g306.ctl g307.ctl g308.ctl g309.ctl g310.ctl g311.ctl g312.ctl g313.ctl g314.ctl g315.ctl g316.ctl g333.ctl g334.ctl
48 49 50 51 52 53 54
55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
MPC555
/ MPC556
MOTOROLA 22-12
USERS MANUAL

Bit Cell Type IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl i.obs i.obs i.obs i.obs i.obs i.obs IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl Pin/Cell Name g334.ctl a_an52_ma0_pqa0 g335.ctl a_an53_ma1_pqa1 g336.ctl a_an54_ma2_pqa2 g337.ctl a_an55_pqa3 g338.ctl a_an56_pqa4 g339.ctl a_an57_pqa5 g340.ctl a_an58_pqa6 g341.ctl a_an59_pqa7 g342.ctl b_an0_anw_pqb0 b_an1_anx_pqb1 b_an2_any_pqb2 b_an3_anz_pqb3 b_an48_pqb4 b_an49_pqb5 b_an50_pqb6 g349.ctl b_an51_pqb7 g350.ctl b_an52_ma0_pqa0 g351.ctl b_an53_ma1_pqa1 g352.ctl Pin Type io io io io io io io io i i i i i i io io io io Output CTL Cell g335.ctl g336.ctl g337.ctl g338.ctl g339.ctl g340.ctl g341.ctl g342.ctl g349.ctl g350.ctl g351.ctl g352.ctl
79 80 81 82 83 84 85
86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109
MPC555
/ MPC556
MOTOROLA 22-13
USERS MANUAL

Bit Cell Type IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl i.obs i.obs IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN Pin/Cell Name b_an54_ma2_pqa2 g353.ctl b_an55_pqa3 g354.ctl b_an56_pqa4 g355.ctl b_an57_pqa5 g356.ctl b_an58_pqa6 g357.ctl b_an59_pqa7 g358.ctl etrig2 etrig1 mda11 g365.ctl mda12 g366.ctl mda13 g367.ctl mda14 g368.ctl mda15 g369.ctl mda27 g370.ctl mda28 g371.ctl mda29 g372.ctl mda30 Pin Type io io io io io io i i io io io io io io io io io Output CTL Cell g353.ctl g354.ctl g355.ctl g356.ctl g357.ctl g358.ctl g365.ctl g366.ctl g367.ctl g368.ctl g369.ctl g370.ctl g371.ctl g372.ctl g403.ctl
110 111 112 113 114 115 116
117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
MPC555
/ MPC556
MOTOROLA 22-14
USERS MANUAL

Bit Cell Type IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl Pin/Cell Name g403.ctl mda31 g404.ctl mpwm0 g405.ctl mpwm1 g406.ctl mpwm2 g407.ctl mpwm3 g408.ctl mpwm16 g409.ctl mpwm17 g410.ctl mpwm18 g411.ctl mpwm19 g412.ctl mpio32b5 g413.ctl mpio32b6 g414.ctl mpio32b7 g415.ctl mpio32b8 g416.ctl mpio32b9 g417.ctl mpio32b10 g418.ctl Pin Type io io io io io io io io io io io io io io io Output CTL Cell g404.ctl g405.ctl g406.ctl g407.ctl g408.ctl g409.ctl g410.ctl g411.ctl g412.ctl g413.ctl g414.ctl g415.ctl g416.ctl g417.ctl g418.ctl
141 142 143 144 145 146 147
148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171
MPC555
/ MPC556
MOTOROLA 22-15
USERS MANUAL

Bit Cell Type IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl o.pin i.obs IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN Pin/Cell Name mpio32b11 g419.ctl mpio32b12 g420.ctl mpio32b13 g421.ctl mpio32b14 g422.ctl mpio32b15 g423.ctl vf0_mpio32b0 g424.ctl vf1_mpio32b1 g425.ctl vf2_mpio32b2 g426.ctl vfls0_mpio32b3 g427.ctl vfls1_mpio32b4 g428.ctl a_cntx0 a_cnrx0 pcs0_ss_b_qgpio0 g435.ctl pcs1_qgpio1 g436.ctl pcs2_qgpio2 g437.ctl pcs3_qgpio3 g438.ctl miso_qgpio4 Pin Type io io io io io io io io io io o i io io io io io Output CTL Cell g419.ctl g420.ctl g421.ctl g422.ctl g423.ctl g424.ctl g425.ctl g426.ctl g427.ctl g428.ctl g435.ctl g436.ctl g437.ctl g438.ctl g439.ctl
172 173 174 175 176 177 178
179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202
MPC555
/ MPC556
MOTOROLA 22-16
USERS MANUAL

Bit Cell Type IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl i.obs o.pin o.pin i.obs i.obs i.obs o.pin i.obs o.pin i.obs i.obs o.pin IO.ctl i.obs o.pin IO.ctl IO.PIN IO.ctl i.obs i.obs IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.PIN Pin/Cell Name g439.ctl mosi_qgpio5 g440.ctl sck_qgpio6 g441.ctl eck txd1_qgpo1 txd2_qgpo2 rxd1_qgpi1 rxd2_qgpi2 epee engclk_buclk extclk clkout poreset_b sreset_b sreset_b g465.ctl hreset_b hreset_b g466.ctl rstconf_b_texp g467.ctl irq7_b_modck3 irq6_b_modck2 irq5_b_sgpioc5_modck1 g503.ctl data_sgpiod[16] g112.ctl data_sgpiod[17] data_sgpiod[18] Pin Type io io i o o i i i o i o i io io io io io i i io io io io Output CTL Cell g440.ctl g441.ctl g465.ctl g466.ctl g467.ctl g503.ctl g112.ctl g112.ctl g112.ctl
203 204 205 206 207 208 209
210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233
MPC555
/ MPC556
MOTOROLA 22-17
USERS MANUAL

Bit Cell Type IO.PIN IO.PIN IO.PIN IO.PIN IO.PIN IO.PIN IO.PIN IO.PIN IO.PIN IO.PIN IO.PIN IO.PIN IO.ctl IO.PIN IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.PIN IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.PIN IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN Pin/Cell Name data_sgpiod[14] data_sgpiod[15] data_sgpiod[19] data_sgpiod[20] data_sgpiod[12] data_sgpiod[13] data_sgpiod[21] data_sgpiod[10] data_sgpiod[11] data_sgpiod[22] data_sgpiod[23] data_sgpiod[8] g111.ctl data_sgpiod[9] data_sgpiod[24] g524.ctl data_sgpiod[25] g525.ctl data_sgpiod[6] data_sgpiod[7] data_sgpiod[26] g528.ctl data_sgpiod[27] g529.ctl data_sgpiod[4] data_sgpiod[5] data_sgpiod[28] g534.ctl data_sgpiod[29] g535.ctl data_sgpiod[2] Pin Type io io io io io io io io io io io io io io io io io io io io io io io io Output CTL Cell g111.ctl g111.ctl g112.ctl g112.ctl g111.ctl g111.ctl g112.ctl g111.ctl g111.ctl g112.ctl g112.ctl g111.ctl g111.ctl g524.ctl g525.ctl g110.ctl g110.ctl g528.ctl g529.ctl g110.ctl g110.ctl g534.ctl g535.ctl g110.ctl
234 235 236 237 238 239 240
241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264
MPC555
/ MPC556
MOTOROLA 22-18
USERS MANUAL

Bit Cell Type IO.PIN IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.PIN IO.ctl IO.PIN IO.PIN IO.PIN IO.PIN IO.PIN IO.PIN IO.ctl IO.PIN IO.PIN IO.PIN IO.PIN IO.PIN IO.PIN IO.ctl IO.PIN IO.PIN IO.PIN IO.PIN IO.PIN IO.PIN IO.ctl IO.PIN IO.PIN Pin/Cell Name data_sgpiod[3] data_sgpiod[30] g540.ctl data_sgpiod[0] g110.ctl data_sgpiod[1] data_sgpiod[31] g545.ctl addr_sgpioa[29] addr_sgpioa[25] addr_sgpioa[26] addr_sgpioa[27] addr_sgpioa[28] addr_sgpioa[24] g102.ctl addr_sgpioa[23] addr_sgpioa[22] addr_sgpioa[30] addr_sgpioa[21] addr_sgpioa[20] addr_sgpioa[8] g100.ctl addr_sgpioa[31] addr_sgpioa[19] addr_sgpioa[18] addr_sgpioa[9] addr_sgpioa[17] addr_sgpioa[16] g101.ctl addr_sgpioa[10] addr_sgpioa[15] Pin Type io io io io io io io io io io io io io io io io io io io io io io io io io Output CTL Cell g110.ctl g540.ctl g110.ctl g110.ctl g545.ctl g102.ctl g102.ctl g102.ctl g102.ctl g102.ctl g102.ctl g101.ctl g101.ctl g102.ctl g101.ctl g101.ctl g100.ctl g102.ctl g101.ctl g101.ctl g100.ctl g101.ctl g101.ctl g100.ctl g100.ctl
265 266 267 268 269 270 271
272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295
MPC555
/ MPC556
MOTOROLA 22-19
USERS MANUAL

Bit Cell Type IO.PIN IO.PIN IO.PIN IO.PIN IO.PIN IO.ctl IO.PIN IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.PIN IO.PIN IO.ctl IO.PIN IO.ctl o.pin IO.PIN IO.ctl o.pin o.pin o.pin o.pin o.pin o.pin o.pin o.pin IO.PIN IO.ctl IO.PIN Pin/Cell Name addr_sgpioa[14] addr_sgpioa[13] addr_sgpioa[11] addr_sgpioa[12] bi_b_sts_b g205.ctl burst_b bdip_b g207.ctl ta_b g208.ctl ts_b tsiz1 tsiz0 g130.ctl tea_b g214.ctl oe_b rd_wr_b g131.ctl cs3_b cs2_b cs1_b cs0_b we_b_at[3] we_b_at[2] we_b_at[1] we_b_at[0] br_b_vf1_iwp2 g227.ctl bg_b_vf0_lwp1 Pin Type io io io io io io io io io io io io o io o o o o o o o o io io Output CTL Cell g100.ctl g100.ctl g100.ctl g100.ctl g205.ctl g131.ctl g207.ctl g208.ctl g131.ctl g130.ctl g130.ctl g214.ctl g131.ctl g227.ctl g228.ctl
296 297 298 299 300 301 302
303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326
MPC555
/ MPC556
MOTOROLA 22-20
USERS MANUAL

Bit Cell Type IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl IO.PIN IO.ctl o.pin o.pin IO.PIN IO.ctl Pin/Cell Name g228.ctl bb_b_vf2_iwp3 g229.ctl sgpioc7_irqout_b_lwp0 g230.ctl irq1_b_rsv_b_sgpioc1 g231.ctl irq0_b_sgpioc0 g232.ctl irq2_b_cr_b_sgpioc2 g233.ctl irq4_b_at2_sgpioc4 g234.ctl irq3_b_kr_b_retry_b_sgpio c3 g237.ctl iwp0_vfls0 iwp1_vfls1 sgpioc6_frz_ptr_b g240.ctl Pin Type io io io io io io io o o io Output CTL Cell g229.ctl g230.ctl g231.ctl g232.ctl g233.ctl g234.ctl g237.ctl g240.ctl
327 328 329 330 331 332 333
334 335 336 337 338 339 340 341 342 343 344 345
MPC555
/ MPC556
MOTOROLA 22-21
USERS MANUAL
MPC555
/ MPC556
MOTOROLA 22-22
USERS MANUAL
APPENDIX A MPC555 / MPC556 INTERNAL MEMORY MAP

The tables below use the following notations. In the Access column: S = Supervisor Access Only U = User Access T = Test Access In the Reset column: S = SRESET H = HRESET M = Module Reset POR = Power-On Reset U = Unchanged X = Unknown The codes in the Reset column indicate which reset has an effect on register values. INDEX of MEMORY MAP TABLES Table A-1 SPR (Special Purpose Registers) Table A-2 CMF (CDR MoneT Flash EEPROM) Flash Array Table A-3 USIU (Unified System Interface Unit) Table A-4 CMF (CDR MoneT Flash EEPROM) Table A-5 DPTRAM (Dual-Port TPU RAM) Table A-6 DPTRAM Array Table A-7 TPU3 (Time Processor Unit) Table A-8 QADC64 (Queued Analog-to-Digital Converter) Table A-9 QSMCM (Queued Serial Multi-Channel Module) Table A-10 MIOS1 (Modular Input/Output Subsystem) Table A-11 TouCAN (CAN 2.0B Controller) Table A-12 UIMB (U-Bus to IMB3 Bus Interface) Table A-13 SRAM (Static RAM Access Memory) Table A-14 SRAM (Static RAM Access Memory) Array
MPC555 / MPC556 USERS MANUAL MPC555 / MPC556 INTERNAL MEMORY MAP MOTOROLA A-1

Table A-1 SPR (Special Purpose Registers)
Address MSR SPR 1 Access S U Symbol MSR XER Register Machine State Register. See Table 3-12 for bit descriptions Integer Exception Register. See Table 3-10 for bit descriptions Link Register. See 3.7.6 Link Register (LR) for bit descriptions. Count Register. See 3.7.7 Count Register (CTR) for bit descriptions. DAE/Source Instruction Service Register. See 3.9.2 DAE/Source Instruction Service Register (DSISR) for bit descriptions. Data Address Register. See 3.9.3 Data Address Register (DAR) for bit descriptions. Decrementer Register. See 3.9.5 Decrementer Register (DEC) for bit descriptions. Machine Status Save/Restore Register 0. See 3.9.6 Machine Status Save/Restore Register 0 (SRR0) for bit descriptions. Machine Status Save/Restore Register 1. See 3.9.7 Machine Status Save/Restore Register 1 (SRR1) for bit descriptions. External Interrupt Enable Register See 3.9.10.1 EIE, EID, and NRI Special-Purpose Registers for bit descriptions. External Interrupt Disable Register See 3.9.10.1 EIE, EID, and NRI Special-Purpose Registers for bit descriptions. Non-Recoverable Interrupt Register See 3.9.10.1 EIE, EID, and NRI Special-Purpose Registers for bit descriptions. Comparator A Value Register. See Table 21-17 for bit descriptions. Comparator B Value Register. See Table 21-17 for bit descriptions. Comparator C Value Register. See Table 21-17 for bit descriptions. Comparator D Value Register. See Table 21-17 for bit descriptions. Exception Cause Register See Table 21-27 for bit descriptions. Debug Enable Register See Table 21-28 for bit descriptions. Breakpoint Counter A Value and Control Register See Table 21-25 for bit descriptions. Size 32 32 Reset S U
SPR 8
LR
32
SPR 9
CTR
32
SPR 18
DSISR
32
SPR 19
DAR
32
SPR 22
DEC
32
SPR 26
SRR0
32
SPR 27
SRR1
32
SPR 80
EIE
32
SPR 81
EID
32
SPR 82
NRI
32
SPR 144 SPR 145 SPR 146 SPR 147 SPR 148 SPR 149
S S S S S S
CMPA CMPB CMPC CMPD ECR DER
32 32 32 32 32 32
U U U U S S
SPR 150
COUNTA
32
MPC555 / MPC556 INTERNAL MEMORY MAP
MOTOROLA A-2

Table A-1 SPR (Special Purpose Registers) (Continued)
Address SPR 151 Access S Symbol COUNTB Register Breakpoint Counter B Value and Control Register See Table 21-26 for bit descriptions. Comparator G Value Register. See Table 21-20 for bit descriptions. Comparator H Value Register. See Table 21-20 for bit descriptions. Comparator E Value Register. See Table 21-18 for bit descriptions. Comparator F Value Register. See Table 21-18 for bit descriptions. L-Bus Support Control Register 1 See Table 21-23 for bit descriptions. L-Bus Support Control Register 2 See Table 21-24 for bit descriptions. I-Bus Support Control Register. See Table 21-21 for bit descriptions. Breakpoint Address Register. See Table 21-19 for bit descriptions. Time Base (Read Only). See Table 3-11 for bit descriptions. General Special Purpose Registers. See 3.9.8 General SPRs (SPRG0SPRG3) for bit descriptions. General Special Purpose Registers. See 3.9.8 General SPRs (SPRG0SPRG3) for bit descriptions. General Special Purpose Registers. See 3.9.8 General SPRs (SPRG0SPRG3) for bit descriptions. General Special Purpose Registers. See 3.9.8 General SPRs (SPRG0SPRG3) for bit descriptions. Time Base Register (Write Only). See Table 3-14 for bit descriptions. Processor Version Registers. See Table 3-16 for bit descriptions. Global Region Attribute Register. See Table 4-7 for bit descriptions. L2U Global Region Attribute Register. See Table 11-10 for bit descriptions. BBC Module Configuration Register. See Table 4-8 for bit descriptions. L2U Module Configuration Register. See Table 11-7 for bit descriptions. Development Port Data Register. Internal Memory Mapping Register. See Table 6-11 for bit descriptions. Size 32 Reset U
SPR 152 SPR 153 SPR 154 SPR 155
S S S S S S S S U read only S
CMPE CMPF CMPG CMPH LCTRL1 LCTRL2 ICTRL BAR TB
32 32 32 32 32 32 32 32 64
U U U U S S S U U
SPR 156 SPR 157 SPR 158 SPR 159 SPR 268, 269
SPR 272
SPRG0
32
SPR 273
SPRG1
32
SPR 274
SPRG2
32
SPR 275
S S write only S read only S S S U S S
SPRG3
32
SPR 284, 285 SPR 287 SPR 528 SPR 536 SPR 560 SPR 568 SPR 630 SPR 638
TB PVR MI_GRA L2U_GRA BBCMCR L2U_MCR DPDR IMMR
64 32 32 32 32 32 32 32
U U H POR, H U POR, H U H
MOTOROLA A-3

Table A-1 SPR (Special Purpose Registers) (Continued)
Address SPR 784 SPR 785 SPR 786 SPR 787 SPR 792 SPR 793 Access S S S S S S S S S S S S S S S S Symbol MI_RBA0 MI_RBA1 MI_RBA2 MI_RBA3 L2U_RBA0 L2U_RBA1 L2U_RBA2 L2U_RBA3 MI_RA0 MI_RA1 MI_RA2 MI_RA3 L2U_RA0 L2U_RA1 L2U_RA2 L2U_RA3 Register Region Address Register 0. See Table 4-5 for bit descriptions. Region Address Register 1. See Table 4-5 for bit descriptions. Region Address Register 2. See Table 4-5 for bit descriptions. Region Address Register 3. See Table 4-5 for bit descriptions. L2U Region 0 Address Register. See Table 11-8 for bit descriptions. L2U Region 1 Address Register. See Table 11-8 for bit descriptions. L2U Region 2 Address Register. See Table 11-8 for bit descriptions. L2U Region 3Address Register. See Table 11-8 for bit descriptions. Region Attribute Register 0. See Table 4-6 for bit descriptions. Region Attribute Register 1. See Table 4-6 for bit descriptions. Region Attribute Register 2. See Table 4-6 for bit descriptions. Region Attribute Register 3. See Table 4-6 for bit descriptions. L2U Region 0 Attribute Register. See Table 11-9 for bit descriptions. L2U Region 1 Attribute Register. See Table 11-9 for bit descriptions. L2U Region 2 Attribute Register. See Table 11-9 for bit descriptions. L2U Region 3 Attribute Register. See Table 11-9 for bit descriptions. Floating-Point Exception Cause Register. See 3.9.10.2 Floating-Point Exception Cause Register (FPECR) for bit descriptions. Size 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 Reset U U U U POR, H POR, H POR, H POR, H U U U U POR, H POR, H POR, H POR, H
SPR 794 SPR 795 SPR 816 SPR 817 SPR 818 SPR 819 SPR 824 SPR 825 SPR 826 SPR 827
SPR 1022
FPECR
32
Table A-2 CMF (CDR MoneT Flash EEPROM) Flash Array

Address 0x00 0000 0x03 FFFF 0x04 0000 0x06 FFFF Access Symbol Register CMF_A Flash Array CMF_B Flash Array Size 8, 16, 32 8, 16, 32 Reset
MOTOROLA A-4

Table A-3 USIU (Unified System Interface Unit)
Address 0x2F C000 0x2F C004 0x2F C008 0x2F C00E Access U1 U2 U, write only U SWSR Symbol SIUMCR SYPCR Register SIU Module Configuration Register. See Table 6-5 for bit descriptions. System Protection Control Register. See Table 6-13 for bit descriptions. Reserved Software Service Register. See Table 6-14 for bit descriptions. Interrupt Pending Register. See 6.13.2.1 SIPEND Register for bit descriptions. Interrupt Mask Register. See 6.13.2.2 SIU Interrupt Mask Register (SIMASK) for bit descriptions. Interrupt Edge Level Mask. See 6.13.2.3 SIU Interrupt Edge Level Register (SIEL) for bit descriptions. Interrupt Vector. See 6.13.2.4 SIU Interrupt Vector Register for bit descriptions. Transfer Error Status Register. See Table 6-15 for bit descriptions. USIU General-Purpose I/O Data Register 1. See Table 6-21 for bit descriptions. USIU General-Purpose I/O Data Register 2. See Table 6-22 for bit descriptions. USIU General-Purpose I/O Control Register. See Table 6-23 for bit descriptions. External Master Mode Control Register. See Table 6-12 for bit descriptions. Pads Module Configuration Register. See Table 2-3 for bit descriptions. Reserved Memory Controller Registers 0x2F C100 0x2F C104 0x2F C108 0x2F C10C 0x2F C110 0x2F C114 0x2F C118 U U U U U U U BR0 OR0 BR1 OR1 BR2 OR2 BR3 Base Register 0. See Table 10-7 for bit descriptions. Option Register 0. See Table 10-8 for bit descriptions. Base Register 1. See Table 10-7 for bit descriptions. Option Register 1. See Table 10-8 for bit descriptions. Base Register 2. See Table 10-7 for bit descriptions. Option Register 2. See Table 10-8 for bit descriptions. Base Register 3. See Table 10-7 for bit descriptions. 32 32 32 32 32 32 32 H H H H H H H Size 32 32 16 Reset H H S
0x2F C010
SIPEND
32
0x2F C014
SIMASK
32
0x2F C018
SIEL
32
0x2F C01C
U, read only U U U U U U
SIVEC
32
0x2F C020 0x2F C024 0x2F C028 0x2F C02C 0x2F C030 0x2F C03C 0x2F C040 0x2F C0FC
TESR SGPIODT1 SGPIODT2 SGPIOCR EMCR PDMCR
32 32 32 32 32 32
S H H H H H
MOTOROLA A-5

Table A-3 USIU (Unified System Interface Unit) (Continued)
Address 0x2F C11C 0x2F C120 0x2F C13C 0x2F C140 0x2F C144 0x2F C148 0x2F C174 0x2F C178 Access U U U U DMBR DMOR MSTAT Symbol OR3 Register Option Register 3. See Table 10-8 for bit descriptions. Reserved Dual-Mapping Base Register. See Table 10-9 for bit descriptions. Dual-Mapping Option Register. See Table 10-10 for bit descriptions. Reserved Memory Status. See Table 10-6 for bit descriptions. System Integration Timers 0x2F C200 U3
U3
Size 32 32 32 16
Reset H H H H
TBSCR
Time Base Status and Control. See Table 6-16 for bit descriptions. Time Base Reference 0. See 6.13.4.3 Time Base Reference Registers for bit descriptions. Time Base Reference 1. See 6.13.4.3 Time Base Reference Registers for bit descriptions. Reserved Real Time Clock Status and Control. See Table 6-17 for bit descriptions. Real Time Clock. See 6.13.4.6 Real-Time Clock Register (RTC) for bit descriptions. Real Time Alarm Seconds, reserved. Real Time Alarm. See 6.13.4.7 Real-Time Clock Alarm Register (RTCAL) for bit descriptions.
16
0x2F C204
TBREF0
32
0x2F C208 0x2F C20C 0x2F C21C 0x2F C220
U3
TBREF1
32
U4
RTCSC
16
0x2F C224 0x2F C228 0x2F C22C 0x2F C230 0x2F C23C 0x2F C240
RTC RTSEC RTCAL
32 32 32
U U
T4 U4
U3
PISCR
Reserved PIT Status and Control. See Table 6-18 for bit descriptions. PIT Count. See Table 6-19 for bit descriptions. PIT Register. See Table 6-20 for bit descriptions.
16 32 (half reserved) 32 (half reserved)
0x2F C244
U3
PITC
0x2F C248 0x2F C24C 0x2F C27C
U, read only
PITR
Reserved Clocks and Reset
0x2F C280
U2
SCCR
System Clock Control Register. See Table 8-9 for bit descriptions.
32
MOTOROLA A-6

Table A-3 USIU (Unified System Interface Unit) (Continued)
Address 0x2F C284 0x2F C288 0x2F C28C 0x2F C290 0x2F C294 0x2F C2FC Access U3,5,6 U3 U U Symbol PLPRCR RSR COLIR VSRMCR Register PLL Low Power and Reset Control Register. See Table 8-10 for bit descriptions. Reset Status Register. See Table 7-3 for bit descriptions. Change of Lock Interrupt Register. See Table 8-11 for bit descriptions. VDDSRM Control Register. See Table 8-12 for bit descriptions. Reserved System Integration Timer Keys Size 32 16 16 16 Reset H POR U U
0x2F C300 0x2F C304 0x2F C308 0x2F C30C 0x2F C310 0x2F C31C 0x2F C320 0x2F C324 0x2F C328 0x2F C32C 0x2F C330 0x2F C33C 0x2F C340 0x2F C344 0x2F C348 0x2F C37C
U U U U U U U U U U
TBSCRK TBREF0K TBREF1K TBK RTCSCK RTCK RTSECK RTCALK PISCRIK PITCK
Time Base Status and Control Key. See Table 8-8 for bit descriptions. Time Base Reference 0 Key. See Table 8-8 for bit descriptions. Time Base Reference 1 Key. See Table 8-8 for bit descriptions. Time Base and Decrementer Key. See Table 8-8 for bit descriptions. Reserved Real-Time Clock Status and Control Key. See Table 8-8 for bit descriptions. Real-Time Clock Key. See Table 8-8 for bit descriptions. Real-Time Alarm Seconds Key. See Table 8-8 for bit descriptions. Real-Time Alarm Key. See Table 8-8 for bit descriptions. Reserved PIT Status and Control Key. See Table 8-8 for bit descriptions. PIT Count Key. See Table 8-8 for bit descriptions. Reserved Clocks and Reset Keys
32 32 32 32 32 32 32 32 32 32
POR POR POR POR POR POR POR POR POR POR
0x2F C380
SCCRK
System Clock Control Key. See Table 8-8 for bit descriptions. PLL Low-Power and Reset Control Register Key. See Table 8-8 for bit descriptions. Reset Status Register Key. See Table 8-8 for bit descriptions.
32
POR
0x2F C384
PLPRCRK
32
POR
0x2F C388 0x2F C38C 0x2F C3FC
RSRK
32
POR
Reserved
MOTOROLA A-7

NOTES: 1. Entire register is locked if bit 15 (DLK) is set. 2. Write once after power on reset (POR). 3. Must use the key register to unlock if it has been locked by a key register, see 8.9.3.2 Keep Alive Power Registers Lock Mechanism. 4. Locked after Power on Reset (POR). A write of 0x55CCAA33 must performed to the key register to unlock. See 8.9.3.2 Keep Alive Power Registers Lock Mechanism. 5. Can have bits 0:11 (MF bits) write-protected by setting bit 4 (MFPDL) in the SCCR register to 1. Bit 21 (CSRC) and bits 22:23 (LPM) can be locked by setting bit 5 (LPML) of the SCCR register to 1. 6. Bit 24 (CSR) is write-once after soft reset.
Table A-4 CMF (CDR MoneT Flash EEPROM)

Address Access Symbol CMF_A 0x2F C800 0x2F C804 S1 S CMFMCR CMFTST CMF_A EEPROM Configuration Register. See Table 19-2 for bit descriptions. CMF_A EEPROM Test Register. See Table 19-3 for bit descriptions. CMF_A EEPROM High Voltage Control Register. See Table 19-6 for bit descriptions. CMF_B 0x2F C840 0x2F C844
S1
Register
Size
Reset
32 32
POR, H POR, H
0x2F C808
CMFCTL
32
POR, H
CMFMCR CMFTST
CMF_B EEPROM Configuration Register. See Table 19-2 for bit descriptions. CMF_B EEPROM Test Register. See Table 19-3 for bit descriptions. CMF_B EEPROM High Voltage Control Register. See Table 19-6 for bit descriptions.
32 32
POR, H POR, H
0x2F C848
CMFCTL
32
POR, H
NOTES: 1. Bit 3 (FIC) is write-once. Bit 0 (LOCK) is write-once unless in freeze or test mode.
MOTOROLA A-8

Table A-5 DPTRAM (Dual-Port TPU RAM)
Address 0x30 0000 0x30 0002 0x30 0004 Access S T S1 S, read only S, read only S, read only Symbol DPTMCR RAMTST RAMBAR Register DPT Module Configuration Register. See Table 18-2 for bit descriptions. Test register, factory test only. RAM Array Address Register. See Table 18-3 for bit descriptions. Multiple Input Signature Register High. See 18.3.4 MISR High (MISRH) and MISR Low (MISRL) for bit descriptions. Multiple Input Signature Register Low. See 18.3.4 MISR High (MISRH) and MISR Low (MISRL) for bit descriptions. MISC Counter. See 18.3.5 MISC Counter (MISCNT) for bit descriptions. Size 16 16 16 Reset S S S
0x30 0006
MISRH
16
0x30 0008
MISRL
16
0x30 000A
MISCNT
16
NOTES: 1. Entire register is write-once.
Table A-6 DPTRAM Array

Address 0x30 2000 0x30 37FF Access U, S1 Symbol DPTRAM Array Register Size Reset
NOTES: 1. Access to the DPTRAM array through the IMB3 bus is disabled once bit 5 (EMU) of either TPUMCR is set.
MOTOROLA A-9

Table A-7 TPU3 (Time Processor Unit)
Address Access Symbol Register Size Reset TPU_A (Note: Bit descriptions apply to TPU_B as well) 0x30 4000 0x30 4002 0x30 4004 S1 T S TPUMCR_A TCR_A DSCR_A TPU3_A Module Configuration Register. See Table 17-6 for bit descriptions. TPU3_A Test Configuration Register. TPU3_A Development Support Control Register. See Table 17-7 for bit descriptions. TPU3_A Development Support Status Register. See Table 17-8 for bit descriptions. TPU3_A Interrupt Configuration Register. See Table 17-9 for bit descriptions. TPU3_A Channel Interrupt Enable Register. See Table 17-10 for bit descriptions. TPU3_A Channel Function Selection Register 0. See Table 17-11 for bit descriptions. TPU3_A Channel Function Selection Register 1. See Table 17-11 for bit descriptions. TPU3_A Channel Function Selection Register 2. See Table 17-11 for bit descriptions. TPU_A Channel Function Selection Register 3. See Table 17-11 for bit descriptions. TPU_A Host Sequence Register 0. See Table 17-12 for bit descriptions. TPU_A Host Sequence Register 1. See Table 17-12 for bit descriptions. TPU_A Host Service Request Register 0. See Table 17-13 for bit descriptions. TPU_A Host Service Request Register 1. See Table 17-13 for bit descriptions. TPU_A Channel Priority Register 0. See Table 17-14 for bit descriptions. TPU_A Channel Priority Register 1. See Table 17-14 for bit descriptions. TPU_A Channel Interrupt Status Register. See Table 17-16 for bit descriptions. TPU_A Link Register TPU_A Service Grant Latch Register TPU_A Decoded Channel Number Register TPU_A Module Configuration Register 2. See Table 17-17 for bit descriptions. 16 only 16 162 S, M S, M S, M
0x30 4006
DSSR_A
162 162 162 162
S, M
0x30 4008 0x30 400A
S S
TICR_A CIER_A
S, M S, M
0x30 400C
CFSR0_A
S, M
0x30 400E
CFSR1_A
162
S, M
0x30 4010
CFSR2_A
162
S, M
0x30 4012
S S/U3
S/U3 S/U3 S/U3
CFSR3_A
162 162 162 162 162 162 162 16 162 162 162 162
S, M
0x30 4014 0x30 4016 0x30 4018 0x30 401A 0x30 401C 0x30 401E 0x30 4020 0x30 4022 0x30 4024 0x30 4026 0x30 4028
HSQR0_A HSQR1_A HSRR0_A HSRR1_A CPR0_A CPR1_A CISR_A LR_A SGLR_A DCNR_A TPUMCR2_A
S, M S, M S, M S, M S, M S, M S, M S, M S, M S, M S, M
S S S T T T S4
MOTOROLA A-10

Table A-7 TPU3 (Time Processor Unit) (Continued)
Address 0x30 402A 0x30 402C 0x30 402E 0x30 4100 0x30 410F 0x30 4110 0x30 411F 0x30 4120 0x30 412F Access S T T
S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3
Symbol TPUMCR3_A ISDR_A ISCR_A
Register TPU_A Module Configuration Register 3. See Table 17-20 for bit descriptions. TPU_A Internal Scan Data Register TPU_A Internal Scan Control Register TPU_A Channel 0 Parameter Registers TPU_A Channel 1 Parameter Registers TPU_A Channel 2 Parameter Registers. TPU_A Channel 3 Parameter Registers. TPU_A Channel 4 Parameter Registers TPU_A Channel 5 Parameter Registers TPU_A Channel 6 Parameter Registers TPU_A Channel 7 Parameter Registers TPU_A Channel 8 Parameter Registers TPU_A Channel 9 Parameter Registers TPU_A Channel 10 Parameter Registers TPU_A Channel 11 Parameter Registers TPU_A Channel 11 Parameter Registers TPU_A Channel 11 Parameter Registers TPU_A Channel 14 Parameter Registers TPU_A Channel 15 Parameter Registers TPU_B
Size 162 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322
Reset S, M
0x30 4130 0x30 413F 0x30 4140 0x30 414F 0x30 4150 0x30 415F 0x30 4160 0x30 416F 0x30 4170 0x30 417F 0x30 4180 0x30 418F 0x30 4190 0x30 419F 0x30 41A0 0x30 41AF 0x30 41B0 0x30 41BF 0x30 41C0 0x30 41CF 0x30 41D0 0x30 41DF 0x30 41E0 0x30 41EF 0x30 41F0 0x30 41FF 44001
0x30
S1 T S S S S
TPUMCR_B TCR_B DSCR_B DSSR_B TICR_B CIER_B
TPU3_B Module Configuration Register TPU3_B Test Configuration Register TPU3_B Development Support Control Register TPU3_B Development Support Status Register TPU3_B Interrupt Configuration Register TPU3_B Channel Interrupt Enable Register
16 only 16 162 162 162 162
S, M S, M S, M S, M S, M S, M
0x30 4402 0x30 4404 0x30 4406 0x30 4408 0x30 440A
MOTOROLA A-11

Address 0x30 440C 0x30 440E 0x30 4410 0x30 4412 0x30 4414 0x30 4416 0x30 4418 Access S S S S S/U3
S/U3 S/U3 S/U3
Symbol CFSR0_B CFSR1_B CFSR2_B CFSR3_B HSQR0_B HSQR1_B HSRR0_B HSRR1_B CPR0_B CPR1_B CISR_B LR_B SGLR_B DCNR_B TPUMCR2_B TPUMCR3_B ISDR_B ISCR_B
Register TPU3_B Channel Function Selection Register 0 TPU3_B Channel Function Selection Register 1 TPU3_B Channel Function Selection Register 2 TPU_B Channel Function Selection Register 3 TPU_B Host Sequence Register 0 TPU_B Host Sequence Register 1 TPU_B Host Service Request Register 0 TPU_B Host Service Request Register 1 TPU_B Channel Priority Register 0 TPU_B Channel Priority Register 1 TPU_B Channel Interrupt Status Register TPU_B Link Register TPU_B Service Grant Latch Register TPU_B Decoded Channel Number Register TPU_B Module Configuration Register 2 TPU_B Module Configuration Register 3 TPU_B Internal Scan Data Register TPU_B Internal Scan Control Register TPU_B Channel 0 Parameter Registers TPU_B Channel 1 Parameter Registers TPU_B Channel 2 Parameter Registers TPU_B Channel 3 Parameter Registers TPU_B Channel 4 Parameter Registers TPU_B Channel 5 Parameter Registers TPU_B Channel 6 Parameter Registers TPU_B Channel 7 Parameter Registers TPU_B Channel 8 Parameter Registers TPU_B Channel 9 Parameter Registers TPU_B Channel 10 Parameter Registers
Size 162 162 162 162 162 162 162 162 162 162 16 162 162 162 162 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322 16, 322
Reset S, M S, M S, M S, M S, M S, M S, M S, M S, M S, M S, M S, M S, M S, M S, M S, M
0x30 441A 0x30 441C 0x30 441E 0x30 4420 0x30 4422 0x30 4424 0x30 4426 0x30 4428 0x30 442A 0x30 442C 0x30 442E 0x30 4500 0x30 450E 0x30 4510 0x30 451E 0x30 4520 0x30 452E 0x30 4530 0x30 453E 0x30 4540 0x30 454E 0x30 4550 0x30 455E 0x30 4560 0x30 456E 0x30 4570 0x30 457E 0x30 4580 0x30 458E 0x30 4590 0x30 459E 0x30 45A0 0x30 45AE
S S S T T T S4 S T T
S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3 S/U3
MOTOROLA A-12

Address 0x30 45B0 0x30 45BF 0x30 45C0 0x30 45CF 0x30 45D0 0x30 45DF 0x30 45E0 0x30 45EF 0x30 45F0 0x30 45FF Access
S/U3 S/U3 S/U3 S/U3 S/U3
Symbol
Register TPU_B Channel 11 Parameter Registers TPU_B Channel 11 Parameter Registers TPU_B Channel 11 Parameter Registers TPU_B Channel 14 Parameter Registers TPU_B Channel 15 Parameter Registers
Size 16, 322 16, 322 16, 322 16, 322 162
Reset
NOTES: 1. Bit 10 (TPU3) and bit 11 (T2CSL) are write-once. Bits 1:2 (TCR1P) and bits 3:4 (TCR2P) are write-once if PWOD is not set in the TPUMCR3 register. This register cannot be accessed with a 32-bit read. It can only be accessed with an 8- or 16-bit read. 2. Some TPU registers can only be read or written with 16- or 32-bit accesses. 8-bit accesses are not allowed. 3. S/U = Supervisor accessible only if SUPV = 1 or unrestricted if SUPV = 0. Unrestricted registers allow both user and supervisor access. The SUPV bit is in the TPUMCR register. 4. Bits 9:10 (ETBANK), 14 (T2CF), and 15 (DTPU) are write-once.
Table A-8 QADC64 (Queued Analog-to-Digital Converter)

Address Access Symbol Register Size Reset QADC_A (Note: Bit descriptions apply to QADC_B as well) 0x30 4800 0x30 4802 0x30 4804 0x30 4806 0x30 4808 0x30 480A 0x30 480C 0x30 480E 0x30 4810 0x30 4812 0x30 4814 0x30 49FE 0x30 4A00 0x30 4A7E S T S S/U S/U S/U S/U1
S/U1
QADC64MCR_A QADC64TEST_ A QADC64INT_A PORTQA_A/ PORTQB_A DDRQA_A/ DDRQB_A QACR0_A QACR1_A QACR2_A QASR0_A QASR1_A CCW_A
QADC64 Module Configuration Register. See Table 13-7 for bit descriptions. QADC64 Test Register Interrupt Register. See Table 13-8 for bit descriptions. Port A and Port B Data. See Table 13-9 for bit descriptions. Port A Data and Port B Direction Register. See Table 13-10 for bit descriptions. QADC64 Control Register 0. See Table 13-11 for bit descriptions. QADC64 Control Register 1. See Table 13-12 for bit descriptions. QADC64 Control Register 2. See Table 13-14 for bit descriptions. QADC64 Status Register 0. See Table 13-16 for bit descriptions. QADC64 Status Register 1. See Table 13-18 for bit descriptions. Reserved Conversion Command Word Table. See Table 13-19 for bit descriptions.
16 16 16 16 16 16 16 16 16 16 16
S S U S S S S S S U
S/U S/U S/U
MOTOROLA A-13

Table A-8 QADC64 (Queued Analog-to-Digital Converter) (Continued)
Address 0x30 4A80 0x30 4AFE 0x30 4B00 0x30 4B7E 0x30 4B80 0x30 4BFE Access S/U Symbol RJURR_A Register Result Word Table Right-Justified, Unsigned Result Register. See 13.12.12 for bit descriptions. Result Word Table Left-Justified, Signed Result Register. See 13.12.12 for bit descriptions. Result Word Table Left-Justified, Unsigned Result Register. See 13.12.12 for bit descriptions. QADC_B 0x30 4C00 S T S S/U S/U S/U
S/U1 S/U1
Size 16
Reset X
S/U
LJSRR_A
16
S/U
LJURR_A
16
QADC64MCR_B QADC64 Module Configuration Register QADC64TEST_ B QADC64INT_B PORTQA_B/ PORTQB_B DDRQA_B/ DDRQB_B QACR0_B QACR1_B QACR2_B QASR0_B QASR1_B CCW_B RJURR_B LJSRR_B LJURR_B QADC64 Test Register Interrupt Register Port A and Port B Data Port A Data and Port B Direction Register QADC64 Control Register 0 QADC64 Control Register 1 QADC64 Control Register 2 QADC64 Status Register 0 QADC64 Status Register 1 Reserved Conversion Command Word Table Result Word Table. Right-Justified, Unsigned Result Register. Result Word Table. Left-Justified, Signed Result Register. Result Word Table. Left-Justified, Unsigned Result Register.
16 16 16 16 16 16 16 16 16 16 16 16 16 16
S S U S S S S S S U X X X
0x30 4C02 0x30 4C04 0x30 4C06 0x30 4C08 0x30 4C0A 0x30 4C0C 0x30 4C0E 0x30 4C10 0x30 4C12 0x30 4C14 0x30 4DFE 0x30 4E00 0x30 4E7E 0x30 4E80 0x30 4EFE 0x30 4F00 0x30 4F7E 0x30 4F80 0x30 4FFE
S/U S/U S/U S/U S/U S/U
NOTES: 1. Bit 3 (SSEx) is readable in test mode only.
MOTOROLA A-14

Table A-9 QSMCM (Queued Serial Multi-Channel Module)
Address 0x30 5000 0x30 5002 0x30 5004 0x30 5006 0x30 5008 0x30 500A Access S T S S S/U S/U S/U S/U Symbol QSMCMMCR QTEST QDSCI_IL QSPI_IL SCC1R0 SCC1R1 SC1SR SC1DR Register QSMCM Module Configuration Register. See Table 14-4 for bit descriptions. QSMCM Test Register Dual SCI Interrupt Level. See Table 14-5 for bit descriptions. Queued SPI Interrupt Level. See Table 14-6 for bit descriptions. SCI1Control Register 0. See Table 14-23 for bit descriptions. SCI1Control Register 1. See Table 14-24 for bit descriptions. SCI1 Status Register. See Table 14-25 for bit descriptions. SCI1 Data Register. See Table 14-26 for bit descriptions. Reserved QSMCM Port QS Data Register. See 14.6.1 Port QS Data Register (PORTQS) for bit descriptions. QSMCM Port QS PIn Assignment Register/ QSMCM Port QS Data Direction Register. See Table 14-11 for bit descriptions. QSPI Control Register 0. See Table 14-13 for bit descriptions. QSPI Control Register 1. See Table 14-15 for bit descriptions. QSPI Control Register 2. See Table 14-16 for bit descriptions. QSPI Control Register 3. See Table 14-17 for bit descriptions. QSPI Status Register 3. See Table 14-18 for bit descriptions. SCI2 Control Register 0 SCI2 Control Register 1 SCI2 Status Register SCI2 Data Register QSCI1 Control Register. See Table 14-30 for bit descriptions. QSCI1 Status Register. See Table 14-31 for bit descriptions. Transmit Queue Locations Receive Queue Locations Reserved Size 16 16 16 16 16 16 16 16 Reset S S S S S S S S
0x30 500C 0x30 500E 0x30 5010 0x30 5012 0x30 5014
S/U
PORTQS
16
0x30 5016
S/U
PQSPAR/ DDRQST SPCR0 SPCR1 SPCR2 SPCR3 SPSR SCC2R0 SCC2R1 SC2SR SC2DR QSCI1CR QSCI1SR SCTQ SCRQ
16
0x30 5018 0x30 501A 0x30 501C 0x30 501E 0x30 501F 0x30 5020 0x30 5022 0x30 5024 0x30 5026 0x30 5028 0x30 502A 0x30 502C 0x30 504A 0x30 504C 0x30 506A 0x30 506C 0x30 5013F
S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U1 S/U2 S/U S/U
16 16 16 8 8 16 16 16 16 16 16 16 16
S S S S S S S S S S S S S
MOTOROLA A-15

Table A-9 QSMCM (Queued Serial Multi-Channel Module) (Continued)
Address 0x30 5140 0x30 517F 0x30 5180 0x30 51BF 0x30 51C0 0x30 51DF Access S/U S/U S/U Symbol RECRAM TRAN.RAM COMD.RAM Register Receive Data RAM Transmit Data RAM Command RAM Size 16 16 16 Reset S S S
NOTES: 1. Bits 03 writeable only in test mode, otherwise read only. 2. Bits 311 writeable only in test mode, otherwise read only.
Table A-10 MIOS1 (Modular Input/Output Subsystem)
Address
Access
Symbol
Register MPWMSM0 Period Register. See Table 15-20 for bit descriptions. MPWMSM0 Pulse Register. See Table 15-21 for bit descriptions. MPWMSM0 Count Register. See Table 15-22 for bit descriptions. MPWMSM0 Status/Control Register. See Table 15-23 for bit descriptions. MPWMSM1 Period Register. See Table 15-20 for bit descriptions. MPWMSM1 Pulse Register. See Table 15-21 for bit descriptions. MPWMSM1 Count Register. See Table 15-22 for bit descriptions. MPWMSM1 Status/Control Register. See Table 15-23 for bit descriptions. MPWMSM2 Period Register. See Table 15-20 for bit descriptions. MPWMSM2 Pulse Register. See Table 15-21 for bit descriptions. MPWMSM2 Count Register. See Table 15-22 for bit descriptions. MPWMSM2 Status/Control Register. See Table 15-23 for bit descriptions. MPWMSM3 Period Register. See Table 15-20 for bit descriptions. MPWMSM3 Pulse Register. See Table 15-21 for bit descriptions. MPWMSM3 Count Register. See Table 15-22 for bit descriptions.
Size
Reset
MPWMSM0 (MIOS Pulse Width Modulation Submodule 0) 0x30 6000 0x30 6002 0x30 6004 0x30 6006 S/U S/U S/U S/U MPWMSMPERR MPWMSMPULR MPWMSMCNTR MPWMSMSCR 16 16 16 16 X X X S
MPWMSM1 (MIOS Pulse Width Modulation Submodule 1) 0x30 6008 0x30 600A 0x30 600C 0x30 600E S/U S/U S/U S/U MPWMSMPERR MPWMSMPULR MPWMSMCNTR MPWMSMSCR 16 16 16 16 X X X S
MPWMSM3 (MIOS Pulse Width Modulation Submodule 3) 0x30 6018 0x30 601A 0x30 601C S/U S/U S/U MPWMSMPERR MPWMSMPULR MPWMSMCNTR 16 16 16 X X X
MOTOROLA A-16

Table A-10 MIOS1 (Modular Input/Output Subsystem) (Continued)
Address 0x30 601E Access S/U Symbol MPWMSMSCR Register MPWMSM3 Status/Control Register. See Table 15-23 for bit descriptions. MMCSM6 Up-Counter Register. See Table 15-12 for bit descriptions. MMCSM6 Modulus Latch Register. See Table 15-13 for bit descriptions. MMCSM6 Status/Control Register Duplicated. See 15.10.1.3 MMCSM Status/Control Register (Duplicated) for bit descriptions. MMCSM6 Status/Control Register. See Table 15-14 for bit descriptions. MDASM11 Data A Register. See 15.11.1.1 MDASM Data A Register for bit descriptions. MDASM11 Data B Register. See 15.11.1.2 MDASM Data B Register (MDASMBR) for bit descriptions. MDASM11 Status/Control Register Duplicated. See 15.11.1.3 MDASM Status/Control Register (Duplicated) for bit descriptions. MDASM11 Status/Control Register. See Table 15-17 for bit descriptions. MDASM12 Data A Register. See 15.11.1.1 MDASM Data A Register for bit descriptions. MDASM12 Data B Register. See 15.11.1.2 MDASM Data B Register (MDASMBR) for bit descriptions. MDASM12 Status/Control Register Duplicated. See 15.11.1.3 MDASM Status/Control Register (Duplicated) for bit descriptions. MDASM12 Status/Control Register. See Table 15-17 for bit descriptions. MDASM13 Data A Register. See 15.11.1.1 MDASM Data A Register for bit descriptions. MDASM13 Data B Register. See 15.11.1.2 MDASM Data B Register (MDASMBR) for bit descriptions. MDASM13 Status/Control Register Duplicated. See 15.11.1.3 MDASM Status/Control Register (Duplicated) for bit descriptions. Size 16 Reset S
MMCSM6 (MIOS Modulus Counter Submodule 6) 0x30 6030 0x30 6032 S/U S/U MMCSMCNT MMCSMML 16 16 X X
0x30 6034
S/U
MMCSMSCRD
16
0x30 6036
S/U
MMCSMSCR
16
MDASM11 (MIOS Double Action Submodule 11) 0x30 6058 S/U MDASMAR 16 X
0x30 605A
S/U
MDASMBR
16
0x30 605C
S/U
MDASMSCRD
16
0x30 605E
S/U
MDASMSCR
16
0x30 6062
S/U
MDASMBR
16
0x30 6064
S/U
MDASMSCRD
16
0x30 6066
S/U
MDASMSCR
16
0x30 606A
S/U
MDASMBR
16
0x30 606C
S/U
MDASMSCRD
16
MOTOROLA A-17

Address 0x30 606E Access S/U Symbol MDASMSCR Register MDASM13 Status/Control Register. See Table 15-17 for bit descriptions. MDASM14 Data A Register. See 15.11.1.1 MDASM Data A Register for bit descriptions. MDASM14 Data B Register. See 15.11.1.2 MDASM Data B Register (MDASMBR) for bit descriptions. MDASM14 Status/Control Register Duplicated. See 15.11.1.3 MDASM Status/Control Register (Duplicated) for bit descriptions. MDASM14 Status/Control Register. See Table 15-17 for bit descriptions. MDASM15 Data A Register. See 15.11.1.1 MDASM Data A Register for bit descriptions. MDASM15 Data B Register. See 15.11.1.2 MDASM Data B Register (MDASMBR) for bit descriptions. MDASM15 Status/Control Register Duplicated. See 15.11.1.3 MDASM Status/Control Register (Duplicated) for bit descriptions. MDASM15 Status/Control Register. See Table 15-17 for bit descriptions. MPWMSM16 Period Register. See Table 15-20 for bit descriptions. MPWMSM16 Pulse Register. See Table 15-21 for bit descriptions. MPWMSM16 Count Register. See Table 15-22 for bit descriptions. MPWMSM16 Status/Control Register. See Table 15-23 for bit descriptions. MPWMSM17 Period Register. See Table 15-20 for bit descriptions. MPWMSM17 Pulse Register. See Table 15-21 for bit descriptions. MPWMSM17 Count Register. See Table 15-22 for bit descriptions. MPWMSM17 Status/Control Register. See Table 15-23 for bit descriptions. Size 16 Reset S
0x30 6072
S/U
MDASMBR
16
0x30 6074
S/U
MDASMSCRD
16
0x30 6076
S/U
MDASMSCR
16
0x30 607A
S/U
MDASMBR
16
0x30 607C
S/U
MDASMSCRD
16
0x30 607E
S/U
MDASMSCR
16
MPWMSM17 (MIOS Pulse Width Modulation Submodule 17) 0x30 6088 0x30 608A 0x30 608C 0x30 608E S/U S/U S/U S/U MPWMSMPERR MPWMSMPULR MPWMSMCNTR MPWMSMSCR 16 16 16 16 X X X S
MOTOROLA A-18

Address Access Symbol Register MPWMSM18 Period Register. See Table 15-20 for bit descriptions. MPWMSM18 Pulse Register. See Table 15-21 for bit descriptions. MPWMSM18 Count Register. See Table 15-22 for bit descriptions. MPWMSM18 Status/Control Register. See Table 15-23 for bit descriptions. MPWMSM19 Period Register. See Table 15-20 for bit descriptions. MPWMSM19 Pulse Register. See Table 15-21 for bit descriptions. MPWMSM19 Count Register. See Table 15-22 for bit descriptions. MPWMSM19 Status/Control Register. See Table 15-23 for bit descriptions. MMCSM Up-Counter Register. See Table 15-12 for bit descriptions. MMCSM Modulus Latch Register. See Table 15-12 for bit descriptions. MMCSM Status/Control Register Duplicated. See 15.10.1.3 MMCSM Status/Control Register (Duplicated) for bit descriptions. MMCSM Status/Control Register. See Table 15-14 for bit descriptions. MDASM27 Data A Register. See 15.11.1.1 MDASM Data A Register for bit descriptions. MDASM27 Data B Register. See 15.11.1.2 MDASM Data B Register (MDASMBR) for bit descriptions. MDASM27 Status/Control Register Duplicated. See 15.11.1.3 MDASM Status/Control Register (Duplicated) for bit descriptions. MDASM27 Status/Control Register. See Table 15-17 for bit descriptions. MDASM28 Data A Register. See 15.11.1.1 MDASM Data A Register for bit descriptions. MDASM28 Data B Register. See 15.11.1.2 MDASM Data B Register (MDASMBR) for bit descriptions. Size Reset MPWMSM18 (MIOS Pulse Width Modulation Submodule 18) 0x30 6090 0x30 6092 0x30 6094 0x30 6096 S/U S/U S/U S/U MPWMSMPERR MPWMSMPULR MPWMSMCNTR MPWMSMSCR 16 16 16 16 X X X S
MPWMSM19 (MIOS Pulse Width Modulation Submodule 19) 0x30 6098 S/U S/U S/U S/U MPWMSMPERR MPWMSMPULR MPWMSMCNTR MPWMSMSCR 16 16 16 16 X X X S
0x30 609A 0x30 609C 0x30 609E
MMCSM22 (MIOS Modulus Counter Submodule 22) 0x30 60B0 0x30 60B2 S/U S/U MMCSMCNT MMCSMML 16 16 X X
0x30 60B4
S/U
MMCSMSCRD
16
0x30 60B6
S/U
MMCSMSCR
16
MDASM27 (MIOS Double Action Submodule 27) 0x30 60D8 S/U MDASMAR 16 X
0x30 60DA
S/U
MDASMBR
16
0x30 60DC
S/U
MDASMSCRD
16
0x30 60DE
S/U
MDASMSCR
16
MDASM28 (MIOS Double Action Submodule 28) 0x30 60E0 S/U MDASMAR 16 X
0x30 60E2
S/U
MDASMBR
16
MOTOROLA A-19

Address Access Symbol Register MDASM28 Status/Control Register Duplicated. See 15.11.1.3 MDASM Status/Control Register (Duplicated) for bit descriptions. MDASM28 Status/Control Register. See Table 15-17 for bit descriptions. MDASM29 Data A Register. See 15.11.1.1 MDASM Data A Register for bit descriptions. MDASM29 Data B Register. See 15.11.1.2 MDASM Data B Register (MDASMBR) for bit descriptions. MDASM29 Status/Control Register Duplicated. See 15.11.1.3 MDASM Status/Control Register (Duplicated) for bit descriptions. MDASM29 Status/Control Register. See Table 15-17 for bit descriptions. MDASM30 Data A Register. See 15.11.1.1 MDASM Data A Register for bit descriptions. MDASM30 Data B Register. See 15.11.1.2 MDASM Data B Register (MDASMBR) for bit descriptions. MDASM30 Status/Control Register Duplicated. See 15.11.1.3 MDASM Status/Control Register (Duplicated) for bit descriptions. MDASM30 Status/Control Register. See Table 15-17 for bit descriptions. MDASM31 Data A Register. See 15.11.1.1 MDASM Data A Register for bit descriptions. MDASM31 Data B Register. See 15.11.1.2 MDASM Data B Register (MDASMBR) for bit descriptions. MDASM31 Status/Control Register Duplicated. See 15.11.1.3 MDASM Status/Control Register (Duplicated) for bit descriptions. MDASM31 Status/Control Register. See Table 15-17 for bit descriptions. MPIOSM Data Register. See Table 15-26 for bit descriptions. MPIOSM Data Direction Register. See Table 15-27 for bit descriptions. Size Reset
0x30 60E4
S/U
MDASMSCRD
16
0x30 60E6
S/U
MDASMSCR
16
MDASM29 (MIOS Double Action Submodule 29) 0x30 60E8 S/U MDASMAR 16 X
0x30 60EA
S/U
MDASMBR
16
0x30 60EC
S/U
MDASMSCRD
16
0x30 60EE
S/U
MDASMSCR
16
MDASM30 (MIOS Double Action Submodule 30) 0x30 60F0 S/U MDASMAR 16 X
0x30 60F2
S/U
MDASMBR
16
0x30 60F4
S/U
MDASMSCRD
16
0x30 60F6
S/U
MDASMSCR
16
MDASM31 (MIOS Double Action Submodule 31) 0x30 60F8 S/U MDASMAR 16 X
0x30 60FA
S/U
MDASMBR
16
0x30 60FC
S/U
MDASMSCRD
16
0x30 60FE
S/U
MDASMSCR
16
MPIOSM (MIOS 16-bit Parallel Port I/O Submodule) 0x30 6100 0x30 6102 S/U S/U MPIOSMDR MPIOSMDDR 16 16 X S
MOTOROLA A-20

Address 0x30 6104 0x30 6106 Access S/U Symbol Reserved Register Size Reset
MBISM (MIOS Bus Interface Submodule) 0x30 6800 0x30 6802 0x30 6804 0x30 6806 0x30 6808 0x30 680E 0x30 6810 0x30 6814 0x30 6816 S1 S S, read only S S MIOS1TPCR MIOS1VNR MIOS1MCR MIOS1 Test and Pin Control Register. See Table 15-3 for bit descriptions. Reserved MIOS1 Module Version Number Register. See Table 15-4 for bit descriptions. MIOS1 Module Control Register. See Table 15-4 for bit descriptions. Reserved 16 16 16 S X S
MCPSM (MIOS Counter Prescaler Submodule) S S MCPSMSCR Reserved MCPSM Status/Control Register. See Table 15-10 for bit descriptions. MIRSM0 Interrupt Status Register. See Table 15-29 for bit descriptions. Reserved MIRSM0 Interrupt Enable Register. See Table 15-30 for bit descriptions. MIRSM0 Request Pending Register. See Table 15-31 for bit descriptions. MIOS1 Interrupt Level Register 0. See Table 15-7 for bit descriptions. MIRSM1 Interrupt Status Register. See Table 15-33 for bit descriptions. Reserved MIRSM1 Interrupt Enable Register. See Table 15-34 for bit descriptions. MIRSM1 Request Pending Register. See Table 15-35 for bit descriptions. MIOS1 Interrupt Level Register 1. See Table 15-8 for bit descriptions. 16 S S
MIRSM0 (MIOS Interrupt Request Submodule 0) 0x30 6C00 0x30 6C02 0x30 6C04 0x30 6C06 S S S S, read only MIOS1SR0 MIOS1ER0 MIOS1RPR0 16 16 16 X S S
MIRSM (MIOS Interrupt Request Submodule) 0x30 6C30 S MIOS1LVL0 16 S
MIRSM1 (MIOS Interrupt Request Submodule 1) 0x30 6C40 0x30 6C42 0x30 6C44 0x30 6C46 S S S S, read only MIOS1SR1 MIOS1ER1 MIOS1RPR1 16 16 16 X S S
MIRSM (MIOS Interrupt Request Submodule) 0x30 6C70 S MIOS1LVL1 16 S
NOTES: 1. Bit 0 (TEST) is reserved for factory testing.
MOTOROLA A-21

Table A-11 TouCAN (CAN 2.0B Controller)
Address Access Symbol Register Size Reset
TouCAN_A (Note: Bit descriptions apply to TouCAN_B as well) 0x30 7080 0x30 7082 0x30 7084 S T S TCNMCR_A CANTCR_A CANICR_A TouCAN_A Module Configuration Register. See Table 16-11 for bit descriptions. TouCAN_A Test Register TouCAN_A Interrupt Configuration Register. See Table 16-12 for bit descriptions. TouCAN_A Control Register 0/ TouCAN_A Control Register 1. See Table 16-13 and Table 16-16 for bit descriptions. TouCAN_A Control and Prescaler Divider Register/ TouCAN_A Control Register 2. See Table 16-17 and Table 16-18 for bit descriptions. TouCAN_A Free-Running Timer Register. See Table 16-19 for bit descriptions. RXGMSKHI_A RXGMSKLO_A Reserved TouCAN_A Receive Global Mask High. See Table 16-20 for bit descriptions. TouCAN_A Receive Global Mask Low. See Table 16-20 for bit descriptions. TouCAN_A Receive Buffer 14 Mask High. See 16.7.10 Receive Buffer 14 Mask Registers for bit descriptions. TouCAN_A Receive Buffer 14 Mask Low. See 16.7.10 Receive Buffer 14 Mask Registers for bit descriptions. TouCAN_A Receive Buffer 15 Mask High. See 16.7.11 Receive Buffer 15 Mask Registers for bit descriptions. TouCAN_A Receive Buffer 15 Mask Low. See 16.7.11 Receive Buffer 15 Mask Registers for bit descriptions. Reserved TouCAN_A Error and Status Register. See Table 16-21 for bit descriptions. TouCAN_A Interrupt Masks. See Table 16-24 for bit descriptions. TouCAN_A Interrupt Flags. See Table 16-25 for bit descriptions. TouCAN_A Receive Error Counter/ TouCAN_A Transmit Error Counter. See Table 16-26 for bit descriptions. 16 16 16 16 16 S S S
0x30 7086
S/U
CANCTRL0_A/ CANCTRL1_A
16
0x30 7088
S/U
PRESDIV_A/ CTRL2_A
16
0x30 708A 0x30 708C 0x30 708E 0x30 7090 0x30 7092
S/U S/U S/U
TIMER_A
S S S
0x30 7094
S/U
RX14MSKHI_A
16
0x30 7096
S/U
RX14MSKLO_A
16
0x30 7098
S/U
RX15MSKHI_A
16
0x30 709A 0x30 709C 0x30 709E 0x30 70A0 0x30 70A2 0x30 70A4
S/U
RX15MSKLO_A
16
S/U S/U S/U ESTAT_A IMASK_A IFLAG_A
16 16 16
S S S
0x30 70A6
S/U
RXECTR_A/ TXECTR_A
16
MOTOROLA A-22

Table A-11 TouCAN (CAN 2.0B Controller) (Continued)
Address 0x307100 0x30710F 0x307110 0x30711F 0x307120 0x30712F 0x307130 0x30713F Access Symbol Register TouCAN_A Message Buffer 0. See Figure 16-3 and Figure 16-4 for message buffer definitions. TouCAN_A Message Buffer 1. See Figure 16-3 and Figure 16-4 for message buffer definitions. TouCAN_A Message Buffer 2. See Figure 16-3 and Figure 16-4 for message buffer definitions. TouCAN_A Message Buffer 3. See Figure 16-3 and Figure 16-4 for message buffer definitions. TouCAN_A Message Buffer 4. See Figure 16-3 and Figure 16-4 for message buffer definitions. TouCAN_A Message Buffer 5. See Figure 16-3 and Figure 16-4 for message buffer definitions. TouCAN_A Message Buffer 6. See Figure 16-3 and Figure 16-4 for message buffer definitions. TouCAN_A Message Buffer 7. See Figure 16-3 and Figure 16-4 for message buffer definitions. TouCAN_A Message Buffer 8. See Figure 16-3 and Figure 16-4 for message buffer definitions. TouCAN_A Message Buffer 9. See Figure 16-3 and Figure 16-4 for message buffer definitions. TouCAN_A Message Buffer 10. See Figure 16-3 and Figure 16-4 for message buffer definitions. TouCAN_A Message Buffer 11. See Figure 16-3 and Figure 16-4 for message buffer definitions. TouCAN_A Message Buffer 12. See Figure 16-3 and Figure 16-4 for message buffer definitions. TouCAN_A Message Buffer 13. See Figure 16-3 and Figure 16-4 for message buffer definitions. TouCAN_A Message Buffer 14. See Figure 16-3 and Figure 16-4 for message buffer definitions. TouCAN_A Message Buffer 15. See Figure 16-3 and Figure 16-4 for message buffer definitions. Size Reset U
S/U
MBUFF0_A
S/U
MBUFF1_A
S/U
MBUFF2_A
S/U
MBUFF3_A
0x307140 0x30714F 0x307150 0x30715F 0x307160 0x30716F 0x307170 0x30717F 0x307180 0x30718F 0x307190 0x30719F 0x3071A0 0x3071AF 0x3071B0 0x3071BF 0x3071C0 0x3071CF 0x3071D0 0x3071DF 0x3071E0 0x3071EF 0x3071F0 0x3071FF
S/U
MBUFF4_A
S/U
MBUFF5_A
S/U
MBUFF6_A
S/U
MBUFF7_A
S/U
MBUFF8_A
S/U
MBUFF9_A
S/U
MBUFF10_A
S/U
MBUFF11_A
S/U
MBUFF12_A
S/U
MBUFF13_A
S/U
MBUFF14_A
S/U
MBUFF15_A
MOTOROLA A-23

Address Access Symbol TouCAN_B 0x30 7480 0x30 7482 0x30 7484 0x30 7486 S T S S/U TCNMCR_B CANTCR_B CANICR_B CANCTRL0_B/ CANCTRL1_B PRESDIV_B/ CTRL2_B TIMER_B RXGMSKHI_B RXGMSKLO_B RX14MSKHI_B RX14MSKLO_B RX15MSKHI_B RX15MSKLO_B ESTAT_B IMASK_B IFLAG_B RXECTR_B/ TXECTR_B MBUFF0_B MBUFF1_B MBUFF2_B MBUFF3_B MBUFF4_B MBUFF5_B MBUFF6_B MBUFF7_B MBUFF8_B MBUFF9_B TouCAN_B Module Configuration Register TouCAN_B Test Register TouCAN_B Interrupt Configuration Register TouCAN_B Control Register 0/ TouCAN_B Control Register 1 TouCAN_B Control and Prescaler Divider Register/ TouCAN_B Control Register 2 TouCAN_B Free-Running Timer Register Reserved TouCAN_B Receive Global Mask High TouCAN_B Receive Global Mask Low TouCAN_B Receive Buffer 14 Mask High TouCAN_B Receive Buffer 14 Mask Low TouCAN_B Receive Buffer 15 Mask High TouCAN_B Receive Buffer 15 Mask Low Reserved TouCAN_B Error and Status Register TouCAN_B Interrupt Masks TouCAN_B Interrupt Flags TouCAN_B Receive Error Counter/ TouCAN_B Transmit Error Counter TouCAN_B Message Buffer 0. TouCAN_B Message Buffer 1. TouCAN_A Message Buffer 2. TouCAN_B Message Buffer 3. TouCAN_B Message Buffer 4. TouCAN_B Message Buffer 5. TouCAN_B Message Buffer 6. TouCAN_B Message Buffer 7. TouCAN_B Message Buffer 8. TouCAN_B Message Buffer 9. 16 16 16 16 16 16 16 16 16 16 16 16 16 16 S S S S Register Size Reset
0x30 7488 0x30 748A
S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U S/U
16
S S S S S S S S S S S S U U U U U U U U U U
0x30 748C 0x30 748E 0x30 7490 0x30 7492 0x30 7494 0x30 7496 0x30 7498 0x30 749A 0x30 749C 0x30 749E 0x30 74A0 0x30 74A2 0x30 74A4 0x30 74A6 0x307500 0x30750F 0x307510 0x30751F 0x307520 0x30752F 0x307530 0x30753F 0x307540 0x30754F 0x307550 0x30755F 0x307560 0x30756F 0x307570 0x30757F 0x307580 0x30758F 0x307590 0x30759F
MOTOROLA A-24

Address 0x3075A0 0x3075AF 0x3075B0 0x3075BF 0x3075C0 0x3075CF 0x3075D0 0x3075DF 0x3075E0 0x3075EF Access S/U S/U S/U S/U S/U S/U Symbol MBUFF10_B MBUFF11_B MBUFF12_B MBUFF13_B MBUFF14_B MBUFF15_B Register TouCAN_B Message Buffer 10. TouCAN_B Message Buffer 11. TouCAN_B Message Buffer 12. TouCAN_B Message Buffer 13. TouCAN_B Message Buffer 14. TouCAN_B Message Buffer 15. Size Reset U U U U U U
0x3075F0 0x3075FF
Table A-12 UIMB (U-Bus to IMB3 Bus Interface)

Address 0x30 7F80 0x30 7F90 0x30 7FA0 Access S1 S/T S, read only Symbol UMCR UTSTCREG UIPEND Register UIMB Module Configuration Register. See Table 12-6 for bit descriptions. Test Register Reserved Pending Interrupt Request Register. See Table 12-7 for bit descriptions. Size 32 32 32 Reset H H
NOTES: 1. Bit 3 (HSPEED) is write-once.
Table A-13 SRAM (Static RAM Access Memory)

Address Access Symbol SRAM_A 0x38 0000 0x38 0004 S1 T SRAMMCR_A SRAMTST_A SRAM_A Module Configuration Register. See Table 20-1 for bit descriptions. SRAM_A Test Register. SRAM_B 0x38 0008 0x38 000C S1 T SRAMMCR_B SRAMTST_B SRAM_B Module Configuration Register. See Table 20-1 for bit descriptions. SRAM_B Test Register. 16 16 S,H, POR S,H, POR 16 16 S,H, POR S,H, POR Register Size Reset
NOTES: 1. Bit 0 (LCK) locks the register (write-protected except in test mode) and is write once.
MOTOROLA A-25

Table A-14 SRAM (Static RAM Access Memory) Array
Address 0x3F 8000 0x3F 97FF 0x3F 9800 0x3F BFFF 0x3F C000 0x3F FFFF Access U, S U, S Symbol Reserved SRAM_A RAM Array (10 K Bytes) SRAM_B RAM Array (16 K Bytes) Register Size 8, 16, 32 8, 16, 32 Reset

MOTOROLA A-26
APPENDIX B REGISTER GENERAL INDEX

A Associated registers 10-4 B BAR (breakpoint address register) 21-46 BBC global region attribute register description (MI_GRA) 4-23 module configuration register (BBCMCR) 4-24 region attribute registers MI_RAx description (MI_RAx) 4-21 region base address registers (MI_RBAx) 4-21 BBCMCR (BBC module configuration register) 4-24 BR0 (BR3 - memory controller base registers 0 - 3) 10-28 Breakpoint address register (BAR) 21-46 Breakpoint counter A value and control register (COUNTA) 21-52 Breakpoint counter B value and control register (COUNTB) 21-53 C CANCTRL0 (control register 0) 16-25 CANCTRL1 (control register 1) 16-26 CANCTRL2 (control register 2) 16-28 CANICR (TouCAN interrupt configuration register) 16-24 CANMCR (TouCAN module configuration register) 16-22 CCW (conversion command word table) 13-46 CFSR0 (TPU3 channel function select register 0) 17-16 CFSR1 (TPU3 channel function select register 1) 17-16 CFSR2 (TPU3 channel function select register 2) 17-16 CFSR3 (TPU3 channel function select register 3) 17-16 CIER (TPU3 channel interrupt enable register) 17-15 CISR (TPU3 channel interrupt status register) 17-19 CMF EEPROM configuration register (CMFMCR) 19-5 EEPROM control registers 19-4 EEPROM high voltage control register (CMFCTL) 19-9 CMFCFIG (hard reset configuration word) 19-17 CMFCTL (CMF EEPROM high voltage control register) 19-7, 19-9 CMFMCR (CMF EEPROM configuration register) 19-5 CMPA-CMPD (comparator A-D value register) 21-45 CMPE-CMPF (comparator E-F value registers) 21-46 CMPG-CMPH (comparator G-H value registers) 21-46 COLIR change of lock interrupt register 8-35 COLIR (change of lock register) 8-35 Comparator A-D value registers (CMPA-CMPD) 21-45 Comparator E-F value registers (CMPE-CMPF) 21-46 Comparator G-H value registers (CMPG-CMPH) 21-46 COUNTA (breakpoint counter A value and control register) 21-52 COUNTB (breakpoint counter B value and control register) 21-53 CPR0 (TPU3 channel priority register 0) 17-18 CPR1 (TPU3 channel priority register 1) 17-18 CR (condition register) 3-16
REGISTER GENERAL INDEX
MOTOROLA B-1

CTR (count register) 3-19 D DAR (data address register) 3-22 DDRQA (port QA data direction register) 13-35 DDRQS (PORTQS data direction register) 14-12 Debug enable register (DER) 21-55 DEC (decrementer register) 3-24, 6-28 Decrementer register (DEC) 6-28 DER (debug enable register) 21-55 Development port data register (DPDR) 21-57 DMBR (dual mapping base register) 10-31 DMOR (dual mapping option register) 10-32 DPTMCR (DPTRAM module configuration register) 18-4 DPTRAM module configuration register (DPTMCR) 18-3 ram base address register (RAMBAR) 18-5 test register 18-4 DSCR (TPU3 development support control register) 17-12 DSISR (dae/source instruction service register) 3-22 DSSR (TPU3 development support status register) 17-14 Dual mapping base register (DMBR) 10-31 Dual mapping option register 10-32 E ECR (exception cause register) 21-54 EMCR (external master control register) 6-22 ESTAT (error and status register) 16-30 Exception cause register (ECR) 21-53 External master control register (EMCR) 6-22 F FPRs - (floating-point registers) 3-12 FPSCR (floating-point status and control register) 3-13 G General-Purpose I/O registers 6-34 GPRs (general-purpose registers) 3-12 H HSQR0 (TPU3 host sequence register 0) 17-17 HSQR1 (TPU3 host sequence register 1) 17-17 HSSR0 (TPU3 host service request register 0) 17-17 HSSR1 (TPU3 host service request register 1) 17-18 I I-Bus support control register (ICTRL) 21-47 ICTRL (i-bus support control register) 21-47 IFLAG (interrupt flag register) 16-33 IMASK (interrupt mask register) 16-32 IMMR (internal memory mapping register) 6-21 Internal memory map register 6-21 K Keep alive power registers lock mechanism 8-23
MOTOROLA B-2

L L2U global region attribute register (L2U_GRA) 11-15 module configuration register (L2U_MCR) 11-13 region attribute registers (L2U_RAx) 11-15 region base address registers (L2U_RBAx) 11-14 L2U_GRA (L2U global region attribute register) 11-16 L2U_MCR (L2U module configuration register) 11-13 L2U_RAx (L2U region X attribute register) 11-15 L2U_RBAx (L2U region x base address register) 11-14 L-Bus support control register 1 (LCTRL1) 21-49 L-Bus support control register 2 (LCTRL2) 21-50 LCTRL1 (l-bus support control register 1) 21-49 LCTRL2 (l-bus support control register 2) 21-50 LJSRR (left justified, signed result register) 13-49 LJURR (left justified, unsigned result register) 13-50 LR (link register) 3-18 M MBISM interrupt registers 15-10 MCPSM status/control register (MCPSMCSCR) 15-13 MCPSMSCR (MCPSM status/control register) 15-13 MDASM data A register (MDASMAR) 15-21 data B register (MDASMBR) 15-21 status/control register - duplicated (MDASMSCRD) 15-22 status/control register (MDASMSCR) 15-23 MDASMAR (MDASM data A register) 15-21 MDASMBR (MDASM data B register) 15-22 MDASMSCR (MDASM status/control register) 15-23 MDASMSCRD (MDASM status/control register - duplicated) 15-22 Memory controller base registers (BR0 - BR3) 10-28 Memory controller option registers (OR0 - OR3) 10-30 Memory controller status registers (MSTAT) 10-28 MI_GRA (global region attribute register) 4-23 MIOS 16-bit parallel port I/O submodule (MPIOSM) Registers 15-30 bus interface (MBISM) Registers 15-8 counter prescaler submodule (MCPSM) Registers 15-12 double action submodule (MDASM) Registers 15-19 interrupt request submodule 0 (MIRSM0) Registers 15-33 interrupt request submodule 1 (MIRSM1) Registers 15-36 modulus counter submodule (MMCSM) Registers 15-15 pulse width modulation submodule (MPWMSM) Registers 15-26 MIOS1 interrupt level register 0 (MIOSLVL0) (MIOS1LVL0) 15-10 interrupt level register 1 (MIOSLVL1) (MIOS1LVL1) 15-11 module and version number register (MIOS1VNR) 15-9 module configuration register (MIOS1MCR) 15-9 test and pin control register 15-8 vector register 15-9 MIOS1ER0 (MIRSM0 interrupt enable register) 15-35 MIOS1ER1 (interrupt enable register) 15-37 MIOS1LVL0 (MIOS1 interrupt level register 0) 15-11 MIOS1LVL1 (MIOS1 interrupt level 1 register) 15-11 MIOS1MCR (MIOS1 module configuration register) 15-9 MIOS1RPR0 (MIRSM0 request pending register) 15-35
MOTOROLA B-3

MIOS1RPR1 (MIRSM1 request pending register) 15-38 MIOS1SR0 (MIRSM0 interrupt status register) 15-34 MIOS1SR1 (MIRSM1 interrupt status register) 15-36 MIOS1TPCR ((test and pin control register) 15-8 MIOS1VNR (MIOS1 module/version number register) 15-9 MIRSM0 interrupt enable register (MIOS1ER0) 15-35 interrupt status register (MIOS1SR0) 15-34 request pending register (MIOS1RPR0) 15-35 MIRSM1 interrupt enable register (MIOS1ER1) 15-37 interrupt status register (MIOS1SR1) 15-36 request pending register (MIOS1RPR1) 15-37 MISCNT (MISC counter) 18-6 MISRH (multiple input signature register high) 18-5 MISRL (multiple input signature register low) 18-6 MMCSM modulus latch register (MMCSMML) 15-16 status/control register - duplicated (MMCSMSCRD) 15-16 status/control register (MMCSMSCR) 15-17 up-counter register (MMCSMCNT) 15-16 MMCSMCNT (MMCSM up-counter register) 15-16 MMCSMML (MMCSM modulus latch register) 15-16 MMCSMSCR (MMCSM status/control register) 15-17 MMCSMSCRD (MMCSM status/control register - duplicated) 15-17 MPIOSM data direction register (MPIOSMDDR) 15-31 data register (MPIOSMDR) 15-30 MPIOSMDDR (MPIOSM data direction register) 15-31 MPIOSMDR (MPIOSM data register) 15-31 MPWMSM counter register (MPWMSMCNTR) 15-28 period register (MPWMSMPERR) 15-27 pulse width register (MPWMSMPULR) 15-27 status/control register (MPWMSMCR) 15-28 MPWMSMCNTR (MPWMSM counter register) 15-28 MPWMSMPERR (MPWMSM period register) 15-27 MPWMSMPULR (MPWMSM pulse width register) 15-27 MPWMSMSCR (MPWMSM status/control register) 15-28 MSR (machine state register) 3-20 MSTAT (memory controller status register) 10-28 O OR0 (OR3 - memory controller option registers 0 - 3) 10-30 P PDMCR (Pad module configuration register) 2-29 Periodic interrupt status and control register (PISCR) 6-32 Periodic interrupt timer count register (PITC) 6-32 Periodic interrupt timer register (PITR) 6-33 PISCR (periodic interrupt status and control register) 6-32 PITC (periodic interrupt timer count) 6-32 PITR (periodic interrupt timer register) 6-33 PLL, low power, and reset control register (PLPRCR) 8-33 PLPRCR (PLL, low power, and reset control register) 8-33 PORTQA (port QA data register) 13-34 PORTQB (port QB data register) 13-34 PORTQS (port QS data register) 14-11
MOTOROLA B-4

PQSPAR (PORTQS pin assignment register) 14-11 PRESDIV (prescaler divide register) 16-27 PVR (processor version register) 3-25 Q QACR0 (QADC64 control register 0) 13-35 QACR1 (QADC64 control register 1) 13-36 QACR2 (QADC64 control register 2) 13-39 QADC64 control register 0 (QACR0) 13-35 control register 1 (QADC64CR1) 13-36 control register 2 (QADC64CR2) 13-38 interrupt register (QADC64INT) 13-33 module configuration register (QADC64MCR) 13-33 port A/B data register (PORTQA/B) 13-34 port data direction register (DDRQA) 13-35 status register 0 (QADC64SR0) 13-40 status register 1 (QADC64SR1) 13-42 successive approximation register (SAR) 13-14 test register (QADC64TEST) 13-33 QADC64INT (QADC64 interrupt register) 13-33 QADC64MCR (QADC64 module configuration register) 13-33 QASR0 (QADC64 status register 0) 13-41, 13-42 QDSCI_IL (QSM2 dual SCI interrupt level register) 14-8 QSCI1CR (QSCI1 control register) 14-59 QSCI1SR (QSCI1 status register) 14-61 QSMCM configuration register (QMCR) 14-7 interrupt level registers (QDSCI_IL, QSPI_IL) 14-8 port QS data register (PORTQS) 14-10 PORTQS data direction register (DDRQS) 14-12 PORTQS pin assignment register (PQSPAR) 14-11 QSCI1 control register (QSCI1CR) 14-59 QSCI1 status register (QSCI1SR) 14-61 QSPI command RAM (CRx) 14-22 QSPI control register 0 (SPCR0) 14-16 QSPI control register 1 (SPCR1) 14-18 QSPI control register 2 (SPCR2) 14-18 QSPI control register 3 (SPCR3) 14-19 QSPI registers 14-15 QSPI status register (SPSR) 14-20 queued SCI1 status and control registers 14-59 SCI control register 0 (SCCxR0) 14-45 SCI control register 1 (SCCxR1) 14-45 SCI data register (SCxDR) 14-49 SCI registers 14-44 SCI status register (SCxSR) 14-47 test register (QTEST) 14-8 QSMCMMCR (QSMCM module configuration register) 14-7 QSPI_IL (QSPI interrupt level register) 14-9 R RAMBAR (ram array base address register) 18-5 RCPU additional implementation-specific registers 3-27 condition register (CR) 3-15 condition register CR0 field definition 3-16 condition register CR1 field definition 3-16 condition register crn field - compare instruction 3-17
MOTOROLA B-5

count register (CTR) 3-19 dae/source instruction service register (DSISR) 3-22 data address register (DAR) 3-22 decrementer register (DEC) 3-23 EIE, EID, and NRI special-purpose registers 3-26 floating-point exception cause register (FPECR) 3-26 floating-point registers (FPRs) 3-12 floating-point status and control register (FPSCR) 3-12 general special-purpose registers (SPRG0-SPRG3) 3-25 general-purpose registers (GPRs) 3-12 implementation-specific special-purpose registers 3-26 integer exception register (XER) 3-17 link register (LR) 3-18 machine state register (MSR) 3-20 machine status save/restore register 0 (SRR0) 3-24 machine status save/restore register 1 (SRR1) 3-24 powerpc OEA register set 3-20 powerpc UISA register set 3-11 powerpc VEA register set - time base 3-19 processor version register (PVR) 3-25 Real-Time clock alarm register (RTCAL) 6-31 Real-Time clock register (RTC) 6-31 Real-Time clock status and control register (RTCSC) 6-30 Region attribute registers (0 - 3) 4-21 Reset status register (RSR) 7-5 RJURR (right justified, unsigned result register) 13-49 RSR (reset status register) 7-5 RTC (real time clock alarm register) 6-31 RTC (real time clock register) 6-31 RTCSC (real time clock status and control register) 6-30 RXECTR (receive error counter) 16-33 RXGMSKHI (receive global mask register high) 16-29 S SCCR (system clock control register) 8-30 SCCxR0 (QSMCM SCI control register 0) 14-45 SCCxR1 (QSMCM SCI control register 1) 14-46 SCDR (QSMCM SCI data register) 14-49 SCxSR (QSMCM SCIx status register) 14-47 SGPIO control register (SGPIOCR) 6-35 data register 1 (SGPIODT1) 6-34 data register 2 (SGPIODT2) 6-34 SGPIOCR (SGPIO control register) 6-35 SGPIODT1 (SGPIO data register 1) 6-34 SGPIODT2 (SGPIO data register 2) 6-34 SIEL (SIU interrupt edge level register) 6-25 SIMASK (SIU interrupt mask register) 6-24 SIPEND register (SIPEND) 6-23 SIPEND (SIU interrupt pending register) 6-24 SIU interrupt edge level register (SIEL) 6-25 interrupt mask register (SIMASK) 6-24 interrupt registers 6-23 interrupt vector register (SIVEC) 6-25 module configuration register (SIUMCR) 6-18 SIUMCR (SIU module configuration register) 6-18 SIVEC (SIU interrupt vector) 6-25 Software service register (SWSR) 6-26
MOTOROLA B-6

SPCR0 (QSPI control register 0) 14-16 SPCR1 (QSPI control register 1) 14-18 SPCR2 (QSPI control register 2) 14-19 SPCR3 (QSPI control register) 14-19 SPRG0-SPRG3 (general special-purpose registers 0-3) 3-25 SPSR (QSPI status register) 14-20 SRAM module configuration register (SRAMMCR) 20-2 test register (SRAMTST) 20-3 SRAMMCR (SRAM module configuration register) 20-3 SRR0 (machine status save/restore register 0) 3-24 SRR1 (machine status save/restore register 1) 3-25 SWSR (software service register) 6-27 SYPCR (system protection control register) 6-26 System clock control register (SCCR) 8-30 System configuration and protection registers 6-18 System configuration registers 6-18 System protection control register (SYPCR) 6-26 System protection registers 6-26 System timer registers 6-28 T TB (time base) 3-19, 3-23, 6-29 TBREF0 (time base reference register 0) 6-29 TBREF1 (time base reference register 1) 6-29 TBSCR (time base control and status register) 6-30 TESR (transfer error status register) 6-27 TICR (TPU3 interrupt configuration register) 17-14 Time base control and status register (TBSCR) 6-29 Time base reference registers (TBREF0) 6-29 TIMER (free running timer register) 16-29 TouCAN control register 0 (CANCTRL0) 16-25 control register 1 (CANCTRL1) 16-26 control register 2 (CANCTRL2) 16-28 error and status register (ESTAT) 16-30 interrupt configuration register (CANICR) 16-24 interrupt flag register (IFLAG) 16-33 interrupt mask register (IMASK) 16-32 module configuration register (CANMCR) 16-22 prescaler divide register (PRESDIV) 16-27 receive buffer 14 mask registers 16-30 receive buffer 15 mask registers 16-30 receive global mask registers (RXGMSKHI) 16-29 receive mask registers 16-7 test configuration register 16-24 TPU3 channel function select registers (CFSRx) 17-15 channel interrupt enable register (CIER) 17-15 channel interrupt status register (CISR) 17-19 channel priority registers (CPRx) 17-18 decoded channel number register (DCNR) 17-19 development support control register (DSCR) 17-12 development support status register (DSSR) 17-14 host sequence registers (HSQRx) 17-16 host service request registers (HSSRx) 17-17 interrupt configuration register (TICR) 17-14 link register (LR) 17-19 module configuration register (TPUMCR) 17-10 module configuration register 2 (TPUMCR2) 17-20
MOTOROLA B-7

module configuration register 3 (TPUMCR3) 17-21 service grant latch register (SGLR) 17-19 test configuration register (TCR) 17-12 test registers (ISDR, ISCR) 17-22 TPUMCR (TPU3 module configuration register) 17-10 TPUMCR2 (TPU3 module configuration register 2) 17-20 TPUMCR3 (TPU3 module configuration register 3) 17-21 Transfer error status register (TESR) 6-27 U UIMB module configuration register (UMCR) 12-7 pending interrupt request register (UIPEND) 12-8 test control register (UTSTCREG) 12-8 UIPEND (UIMB pending interrupt reqiuest register) 12-8 UMCR (UIMB module configuration register) 12-7
V VDDSRM sensor register (VSRMSR) 8-36 VSRMSR (VDDSRM control register) 8-36 X XER (integer exception register) 3-17
MOTOROLA B-8
APPENDIX C REGISTER DIAGRAM INDEX

B BAR (breakpoint address register) 21-46 BBCMCR (BBC module configuration register) 4-24 BR0 (BR3 - memory controller base registers 0 - 3) 10-28 C CANCTRL0 (control register 0) 16-25 CANCTRL1 (control register 1) 16-26 CANCTRL2 (control register 2) 16-28 CANICR (TouCAN interrupt configuration register) 16-24 CANMCR (TouCAN module configuration register) 16-22 CCW (conversion command word table) 13-46 CFSR0 (TPU3 channel function select register 0) 17-16 CFSR1 (TPU3 channel function select register 1) 17-16 CFSR2 (TPU3 channel function select register 2) 17-16 CFSR3 (TPU3 channel function select register 3) 17-16 CIER (TPU3 channel interrupt enable register) 17-15 CISR (TPU3 channel interrupt status register) 17-19 CMFCFIG (hard reset configuration word) 19-17 CMFCTL (CMF EEPROM high voltage control register) 19-7, 19-9 CMFMCR (CMF EEPROM configuration register) 19-5 CMPA-CMPD (comparator A-D value register) 21-45 CMPE-CMPF (comparator E-F value registers) 21-46 CMPG-CMPH (comparator G-H value registers) 21-46 COLIR (change of lock interrupt register) 8-35 COUNTA (breakpoint counter A value and control register) 21-52 COUNTB (breakpoint counter B value and control register) 21-53 CPR0 (TPU3 channel priority register 0) 17-18 CPR1 (TPU3 channel priority register 1) 17-18 CR (condition register) 3-16 CTR (count register) 3-19 D DAR (data address register) 3-22 DDRQA (port QA data direction register) 13-35 DDRQS (PORTQS data direction register) 14-12 DEC (decrementer register) 3-24, 6-28 DER (debug enable register) 21-55 DMBR (dual mapping base register) 10-31 DMOR (dual mapping option register) 10-32 DPTMCR (DPTRAM module configuration register) 18-4 DSCR (TPU3 development support control register) 17-12 DSISR (dae/source instruction service register) 3-22 DSSR (TPU3 development support status register) 17-14 E ECR (exception cause register) 21-54 EMCR (external master control register) 6-22 ESTAT (error and status register) 16-30
REGISTER DIAGRAM INDEX
MOTOROLA C-1

F FPRs - (floating-point registers) 3-12 FPSCR (floating-point status and control register) 3-13 G GPRs (general-purpose registers) 3-12 H HSQR0 (TPU3 host sequence register 0) 17-17 HSQR1 (TPU3 host sequence register 1) 17-17 HSSR0 (TPU3 host service request register 0) 17-17 HSSR1 (TPU3 host service request register 1) 17-18 I
ICTRL (i-bus support control register) 21-47 IFLAG (interrupt flag register) 16-33 IMASK (interrupt mask register) 16-32 IMMR (internal memory mapping register) 6-21 L L2U_GRA (L2U global region attribute register) 11-16 L2U_MCR (L2U module configuration register) 11-13 L2U_RAx (L2U region X attribute register) 11-15 L2U_RBAx (L2U region x base address register) 11-14 LCTRL1 (l-bus support control register 1) 21-49 LCTRL2 (l-bus support control register 2) 21-50 LJSRR (left justified, signed result register) 13-49 LJURR (left justified, unsigned result register) 13-50 LR (link register) 3-18 M MCPSMSCR (MCPSM status/control register) 15-13 MDASMAR (MDASM data A register) 15-21 MDASMBR (MDASM data B register) 15-22 MDASMSCR (MDASM status/control register) 15-23 MDASMSCRD (MDASM status/control register - duplicated) 15-22 MI_GRA (global region attribute register) 4-23 MIOS1ER0 (MIRSM0 interrupt enable register) 15-35 MIOS1ER1 (interrupt enable register) 15-37 MIOS1LVL0 (MIOS1 interrupt level register 0) 15-11 MIOS1LVL1 (MIOS1 interrupt level 1 register) 15-11 MIOS1MCR (MIOS1 module configuration register) 15-9 MIOS1RPR0 (MIRSM0 request pending register) 15-35 MIOS1RPR1 (MIRSM1 request pending register) 15-38 MIOS1SR0 (MIRSM0 interrupt status register) 15-34 MIOS1SR1 (MIRSM1 interrupt status register) 15-36 MIOS1TPCR (test and pin control register) 15-8 MIOS1VNR (MIOS1 module/version number register) 15-9 MISCNT (MISC counter) 18-6 MISRH (multiple input signature register high) 18-5 MISRL (multiple input signature register low) 18-6 MMCSMCNT (MMCSM up-counter register) 15-16 MMCSMML (MMCSM modulus latch register) 15-16 MMCSMSCR (MMCSM status/control register) 15-17 MMCSMSCRD (MMCSM status/control register - duplicated) 15-17 MPIOSMDDR (MPIOSM data direction register) 15-31 MPIOSMDR (MPIOSM data register) 15-31
MOTOROLA C-2

MPWMSMCNTR (MPWMSM counter register) 15-28 MPWMSMPERR (MPWMSM period register) 15-27 MPWMSMPULR (MPWMSM pulse width register) 15-27 MPWMSMSCR (MPWMSM status/control register) 15-28 MSR (machine state register) 3-20 MSTAT (memory controller status register) 10-28 O OR0 (OR3 - memory controller option registers 0 - 3) 10-30 P PDMCR (Pad module configuration register) 2-29 PISCR (periodic interrupt status and control register) 6-32 PITC (periodic interrupt timer count) 6-32 PITR (periodic interrupt timer register) 6-33 PLPRCR (PLL, low power, and reset control register) 8-33 PORTQA (port QA data register) 13-34 PORTQB (port QB data register) 13-34 PORTQS (port QS data register) 14-11 PQSPAR (PORTQS pin assignment register) 14-11 PRESDIV (prescaler divide register) 16-27 PVR (processor version register) 3-25 Q QACR0 (QADC64 control register 0) 13-35 QACR1 (QADC64 control register 1) 13-36 QACR2 (QADC64 control register 2) 13-39 QADC64INT (QADC64 interrupt register) 13-33 QADC64MCR (QADC64 module configuration register) 13-33 QASR0 (QADC64 status register 0) 13-41, 13-42 QDSCI_IL (QSM2 dual SCI interrupt level register) 14-8 QSCI1CR (QSCI1 control register) 14-59 QSCI1SR (QSCI1 status register) 14-61 QSMCMMCR (QSMCM module configuration register) 14-7 QSPI_IL (QSPI interrupt level register) 14-9 R RAMBAR (ram array base address register) 18-5 Regionattribute registers (0 - 3) 4-21 RJURR (right justified, unsigned result register) 13-49 RSR (reset status register) 7-5 RTC (real time clock) 6-31 RTCAL (real time clock alarm) 6-31 RTCSC (real time clock status and control register) 6-30 RXECTR (receive error counter) 16-33 RXGMSKHI (receive global mask register high) 16-29 S SCCR (system clock control register) 8-30 SCCxR0 (QSMCM SCI control register 0) 14-45 SCCxR1 (QSMCM SCI control register 1) 14-46 SCDR (QSMCM SCI data register) 14-49 SCxSR (QSMCM SCIx status register) 14-47 SGPIOCR (SGPIO control register) 6-35 SGPIODT1 (SGPIO data register 1) 6-34 SGPIODT2 (SGPIO data register 2) 6-34 SIEL (SIU interrupt edge level register) 6-25 SIMASK (SIU interrupt mask register) 6-24
MOTOROLA C-3

SIPEND (SIU interrupt pending register) 6-24 SIUMCR (SIU module configuration register) 6-18 SIVEC (SIU interrupt vector) 6-25 SPCR0 (QSPI control register 0) 14-16 SPCR1 (QSPI control register 1) 14-18 SPCR2 (QSPI control register 2) 14-19 SPCR3 (QSPI control register) 14-19 SPRG0-SPRG3 (general special-purpose registers 0-3) 3-25 SPSR (QSPI status register) 14-20 SRAMMCR (SRAM module configuration register) 20-3 SRR0 (machine status save/restore register 0) 3-24 SRR1 (machine status save/restore register 1) 3-25 SWSR (software service register) 6-27 SYPCR (system protection control register) 6-26 T
TB (time base) 3-19, 3-23, 6-29 TBREF0 (time base reference register 0) 6-29 TBREF1 (time base reference register 1) 6-29 TBSCR (time base control and status register) 6-30 TESR (transfer error status register) 6-27 TICR (TPU3 interrupt configuration register) 17-14 TIMER (free running timer register) 16-29 TPUMCR (TPU3 module configuration register) 17-10 TPUMCR2 (TPU3 module configuration register 2) 17-20 TPUMCR3 (TPU3 module configuration register 3) 17-21 U UIPEND (UIMB pending interrupt reqiuest register) 12-8 UMCR (UIMB module configuration register) 12-7 V VSRMSR (VDDSRM control register) 8-36 X XER (integer exception register) 3-17
MOTOROLA C-4
APPENDIX D TPU ROM FUNCTIONS

The following pages provide brief descriptions of the pre-programmed functions in the TPU3. For detailed descriptions, refer to the programming note for the individual function. The Motorola TPU Literature Pack, TPULITPAK/D, provides a list of available programming notes. D.1 Overview The TPU3 contains four Kbytes of microcode ROM. This appendix defines the functions that are in the standard ROM on the MPC555 / MPC556. The TPU3 can have up to eight Kbytes of memory and a maximum of four entry tables (see Figure D-1).
TPUROM
0 Bank 0 Code Entry Code Add - Entry Code Add - Entry Code Add - Entry Bank 3 Code Entry Code Add - Entry (Unimplemented) Code Add - Entry
DPTRAM*
0 Bank 0 1FF Bank 1 3FF Bank 2 5FF
1FF Bank 1 3 FF Bank 2 7FF
*The DPTRAM is located at 0x30 2000 until it is switched to emulation mode. In emulation mode, the DPTRAM is accessible by the TPUs only.
Figure D-1 TPU3 Memory Map The TPU3 can address up to eight Kbytes of memory at any one time. It has four Kbytes of internal ROM, located in Bank 0 and Bank 1, and six Kbytes of dual-ported SRAM (DPTRAM), located in Bank 0, Bank 1and Bank 2. As only one type of memory can be used at a time, the TPU3 must either use the internal ROM or the SRAM. Functions from both memory types cannot be used in conjunction.
MPC555 / MPC556 USERS MANUAL TPU ROM FUNCTIONS MOTOROLA D-1

A new feature of the TPU3 microcode ROM is the existence of two entry tables in the four Kbytes of internal ROM. Each entry table has a set of sixteen functions that define which of the two tables the TPU3 will be able to access. Only one table can be used at a time and functions from the two entry tables cannot be mixed. The default entry table is located in Bank 0. This table is identical to the standard microcode ROM in the TPU2, so any CPU code written for the TPU2 will work unchanged on the TPU3. The TPU2 and TPU3 ROMs are different than the original TPU ROM. The functions in the default entry table in Bank 0 are listed in Table D-1. Table D-1 Bank 0 Functions
Function Number 0xF Function Nickname PTA QOM TSM FQM UART NITC COMM HALLD MCPWM FQD PPWA OC PWM DIO SPWM SIOP Function Name Programmable Time Accumulator Queued Output Match Table Stepper Motor Frequency Measurement Universal Asynchronous Receiver/Transmitter New Input Capture/Input Transition Counter Multiphase Motor Commutation Hall Effect Decode Multi-Channel Pulse Width Modulation Fast Quadrature Decode Period/Pulse Width Accumulator Output Compare Pulse Width Modulation Discrete Input/Output Synchronized Pulse Width Modulation Serial Input/output Port
0xE 0xD 0xC 0xB 0xA 9 8 7 6 5 4 3 2 1 0
The functions in the entry table in bank one are listed in Table D-2.
TPU ROM FUNCTIONS
MOTOROLA D-2

Table D-2 Bank 1 Functions
Function Number 0xF 0xE 0xD 0xC 0xB 0xA 9 8 7 Function Nickname PTA QOM TSM FQM UART NITC COMM HALLD Reserved FQD ID OC PWM DIO RWTPIN SIOP Fast Quadrature Decode Identification Output Compare Pulse Width Modulation Discrete Input/Output Read/Write Timers and Pin Serial Input/output Port Function Name Programmable Time Accumulator Queued Output Match Table Stepper Motor Frequency Measurement Universal Asynchronous Receiver/Transmitter New Input Capture/Input Transition Counter Multiphase Motor Commutation Hall Effect Decode
6 5 4 3 2 1 0
The functions in the Bank 1 entry table are identical to the Bank 0 entry table functions with three exceptions. Function 1, SPWM, has been replaced by RWTPIN. This is a function that allows reads and writes to the TPU time bases and corresponding pin. Function 5, PPWA, is now an identification function in Table D-2. The microcode ROM revision number is provided by this function. Finally, Function 7, MCPWM, has been removed and left open for future use. The CPU selects which entry table to use by setting the ETBANK field in the TPUMCR2 register. This register is write once after reset. Although one entry table is specified at start-up, it is possible, in some cases, to use functions from both tables without resetting the microcontroller. A customer may, for example, wish to use the ID function from Bank 1 to verify the TPU microcode version but then use the MCPWM function from Bank 0. As a customer will typically only run the ID function during system configuration, and not again after that, the Bank 1 entry table can be changed to the Bank 0 entry table using the soft reset feature of the TPU3. The procedure should be: 1. Set ETBANK field in TPUMCR2 to 0b01 to select the entry table in Bank 1 2. Run the ID function 3. Stop the TPU3 by setting the STOP bit in the TPUMCR to one. 4. Reset the TPU3 by setting the SOFTRST bit in the TPUMCR2 register 5. Wait at least nine clocks 6. Clear the SOFTRST bit in the TPUMCR2 register The TPU3 stays in reset until the CPU clears the SOFTRST bit. After the SOFTRST bit has been cleared the TPU3 will be reset and the entry table in Bank 0 will be selected by default. To select the Bank 0 entry table, write 0b00 to the ETBANK field in

TPUMCR 2. It is good practice always to initialize any write once register to ensure an incorrect value is not accidentally written. The descriptions below document the functions listed in Table D-1 (Bank 0) and Table D-2 (Bank 1) of the TPU3 ROM module. D.2 Programmable Time Accumulator (PTA) PTA accumulates a 32-bit sum of the total high time, low time, or period of an input signal over a programmable number of periods or pulses. The period accumulation can start on a rising or falling edge. After the specified number of periods or pulses, the PTA generates an interrupt request. From one to 255 period measurements can be accumulated before the TPU interrupts the CPU, providing instantaneous or average frequency measurement capability. See Motorola TPU Progamming Note Programmable Time Accumulator TPU Function (PTA), (TPUPN06/D). Figure D-2 shows all of the host interface areas for the PTA function.
TPU ROM FUNCTIONS
MOTOROLA D-4

CONTROL BITS OPTIONS PTA Function Number (Assigned During Microcode Assembly) 00 High Time Accumulate 01 Low Time Accumulate 10 Period Accumulate, Rising 11 Period Accumulate, Falling 1 0 Host Service Request 00 No Host Service (Reset Condition) 01 Not Used 10 Not Used 11 Initialize 1 0 Channel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted 0x30YY20 0x30YY0A 0x30YY1C 0x30YY1E 0x30YY18 0x30YY1A
NAME 3 2 1 0 Channel Function Select 1 0 Host Sequence
ADDRESSES 0x30YY0C 0x30YY12
0x30YY14 0x30YY16
PARAMETER RAM 15 14 13 12 11 10 9 8 7 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE = Written By CPU = Written By TPU MAX_COUNT
CHANNEL_CONTROL PERIOD_COUNT LAST_TIME ACCUM HW LW
= Written by CPU and TPU = Unused Parameters
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B
Figure D-2 PTA Parameters
TPU ROM FUNCTIONS
MOTOROLA D-5

D.3 Queued Output Match TPU Function (QOM) QOM can generate single or multiple output match events from a table of offsets in parameter RAM. Loop modes allow complex pulse trains to be generated once, a specified number of times, or continuously. The function can be triggered by a link from another TPU channel. In addition, the reference time for the sequence of matches can be obtained from another channel. QOM can generate pulse-width modulated waveforms, including waveforms with high times of 0% or 100%. QOM also allows a TPU channel to be used as a discrete output pin. See Motorola TPU Progamming Note Queued Output Match TPU Function (QOM), (TPUPN01/D). Figure D-3 shows all of the host interface areas for the QOM function. The bit encodings shown in Table D-3 describe the corresponding fields in parameter RAM.
Table D-3 QOM Bit Encoding

A 0 1 Timebase Selection Use TCR1 as Timebase Use TCR2 as Timebase Edge Selection 0 1 B:C 00 01 10 11 Falling Edge at Match Rising Edge at Match Reference for First Match Immediate TCR Value Last Event Time Value Pointed to by REF_ADDR Last Event Time
TPU ROM FUNCTIONS
MOTOROLA D-6

CONTROL BITS OPTIONS COM Function Number (Assigned During Microcode Assembly) 00 Single-Shot Mode 01 Loop Mode 10 Continuous Mode 11 Continuous Mode 1 0 Host Service Request 00 No Host Service (Reset Condition) 01 Initialize, No Pin Change 10 Initialize, Pin Low 11 Initialize, Pin High 1 0 Channel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted 0x30YY20 0x30YY0A 0x30YY1C 0x30YY1E 0x30YY18 0x30YY1A
0x30YY14 0x30YY16
PARAMETER RAM 15 14 13 12 11 10 9 8 7 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE 0x30YY(W=1)0 0x30YY(W=1)2 : 0x30YY(W=1)14 *Not Available On All Channels. = Written By CPU = Written By TPU : OFFSET_14* REF_ADDR LOOP_CNT B
0 A C ; ; ; ; ; ; ; ; : ;
LAST_OFF_ADDR OFF_PTR
(LAST_MATCH_TM) OFFSET_1 OFFSET_2 OFFSET_3 OFFSET_4 OFFSET_5* OFFSET_6* OFFSET_7* OFFSET_8*
Figure D-3 QOM Parameters
TPU ROM FUNCTIONS
MOTOROLA D-7

D.4 Table Stepper Motor (TSM) The TSM function provides for acceleration and deceleration control of a stepper motor with a programmable number of step rates up to 58. TSM uses a table in parameter RAM, rather than an algorithm, to define the stepper motor acceleration profile, allowing full defininition of the profile. In addition, a slew rate parameter allows fine control of the terminal running speed of the motor independent of the acceleration table. The CPU need only write a desired position, and the TPU accelerates, slews, and decelerates the motor to the required position. Full and half step support is provided for twophase motors. In addition, a slew rate parameter allows fine control of the terminal running speed of the motor independent of the acceleration table. See Motorola TPU Progamming Note Table Stepper Motor TPU Function (TSM), (TPUPN04/D). Figure D-4 and Figure D-5 show all of the host interface areas for the TSM function when operating in master and slave mode, respectively.
TPU ROM FUNCTIONS
MOTOROLA D-8

CONTROL BITS OPTIONS TSM Function Number (Assigned During Microcode Assembly) x0 Rotate Pin_Sequence Once Between Steps x1 Split Mode Acceleration Table 0x Rotate Pin_Sequence Once Between Steps 1x Rotate Pin_Sequence Twice Between Steps 1 0 Host Service Reques 00 No Host Service (Reset Condition) 01 Initialize, Pin Low 10 Initialize, Pin High 11 Move Request (Master Only) 1 0 Channel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted 0x30YY20 0x30YY0A 0x30YY1C 0x30YY1E 0x30YY18 0x30YY1A
0x30YY14 0x30YY16
PARAMETER RAM 15 14 13 12 11 10 9 8 7 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE = Written By CPU = Written By TPU
TABLE_SIZE SLEW_PERIOD START_PERIOD
DESIRED_POSITION CURRENT_POSITION TABLE_INDEX S A
PIN_SEQUENCE
Figure D-4 TSM Parameters Master Mode
TPU ROM FUNCTIONS
MOTOROLA D-9

CONTROL BITS OPTIONS TSM Function Number (Assigned During Microcode Assembly) x0 Rotate Pin_Sequence Once Between Steps x1 Split Mode Acceleration Table 0x Rotate Pin_Sequence Once Between Steps 1x Rotate Pin_Sequence Twice Between Steps 1 0 Host Service Bits 00 No Host Service (Reset Condition) 01 Initialize, Pin Low 10 Initialize, Pin High 11 Move Request (Master Only) 1 0 Channel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted 0x30YY20 0x30YY0A 0x30YY1C 0x30YY1E 0x30YY18 0x30YY1A
NAME 3 2 1 0 Channel Function Select 1 0 Host Sequence Bits
0x30YY14 0x30YY16
PARAMETER RAM 15 14 13 12 11 10 9 8 7 0x30YY(W+1)0 0x30YY(W+1)2 0x30YY(W+1)4 0x30YY(W+1)6 0x30YY(W+1)8 0x30YY(W+1)A 0x30YY(W+1)C* : ACCEL_RATIO_2 ACCEL_RATIO_4 ACCEL_RATIO_6 ACCEL_RATIO_8 ACCEL_RATIO_10 ACCEL_RATIO_12 ACCEL_RATIO_14* :
ACCEL_RATIO_1 ACCEL_RATIO_3 ACCEL_RATIO_5 ACCEL_RATIO_7 ACCEL_RATIO_9 ACCEL_RATIO_11 ACCEL_RATIO_13* :
0x30YY(W+3)A* ACCEL_RATIO_36* ACCEL_RATIO_35* *Optional Additional Parameters not Available in all cases. Refer to Motorola Programming Note TPUPN04/D for details = Written By CPU = Written by CPU and TPU W = Channel Number = Written By TPU = Unused Parameters YY = 41 for TPU_A and 44 for TPU_B
Figure D-5 TSM Parameters Slave Mode
TPU ROM FUNCTIONS
MOTOROLA D-10

D.5 Frequency Measurement (FQM) FQM counts the number of input pulses to a TPU channel during a user-defined window period. The function has single shot and continuous modes. No pulses are lost between sample windows in continuous mode. The user selects whether to detect pulses on the rising or falling edge. This function is intended for high speed measurement; measurement of slow pulses with noise rejection can be made with PTA.See Motorola TPU Progamming Note Frequency Measurement TPU Function (FQM), (TPUPN03/D). Figure D-6 shows all of the host interface areas for the FQM function.

TPU ROM FUNCTIONS
MOTOROLA D-11

CONTROL BITS NAME OPTIONS cChannel Interrupt Enable 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled cChannel Function Select xxxx FQD Function Number (Assigned During Microcode Assembly) 00 Begin with Falling Edge, Single-Shot Mode
ADDRESSES 0x30YY0A
0 0x30YY0C 0x30YY12
0 cHost Sequence Bits 0x30YY14 0x30YY16
01 Begin with Falling Edge, Continuous Mode 10 Begin with Rising Edge, Single-Shot Mode 11 Begin with Rising Edge, Continuous Mode 1 0 cHost Service Bits 00 No Host Service (Reset Condition) 01 Not Used 10 Initialize 11 Not Used 1 0 cChannel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted 0x30YY20 0x30YY1C 0x30YY1E 0x30YY18 0x30YY1A
CHANEL_CONTROL WINDOW_SIZE PULSE_COUNT IN_WINDOW_ACCUMULATOR
W = Primary Channel Number YY = 41 for TPU_A and 44 for TPU_B
Figure D-6 FQM Parameters
TPU ROM FUNCTIONS
MOTOROLA D-12

D.6 Universal Asynchronous Receiver/Transmitter (UART) The UART function uses one or two TPU channels to provide asynchronous communications. Data word length is programmable from one to 14 bits. The function supports detection or generation of even, odd, and no parity. Baud rate is freely programmable and can be higher than 100 Kbaud. Eight bi-directional UART channels running in excess of 9600 baud could be implemented on the TPU. See Motorola TPU Progamming Note Asynchronous Serial Interface TPU Function (UART), (TPUPN07/D). Figure D-7 and Figure D-8 show all of the host interface areas for the UART function in transmitting and receiving modes, respectively.

TPU ROM FUNCTIONS
MOTOROLA D-13

CONTROL BITS OPTIONS UART Function Number (Assigned During Microcode Assembly) 00 No Parity 01 No Parity 10 Even Parity 11 Odd Parity 1 0 Host Service Bits 00 Not Used 01 Not Used 10 Transmit 11 Receive 1 0 Channel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted 0x30YY20 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 0x30YY0A 0x30YY1C 0x30YY1E 0x30YY18 0x30YY1A
0x30YY14 0x30YY16
PARAMETER RAM 15 14 13 12 11 10 9 8 7 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWA = Written By CPU = Written By TPU TDRE
PARITY_TEMP MATCH_RATE TRANSMIT_DATA_REG DATA_SIZE ACTUAL_BIT_COUNT SHIFT_REGISTER
Figure D-7 UART Transmitter Parameters
TPU ROM FUNCTIONS
MOTOROLA D-14

CONTROL BITS OPTIONS UART Function Number (Assigned During Microcode Assembly) 00 No Parity 01 No Parity 10 Even Parity 11 Odd Parity 1 0 Host Service Bits 00 Not Used 01 Not Used 10 Transmit 11 Receive 1 0 Channel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted 0x30YY20 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 0x30YY0A 0x30YY1C 0x30YY1E 0x30YY18 0x30YY1A
0x30YY14 0x30YY16
PARAMETER RAM 15 14 13 12 11 10 9 8 7 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWA = Written By CPU = Written By TPU PE RE
PARITY_TEMP MATCH_RATE TRANSMIT_DATA_REG DATA_SIZE ACTUAL_BIT_COUNT SHIFT_REGISTER
Figure D-8 UART Receiver Parameters
TPU ROM FUNCTIONS
MOTOROLA D-15

D.7 New Input Capture/Transition Counter (NITC) Any channel of the TPU can capture the value of a specified TCR or any specified location in parameter RAM upon the occurrence of each transition or specified number of transitions, and then generate an interrupt request to notify the bus master. The times of the most recent two transitions are maintained in parameter RAM. A channel can perform input captures continually, or a channel can detect a single transition or specified number of transitions, ceasing channel activity until reinitialization. After each transition or specified number of transitions, the channel can generate a link to other channels. See Motorola TPU Progamming Note New Input Capture/Input Transition Counter TPU Function (NITC), (TPUPN08/D). Figure D-9 shows all of the host interface areas for the NITC function.

TPU ROM FUNCTIONS
MOTOROLA D-16

CONTROL BITS OPTIONS NITC Function Number (Assigned During Microcode Assembly) 00 Single-Shot Mode, No Links 01 Continuous Mode, No Links 10 Single-Shot Mode, Links 11 Continuous Mode, Links 1 0 Host Service Request 00 No Host Service (Reset Condition) 01 Initialize TCR Mode 10 Initialize Parameter Mode 11 Not Used 1 0 Channel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted 0x30YY20 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 0x30YY0A 0x30YY1C 0x30YY1E 0x30YY18 0x30YY1A
0x30YY14 0x30YY16
START_LINK_ CHANNEL LINK_CHAN NEL_COUNT
CHANNEL_CONTROL PARAM_ADDR 0
MAX_COUNT TRANS_COUNT FINAL_TRANS_TIME LAST_TRANS_TIME
Figure D-9 NITC Parameters
TPU ROM FUNCTIONS
MOTOROLA D-17

D.8 Multiphase Motor Commutation (COMM) The COMM function generates the phase commutation signals for a variety of brushless motors, including three-phase brushless direct current. It derives the commutation state directly from the position decoded in FQD, thus eliminating the need for hall effect sensors. The state sequence is implemented as a user-configurable state machine, thus providing a flexible approach with other general applications. A CPU offset parameter is provided to allow all the switching angles to be advanced or retarded on the fly by the CPU. This feature is useful for torque maintenance at high speeds. See Motorola TPU Progamming Note Multiphase Motor Commutation TPU Function (COMM), (TPUPN09/D).
Figure D-10 and Figure D-11 show all of the host interface areas for the COMM function.
TPU ROM FUNCTIONS
MOTOROLA D-18

CONTROL BITS OPTIONS
NAME 0
ADDRESSES 0x30YY0A
cChannel Interrupt Enable 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 3 2 1 0 cChannel Function Select xxxx FQD Function Number (Assigned During Microcode Assembly) 00 Sensorless Match Update Mode 01 Sensorless Match Update Mode 10 Sensorless Link Update Mode 11 Sensorled Mode 1 0 cHost Service Request 00 No Host Service (Reset Condition) 01 Not Used 10 Initialize or Force State 11 Initialize or Force Immediate State Test 1 0 cChannel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted
0x30YY0C 0x30YY12
0 cHost Sequence 0x30YY14 0x30YY16
0x30YY18 0x30YY1A
0x30YY1C 0x30YY1E
0x30YY20
0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE
PARAMETER RAM 15 14 13 12 11 10 9 8 7 START_LINK_ CHANNEL

NO_OF_STATES
COUNTER_ADDR STATE_NO
OFFSET UPDATE_PERIO UPPER LOWER
= Written By CPU = Written By TPU
Figure D-10 COMM Parameters (Part 1 of 2)
TPU ROM FUNCTIONS
MOTOROLA D-19

CONTROL BITS 15 14 13 12 11 10 9 8 7 0x30YY(W + 1)0 0x30YY(W + 1)2 0x30YY(W + 1)4 0x30YY(W + 1)6 0x30YY(W + 1)8 0x30YY(W + 1)A 0x30YY(W + 1)C 0x30YY(W + 1)E 0x30YY(W + 2)0 0x30YY(W + 2)2 LENGTH LENGTH LENGTH LENGTH LENGTH LENGTH LENGTH LENGTH LENGTH LENGTH STATE STATE STATE STATE STATE STATE STATE STATE STATE STATE 0 1 2 3 4 5 6* 7* 8* 9*
PIN_CONFIG PIN_CONFIG PIN_CONFIG PIN_CONFIG PIN_CONFIG PIN_CONFIG PIN_CONFIG PIN_CONFIG PIN_CONFIG PIN_CONFIG

0x30YY(W + 3)A *Not Available on all Channels = Written By CPU = Written By TPU LENGTH

STATE 21* PIN_CONFIG W = Master Channel Number YY = 41 for TPU_A and 44 for TPU_B
Figure D-11 COMM Parameters (Part 2 of 2) D.9 Hall Effect Decode (HALLD) The HALLD function decodes the sensor signals from a brushless motor, along with a direction input from the CPU, into a state number. The function supports two- or threesensor decoding. The decoded state number is written into a COMM channel, which outputs the required commutation drive signals. In addition to brushless motor applications, the function can have more general applications, such as decoding option switches. See Motorola TPU Progamming Note Hall Effect Decode TPU Function (HALLD), (TPUPN10/D). Figure D-12 shows all of the host interface areas for the HALLD function.
TPU ROM FUNCTIONS
MOTOROLA D-20

NAME 0
ADDRESSES 0x30YY0A
cChannel Interrupt Enable 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 3 2 1 0 cChannel Function Select xxxx FQD Function Number (Assigned During Microcode Assembly) 00 Channel A 01 Channel B 10 Channel B 11 Channel C (3-Channel Mode Only) 1 0 cHost Service Request 00 No Host Service (Reset Condition) 01 Not Used 10 Initialize, 2-Channel Mode 11 Initialize, 3-Channel Mode 1 0 cChannel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Status x Not Used
0x30YY0C 0x30YY12
0x30YY18 0x30YY1A
0x30YY1C 0x30YY1E
0x30YY20
PARAMETER RAM 15 14 13 12 11 10 9 8 7 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE = Written By CPU PINSTATE
DIRECTION (1) STATE_NO_ADDR (2)
= Written by CPU and TPU
W = Channel Number
NOTES:
YY = 41 for TPU_A and 44 for TPU_B = Written By TPU = Unused Parameters 1. Channel A Only. 2. One Channel Only (Channel B in 2-Channel Mode, Channel C in 3-Channel Mode.
Figure D-12 HALLD Parameters
TPU ROM FUNCTIONS
MOTOROLA D-21

D.10 Multichannel Pulse-Width Modulation (MCPWM) MCPWM generates pulse-width modulated outputs with full 0% to 100% duty cycle range independent of other TPU activity. This capability requires two TPU channels plus an external gate for one PWM channel. (A simple one-channel PWM capability is supported by the QOM function.) Multiple PWMs generated by MCPWM have two types of high time alignment: edge aligned and center aligned. Edge-aligned mode uses n + 1 TPU channels for n PWMs; center-aligned mode uses 2n + 1 channels. Center-aligned mode allows a user-defined dead time to be specified so that two PWMs can be used to drive an H-bridge without destructive current spikes. This feature is important for motor control applications. See Motorola TPU Progamming Note Multichannel PWM TPU Function (MCPWM), (TPUPN05/D).
Figure D-13 through Figure D-18 show the host interface areas for the MCPWM function in each mode.
TPU ROM FUNCTIONS
MOTOROLA D-22

NAME 0
ADDRESSES 0x30YY0A
cChannel Interrupt Enable 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 3 2 1 0 cChannel Function Select xxxx FQD Function Number (Assigned During Microcode Assembly) 00 Edge-Aligned Mode 01 Slave A Type Center-Aligned Mode 10 Slave B Type Center-Aligned Mode 11 Slave C Type Center-Aligned Mode 1 0 cHost Service Request 00 No Host Service (Reset Condition) 01 Initialize as Slave (Inverted) 10 Initialize, as Slave (Normal) 11 Initialize as Master 1 0 cChannel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted
0x30YY0C 0x30YY12
0x30YY18 0x30YY1A
0x30YY1C 0x30YY1E
0x30YY20
IRQ_RATE
PERIOD PERIOD_COUNT LAST_RISE_TIME LAST_FALL_TIME RISE_TIME_PTR FALL_TIME_PTR
Figure D-13 MCPWM Parameters Master Mode
TPU ROM FUNCTIONS
MOTOROLA D-23

CONTROL BITS OPTIONS MCPWM Function Number (Assigned During Microcode Assembly) 00 Edge-Aligned Mode 01 Slave A Type Center Aligned Mode 10 Slave B Type Center Aligned Mode 11 Slave C Type Center Aligned Mode 1 0 cHost Service Request 00 No Host Service (Reset Condition) 01 Initialize As Slave (Inverted) 10 Initialize As Slave (Normal) 11 Initialize As Master 1 0 cChannel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted 0x30YY20 0x30YY1C 0x30YY1E 0x30YY18 0x30YY1E 0x30YY14 0x30YY16
NAME 3 2 1 0 cChannel Function Select 1 0 cHost Sequence
ADDRESSES 0x30YY0A
0x30YY0C 0x30YY12
PARAMETER RAM 15 14 13 12 11 10 9 8 7 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE = Written By CPU = Written By TPU PERIOD HIGH_TIME
HIGH_TIME_PTR RISE_TIME_PTR FALL_TIME_PTR
Figure D-14 MCPWM Parameters Slave Edge-Aligned Mode
TPU ROM FUNCTIONS
MOTOROLA D-24

CONTROL BITS OPTIONS MCPWM Function Number (Assigned During Microcode Assembly) 00 Edge-Aligned Mode 01 Slave A Type Center Aligned Mode 10 Slave B Type Center Aligned Mode 11 Slave C Type Center Aligned Mode 1 0 cHost Service Request 00 No Host Service (Reset Condition) 01 Initialize As Slave (Inverted) 10 Initialize As Slave (Normal) 11 Initialize As Master 1 0 cChannel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted 0x30YY20 0x30YY1C 0x30YY1E 0x30YY18 0x30YY1A 0x30YY14 0x30YY16
ADDRESSES 0x30YY0A
0x30YY0C 0x30YY12
PARAMETER RAM 15 14 13 12 11 10 9 8 7 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE = Written By CPU = Written By TPU DEAD_TIME PERIOD
NXT_B_RISE_TIME NXT_B_FALL_TIME
Figure D-15 MCPWM Parameters Slave Ch A Non-Inverted Center-Aligned Mode
TPU ROM FUNCTIONS
MOTOROLA D-25

CONTROL BITS OPTIONS MCPWM Function Number (Assigned During Microcode Assembly) 00 Edge-Aligned Mode 01 Slave A Type Center Aligned Mode 10 Slave B Type Center Aligned Mode 11 Slave C Type Center Aligned Mode 1 0 cHost Service Request 00 No Host Service (Reset Condition) 01 Initialize As Slave (Inverted) 10 Initialize As Slave (Normal) 11 Initialize As Master 1 0 cChannel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted 0x30YY20 0x30YY0A 0x30YY1C 0x30YY1E 0x30YY18 0x30YY1A
0x30YY14 0x30YY16
PARAMETER RAM 15 14 13 12 11 10 9 8 7 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE = Written By CPU = Written By TPU HIGH_TIME
CURRENT_HIGH_TIME TEMP_STORAGE
B_FALL_TIME_PTR B_RISE_TIME_PTR
Figure D-16 MCPWM Parameters Slave Ch B Non-Inverted Center-Aligned Mode
TPU ROM FUNCTIONS
MOTOROLA D-26

CONTROL BITS OPTIONS MCPWM Function Number (Assigned During Microcode Assembly) 00 Edge-Aligned Mode 01 Slave A Type Center Aligned Mode 10 Slave B Type Center Aligned Mode 11 Slave C Type Center Aligned Mode 1 0 cHost Service Request 00 No Host Service (Reset Condition) 01 Initialize As Slave (Inverted) 10 Initialize As Slave (Normal) 11 Initialize As Master 1 0 cChannel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted 0x30YY20 0x30YY1C 0x30YY1E 0x30YY18 0x30YY1A 0x30YY14 0x30YY16
ADDRESSES 0x30YY0A
0x30YY0C 0x30YY12
PARAMETER RAM 15 14 13 12 11 10 9 8 7 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE = Written By CPU = Written By TPU DEAD_TIME PERIOD
NXT_B_RISE_TIME NXT_B_FALL_TIME
Figure D-17 MCPWM Parameters Slave Ch A Inverted Center-Aligned Mode
TPU ROM FUNCTIONS
MOTOROLA D-27

CONTROL BITS OPTIONS MCPWM Function Number (Assigned During Microcode Assembly) 00 Edge-Aligned Mode 01 Slave A Type Center Aligned Mode 10 Slave B Type Center Aligned Mode 11 Slave C Type Center Aligned Mode 1 0 cHost Service Request 00 No Host Service (Reset Condition) 01 Initialize As Slave (Inverted) 10 Initialize As Slave (Normal) 11 Initialize As Master 1 0 cChannel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 0 cChannel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted 0x30YY20 0x30YY0A 0x30YY1C 0x30YY1E 0x30YY18 0x30YY1A
0x30YY14 0x30YY16
PARAMETER RAM 15 14 13 12 11 10 9 8 7 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE = Written By CPU = Written By TPU HIGH_TIME
CURRENT_HIGH_TIME TEMP_STORAGE
B_FALL_TIME_PTR B_RISE_TIME_PTR
Figure D-18 MCPWM Parameters Slave Ch B Non-Inverted Center-Aligned Mode
TPU ROM FUNCTIONS
MOTOROLA D-28

D.11 Fast Quadrature Decode TPU Function (FQD) FQD is a position feedback function for motor control. It decodes the two signals from a slotted encoder to provide the CPU with a 16-bit free-running position counter. FQD incorporates a speed switch which disables one of the channels at high speed, allowing faster signals to be decoded. A time stamp is provided on every counter update to allow position interpolation and better velocity determination at low speed or when low resolution encoders are used. The third index channel provided by some encoders is handled by the ITC function. See Motorola TPU Progamming Note Fast Quadrature Decode TPU Function (FQD), (TPUPN02/D). Figure D-19 and Figure D-20 show the host interface areas for the FQD function for primary and secondary channels, respectively.

TPU ROM FUNCTIONS
MOTOROLA D-29

CONTROL BITS NAME 3 2 1 0 cChannel Function Select xxxx FQD Function Number (Assigned During Microcode Assembly) 00 Primary Channel (Normal Mode) 01 Secondary Channel (Normal Mode) 10 Primary Channel (Fast Mode) 11 Secondary Channel (Fast Mode) 1 0 cHost Service Bits 00 No Host Service (Reset Condition) 01 Not Used 10 Read TCR1 11 Initialize 1 0 cChannel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable x Not Used 0 cChannel Interrupt Status xx Not Used 0x30YY20 0x30YY0A 0x30YY1C 0x30YY1E 0x30YY18 0x30YY1A 0x30YY0C 0x30YY12 OPTIONS ADDRESSES
EDGE_TIME
POSITION_COUNT
TCR1_VALUE CHAN_PINSTATE CORR_PINSTATE_ADDR EDGE_TIME_LSB_ADDR
Figure D-19 FQD Parameters Primary Channel
TPU ROM FUNCTIONS
MOTOROLA D-30

NAME 3 2 1 0 cChannel Function Select
ADDRESSES
xxxx FQD Function Number (Assigned During Microcode Assembly) 00 Primary Channel (Normal Mode) 01 Secondary Channel (Normal Mode) 10 Primary Channel (Fast Mode) 11 Secondary Channel (Fast Mode)
0x30YY0C 0x30YY12
0 cHost Service Bits 00 No Host Service (Reset Condition) 01 Not Used 10 Read TCR1 11 Initialize 0x30YY18 0x30YY1A
0 cChannel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 cChannel Interrupt Enable x Not Used 0 cChannel Interrupt Status xx Not Used 0x30YY20 0x30YY0A 0x30YY1C 0x30YY1E
TCR1_VALUE CHAN_PINSTATE CORR_PINSTATE_ADDR EDGE_TIME_LSB_ADDR
Figure D-20 FQD Parameters Secondary Channel
TPU ROM FUNCTIONS
MOTOROLA D-31

D.12 Period/Pulse-Width Accumulator (PPWA) The period/pulse-width accumulator (PPWA) algorithm accumulates a 16-bit or 24-bit sum of either the period or the pulse width of an input signal over a programmable number of periods or pulses (from one to 255). After an accumulation period, the algorithm can generate a link to a sequential block of up to eight channels. The user specifies a starting channel of the block and number of channels within the block. Generation of links depends on the mode of operation. Any channel can be used to measure an accumulated number of periods of an input signal. A maximum of 24 bits can be used for the accumulation parameter. From one to 255 period measurements can be made and summed with the previous measurement(s) before the TPU interrupts the CPU, allowing instantaneous or average frequency measurement, and the latest complete accumulation (over the programmed number of periods). The pulse width (high-time portion) of an input signal can be measured (up to 24 bits) and added to a previous measurement over a programmable number of periods (one to 255). This provides an instantaneous or average pulse-width measurement capability, allowing the latest complete accumulation (over the specified number of periods) to always be available in a parameter. By using the output compare function in conjunction with PPWA, an output signal can be generated that is proportional to a specified input signal. The ratio of the input and output frequency is programmable. One or more output signals with different frequencies, yet proportional and synchronized to a single input signal, can be generated on separate channels. See Motorola TPU Progamming Note Period/Pulse-Width Accumulator TPU Function (PPWA), (TPUPN11/D). Figure D-21 shows the host interface areas and parameter RAM for the PPWA function.
TPU ROM FUNCTIONS
MOTOROLA D-32

CONTROL BITS OPTIONS PPWA Function Number (Assigned During Microcode Assembly) 00 Channel Disabled 01 Low Priority 10 Medium Priority 11 High Priority 1 0 cHost Sequence Bits 00 Accumulate 24-Bit Periods, No Links 01 Accumulate 16-Bit Periods, Links 10 Accumulate 24-Bit Pulse Widths, No Links 11 Accumulate 16-Bit Pulse Widths, Links 00 Not Used 01 Not Used 10 Initialize 11 Not Used 0 cInterrupt Enable 0 cInterrupt Status PARAMETER RAM 15 14 13 12 11 10 9 8 7 START_LINK_ LINK_CHANNEL CHANNEL _COUNT
MAX_COUNT LAST_ACCUM
NAME 3 2 1 0 cChannel Function Select 1 0 cChannel Priority
0x30YY1C 0x30YY1E
0x30YY14 0x30YY16
0 cHost Service Bits 0x30YY18 0x30YY1A
0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted
0x30YY0A
0x30YY20 6 5 4 3 2 1 0
CHANNEL_CONTROL PERIOD_COUNT
ACCUM ACCUM_RATE PPWA_LW PPWA_UB
NOTES: 1. The TPU does not check the value of LINK_CHANNEL_COUNT. If this parameter is NOT >0 and 8, results are unpredictible. 2. MAX_COUNT may be written at any time by the host CPU, but if the value written is PERIOD_COUNT, a period or pulse-width accumulation is terminated. If this happens, the number of periods over which the accumulation is done will not correspond to MAX_COUNT.
Figure D-21 PPWA Parameters
TPU ROM FUNCTIONS
MOTOROLA D-33

D.13 Output Compare (OC) The output compare (OC) function generates a rising edge, falling edge, or a toggle of the previous edge in one of three ways: 1. Immediately upon CPU initiation, thereby generating a pulse with a length equal to a programmable delay time 2. At a programmable delay time from a user-specified time 3. Continuously. Upon receiving a link from a channel, OC references, without CPU interaction, a specifiable period and calculates an offset: Offset = Period Ratio
where RATIO is a parameter supplied. This algorithm generates a 50% duty-cycle continuous square wave with each high/ low time equal to the calculated OFFSET. Due to offset calculation, there is an initial link time before continuous pulse generation begins. See Motorola TPU Progamming Note Output Compare TPU Function (OC), (TPUPN12/D). Figure D-22 shows the host interface areas and parameter RAM for the OC function.
TPU ROM FUNCTIONS
MOTOROLA D-34

CONTROL BITS OPTIONS OC Function Number (Assigned During Microcode Assembly) 00 Channel Disabled 01 Low Priority 10 Medium Priority 11 High Priority 1 0 cHost Sequence Bits 1 0 cHost Service Bits 00 No Host Service Request 01 Host-Initiated Pulse 10 Not Used 11 Initialize, Continuous Pulses 0 cInterrupt Enable 0 cInterrupt Status PARAMETER RAM 15 14 13 12 11 10 9 8 7 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE c= Written By CPU c= Written By TPU
RATIO OFFSET
0x30YY1C 0x30YY1E
0x Matches and Pulses Scheduled x1 Only Read TCR1, TCR2
0x30YY14 0x30YY16
0x30YY18 0x30YY1A
0 Interrupt Not Asserted 1 Interrupt Asserted
0x30YY0A
0x30YY20 6 5 4 3 2 1 0
CHANNEL_CONTROL REF_ADDR1 0 REF_TIME ACTUAL_MATCH_TIME TCR1 TCR2 c= Written by CPU and TPU c= Unused Parameters W = Channel Number YY = 41 for TPU_A and 44 for TPU_B REF_ADDR3 0 0
REF_ADDR2
Figure D-22 OC Parameters
TPU ROM FUNCTIONS
MOTOROLA D-35

D.14 Pulse-Width Modulation (PWM) The TPU can generate a pulse-width modulation (PWM) waveform with any duty cycle from zero to 100% (within the resolution and latency capability of the TPU). To define the PWM, the CPU provides one parameter that indicates the period and another parameter that indicates the high time. Updates to one or both of these parameters can direct the waveform change to take effect immediately, or coherently beginning at the next low-to-high transition of the pin. See Motorola TPU Progamming Note Pulse-Width Modulation TPU Function (PWM), (TPUPN17/D). Figure D-23 shows the host interface areas and parameter RAM for the PWM function.

TPU ROM FUNCTIONS
MOTOROLA D-36

CONTROL BITS OPTIONS PWM Function Number (Assigned During Microcode Assembly) 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 1 0 cHost Sequence Bits xx Not Used 0x30YY14 0x30YY16
0x30YY1C 0x30YY1E
0 cHost Service Bits 00 Not Used 01 Immediate Update of PWM 10 Initialize 11 Not Used 0 cInterrupt Enable 0 cInterrupt Status PARAMETER RAM 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0x30YY20 0 0 Interrupt Not Asserted 1 Interrupt Asserted 0x30YY0A 0x30YY18 0x30YY1A
0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE c= Written By CPU c= Written By TPU
OLDRIS
CHANNEL_CONTROL
PWMHI (1, 3)
PWMPER (2, 3) PWMRIS
c= Written by CPU and TPU c= Unused Parameters
W = Channel Number YY = 41 for TPU_A and 44 for TPU_B.
Figure D-23 PWM Parameters
TPU ROM FUNCTIONS
MOTOROLA D-37

D.15 Discrete Input/Output (DIO) The DIO function allows a TPU channel to be used as a digital I/O pin. When a pin is used as a discrete input, a parameter indicates the current input level and the previous 15 levels of a pin. Bit 15, the most significant bit of the parameter, indicates the most recent state. Bit 14 indicates the next most recent state, and so on. The programmer can choose one of the three following conditions to update the parameter: 1. when a transition occurs 2. when the CPU makes a request, or 3. when a rate specified in another parameter is matched When a pin is used as a discrete output, it is set high or low only upon request by the CPU. See Motorola TPU Progamming Note Discrete Input/Output TPU Function (DIO), (TPUPN18/D). Figure D-24 shows the host interface areas for the DIO function.
TPU ROM FUNCTIONS
MOTOROLA D-38

CONTROL BITS OPTIONS DIO Function Number (Assigned During Microcode Assembly) 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 1 0 cHost Sequence Bits 00 Update on Transition 01 Update at Match Rate 10 Update on HSR 11 11 Not Used 1 0 cHost Service Bits 00 Not Used 01 Drive Pin High 10 Drive Pin Low 11 Initialize 0 cInterrupt Enable 0 cInterrupt Status 0x30YY20 0 Interrupt Not Asserted 1 Interrupt Asserted 0x30YY0A 0x30YY18 0x30YY1A 0x30YY14 0x30YY16
0x30YY1C 0x30YY1E
PIN_LEVEL
CHANNEL_CONTROL
MATCH_RATE
Figure D-24 DIO Parameters
TPU ROM FUNCTIONS
MOTOROLA D-39

D.16 Synchronized Pulse-Width Modulation (SPWM) The SPWM function generates a pulse-width modulated waveform (PWM). The CPU can change the period or high time of the waveform at any time. Three different operating modes allow the function to maintain complex timing relationships between channels without CPU intervention. The SPWM output waveform duty cycle excludes 0% and 100%. If a PWM does not need to maintain a time relationship to another PWM, the PWM function should be used instead. See Motorola TPU Progamming Note Synchronized Pulse-Width Modulation TPU Function (SPWM), (TPUPN19/D). Figure D-25 and Figure D-26 show all of the host interface areas for the SPWM function.

TPU ROM FUNCTIONS
MOTOROLA D-40

CONTROL BITS OPTIONS SPWM Function Number (Assigned During Microcode Assembly) 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 1 0 cHost Sequence Bits 00 Mode 0 01 Mode 1 10 Mode 2 11 Not Used 1 0 cHost Service Bits 00 No Host Service Request 01 Not Used 10 Initialize 11 Immediate Update (Mode 1) 0 cInterrupt Enable 0 cInterrupt Status 0x30YY20 0 Interrupt Not Asserted 1 Interrupt Asserted 0x30YY0A 0x30YY18 0x30YY1A 0x30YY14 0x30YY16
0x30YY1C 0x30YY1E
PARAMETER RAM 15 14 13 12 11 10 9 8 7 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE = Written By CPU = Written By TPU DELAY LASTRISE
NEXTRISE HIGH_TIME
CHANNEL_CONTROL
PERIOD REF_ADDR1
Figure D-25 SPWM Parameters, Part 1 of 2
TPU ROM FUNCTIONS
MOTOROLA D-41
PARAMETER RAM (MODE 1) 15 14 13 12 11 10 9 8 7 6 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE REF_ADDR1 REF_VALUE LASTRISE
NEXTRISE HIGH_TIME
CHANNEL_CONTROL
DELAY REF_ADDR2
PARAMETER RAM (MODE 2) 15 14 13 12 11 10 9 8 7 6 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE = Written By CPU = Written By TPU START_LINK_ CHANNEL LASTRISE
NEXTRISE HIGH_TIME
CHANNEL_CONTROL
PERIOD LINK_CHANNEL _COUNT DELAY
REF_ADDR1
Figure D-26 SPWM Parameters, Part 2 of 2
TPU ROM FUNCTIONS
MOTOROLA D-42

D.17 Read / Write Timers and Pin TPU Function (RWTPIN) The RWTPIN TPU function enables the CPU to read both the TCR1 and TCR2 timer counters via locations in PRAM and selectively load TCR1 or TCR2 with a CPU supplied value contained in PRAM. The function also allows control of the pin state and direction of the RWTPIN channel. A pin state parameter is maintained in PRAM and is updated upon every service request. It can contain a value of the current pinstate whether the pin is programmed as an input or output. The function also receives links, and upon receipt will read the two TCRs into PRAM, updating the pinstate parameter. A maskable interrupt request to the CPU is generated.
The CPU can control the channel pin, the channel pin and the TCRs, or just the TCRs. To control the pin only, the read TCR option is used and the values returned ignored. Controlling the TCRs without effect on the pin allows this function to be run on a TPU channel whose pin is being controlled by a different function running on another channel (e.g., a slave stepper motor channel). See Motorola TPU Progamming Note Using The TPU Function Library And TPU Emulation Mode, (TPUPN00/D). Figure D-27 shows all of the host interface areas for the PTA function.
TPU ROM FUNCTIONS
MOTOROLA D-43

CONTROL BITS OPTIONS Read/Write Timers and Pin Function Number (Assigned During Microcode Assembly) XX Not Used
NAME 3 2 1 0 Channel Function Select
0 Host Sequence 0x30YY14 0x30YY16
0 Host Service Request 00 No Action 01 Read TCRs and read/write pin 0x30YY18 0x30YY1A
10 Write TCR1, read TCRs and read/write pin 11 Write TCR2, read TCRs and read/write pin
0 Channel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted 0x30YY20 0x30YY0A 0x30YY1C 0x30YY1E
CHANNEL_CONTROL CHANNEL_PIN_STATE TCR1_VALUE TCR2_VALUE
W = Channel Number YY = 41 For TPU_A 44 For TPU_B and 5C For TPU_C
Figure D-27 RWTPIN Parameters
TPU ROM FUNCTIONS
MOTOROLA D-44

D.18 ID TPU Function (ID) This is a simple function that returns the version of the TPU ROM on the current device. Figure D-28 shows all of the host interface areas for the ID function.

TPU ROM FUNCTIONS
MOTOROLA D-45

CONTROL BITS OPTIONS Identification Function Number (Assigned During Microcode Assembly) XX Not Used
NAME 3 2 1 0 Channel Function Select 1 0 Host Sequence 1 0 Host Service Request
0x30YY14 0x30YY16
00 No Action 01 Read Read TPU ROM version 10 Not Used 11 Not Used
0x30YY18 0x30YY1A
0 Channel Priority 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 0 Channel Interrupt Enable 0 Channel Interrupts Disabled 1 Channel Interrupts Enabled 0 Channel Interrupt Status 0 Channel Interrupt Not Asserted 1 Channel Interrupt Asserted 0x30YY20 0x30YY0A 0x30YY1C 0x30YY1E
PARAMETER RAM 15 14 13 12 11 10 9 8 7 TPU3_ID
5 4 3 2 1 ROM_REVISION
W = Channel Number YY = 41 For TPU_A 44 For TPU_B and 5C For TPU_C
Figure D-28 ID Parameters
TPU ROM FUNCTIONS
MOTOROLA D-46

D.19 Serial Input/Output Port (SIOP) The serial input/output port (SIOP) TPU function uses two or three TPU channels to form a uni- or bi-directional synchronous serial port that can be used to communicate with a wide variety of devices. Features such as baud rate and transfer size are user programmable. The function can also produce a clock-only, when it uses just one channel. The SIOP TPU function has been designed to closely resemble the SIOP hardware port found on some Motorola MCUs and can be used to add serial capabilities to a device without a serial port, or extend the capabilities of one with a hardware synchronous port. SIOP operates in master mode (i.e., the TPU always generates the clock) and the following features are programmable: 1. Choice of clock-only (one channel), clock + transmit (two channels), clock + receive (two channels) or clock + transmit + receive (three channels) operating modes 2. Baud rate period is freely programmable over a 15-bit range of TCR1 counts 3. Selection of msb or lsb first shift direction 4. Variable transfer size from one to 16 bits 5. Clock polarity is programmable When a transfer of data is complete the SIOP function notifies the host CPU by issuing an interrupt request. The arrangement of the multiple SIOP channels is fixed: the data out channel is the channel above the clock channel and the data in channel is the channel below the clock channel. In clock-only or uni-directional mode, the unused TPU channels are free to run other TPU functions. Two possible SIOP configurations are show in Figure D-29.
Da ta Out-Chan x+1 Cloc k Out-Chan x Da ta In-Cha n x-1
8-bit bi-directional transfer, MSB first with data valid on clock rising edge
Da ta Out-Cha n x+1 Cloc k Out-Chan x
10-bit output only transfer, LSB first with data valid on clock falling edge
Figure D-29 Two Possible SIOP Configurations
TPU ROM FUNCTIONS
MOTOROLA D-47

D.19.1 Parameters Figure D-30 shows the host interface areas and parameter RAM for the SIOP function. The following sections describe these parameters. Note that only the clock channel requires any programming the data in and out channels are entirely under TPU microcode control.

TPU ROM FUNCTIONS
MOTOROLA D-48

CONTROL BITS OPTIONS SIOP Function Number (Assigned During Microcode Assembly) 00 Disabled 01 Low Priority 10 Medium Priority 11 High Priority 1 0 cHost Sequence Bits 00 Clock Channel Active Only, No Data Transfer 01 DOUT Channels Active, No Data Receive 10 Clock and DIN Channels Active, No Data Transmit 11 Full Bidirectional Tansmit and Receive 1 0 cHost Service Bits 00 No Host Service (Reset Condition) 01 No Action 10 No Action 11 Initialize Clock Channel and Start Transfer 0 cInterrupt Enable 0 Interrupt Not Asserted 1 Interrupt Asserted 0x30YY0A 0x30YY18 0x30YY1A 0x30YY14 0x30YY16
0x30YY1C 0x30YY1E
0 cInterrupt Status 0 Interrupt Not Asserted 1 Interrupt Asserted 0x30YY20
PARAMETER RAM 15 14 13 12 11 10 9 8 7 0x30YYW0 0x30YYW2 0x30YYW4 0x30YYW6 0x30YYW8 0x30YYWA 0x30YYWC 0x30YYWE = Written By CPU = Written By TPU DATA S
CHANNEL_CONTROL
HALF-PERIOD
BIT_COUNT XFER_SIZE
Figure D-30 SIOP Parameters


D.19.1.1 CHAN_CONTROL This 9-bit CPU written parameter is used to setup the clock polarity for the SIOP data transfer. The valid values for CHAN_CONTROL for this function are given in the table below. CHAN_CONTROL must be written by the host prior to issuing the host service request (HSR) to initialize the function. Table D-4 SIOP Function Valid CHAN_Control Options
CHAN_CONTROL1 876543210 010001101 010001110 Resulting Action Data valid on clock Falling edge. Data valid on clock Rising edge.
NOTES: 1. Other values of CHAN_CONTROL may result in indeterminate operation.
D.19.1.2 BIT_D BIT_D is a CPU written bit that determines the direction of shift of the SIOP data. If BIT_D is zero then SIOP_DATA is right shifted (lsb first). If BIT_D is one then SIOP_DATA is left shifted (msb first). D.19.1.3 HALF_PERIOD This CPU-written parameter defines the baud rate of the SIOP function. The value contained in HALF_PERIOD is the number of TCR1 counts for a half SIOP clock period (e.g., for a 50 KHz baud rate, with a TCR1 period of 240 ns, the value [(1/50 KHz)/ 2]/240 ns = 42 should be written to HALF_PERIOD. The range for HALF_PERIOD is 1 to 0x8000, although the minimum value in practice will be limited by other system conditions. See notes on use and performance of SIOP function. D.19.1.4 BIT_COUNT This parameter is used by the TPU to count down the number bits remaining while a transfer is in progress. During the SIOP initialization state, BIT_COUNT is loaded with the value contained in XFER_SIZE. It is then decremented as the data is transferred and when it reaches zero, the transfer is complete and the TPU issues an interrupt request to the CPU. D.19.1.5 XFER_SIZE This CPU-written parameter determines the number of bits that make up a data transfer. During initialization, XFER_SIZE is copied into BIT_COUNT. XFER_SIZE is shown as a 5-bit parameter to match the maximum size of 16 bits in SIOP_DATA, although the TPU uses the whole word location. For normal use, XFER_SIZE should be in the range 1-to-16. D.19.1.6 SIOP_DATA This parameter is the data register for all SIOP transfers. Data is shifted out of one end of SIOP_DATA and shifted in at the other end, the shift direction being determined
TPU ROM FUNCTIONS
MOTOROLA D-50

by the value of BIT_D. In output only mode, zero will be shifted into SIOP_DATA and in input only mode, the data shifted out is ignored. In clock-only mode SIOP_DATA is still shifted. Note that no justifying of SIOP_DATA is performed by the TPU, (e.g., if an 8-bit bi-directional transfer is made, shifting lsb first, then the bottom byte of SIOP_DATA will be shifted out and the input data will be shifted into the upper byte of SIOP_DATA). NOTE SIOP_DATA is not buffered. The CPU should only access it between completion of one transfer and the start of the next. D.19.2 Host CPU Initialization of the SIOP Function The CPU initializes the SIOP function by:
1. Disabling the channel by clearing the two channel priority bits 2. Selecting the SIOP function on the channel by writing the assigned SIOP function number to the function select bits 3. Writing CHAN_CONTROL in the clock channel parameter RAM 4. Writing HALF_PERIOD, BIT_D and XFER_SIZE in the clock channel parameter RAM to determine the speed, shift direction and size of the transfer 5. Writing SIOP_DATA if the data output is to be used 6. Selecting the required operating mode via the two host sequence bits 7. Issuing a host service request type 0b11 8. Enabling service by assigning H, M or L priority to the clock channel via the two channel priority bits The TPU then starts the data transfer, and issues an interrupt request when the transfer is complete. Once the function has been initialized, the CPU only needs to write SIOP_DATA with the new data and issue a HSR 0b11 to initiate a new transfer. In input or clock-only modes, just the HSR 0b11 is required. D.19.3 SIOP Function Performance Like all TPU functions, the performance limit of the SIOP function in a given application is dependent to some extent on the service time (latency) associated with other active TPU channels. This is due to the operational nature of the scheduler. Where two channels are being used for a uni-directional system, and no other TPU channels are active, the maximum baud rate is approximately 230 KHz at a bus speed of 16.77 MHz. A three-channel bi-directional system under the same conditions has a maximum baud rate of approximately 200 KHz. When more TPU channels are active, these performance figures will be degraded, however, the scheduler assures that the worst case latency in any TPU application can be closely approximated. It is recommended that the guidelines given in the TPU reference manual be used along with the information given in the SIOP state timing table to perform an analysis on any proposed TPU application that appears to approach the performance limits of the TPU.
TPU ROM FUNCTIONS
MOTOROLA D-51

Table D-5 SIOP State Timing1
State Number and Name S1 SIOP_INIT HSQ = X0 X1 S2 DATA_OUT HSQ = X0 X1 S3 DATA_IN HSQ = 0X 1X 14 28 4 6 14 24 4 4 28 38 7 7 Max. CPU Clock Cycles Number of RAM Accesses by TPU
NOTES: 1. Execution times do not include the time slot transition time (TST = 10 or 14 CPU clocks).
D.19.3.1 XFER_SIZE Greater Than 16 XFER_SIZE is normally programmed to be in the range 1-to-16 to match the size of SIOP_DATA, and has thus been shown as a 5-bit value in the host interface diagram. However, the TPU actually uses all 16 bits of the XFER_SIZE parameter when loading BIT_COUNT. In some unusual circumstances this can be used. If an input device is producing a data stream of greater than 16 bits then manipulation of XFER_SIZE will allow selective capturing of the data. In clock-only mode, the extended XFER_SIZE can be used to generate up to 0xFFFF clocks. D.19.3.2 Data Positioning As stated above, no justifying of the data position in SIOP_DATA is performed by the TPU. This means that in the case of a byte transfer, the data output will be sourced from one byte and the data input will shift into the other byte. This rule holds for all data size options except 16 bits when the full SIOP_DATA register is used for both data output and input. D.19.3.3 Data Timing In the example given in Figure D-31, the data output transitions are shown as being completely synchronous with the relevant clock edge and it is assumed that the data input is latched exactly on the opposite clock edge. This is the simplest way to show the examples, but is not strictly true. Since the TPU is a multi-tasking system, and the data channels are manipulated directly by microcode software while servicing the clock edge, there is a finite delay between the relevant clock edge and the data-out being valid or the data-in being latched. This delay is equivalent to the latency in servicing the clock channel due to other TPU activity and is shown as Td in the timing diagram. Td is the delay between the clock edge and the next output data being valid and also the delay between the opposite clock edge and the input data being read. For the vast majority of applications, the delay Td will not present a problem and can be ignored. Only for a system which heavily loads the TPU should calculations be made for the worst case latency for the SIOP clock channel + actual SIOP service time ( = Td) and ensure that the baud rate is chosen such that HALF_PERIOD - Td is not less

that the minimum setup time of the receiving device. A transmitting device must also hold data valid for a minimum time of Td after the clock.
DATA OUT c h a n x+ 1
Td CLO C K ch a n x
Td D ATA IN c h a n x-1
Figure D-31 SIOP Function Data Transition Example
TPU ROM FUNCTIONS
MOTOROLA D-53

TPU ROM FUNCTIONS
MOTOROLA D-54
APPENDIX E CLOCK AND BOARD GUIDELINES

E.1 INTRODUCTION The MPC555 / MPC556 built-in PLL, oscillator, and other analog and sensitive circuits, require that the board design follow special layout guidelines to ensure proper operation of the chip clocks. This appendix describes how the clock supplies and external components should be connected in the board. These guidelines must be fulfilled to reduce switching noise which is generated on internal and external buses during operation. Any noise injected into the sensitive clock and PLL logic reduces clock performance. The USIU maintains a PLL loss-of-lock warning indication that can be used to determine the clock stability in the MPC555 / MPC556.
CLOCK AND BOARD GUIDELINES
MOTOROLA E-1

E.2 MPC555 / MPC556 Family Power Distribution
VDDL (external 3 V)
Keyed Vcc 3.3 V (Main Supply)
100 nF (1 for each pad, 8 total)
VSS (external gnd shorted to vss) VDDI (internal 3 V)
1 nF
1 F
100 nF (1 for each pad 4 total) 100 nF
VSS (internal gnd)
VDDF >10 VDDSYN Cxfc XFC 100 nF VSSSYN Cx(pf) EXTAL

NOTE 1: The main power supply may optionally supply operating current to reduce the keep alive current requirements. See the circuit in
Q1 Cy(pf) 100 nF
R13 XTAL
8.12.1 System Clock Control Register (SCCR).
KAP 3 V
<50
KAPWR VDDSRAM 100 nF
1 nF
1F
BOARD
MPC555 / MPC556
NOTE 3: All 100 nF capacitors should be placed close to the pin. NOTE 4: CL is a function of specific crystal, CL = CX + CY.
NOTE 2: Resistor R1 is currently not required. Space should be left on the board to add it in the future if necessary.
Figure E-1 MPC555 / MPC556 Family Power Distribution Diagram 3 V
MOTOROLA E-2
VDDH (digital 5v)
Keyed Vcc 5 V
<50 VDDA 100 nF 1nF 1uF <50 Vrh 100 nF Vrl VSSA
To Sensors
100 nF
R2
NOTE: The size of resistor R2 depends on the sensor load current. It should be sized to match the voltage at Vrh.
Analog ground plane From Sensors

~10k
An* (Analog Input) ~10 nF
BOARD
MPC555 / MPC556
Figure E-2 MPC555 / MPC556 Family Power Distribution Diagram 5 V and Analog
MOTOROLA E-3

E.3 PLL and Crystal Oscillator External Components E.3.1 Crystal Oscillator External Components
CX
EXTAL
CY
Q1
R1
XTAL
VSSSYN
BOARD
MPC555 / MPC556
NOTE: Resistor R1 is currently not required.
Figure E-3 Crystal Oscillator Circuit
Table E-1 External Components Value For Different Crystals (Q1)

Component CL1 R13 CX CY NDK CP32C 20 MHz 6 1MEG3 6 6 KINSEKI CX-11F 20 MHz 14 1MEG3 16 16 MURATA CCSTC 4 MHz 1MEG3 2 Units pF Ohm pF pF
NOTES: 1. CL according to crystal specification, CL = CX + CY. 2. The Murata ceramic resonator includes the load capacitors. (8pF should be selected) 3. Resistor R1 is currently not required. Space should be left on the board to add it in the future if necessary.
Load capacitances specified in the table include all stray capacitance. Tolerance of the capacitors are 10%. The oscillator capacitors were calculated as follows:
MOTOROLA E-4
C XX = C YY = 2C L C XX = C X + C pad + C socket C YY = C Y + C pad + C socket

Where C X is real capacitor
C pad is pad capacitance
C socket is socket and trace capacitance C L is load capacitance

Capacitance of the socket C 1pF Capacitance of the board trace C 1pF . It should be low since the crystal must be located very close to the chip. Capacitance of the MPC555 / MPC556 XTAL pin is C pad 7pF Capacitance of the MPC555 / MPC556 EXTAL pin is C pad 7pF Tolerance of the capacitors taken into account is 10% E.3.2 KAPWR Filtering KAPWR pin is the MPC555 / MPC556 keep-alive power. KAPWR is used for the crystal oscillator circuit, and should be isolated from the noisy supplies. It is recommended that an RC filter be used on KAPWR, or bypass capacitors which are located as close as possible to the part.
KAP 3 V
50 100 nF VSSSYN
KAPWR
BOARD
MPC555 / MPC556
Figure E-4 RC Filter Example
MOTOROLA E-5
KAP 3 V
100 nF 1 F
KAPWR
VSSSYN
BOARD
MPC555 / MPC556
Figure E-5 Bypass Capacitors Example (Alternative) E.3.3 PLL External Components VDDSYN and VSSSYN are the PLL dedicated power supplies. These supplies must be used only for the PLL and isolated from all other noisy signals in the board. VDDSYN could be isolated with RC filter (see Figure E-1), or LC filter. The maximum noise allowed on VDDSYN, and VSSSYN is 50 mV with typical cut-off frequency of 500 Hz.
Keyed Vcc 3 V
10 100 nF VSSSYN
VDDSYN
BOARD
MPC555 / MPC556
Figure E-6 RC Filter Example
MOTOROLA E-6
Keyed Vcc 3 V
8.2 mH VDDSYN 100 nF VSSSYN
BOARD
MPC555 / MPC556
Figure E-7 LC Filter Example (Alternative) E.3.4 PLL Off-Chip Capacitor CXFC CXFC is the PLL feedback capacitor. It must be located as close as possible to the XFC and VDDSYN pads. The maximum noise allowed on XFC is 50 mV peak to peak with typical cut-off frequency of 500 Hz. The required value for CFXC are determined by the following two cases. MF is the multiplication factor as defined in the PLPRCR register (refer to Table 8-10). 1. 0 < (MF + 1) < 4 2. (MF + 1) 4 CXFC = (680 x (MF + 1) 120) pF CXFC = 1100 x (MF +1) pF
XFC CXFC VDDSYN
BOARD
MPC555 / MPC556
Figure E-8 PLL Off-Chip Capacitor Example E.4 Clock Oscillator and PLL External Components Layout Requirements E.4.1 Traces and Placement Traces connecting capacitors, crystal, resistor should be as short as possible. Therefore, the components (crystal, resistor and capacitors) should be placed as close to the oscillator pins of the MPC555 / MPC556 as possible.
MOTOROLA E-7

The voltage to the VDDSYN pin should be well regulated and the pin should be provided with an extremely low impedance path from the VDDSYN filter to the VDDSYN pad. The VSSSYN pin should be provided with an extremely low impedance path in the board. All the filters for the supplies should be located as close as possible to the chip package. It is recommended to design individual VSSSYN plane to improve VSSSYN quietness. E.4.2 Grounding/Guarding The traces from the oscillator pins and PLL pins of the MPC555 / MPC556 should be guarded from all other traces to reduce crosstalk. It can be provided by keeping other traces away from the oscillator circuit and placing a ground plane around the components and traces.
MOTOROLA E-8
APPENDIX F MEMORY ACCESS TIMING

F.1 Introduction Table F-1 lists all possible memory access timing to internal and external memory combinations. The clock values show the number of clocks from the moment an address is valid on a specific bus, until data is back on that same bus. The following assumptions were used when compiling the information:
The arbitration time was ignored. The values assume that the bus (or buses) involved in a transaction was in the IDLE state when the transaction needs that bus. The UIMB works in a mode of 1:1. This is relevant for IMB accesses values. In the case of 2:1 mode, the clock latency for a cycle on the IMB should be doubled. (each IMB access takes two clocks.) The basic delay of external bus to U-bus is four clocks (external master case). All IMB accesses are assumed to be 16-bit accesses only. If 32-bit accesses are used, then each such IMB access is split into two separate 16-bit cycles with normal IMB performance for each. Table F-1 Memory Access Times Using Different Buses
INTERNAL EXTERNAL RAM/ FLASH Internal Memory Mapped External 4+N2 2+N Nonmapped Internal Memory 4+N 2+N SHOW CYCLE
FLASH
RAM
IMB
SIU
Write
Read
RCPU Load/Store RCPU Instruction Fetches Peripheral Mode (ony ext. master is active) Slave Mode (both ext. & int. CPUs are active)
3/41 2-1-1-1-1...
1 33
6 -
5 -
2 -
2 14
4/5
5/6
NOTES: 1. / comes for on/off page flash access. 2. N is the number of clocks from external address valid till external data valid in the case of read cycle. In the case of zero wait states, N = 2. 3. Assuming BBC is parked on U-BUS. 4. Until address is valid on external pins
MEMORY ACCESS TIMING
MOTOROLA F-1

Table F-2 Timing Examples
Access Load/Store -> Ebus Load/Store -> IMB 16 bits # Clock 1 L L C,U Instruction Fetch-> cmf new page 3 concecutive accesses U2 C,U U C,U U Instruction Fetch-> cmf new page Load/Store -> IMB Instruction Fetch-> cmf new page Load/Store -> IMB External Bus-> cmf new page External Bus-> IMB Instruction Fetch-> cmf 2 concecutive accesses & External Bus-> cmf C,U U L U C L E U IMB IMB U U IMB IMB U U E C,U U C -3 E4 U U E retry U U E 8 U IMB IMB U E E 5 U L U L 2 2 U U 3 E E IMB IMB U L U L 4 5 6 7 8 9 10 11 12 13 Total 61 6
1 1 2 6 6 6
7 2
11
NOTES: 1. N is the number of clocks from external address valid until external data valid in the case of read cycle. In the case of zero wait states, N = 2. 2. Core instruction fetch data bus is usualy the UBUS 3. 8 clocks are dedicated for external access, and internal accesses are denied. 4. Assuming the external master immediately retries
LEGEND Shaded areas = address phase ; Non-shaded areas = data phase
MEMORY ACCESS TIMING
MOTOROLA F-2
APPENDIX G ELECTRICAL CHARACTERISTICS

This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing characteristics of the MPC555 / MPC556. The MPC555 / MPC556 is designed to operate at 40 MHz with nominal 3.3-V and 5.0-V power supplies. G.1 Absolute Maximum Ratings (VSS = 0 V)
Table G-1 Absolute Maximum Ratings

Rating 3-V Supply Voltage1,2 Flash Supply Voltages3 Flash Core Voltage1 Oscillator, Keep Alive Reg. Supply Voltage1 SRAM Supply Voltage1 Clock Synthesizer Supply Voltage1 QADC Supply Voltage4 5-V Supply Voltage DC Input Voltages5 Reference Supply VRH, with Reference to VRL VSS Differential Voltage VDD Differential Voltage6 VRL to VSSA Differential Voltage Maximum Input Current per pin 7, 8, 9 QADC Maximum Input Current per Pin Operating Temperature Range (Packaged) Operating Temperature Range (Die Form) (Maximum junction temperature for packaged devices) Storage Temperature Range Maximum Solder Temperature10 Moisture Sensitivity Level11 Symbol VDDL/VDDI VPP VDDF KAPWR VDDSRAM VDDSYN VDDA VDDH VIN VRH VRL VSS VSSA VDDL VDDA VRL VSSA IMA Imax TA TJ TSTG Tsdr MSL Min. Value -6.0 -6.0 -6.0 -6.0 -6.0 -6.0 -6.0 -0.3 VSS -0.3 -0.3 -0.1 -6.0 -6.0 -25 -25 -40 (TL) -40 -55 Max. Value 4.0 6.0 4.0 4.0 4.0 4.0 6.0 6.0 VDDH +0.3 6.0 0.1 4.0 0.3 25 25 +125 (TH) +150 +155 220 3 Unit V V V V V V V V V V V V V mA mA C C C C
NOTES: 1. For internal digital supply of VDDL = 3.3 V typical. 2. VDDL and VDDI should always be connected to the same potential with no differential voltage.
ELECTRICAL CHARACTERISTICS
MOTOROLA G-1

3. During program/erase operation the value of VPP must be 5.0 V 5%. 4. VDDA = 5.0 V 10%. 5. All 3-V input pins are 5-V tolerant. This applies to all input pins. 6. Refers to allowed random sequencing of power supplies. 7. Maximum continuous current on I/O pins provided the overall power dissipation is below the power dissipation of the package. Proper operation is not guaranteed at this condition. 8. Condition applies to one pin at a time. 9. Transitions within the limit do not affect device reliability or cause permanent damage. Exceeding limit may cause permanent conversion error on stressed channels and on unstressed channels. 10. Solder profile per CDF-AEC-Q100, current revision. 11. Moisture sensitivity per JEDEC test method A112.
Functional operating conditions are given in G.7 DC Electrical Characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage to the device. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or VDD). G.2 Target Failure Rate Target failure rate of TBD ppm pending characterization and evaluation of qualifiable silicon. G.3 Package The MPC555 / MPC556 is available in two forms, packaged and die. The package is a 272-ball PBGA, Motorola case outline 1135A-01 (See Figure 2-1 of the MPC555 Users Manual for a case drawing or contact Motorola.) For die characteristics, contact the Motorola factory. G.4 EMI Characteristics G.4.1 Reference Documents The documents referenced for the EMC testing of MPC555 / MPC556 are listed below. 1. SAE J1752/3 Issued 1995-03 2. VDE UK 767.14/ZVEI-Ad-Hoc-HL-AK Version1.0 May 1994 G.4.2 Definitions and Acronyms EMC Electromagnetic compatibility EMI Electromagnetic interference TEM cell Transverse electromagnetic mode cell
MOTOROLA G-2

G.4.3 Testing Characteristics 1. Scan range: 150 kHz 1000 MHz 2. Operating frequency: 20 MHz, 40 MHz 3. Operating voltages: 3.3 V, 5.0 V 4. Max spikes: 50 dBuV 5. I/O port waveforms: 50% duty cycle @ 100 s period 6. Temperature: 25C (-40C, 125C if available) G.5 Thermal Characteristics Table G-2 Thermal Characteristics
Characteristic Symbol RJA RMA RJB RJC JT Value 42.81,2 Unit C/W BGA Package Thermal Resistance, Junction to Ambient Natural Convection BGA Package Thermal Resistance, Junction to Ambient Four layer (2s2p) board, natural convection BGA Package Thermal Resistance, Junction to Board BGA Package Thermal Resistance, Junction to Case (top) BGA Package Thermal Resistance, Junction to Package Top, Natural Convection
30.43,4
C/W
19.95 6.36 2.77
C/W C/W C/W
NOTES: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and the board thermal resistance. 2. Per SEMI G38-87 and JESD51-2 with the board horizontal. 3. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and the board thermal resistance. 4. Per JESD51-6 with the board horizontal. 5. Thermal resistance between the die and the printed circuit board (Four layer [2s2p] board, natural convection). 6. Indicates the thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. 7. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per EIA/JESD51-2.
MOTOROLA G-3

An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: TJ = TA + (RJA x PD) where: TA = ambient temperature (C) RJA = package junction to ambient resistance (C/W) PD = power dissipation in package The junction to ambient thermal resistance is an industry standard value which provides a quick and easy estimation of thermal performance. Unfortunately, the answer is only an estimate; test cases have demonstrated that errors of a factor of two are possible. As a result, more detailed thermal characterization is supplied. Historically, the thermal resistance has frequently been expressed as the sum of a junction to case thermal resistance and a case to ambient thermal resistance: RJA = RJC + RCA where: RJA = junction to ambient thermal resistance (C/W) RJC = junction to case thermal resistance (C/W) RJA = case to ambient thermal resistance (C/W) RJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RCA. For instance, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for ceramic packages with heat sinks where some 90% of the heat flow is through the case to the heat sink to ambient. For most packages, a better model is required. The simplest thermal model of a package which has demonstrated reasonable accuracy (about 20%) is a two resistor model consisting of a junction to board and a junction to case thermal resistance. The junction to case covers the situation where a heat sink will be used or where a substantial amount of heat is dissipated from the top of the package. The junction to board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. It has been observed that the thermal performance of most plastic packages and especially PBGA packages is strongly dependent on the board. temperature. If the board temperature is known, an estimate of the junction temperature in the environment can be made using the following equation:
MOTOROLA G-4

TJ = TB + (RJB x PD) where: TB = board temperature (C) RJB = package junction to board resistance (C/W) PD = power dissipation in package (W) If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. For this method to work, the board and board mounting must be similar to the test board used to determine the junction to board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane.
When the board temperature is not known, a thermal simulation of the application is needed. The simple two resistor model can be used with the thermal simulation of the application [2], or a more accurate and complex model of the package can be used in the thermal simulation. Consultation on the creation of the complex model is available. To determine the junction temperature of the device in the application after prototypes are available, the thermal characterization parameter (JT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using the following equation: TJ = TT + (JA x PD) where: TT = thermocouple temperature on top of package (C) RJA = thermal characterization parameter PD = power dissipation in package The thermal characterization parameter is measured per JESD51-2 characteristic published by JEDEC using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. G.5.1 Thermal References: Semiconductor Equipment and Materials International 805 East Middlefield Rd Mountain View, CA 94043 (415) 964-5111
MOTOROLA G-5

MIL-SPEC and EIA/JESD (JEDEC) characteristics are available from Global Engineering Documents at 800-854-7179 or 303-397-7956. JEDEC characteristics are available on the WEB at: http://www.jedec.org 1. C.E. Triplett and B. Joiner, An Experimental Characterization of a 272 PBGA Within an Automotive Engine Controller Module, Proceedings of SemiTherm, San Diego, 1998, pp. 47-54. 2. B. Joiner and V. Adams, Measurement and Simulation of Junction to Board Thermal Resistance and Its Application in Thermal Modeling, Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.
G.6 ESD Protection
Table G-3 ESD Protection

Characteristics ESD Target for Human Body Model (HBM) R1 HBM Circuit Description C ESD Target for Machine Model (MM) R1 MM Circuit Description C Number of Pulses Per Pin Positive Pulses (MM) Negative Pulses (MM) Positive Pulses (HBM) Negative Pulses (HBM) Interval of Pulses 200 3 3 1 1 1 100 200 0 Symbol Value 2000 1500 Units V pF V pF
Second
Notes: 1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2. A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device characteristic requirements. Complete DC parametric and functional testing shall be performed per applicable device characteristic at room temperature followed by hot temperature, unless specified otherwise in the device characteristic.
MOTOROLA G-6

G.7 DC Electrical Characteristics Table G-4 DC Electrical Characteristics
(VDDL = 3.3 V 0.3 V, VDDH = 5.0 V 0.5 V, TA = TL to TH) Characteristic 3-V only Input High Voltage1 Except EXTAL and EXTCLK 3-V Input High Voltage EXTCLK 5-V Input Only High Voltage 2 5-V Input High Voltage (QADC PQA, PQB) Symbol VIH3 VIHC VIH5 VIHA5 Min 2.0 2.4 0.7*VDDH 0.7*VDDA Max VDDH +0.3 VDDH +0.3 VDDH +0.3 VDDA +0.3 Unit V V V V
Muxed 3-V/ 5-V Pins (GPIO Muxed with Addr. (Port A), Data (Port D), and Control (Port C)) 3-V Input High Voltage Addr. (Port A), Data (Port D), Control (Port C) 5-V Input High Voltage (GPIO) 3-V Input Low Voltage Except EXTCLK 3-V Input Low Voltage EXTCLK 5-V Input Low Voltage 5-V Input Low Voltage (QADC PQA, PQB) Muxed 3-V/ 5-V Pins (GPIO Muxed with Addr. (Port A), Data (Port D), and Control (Port C)) 3-V Input Low Voltage (Addr. (Port A), Data (Port D), Control (Port C)) 5-V Input Low Voltage (GPIO) QADC Analog Input Voltage3 3-V Mode Select Current Pull-up @ 0 V to VIL3, Pull-down @ VIH3 to VDDL 5-V Mode Select Current Pull-up @ 0 to VIL5, Pull-down @ VIH5 to VDDH 3-V Input Leakage Current Pull-up/down Inactive 5-V Input Leakage Current Pull-up/down Inactive QADC64 Input Current, Channel Off 4 PQA PQB
VIH3M VIH5M
2.0 0.7*VDDH
VDDH +0.3 VDDH +0.3
VIL3 VIL3C VIL5 VILA5
VSS -0.3 VSS -0.3 VSS -0.3 VSSA -0.3
0.8 0.4 0.4*VDDH 0.4*VDDA
V V V V
VIL3M VIL5M VINDC Iact3 V Iact5 V Iinact3 V Iinact5 V
VSS -0.3 VSS -0.3 VSSA -0.3 20
0.8 0.4*VDDH VDDA +0.3 130
V V V A A A A
20
130
1.0 1.0
IOFF
-200 -150
200 150
nA
MOTOROLA G-7

Table G-4 DC Electrical Characteristics (Continued)
(VDDL = 3.3 V 0.3 V, VDDH = 5.0 V 0.5 V, TA = TL to TH) Characteristic 3-V Output High Voltage VDD = VDDL (IOH = -2 mA) 5-V Output High Voltage VDD = VDDH (IOH = -2 mA) All 5-V Only Outputs Except TPU. 5-V Output High Voltage VDD = VDDH (IOH = -5 mA) For TPU Pins Only Muxed 3-V/ 5-V Pins (GPIO Muxed with Addr. (Port A), Data (Port D), and Control (Port C)) 3-V Output High Voltage (IOH = -2 mA) 5-V Output High Voltage (IOH = -2 mA) Symbol VOH3 VOH5 VOHTP5 Min 2.4 VDDH -0.7 VDDH -0.65 Max Unit V V V
VOH3M VOH5M VOL3 VOL5
2.4 VDDH -0.7
3-V Output Low voltage VDD = VDDL (IOL = 3.2 mA) 5-V Output Low Voltage VDD = VDDH (IOL = 2 mA) All 5-V Only Outputs Except TPU. 5-V Output Low Voltage VDD = VDDH For TPU Pins Only IOL = 10 mA IOL = 2 mA Muxed 3-V/ 5-V Pins (GPIO Muxed with Addr. (Port A), Data (Port D), and Control (Port C)) 3-V Output Low Voltage (IOL = 3.2 mA) 5-V Output Low Voltage (IOL = 2 mA) Output Low Current CLKOUT @ VOL = 0.5 V Output High Current CLKOUT @ VOH = 2.4 V CLKOUT Capacitance (@ 40 MHz) COM[1:0] of SCCR = 0b01 COM[1:0] of SCCR = 0b00 ENGCLK Capacitance@20Mhz EECLK[1:0] of SCCR = 0b01 EECLK[1:0] of SCCR = 0b00 Capacitance for Input, Output, and Bidirectional Vin = 0 V, f = 1 MHz (except QADC) Load Capacitance for Bus Pins Only7 COM[1:0] of SCCR = 0bX1 COM[1:0] of SCCR = 0bX0 QADC Total Input Capacitance PQA Not Sampling PQB Not Sampling Incremental Capacitance Added During Sampling Hysteresis (Only IRQ, TPU, MIOS, GPIO, QADC [Digital Inputs] and PORESET, HRESET, SRESET)8
0.5 0.45
V V
VOLTP5
1.0 0.45
VOL3M VOL5M IOL IOH
0.5 0.45
2.0 2.0
mA mA
Cclk
305 90 255 506 7
pF
Ceng
pF
Cin
pF
CL
25 50 15 10 5
pF
CIN
0.5
pF
VH
MOTOROLA G-8

(VDDL = 3.3 V 0.3 V, VDDH = 5.0 V 0.5 V, TA = TL to TH) Characteristic Operating Current (3-V Supplies) @ 33 MHz Expanded VDDL / VDDI KAPWR VDDSRAM VDDSYN (Crystal Frequency: 20 Mhz) VDDF9 Single Chip VDDL / VDDI KAPWR VDDSRAM VDDSYN (Crystal Frequency: 20 Mhz) VDDF9 Operating Current (5-V Supplies)@ 33 MHz VDDH VDDA VPP10 Operating Current (3-V Supplies)@ 40 MHz11 Expanded VDDL / VDDI KAPWR VDDSRAM VDDSYN (Crystal Frequency: 20 Mhz) VDDF9 Single Chip VDDL / VDDI KAPWR VDDSRAM VDDSYN (Crystal Frequency: 20 Mhz) VDDF9 Operating Current (5-V Supplies)@ 40 MHz VDDH VDDA12 VPP10 QADC64 Low Power Stop Mode (VDDA) Low Power Current @ 40 MHz (VDDI) DOZE, Active PLL and Active Clocks SLEEP, Active PLL with Clocks off DEEP SLEEP13 PLL and Clocks off VDDL, VDDI, VDDF Operating Voltage VPP Flash Operating Voltage Symbol Min Max Unit mA IDDL IDDKAP IDDSRM IDDSYN IDDF 206 6.6 1.7 1.7 8.3
IDDL IDDKAP IDDSRM IDDSYN IDDF
206 6.6 1.7 1.7 8.3
IDDH5 IDDA IDDPP
16.5 5 30
mA
250 8.0 2.0 2.0 10
mA
250 8.0 2.0 2 10 20 5.0 30 10
IDDH5 IDDA IDDVPP IDDA IDDDZ IDDSLP IDDDPSLP VDDL, VDDI, VDDF VPP 3.0 VDDF -0.35 V
mA
A mA mA mA V V
100 10 4 3.6 5.50
MOTOROLA G-9

(VDDL = 3.3 V 0.3 V, VDDH = 5.0 V 0.5 V, TA = TL to TH) Characteristic VPP Flash Programming Voltage Oscillator, Keep Alive Registers Operating Voltage during normal operation (VDDL powered-up)13,14 Oscillator, Keep Alive Registers Operating Voltage during powered-down operation SRAM Operating Voltage during normal operation (VDDL powered-up)14 VDDH Operating Voltage Symbol VPP KAPWR KAPWR VDDSRAM VDDH VDDA VDDSYN VSS VSSA VRL VRH VRH VRL IREF IREF Min 4.75 VDDL -0.2 3.0 VDDL -0.2 4.5 4.5 VDDL -0.2 -100 VSSA VDDA -0.3 4.5 Max 5.25 VDDL +0.2 3.6 VDDL + 0.2 5.5 5.5 VDDL +0.2 100 VSSA +0.1 VDDA 5.5 500 4.0 Unit V V V V V V V mV V V V A mA
QADC Operating Voltage Clock Synthesizer Operating Voltage13 VSS Differential Voltage QADC64 Reference Voltage Low15 QADC64 Reference Voltage High16 QADC64 VREF Differential Voltage QADC64 Reference Supply Current, DC QADC64 Reference Supply Current, Transient Measured on VRH Standby Supply Current KAPWR Only VDDSRAM Only (RAM Standby Current) @ TJ = 90C VDDSRAM Only (RAM Standby Current) @ TJ = 90C with Low Voltage Protection Circuitry VDDSRAM Only (RAM Standby Current) @ TJ = 150C RAM Standby Voltage for Data Retention (Powered-down Mode) Specified VDD Applied (VDD = VSS) DC Injection Current per Pin GPIO, TPU, MIOS, QSM, EPEE and 5 V 18,19 DC Injection Current Per Pin 3 V 18, 19 QADC64 Disruptive Input Current 18, 20 Power Dissipation -40 MHz 33 MHz
4 100 150 250
mA A A A V
VDDSRAM
1.417
3.6
IIC5 IIC3 INA PD
-1.0 -1.0 -3
1.0 1.0 3 1 0.8
mA mA mA W
NOTES: 1. This spec is for 3-V output and 5-V input friendly pins. 2. This spec is for 5-V output and 5-V input pins. 3. Within this range, no significant injection will be seen. See QADC64 disruptive input current (INA). 4. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each 8 12C, in the ambient temperature range of 50 125C. 5. 45 pF maximum for mask sets prior to K62N
MOTOROLA G-10

6. 90 pF maximum for mask sets prior to K62N 7. All bus pins support two drive strengths capabilities, 25 pF and 50 pF. Current drive is less at the 25-pF capacitive load. Both modes achieve 40-MHz timing. 8. Only IRQ, TPU, MIOS, GPIO, QADC (when digital inputs) and RESET pins have hysteresis, thus there is no hysteresis characteristic required for all other pins 9. The worst case VDDF occurs during HRESET active (booting), other modules will not be running. 10. Maximum occurs during programming and erase. Read IPP is lower. 11. All power consumption characteristics assume 50-pF loads and running a typical application.The power consumption of some modules could go up is they are exercised heavier, but the power consumption of other modules would decrease. 12. Current measured at maximum system clock frequency with QADC active. 13. This parameter is periodically sampled rather than 100% tested. 14. KAPWR and VDDSRAM are powered up prior to any other supply. 15. To obtain full-range results, VSSA VRL VINDC VRH VDDA 16. To obtain full-range results, VSSA VRL VINDC VRH VDDA 17. The voltage at which the LVSRS bits in the VSRMCR register will be set ranges from 1.5 2.4 V. 18. All injection current is transferred to the VDDH. An external load is required to dissipate this current to maintain the power supply within the specified voltage range. 19. Total injection current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation. 20. Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater than VRH and $000 for values less than VRL. This assumes that VRH VDDA and VRL VSSA due to the presence of the sample amplifier. Other channels are not affected by non-disruptive conditions.
MOTOROLA G-11

G.8 Oscillator and PLL Electrical Characteristics Table G-5 Oscillator and PLL
Characteristic Oscillator Startup Time (For Typical Crystal Capacitive Load) 4-MHz Crystal 20-MHz Crystal PLL Lock Time PLL Operating Range Crystal Operating Range, MODCK[1:3]=0b010, or 0b110 MODCK[1:3] = 0b001, 0b011, 0b100, 0b101, 0b111 Symbol Min Typical Max Unit
OSCstart4 OSCstart20 TLOCK FVCOOUT FCRYSTAL FJIT FJIT10 FLIMP IBIAS Iosc ROSC 30 2 15 -1% -0.3 31 81 0.721 1.1 7
10 10 500 80 5 25 +1% +0.3 121 -0.41 -0.81 251 1.931
mS
Input Clocks MHz MHz
PLL Jitter PLL Jitter (averaged over 10 s) MF < 20 Limp Mode Clock Frequency Oscillator Bias Current (XTAL) 4 MHz 20 MHz Oscillator Drive (XTAL) Oscillator Bias Resistor NOTES: 1. Values to be evaluated upon further characterization.
MHz
mA
mA M
G.9 Power Up/Down Sequencing See SECTION 8 CLOCKS AND POWER CONTROL.
MOTOROLA G-12

G.10 FLASH Electrical Characteristics NOTE See APPENDIX H FLASH ELECTRICAL CHARACTERISTICS FOR ALL J76N MASK SETS AND 0K02A AND 1K02A ONLY for flash electrical characteristics for all J76N, 0K02A, and 1K02A mask sets. Contact Motorola for flash electrical characteristics for all J12F mask sets. Table G-6 Program and Erase Characteristics
(VDDF = 3.3 V 0.3 V, VPP= 4.75 V to 5.25 V, TA = TL to TH) Value Symbol Meaning Minimum EPULSE TERASE PPULSE(4.75 Vpp) PPULSE(5.0 Vpp) PPULSE(5.25 Vpp) TPROG CPULSE(4.75 Vpp) CPULSE(5.0 Vpp) CPULSE(5.25 Vpp) TCLEAR SPULSE(4.75 Vpp) SPULSE(5.0Vpp) SPULSE(5.25 Vpp) TSET Number of Erase Pulses Erase Pulse Time Number of Program Pulses @VPP = 4.75 Number of Program Pulses @VPP = 5.00 Number of Program Pulses @VPP = 5.25 Program Pulse Time Number of CENSOR Clear Pulses @VPP = 4.75 Number of CENSOR Clear Pulses @VPP = 5.00 Number of CENSOR Clear Pulses @VPP = 5.25 CENSOR Clear Pulse Time Number of CENSOR Set Pulses @VPP = 4.75 Number of CENSOR Set Pulses @VPP = 5.00 Number of CENSOR Set Pulses @VPP = 5.25 CENSOR Set Pulse Time 8 98 48 47 11 8 98 47 11 8 98 Typical 8 100 45000 800 250 50 87 17 10 100 87 17 10 100 Maximum 27 102 480001,2 7000 20003 256.5 700 57 37 102 700 57 37 102 mS Pulses Pulses Pulses S Pulses Pulses Pulses mS Pulses Pulses Pulses mS Units
NOTES: 1. The worst case programming time occurs at VPP = 4.75 V and TA = -40 C. 2. This value is based on initial device characterization and may not be tested in production. 3. The best case (fastest) programming time of < 50 pulses is at VPP = 5.25 V and TA = 125C.
MOTOROLA G-13

Table G-7 CMF AC and DC Power Supply Characteristics
Symbol VDDF Operating Voltage Read, Program or Erase Operating Current at 40.0 MHz, IDDF VDDF = 3.3 V for a 256-Kbyte Module Read, Program or Erase Operation Disabled External Program or Erase Voltage Read Program or Erase External Program and Erase Current1 Read, VPP = 5 V Program, VPP = 5.25 V Erase, VPP = 5.25 V 10 5 mA Meaning Min. Value 3.0 Max Value 3.6 Unit V
VPP
VDDF -0.35 4.75
5.5 5.25 <100 301 301
IDDPP
A mA mA
NOTES: 1. Average current is less than 30 mA when programming both modules simultaneously.
G.10.1 Flash Module Life Table G-8 Flash Module Life

Symbol P/E Cycles1 P/E Cycles1 Retention Meaning Maximum Number of Program/Erase Cycles2 to Guarantee Data Retention Array Blocks Maximum Number of Program/Erase Cycles2 to Guarantee Data Retention Censor Bits Data Retention at Average Operating Temperature of 85 C Value 1003,4 104 Minimum 10 years
NOTES: 1. Target failure rate at specified number of program/erase cycles of 2 ppm pending characterization of production silicon. 2. A program/erase cycle is defined as switching the bits from 1 0 1. 3. Reprogramming of a CMF array block prior to erase is not required. 4. Number of program/erase cycles to be adjusted pending characterization of production silicon.
MOTOROLA G-14

G.10.2 Programming and Erase Algorithm Table G-9 CMF Programming Algorithm (v6 and Later)
No. of Pulses 4 4 4 4 20 20 20 max. 48,000 Pulse Width 256 s 256 s 256 s 256 s 50 s 50 s 50 s 50 s NVR 1 1 1 1 0 0 0 0 PAWs 100 101 110 111 100 101 110 111 GDB 1 1 1 1 1 1 1 1 PAWs Mode Mode 4NL Mode 5NL Mode 6NL Mode 7NL Mode 4NL Mode 5NL Mode 6NL Mode 7NL Negative gate ramp (high range) Negative gate ramp (low range) Description
Table G-10 CMF Erase Algorithm (v6)

No. of Pulses 1 1 1 1 1 1 1 20 Pulse Width 100 ms1 100 ms1 100 ms1 100 ms1 100 ms1 100 ms1 100 ms1 NVR 1 1 1 1 0 0 0 0 PAWs 100 101 110 111 100 101 110 111 GDB 1 1 1 1 1 1 1 1 PAWs Mode Mode 4NL Mode 5NL Negative gate ramp (low range) Mode 6NL Mode 7NL Mode 4NL Mode 5NL Negative gate ramp (high range) Mode 6NL Mode 7NL Description
100 ms2
NOTES: 1. No margin read after pulse. 2. Do margin read after each pulse.
MOTOROLA G-15

G.11 Generic Timing
VIH
VIH VIL A VIL
CLKOUT
B
OUTPUTS
VIH VIL
VIH VIL
A B VIH VIL VIH VIL
OUTPUTS
INPUTS
VIH VIL
VIH VIL C D VIH VIL
INPUTS
VIH VIL
A. Maximum Output Delay Characteristic B. Minimum Output Hold Time C. Minimum input Setup Time Characteristic D. Minimum input Hold Time Characteristic
Figure G-1 CLKOUT Timing
MOTOROLA G-16

Table G-11 Bus Operation Timing
(TA = TL to TH) Characteristic 1 1a 2 3 4 CLKOUT Period ENGCLK2 Clock Pulse Width Low Clock Pulse Width High CLKOUT Rise Time ENGCLK Rise Time CLKOUT Fall Time ENGCLK Fall Time Circuit Parameter CLKOUT to Signal Invalid (Hold Time) A[0:31] RD/WR BURST D[0:31] CLKOUT to Signal Invalid: (Hold Time) TSIZ[0:1] RSV AT[0:3] BDIP CLKOUT to Signal Invalid (Hold Time)3 BR BG FRZ VFLS[0:1] VF[0:2] IWP[0:2] LWP[0:1] PTR RETRY STS4 Slave mode CLKOUT to Signal Invalid D[0:31] CLKOUT to Signal Valid A[0:31] RD/WR BURST TCC 8 15 2% 15 2% 5 20 5 20 7.75 Expression1 TC 33 MHz Min 30.30 20 12.5 2% 12.5 2% 5 20 5 20 Max 40 MHz Unit Min 25 20 Max ns MHz ns ns ns ns ns ns ns
4a 5 5a 6
0.2TC 1.0
ns
7a
0.2TC 1.0
ns
7b
0.2TC 1.0
ns
7c
0.25TC + TCC
ns
0.25TC + TCC
7.5
14
6.25
14
ns
MOTOROLA G-17

Table G-11 Bus Operation Timing (Continued)
(TA = TL to TH) Characteristic CLKOUT to Signal Valid TSIZ[0:1] RSV AT[0:3] BDIP CLKOUT to Signal Valid3 BR BG VFLS[0:1] VF[0:2] IWP[0:2] FRZ LWP[0:1] PTR RETRY MTS Slave Mode CLKOUT to Signal Valid D[0:31] CLKOUT to Signal Valid D[0:31] CLKOUT to Signal invalid A[0:31] RD/WR BURST D[0:31] TSIZ[0:1] RSV AT[0:3] PTR RETRY CLKOUT to TS, BB Assertion CLKOUT to TA, BI Assertion (When Driven by the Memory Controller) CLKOUT to RETRY Assertion (When Driven by the Memory Controller) CLKOUT to TS, BB Negation CLKOUT to TA, BI Negation (When Driven by the Memory Controller) CLKOUT to RETRY Negation (When Driven by the Memory Controller) CLKOUT to TS, BB Signal invalid Expression1 33 MHz Min Max 40 MHz Unit Min Max
8a
0.25TC + TCC
7.5
15
6.25
15
ns
8b
0.25TC + TCC
7.5
15
6.25
14
ns
8c 8d
0.25TC + TCC + 4 0.25TC + TCC
7.5 7.5
15 14
6.25 6.25
14 14
ns ns
0.25TC + TCC
7.5
15
6.25
13
ns
10 10a
0.25TC + TCC
7.5
15 10
6.25
14 10
ns ns
10b 11 11a
0.25TC + TCC 7.5
10 15 11 6.25
10 14 11
ns ns ns
11b 12
0.25TC + 14 7.5
11 21 6.25
11 20
ns ns
MOTOROLA G-18

(TA = TL to TH) Characteristic CLKOUT to TA, BI Signal invalid (When Driven by the Memory Controller) CLKOUT to TEA Assertion CLKOUT to TEA Signal invalid Input Valid to CLKOUT (Setup Time) TA TEA BI3 Input Valid to CLKOUT (Setup Time) KR CR RETRY Input Valid to CLKOUT (Setup Time) BB BG BR5 CLKOUT to Signal Invalid (Hold Time) TA TEA BI BB BG BR 4 CLKOUT to Signal Invalid (Hold Time) RETRY KR CR Signal Valid to CLKOUT Rising Edge (Setup Time) D[0:31]6 CLKOUT Rising Edge to Signal Invalid (Hold Time) D[0:31]6 CLKOUT Rising Edge to CS asserted -GPCM- ACS = 00 CLKOUT Falling Edge to CS Asserted -GPCM- ACS = 10, TRLX = 0 or 1 CLKOUT Falling Edge to CS Asserted -GPCM- ACS = 11, TRLX = 0 or 1 0.25TC + TCC + 1 TCC + 1 0.25TC + TCC + 1 7.5 Expression1 33 MHz Min 12a 13 14 Max 15 11 15 40 MHz Unit Min Max 15 11 15 ns ns ns
15
13
12
ns
15a
11
10
ns
15b
10
ns
16
ns
16a
ns
17
ns
18
ns
19 19a 19b
7.5
16 9 16
6.25
14 8
ns ns ns
6.25
14
MOTOROLA G-19

(TA = TL to TH) Characteristic CLKOUT Falling Edge to CS Asserted -GPCM- ACS = 11, TRLX = 0, EBDF = 1 CLKOUT Rising Edge to CS Negated -GPCM- Read Access or Write Access When CSNT = 0 or Write Access When CSNT = 1 and ACS = 00 A[0:31] to CS Asserted -GPCM- ACS = 10, TRLX = 0 A[0:31] to CS Asserted -GPCM- ACS = 11, TRLX = 0 CLKOUT Rising Edge to OE, WE[0:3]/ BE[0:3] Asserted CLKOUT Rising Edge to OE Negated A[0:31] to CS Asserted -GPCM- ACS = 10, TRLX = 1 A[0:31] to CS Asserted -GPCM- ACS = 11, TRLX = 1 CLKOUT Rising Edge to WE[0:3]/ BE[0:3] Negated -GPCM-Write Access CSNT = 0 CLKOUT Falling Edge to WE[0:3]/ BE[0:3] Negated -GPCM-Write Access TRLX = 0 or 1, CSNT = 1, EBDF = 0. CLKOUT Falling Edge to CS Negated -GPCM-Write Access TRLX = 0 or 1, CSNT = 1, ACS = 10 or ACS=11, EBDF = 0 CLKOUT Falling Edge to WE[0:3]/ BE[0:3] Negated -GPCM-Write Access TRLX = 0, CSNT = 1, EBDF = 1. CLKOUT Falling Edge to CS Negated -GPCM-Write Access TRLX = 0, CSNT = 1, ACS = 10 or ACS=11, EBDF = 1 WE[0:3]/BE[0:3] Negated to D[0:31] Signal invalid -GPCM- Write Access, CSNT = 0 WE[0:3]/BE[0:3] Negated to D[0:31] Signal invalid -GPCM- Write Access, TRLX = 0, CSNT = 1, EBDF = 0 2 30 38 Expression1 33 MHz Min 19c 0.25TC + TCC + 4 7.5 Max 20 40 MHz Unit Min 6.25 Max 17 ns
20
TCC + 1
ns
21 21a 22 23 24 24a
2 8 11 11
1.5 7 9 0 25 32 8
ns ns ns ns ns ns
25
ns
25a
0.25TC + TCC + 1
7.5
6.25
14
ns
25b
0.25TC + TCC + 1
7.5
16
14
ns
25c
0.25TC +TCC + 4
7.5
20
6.25
17
ns
25d
0.25TC +TCC + 4
7.5
20
6.25
17
ns
26
ns
26a
ns
MOTOROLA G-20

(TA = TL to TH) Characteristic CS Negated to D[0:31], Signal invalid -GPCM- Write Access, ACS = 00, TRLX = 0 & CSNT = 0 CS Negated to D[0:31], Signal invalid -GPCM- Write Access, TRLX = 0, CSNT = 1, ACS = 10 or ACS=11, EBDF = 0 WE[0:3] Negated to D[0:31] Signal invalid -GPCM- Write Access, TRLX = 1, CSNT = 1, EBDF = 0 CS Negated to D[0:31] Signal invalid -GPCM- Write Access, TRLX = 1, CSNT = 1, ACS = 10 or ACS=11, EBDF = 0 WE[0:3]/BE[0:3] Negated to D[0:31] Signal Invalid -GPCM- Write Access, TRLX = 0, CSNT = 1, EBDF = 1 CS Negated to D[0:31] Signal invalid -GPCM- Write Access, TRLX = 0, CSNT = 1, ACS = 10 or ACS=11, EBDF = 1 WE[0:3]/BE[0:3] Negated to D[0:31] Signal invalid -GPCM- Write Access, TRLX = 1, CSNT = 1, EBDF = 1 CS Negated to D[0:31] Signal invalid -GPCM- Write Access, TRLX = 1, CSNT = 1, ACS = 10 or ACS=11, EBDF = 1 CS, WE[0:3] Negated to A[0:31] Invalid -GPCM- Write Access7 WE[0:3]/BE[0:3] Negated to A[0:31] Invalid -GPCM- Write Access, TRLX = 0, CSNT = '1. 27a CS Negated to A[0:31] Invalid -GPCM- Write Access, TRLX = 0, CSNT = '1, ACS = 10,ACS = =11, EBDF = 0 18 4 ns Expression1 33 MHz Min 26b 0 Max 40 MHz Unit Min 0 Max ns
26c
ns
26d
38
29
ns
26e
38
29
ns
26f
12
ns
26g
12
ns
26h
30
24
ns
26i
30
24
ns
27
ns
MOTOROLA G-21

(TA = TL to TH) Characteristic WE[0:3]/BE[0:3] Negated to A[0:31] Invalid -GPCM- Write Access, TRLX = 1, CSNT = '1. 27b CS Negated to A[0:31] Invalid -GPCM- Write Access, TRLX = 1, CSNT = '1, ACS = 10, ACS = =11, EBDF = 0 38 29 ns Expression1 33 MHz Min Max 40 MHz Unit Min Max
WE[0:3]/BE[0:3] Negated to A[0:31] Invalid -GPCM- Write Access, TRLX = 0, CSNT = '1. 27c CS Negated to A[0:31] Invalid -GPCM- Write Access, TRLX = 0, CSNT = '1, ACS = 10,ACS = =11, EBDF = 1 WE[0:3]/BE[0:3] Negated to A[0:31] Invalid -GPCM- Write Access, TRLX = 1, CSNT = '1. 27d CS Negated to A[0:31] Invalid -GPCM- Write Access, TRLX = 1, CSNT = '1, ACS = 10,ACS = =11, EBDF = 1 28 A[0:31], TSIZ[0:1], RD/WR, BURST, BDIP Valid to CLKOUT Rising Edge. (Slave Mode Setup Time) Slave Mode D[0:31] Valid to CLKOUT Rising Edge TS Valid to CLKOUT Rising Edge (Setup Time) CLKOUT Rising Edge to TS Valid (Hold Time). 9 2 11 9 ns 30 24 ns 5 4 ns
28a 29 30
7 7 2
ns ns ns
NOTES: 1. Expressions are approximate equations only. 2. This is the maximum frequency at which ENGCLK will meet output drive and rise/fall time specifications. 3. The timing for BR ouput is relevant when the MPC555 / MPC556 is selected to work with external bus arbiter. The timing for BG output is relevant when the MPC555 / MPC556 is selected to work with internal bus arbiter. 4. The setup times required for TA, TEA, and BI are relevant only when they are supplied by the external device (and not the memory controller). 5. The timing required for BR input is relevant when the MPC500 family microcontroller is selected to work with internal bus arbiter. The timing for BG is relevant when the MPC500 is selected to work with external bus arbiter. 6. The D[0:31] input timings 17 and 18 refer to the rising edge of the CLKOUT in which the TA input signal is asserted. 7. The timing 27 refers to CS when ACS = 00 and to WE[0:3] when CSNT = 0.
MOTOROLA G-22
CLKOUT
1 5 3 2
Figure G-2 External Clock Timing
MOTOROLA G-23
CLKOUT
8 9 7
OUTPUT SIGNALS
8a 9 7a
OUTPUT SIGNALS
8b
7b
OUTPUT SIGNALS
Figure G-3 Synchronous Output Signals Timing
MOTOROLA G-24
CLKOUT
12 10 11
TS, BB
12a 10a 11a
TA, BI
13 14
TEA
Figure G-4 Synchronous Active Pull-Up and Open Drain Outputs Signals Timing
MOTOROLA G-25
CLKOUT
15 16
TA, BI
15a 16a
TEA, KR, RETRY, CR
15b 16
BB, BG, BR
Figure G-5 Synchronous Input Signals Timing
MOTOROLA G-26
CLKOUT
15a 16
TA
17 18
D[0:31]
Figure G-6 Input Data Timing in Normal Case
MOTOROLA G-27
CLKOUT
10 11
TS
8
A[0:31]
19 20
CSx
22 23
OE
25
WE[0:3]
17
D[0:31]
18
Figure G-7 External Bus Read Timing (GPCM Controlled ACS = 00)
MOTOROLA G-28
CLKOUT
10 11
TS
8
A[0:31]
19a 20
CSx
21 23
OE
22 17
D[0:31]
18
Figure G-8 External Bus Read Timing (GPCM Controlled TRLX = 0 ACS = 10)
MOTOROLA G-29
CLKOUT
10 11
TS
8
A[0:31]
19b 19c 20
CSx
21a 23
OE
22 17
D[0:31]
18
Figure G-9 External Bus Read Timing (GPCM Controlled TRLX = 0 ACS = 11)
MOTOROLA G-30
CLKOUT
10 11
TS
8
A[0:31]
19a 20
CSx
24 24a 23
OE
19b 19c 17
D[0:31]
18
Figure G-10 External Bus Read Timing (GPCM Controlled TRLX = 1, ACS = 10, ACS = 11)
MOTOROLA G-31
CLKOUT
10
11 9
TS
A[0:31]
Figure G-11 Address Show Cycle Bus Timing
MOTOROLA G-32
CLKOUT
10
11
TS
8 27
A[0:31]
20
26b
CSx
WE[0:3]
26 8
D[0:31]
Figure G-12 Address and Data Show Cycle Bus Timing
MOTOROLA G-33
CLKOUT
10
11
TS
27
A[0:31]
19 20
CSx
22 25
26b
WE[0:3]
23
OE
26 8
D[0:31]
9
Figure G-13 External Bus Write Timing (GPCM Controlled TRLX = 0, CSNT = 0)
MOTOROLA G-34
CLKOUT
10
11
TS
27c 8 27a
A[0:31]
19 25b
20
CSx
22
25d 26c 26g
WE[0:3]
23 26a 26g
OE
8
25a 25c
D[0:31]
9
MOTOROLA G-35
CLKOUT
10
11
TS
27d 27b
A[0:31]
19 25b 20
CSx
22
25d 26i 26e
WE[0:3]
23 26h 26d 25a 25c 8 26b
OE
D[0:31]
9
MOTOROLA G-36
CLKOUT
29 30
TS
28
A[0:31], TSIZ[0:1],RD/WR, BURST
10a 11a
12a
TA, BI
13 14
TEA,
D[0:31]
10b 11b 9
RETRY
Figure G-16 External Master Read from Internal Registers Timing
MOTOROLA G-37
CLKOUT
30
29
TS
28
A[0:31], TSIZ[0:1], RD/WR, BURST
10a 11a
12a
TA, BI
13 14
TEA,
28a
D[0:31]
10b
18 11b
RETRY
Figure G-17 External Master Write to Internal Registers Timing
MOTOROLA G-38

G.12 Interrupt Timing Table G-12 Interrupt Timing
(TA = TL to TH) 33MHz Characteristic IRQx Valid to CLKOUT Rising Edge (Setup Time)1 IRQx Hold Time After CLKOUT1 IRQx Pulse Width Low IRQx Pulse Width High IRQx Edge to Edge Time 4*TC Expression Min 31 32 33 34 10 2 3 3 121 Max Min 10 2 3 3 100 Max ns ns ns ns ns 40MHz Unit
35
NOTES: 1. The timings 31 and 32 describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT.
CLKOUT
31 32
IRQx
Figure G-18 Interrupt Detection Timing for External Level Sensitive Lines
MOTOROLA G-39
CLKOUT
31
IRQx
35
35 33 34
Figure G-19 Interrupt Detection Timing for External Edge Sensitive Lines G.13 Debug Port Timing Table G-13 Debug Port timing
(TA = TL to TH) 33MHz Characteristic 36 37 38 39 40 41 42 DSCK Cycle Time DSCK Clock Pulse Width DSCK Rise and Fall Times DSDI Input Data Setup Time DSDI Data Hold Time DSCK low to DSDO Data Valid DSCK low to DSDO Invalid Expression Min 120 50 0 12 5 0 0 Max 3 18 Min 60 25 0 12 5 0 0 Max 3 18 ns ns ns ns ns ns ns 40MHz Unit
MOTOROLA G-40
36
37 37 36
DSCK
38
38
Figure G-20 Debug Port Clock Input Timing
MOTOROLA G-41
DSCK
39 40
DSDI
41 42
DSDO
Figure G-21 Debug Port Timings
MOTOROLA G-42

G.14 Reset Timing Table G-14 RESET Timing
(TA = TL to TH) 33MHz Characteristic 43 44 45 46 47 48 49 49a 50 51 CLKOUT to HRESET High Impedance CLKOUT to SRESET High Impedance RSTCONF Pulse Width Configuration Data to HRESET Rising Edge Setup Time Configuration Data to RSTCONF Rising Edge Set Up Time Configuration Data Hold Time After RSTCONF Negation Configuration Data Hold Time After HRESET Negation RSTCONF Hold Time After HRESET Negation1 HRESET and RSTCONF Asserted to Data Out Drive RSTCONF Negated to Data Out High Impedance. CLKOUT of Last Rising Edge Before Chip Tristates HRESET to Data Out High Impedance. DSDI, DSCK Set Up DSDI, DSCK hold time SRESET Negated to CLKOUT Rising Edge for DSDI and DSCK Sample HRESET, SRESET, PORESET Pulse Width 2 8*TC 3*TC 17*TC 15*TC + TCC 15*TC + TCC 515 463 463 0 0 60 25 25 Expression Min Max 20 20 425 382 382 0 0 50 25 25 Min Max 20 20 ns ns ns ns ns ns ns ns ns ns 40MHz Unit
52 53 54 55 55a
25 91 0 243 100
25 75 0 200 100
ns ns ns ns ns
NOTES: 1. Weak pullups and pulldowns used for Reset timing will comply with the 130-A mode select current outlined in Table G-4.The simplest way to insure meeting this requirement in systems that require the use of the TEXP function, is to connect RSTCONF/TEXP to SRESET. The maximum rise time of HRESET should be less than six clock cycles. 2. HRESET, SRESET and PORESET have a glitch detector to ensure that spikes less than 20 ns are rejected. The internal HRESET, SRESET and PORESET will assert only if these signals are asserted for more than 100 ns.
MOTOROLA G-43
HRESET
45 49a RSTCONF
49 46 48
D[0:31] (IN)
47
Figure G-22 Reset Timing Configuration from Data Bus
MOTOROLA G-44
CLKOUT
43 55 HRESET
RSTCONF
51 50 52
D[0:31] (OUT) (Weak)
Figure G-23 Reset Timing Data Bus Weak Drive During Configuration
MOTOROLA G-45
CLKOUT
44 55
SRESET
53
53
54
54
DSCK, DSDI
Figure G-24 Reset Timing Debug Port Configuration
MOTOROLA G-46

G.15 IEEE 1149.1 Electrical Characteristics Table G-15 JTAG Timing1
(TA = TL to TH) 33 MHz Characteristic 56 57 58 59 60 TCK Cycle Time TCK Clock Pulse Width Measured at VDD/2 TCK Rise and Fall Times TMS, TDI Data Setup Time TMS, TDI Data Hold Time TCK Low to TDO Data Valid TCK Low to TDO Data Invalid TCK Low to TDO High Impedance TRST Assert Time TRST Setup Time to TCK Low TCK Falling Edge to Output Valid TCK Falling Edge to Output Valid out of High Impedance TCK Falling Edge to Output High Impedance Boundary Scan Input Valid to TCK Rising Edge TCK Rising Edge to Boundary Scan Input Invalid Expression Min 100 40 0 5 25 0 100 40 50 50 Max 10 20 20 50 50 50 Min 100 40 0 5 25 0 100 40 50 50 Max 10 20 20 50 50 50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 40 MHz Unit
61 62 63 64 65 66 67 68 69 70
NOTES: 1. JTAG timing is only tested at 10 MHz
MOTOROLA G-47
TCK
56
57 57 56
58
Figure G-25 JTAG Test Clock Input Timing
MOTOROLA G-48
TCK
59 60
TMS, TDI
61 63 62
TDO
Figure G-26 JTAG Test Access Port Timing Diagram
MOTOROLA G-49
TCK
65
TRST
64
Figure G-27 JTAG TRST Timing Diagram
MOTOROLA G-50
TCK
66 68
OUTPUT SIGNALS
67
OUTPUT SIGNALS
70 69
OUTPUT SIGNALS
Figure G-28 Boundary Scan (JTAG) Timing Diagram
MOTOROLA G-51

G.16 QADC64 Electrical Characteristics
Table G-16 QADC64 Conversion Characteristics (Operating)

(TA = TL to TH) Num 97 98 Parameter QADC Clock (QCLK) Frequency1 Conversion Cycles2 Conversion Time3 99 FQCLK = 2.0 MHz1,4 Min = CCW/IST = 0b00 Max = CCW/IST = 0b11 Stop Mode Recovery Time Resolution5 Absolute (Total Unadjusted) Error6, 7, 8, 9 FQCLK = 2.0 MHz3, 2 Clock Input Sample Time DC Disruptive Input Injection Current10, 11, 12, 13, 14 Current Coupling Ratio17 PQA PQB Incremental Error Due to Injection Current 105 All Channels Have Same 10 K < Rs < 100 K Channel Under Test has Rs = 10 K, IINJ = +3 mA 106 107 Source Impedance At Input 18 Incremental Capacitance During Sampling 19 RS CSAMP EINJ +1.0 +1.0 100 5 Counts TCONV 7.0 14.0 Symbol FQCLK CC Min 0.5 14 Max 3.0 28 Units MHz QCLK cycles s
100 101 102
TSR AE IINJ15 IINJ16 K
5 -2.0 -3 -1
10 2.0 3 1 8x10-5 8x10-5
s mV Counts mA
103
104
K pF
NOTES: 1. Conversion characteristics vary with FQCLK rate. Reduced conversion accuracy occurs at max FQCLK rate. 2. The number of conversion cycles is dependent on the IST bits in the CCW register. 3. Assumes that fSYS = 40 MHz 4. Assumes FQCLK = 2.00 MHz, with clock prescaler values of: QACR0: PSH =0b01111, PSA = 0b0, PSL = 0b011) CCW: BYP = 0b0 5. At VRH VRL = 5.12 V, one count = 5 mV (at 5.0 V, one count = 4.8875 mV). 6. Accuracy tested and guaranteed at VRH VRL = 5.0 V 0.5 V 7. This parameter is periodically sampled rather than 100% tested. 8. Absolute error includes 1/2 count (~2.5 mV) of inherent quantization error and circuit (differential, integral, and offset) error. Characteristic assumes that adequate low-pass filtering is present on analog input pins capacitive filter with 0.01 F to 0.1 F capacitor between analog input and analog ground, typical source isolation impedance of 10 Kbytes. 9. Input signals with large slew rates or high frequency noise components cannot be converted accurately. These signals may affect the conversion accuracy of other channels. 10. Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater than VRH and 0x000 for values less than VRL. This assumes that VRH <= VDDA and VRL <= VSSA due to the presence of the sample amplifier. Other channels are not affected by non-disruptive conditions. 11. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage.
MOTOROLA G-52

12. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using VPOSCLAMP = (the lower of VDDA or VDDH) + 0.3 V and VNEGCLAMP = -0.3 V, then use the larger of the calculated values. The diode drop voltage is a function of current and varies approximately 0.4 to 0.8 volts over temperature 13. This parameter is periodically sampled rather 100% tested. 14. Derate linearly to 0.3 mA if VDDH - VDDA = 1 volt. This characteristic is preliminary and may change after further characterization. 15. Condition applies to two adjacent pins. 16. Condition applies to all analog channels. 17. Current coupling ratio, K, is defined as the ratio of the output current, Iout, measured on the pin under test to the injection current, Iinj, when both adjacent pins are overstressed with the specified injection current. K = Iout/ Iinj The input voltage error on the channel under test is calculated as Verr = Iinj * K * RS 18. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction leakage into the pin and on leakage due to charge-sharing with internal capacitance. Error from junction leakage is a function of external source impedance and input leakage current. In the following expression, expected error in result value due to junction leakage is expressed in voltage (Verrj): Verrj = RS * IOFF where IOFF is a function of operating temperature. Charge-sharing leakage is a function of input source impedance, conversion rate, change in voltage between successive conversions, and the size of the filtering capacitor used. Error levels are best determined empirically. In general, continuous conversion of the same channel may not be compatible with high source impedance 19. For a maximum sampling error of the input voltage <= 1LSB, then the external filter capacitor, Cf >= 1024 * CSAMP. The value of CSAMP in the new design may be reduced.
G.17 QSMCM Electrical Characteristics Table G-17 QSPI Timing

(TA = TL to TH, 50 pF load on all QSPI pins except as noted) Name 108 Function Operating Frequency1 Master Slave Cycle Time Master Slave Enable Lead Time Master Slave Enable Lag Time Master Slave Clock (SCK) High or Low Time Master Slave3 Sequential Transfer Delay Master Slave (Does Not Require Deselect) Data Setup Time (Inputs) Master Slave Symbol fop Min DC DC 4*TC 4*TC 2*TC 2*TC 2*TC 2*TC 60 2*TC n 17*TC 13*TC 30 20 Max FSYS/4 FSYS/4 ns tqcyc 510*TC2 ns tlead 128*TC ns tlag SCK/2 ns tsw 255*TC ns ttd 8192*TC ns tsu Unit Hz
109
110
111
112
113
114
MOTOROLA G-53

Table G-17 QSPI Timing (Continued)
(TA = TL to TH, 50 pF load on all QSPI pins except as noted) Name 115 116 117 118 Function Data Hold Time (Inputs) Master Slave Slave Access Time Slave MISO Disable Time Data Valid (After SCK Edge) Master Slave Data Hold Time (Outputs) Master Slave Rise Time Input 120 Output up to 50 pF Load, SLRC Bit of PDMCR = 0 up to 200 pF Load, SLRC Bit of PDMCR = 0 up to 50 pF, SLRC Bit of PDMCR = 1 Fall Time Input 121 Output up to 50 pF Load, SLRC Bit of PDMCR = 0 up to 200 pF Load, SLRC Bit of PDMCR = 0 up to 50 pF, SLRC Bit of PDMCR = 1 tfi tfo 10 20 2 50 100 25 ns ns ns 1 s tri tro 10 20 2 50 100 25 ns ns ns 1 s Symbol thi ta tdis tv Min 0 20 0 0 Max TC 2*TC 50 50 Unit ns ns ns ns
119
tho
ns
NOTES: 1. All AC timing is tested to the 5-V levels outlined in Table G-4. 2. TC is defined to be the clock period of fSYS (IMB Clock). 3. For high time, n = External SCK rise time; for low time, n = External SCK fall time.
MOTOROLA G-54
111
PCS[3:0] OUTPUT
110
121
SCK CPOL = 0 OUTPUT
120
113
112
SCK CPOL = 1 OUTPUT
109 120
114 115
111
121
MISO INPUT
MSB IN
DATA
LSB IN
MSB IN
119
MOSI OUTPUT PD MSB OUT DATA
118
LSB OUT PORT DATA MSB OUT
121
120
QSPI MAST CPHA0
Figure G-29 QSPI Timing Master, CPHA = 0
111
PCS[3:0] OUTPUT
110
121 109
SCK CPOL = 0 OUTPUT
120
113
112
SCK CPOL = 1 OUTPUT
109
115
112
MISO INPUT MSB IN
120
DATA
121 114
LSB IN MSB
119
MOSI OUTPUT PORT DATA MSB OUT DATA
118
LSB OUT PORT DATA MSB
121
120
QSPI MAST CPHA1
Figure G-30 QSPI Timing Master, CPHA = 1
MOTOROLA G-55
111
SS INPUT
110
121
SCK CPOL = 0 INPUT
120
113
112
SCK CPOL = 1 INPUT
109
111 116 120 119

DATA
121 118
LSB OUT
119 117
PD MSB OUT
MISO OUTPUT
MSB OUT
114
MOSI INPUT MSB IN
115
DATA LSB IN
121
MSB IN
QSPI SLV CPHA0
Figure G-31 QSPI Timing Slave, CPHA = 0
SS INPUT
109
SCK CPOL = 0 INPUT
121 111 120
113
110
SCK CPOL = 1 INPUT
112 120 119

SLAVE LSB OUT
111
118 116
MISO OUTPUT PD MSB OUT
121 118
DATA
117
PD
114
MOSI INPUT MSB IN
115
DATA
121
LSB IN
QSPI SLV CPHA1
Figure G-32 QSPI Timing Slave, CPHA = 1
MOTOROLA G-56

G.18 GPIO Electrical Characteristics Table G-18 GPIO Timing1
(TA = TL to TH)
Num Rise Time Input 122 Output2 (SLR0 of PDMCR = 0), 50 pF to 200 pF Load Output2 (SLR0 of PDMCR = 0), up to 20 nF Load3 Output (SLR0 of PDMCR = 1), up to 50 pF Load Fall Time Input 123 Output2(SLR0 of PDMCR = 0), 50 pF to 200 pF Load Output2 (SLR0 of PDMCR = 0), up to 20 nF Load3 Output (SLR0 of PDMCR = 1), up to 50 pF Load Rating Symbol tri Min Max 1 Unit
s ns ns ns s
tro
90 2000 3
600 7500 25
tfi
tfo
90 2000 3
600 7500 25
ns ns ns
NOTES: 1. GPIO applies to all pins used as GPIO: SGPIOA[8:31], SQPIOD[0:31], SGPIOC[0:7], QGPIO[0:6], QGPO[1:2], MPIO[0:15], A_PQA[0:7], B_PQA[0:7], A_PQB[0:7] (inputs only), B_PQB[0:7] (inputs only). 2. This parameter is tested during initial characterization and is not tested in production. 3. Care should be taken to insure that the total power dissipation of the device remain below the absolute maximum rating under this condition. See Table G-1. With a capacitive load > 20 nF (up to 100 nF maximum), the user must insure that the pin is always configured as an output and set to slow slew rate mode (SLR0 of PDMCR = 0). Do not change SLR0 of PDMCR to a 1 under these conditions.
G.19 TPU3 Electrical Characteristics Table G-19 TPU3 Timing

(TA = TL to TH)
Num Rating Slew Rate of TPU Output Channel Valid1,2 (SLR0 of PDMCR = 0, 50 pF to 200 pF Load) (SLR0 of PDMCR = 0, up to 20 nF Load)3 (SLR0 of PDMCR = 1, up to 50 pF Load) CLKOUT High to TPU Output Channel Hold TPU Input Channel Pulse Width4 Symbol tCHTOV Min 92 2000 3 0 4 Max 650 7550 25 15 ns tcyc Unit ns
124
125 126
tCHTOH tTIPW
NOTES: 1. AC timing is shown with respect to 10% VDDH and 90% VDDH levels. Total slew rate from 0 to VDDH will be larger. 2. Timing not valid for external T2CLK input. 3. Care should be taken to insure that the total power dissipation of the device remain below the absolute maximum rating under this condition. See Table G-1. With a capacitive load > 20 nF, the user must insure that the pin is always configured as an output. 4. tcyc is defined as the IMB Clock Period.
MOTOROLA G-57
CLKOUT
124
TPU OUTPUT
125
TPU INPUT
126
Figure G-33 TPU3 Timing G.20 TouCAN Electrical Characteristics Table G-20 TouCAN Timing1
(TA = TL to TH) Num 127 128 Rating CNTX0 (Delay from ICLOCK) CNRX0 (Set-Up to ICLOCK Rise) Rise Time Input 129 Output Up to 50 pF Load, SLRC Bit of PDMCR = 0 Up to 200 pF Load, SLRC Bit of PDMCR = 0 Up to 50 pF Load, SLRC Bit of PDMCR = 1 Fall Time Input 130 Output Up to 50 pF Load, SLRC Bit of PDMCR = 0 Up to 200 pF Load, SLRC bit of PDMCR = 0 Up to 50 pF Load, SLRC Bit of PDMCR = 1 Serial Pins tfi tfo 10 20 2 tf 50 100 25 1 ns ns ns Mhz 1 s tri tro 10 20 2 50 100 25 ns ns ns 1 s Symbol tCNTX0 tCNRX0 Min 19 0 Max Unit ns ns
NOTES: 1. AC timing is shown is tested to the 5-V levels outlined in Table G-4.
MOTOROLA G-58

G.21 MIOS Timing Characteristics All MIOS output pins are slew rate controlled. Slew rate control circuitry adds 90 ns as minimum to the output timing and 650 ns as a maximum. This slew rate is from 10% VDDH to 90% VDDH, an additional 100 ns should be added for total 0 to VDDH slew rate. Table G-21 MCPSM Timing Characteristics
Characteristic MCPSM Enable to vs_pclk Pulse1 Symbol tCPSMC Delay (MCPSMSCR_PSL[3:0]) -12 Unit IMB Clock Cycles
NOTES: 1. The MCPSM clock prescaler value (MCPSMSCR_PSL[3:0]) should be written to the MCPSMSCR (MCPSM status/control register) before rewriting the MCPSMSCR to set the enable bit (MCPSMSCR_PREN). If this is not done the prescaler will start with the old value in the MCPSMSCR_PSL[3:0] before reloading the new value into the counter. vs_pclk is the MIOS prescaler clock which is distributed to all the counter (e.g., MPWMSM and MMCSM) submodules. 2. After reset MCPSMSCR_PSL[3:0] is set to 0b0000.
tCPSMC fSYS Prescaler enable bit (PREN)
MIOB vs_pclk
Note 1: fSYS is the internal system clock for the IMB3 bus. Note 2: The numbers associated with the fSYS ticks refer to the IMB3 internal state. Note 3: vs_pclk is the MIOS prescaler clock which is distributed around the MIOS to counter modules such as the MMCSM and MPWMSM.
Figure G-34 MCPSM Enable to vs_pclk Pulse Timing Diagram
MOTOROLA G-59

G.21.1 MPWMSM Timing Characteristics
.
Table G-22 MPWMSM Timing Characteristics

(All delays are in IMB clock periods) Characteristic PWMSM Output Resolution PWM Output Pulse3 mpwmi Input Pin to MPWMSCR_PIN Status Set CPSM Enable To Output Set4 Symbol tPWMR tPWMO tPIN tPWMP Min 1 2.0 1 Max 2.0 2 2
(MPWMPERR MPWMPULR+ 1) * (256 MPWMSCR_CP) * MCPSMSCR_PSL +1 (MPWMPERR MPWMPULR) * (256 MPWMSCR_CP) * MCPSMSCR_PSL +3 + (255 MPWMSCR_CP) * MCPSMSCR_PSL 6 tPWME(MIN) + MCPSMSCR_PSL 1 6 (256 MPWMSCR_CP) * MCPSMSCR_PSL 1 6
MPWMSM Enable to Output Set (MIN)5 MPWMSM Enable to Output Set (MAX)5 Interrupt Flag to Output Pin Reset (Period Start)7
tPWME tPWME tFLGP
NOTES: 1. Minimum output resolution depends on MPWMSM and MCPSM prescaler settings. 2. Maximum resolution is obtained by setting CPSMPSL[3:0] =0x2 and MPWMSCR_CP[7:0] =0xFF. 3. Excluding the case where the output is always 0. 4. With MPWMSM enabled before enabling the MCPSM. Please also see Note *1 on the MCPSM timing information. 5. The exact timing from mpwmsm enable to the pin being set depends on the timing of the register write and the MCPSM vs_pclk. 6. When MCPSMSCR_PSL = 0x0000, this gives a prescale value of 16 and it is 16 which should be used in these calculations. When MCPSMSCR_PSL = 0x0001, the CPSM is inactive. 7. Note: the interrupt is set before the output pin is reset (Signifying the start of a new period).
tPWMO min
fSYS
MPWMO output pin
Figure G-35 MPWMSM Minimum Output Pulse Example Timing Diagram
MOTOROLA G-60
tPWMP
fSYS
Prescaler enable bit (PREN)
MIOB vs_pclk
MPWMO output pin
Note: FSYS is the internal IMB clock for the IMB3 bus.
Figure G-36 MCPSM Enable to MPWMO Output Pin Rising Edge Timing Diagram
tPWME
fSYS
MPWMSCR enable bit
MPWMO output pin
Figure G-37 MPWMSM Enable to MPWMO Output Pin Rising Edge Timing Diagram
MOTOROLA G-61

tFLGP
MPSMO pin output MPWMSM interrupt flag
Figure G-38 MPWMSM Interrupt Flag to MPWMO Output Pin Falling Edge Timing Diagram G.21.2 MMCSM Timing Characteristics Table G-23 MMCSM Timing Characteristics
(All delays are in IMB clock periods.) Characteristic MMCSM Input Pin Period MMCSM Pin Low Time MMCSM Pin High Time Clock Pin to Counter Bus Increment Load Pin to New Counter Bus Value Clock Pin to PINC Delay Load Pin to PINL Delay Counter Bus Resolution Counter Bus Overflow Reload to Interrupt Flag MCPSM Enable to Counter Bus Increment MMCSM Enable to Counter Bus Increment (MIN)4 MMCSM Enable to Counter Bus Increment (MAX)4 Symbol tPPER tPLO tPHI tPCCB tPLCB tPINC tPINL tCBR tCBFLG tMCMP tMCME tMCME Min 4 2 2 1 1 1 1 1 1 (256 MMCSMSCR_CP) * MCPSMSCR_PSL + 23 4 + MCPSMSCR_PSL* (255 MMCSMSCR_CP)3 4 + MCPSMSCR_PSL * (255 MMCSMSCR_CP) + (MCPSMSCR_PSL 1)3 Max 2 2 2 2 22
NOTES: 1. Minimum output resolution depends on MMCSM and MCPSM prescaler settings. 2. Maximum resolution is obtained by setting CPSMPSL[3:0] = 0x2 and MMCSMSCR_CP[7:0] = 0xFF. 3. When MCPSMSCR_PSL = 0x0000, this gives a prescale value of 16 and it is 16 which should be used in these calculations. When MCPSMSCR_PSL = 0x0001, the CPSM is inactive. 4. The exact timing from MMCSM enable to the pin being set depends on the timing of the MMCSMSCR register write and the MCPSM vs_pclk. The MMCSM enable is taken to mean the MMCSMSCR_CLS[1:0] being written to 2b11.
fSYS
MOTOROLA G-62
tPPER min
tPLO min
tPHI min
fSYS
MMCSM pin
Figure G-39 MMCSM Minimum Input Pin (Either Load or Clock) Timing Diagram
tPCCB
fSYS
MMCSM clock pin A
Counter bus[15:0]
A+1
Note: FSYS is the internal IMB clock for the IMB3 bus.
Figure G-40 MMCSM Clock Pin to Counter Bus Increment Timing Diagram
tPLCB
fSYS
MMCSM load pin A
Counter bus[15:0]
Figure G-41 MMCSM Load Pin to Counter Bus Reload Timing Diagram
MOTOROLA G-63
tCBFLG
MMCSM interrupt flag Counter bus[15:0] MMCSMML[15:0] FFFE 5AFE FFFF 5AFE
Figure G-42 MMCSM Counter Bus Reload to Interrupt Flag Setting Timing Diagram
tMCME 3 4 1 11 A A+1 ELECTRICAL CHARACTERISTICS
fSYS
fSYS
MMCSMSCR_CLS[1:0]
2 00
Counter bus[15:0]
Figure G-43 MMCSM Prescaler Clock Select to Counter Bus Increment Timing Diagram
MOTOROLA G-64

G.21.3 MDASM Timing Characteristics Table G-24 MDASM Timing Characteristics
(All delays are in IMB clock periods.) Characteristic Symbol Min Max
Input Modes: (IPWM, IPM, IC, DIS) MDASM Input Pin Period MDASM Pin Low Time MDASM Pin High Time Input Capture Resolution Input Pin to Counter Bus Capture Delay tPPER tPLO tPHI tCAPR tPCAP tPFLG tPIN tCBR Output Modes: (OC, OPWM) Output Pulse Width3 Compare Resolution Counter Bus to Pin Change Counter Bus to Interrupt Flag Set. tPULW tCOMR tCBP tCBFLG 2 3 3 22 4 2 2 1 2 1 2 31 3 2 22
Input Pin to Interrupt Flag Delay Input Pin to PIN Delay Counter Bus Resolution
NOTES: 1. If the counter bus capture occurs when the counter bus is changing then the capture is delayed one cycle. In situations where the counter bus is stable when the input capture occurs the tPCAP has a maximum delay of 2 cycles. (the 1 cycle uncertainty is due to the synchronizer). 2. Maximum resolution is obtained by setting CPSMPSL[3:0] = 0x2 and MDASMSCR_CP[7:0] = 0xFF. 3. Maximum output resolution and pulse width depends on counter (e.g., MMCSM) and MCPSM prescaler settings.
tPPER min
tPLO min
tPHI min
fSYS
MDAI input pin
fSYS is the internal IMB clock for the IMB3 bus.
Figure G-44 MDASM Minimum Input Pin Timing Diagram
MOTOROLA G-65
tPCAP
fSYS
MDAI input pin XXXX
MDASMAR[15:0]
Counter bus[15:0]
Figure G-45 MDASM Input Pin to Counter Bus Capture Timing Diagram
tPFLG
fSYS
MDAI input pin
MDASM interrupt flag
Figure G-46 MDASM Input Pin to MDASM Interrupt Flag Timing Diagram
tPULW min
fSYS
MDAO output pin
Figure G-47 MDASM Minimum Output Pulse Width Timing Diagram
MOTOROLA G-66
tCBP
fSYS
MDAO output pin Counter bus[15:0] MDASMAR[15:0] 5AFC 5AFE 5AFD 5AFE
Figure G-48 Counter Bus to MDASM Output Pin Change Timing Diagram
tCBFLG
fSYS
MDASM interrupt flag Counter bus[15:0] MDASMAR[15:0] 5AFC 5AFE 5AFD 5AFE
Figure G-49 Counter Bus to MDASM Interrupt Flag Setting Timing Diagram
MOTOROLA G-67

G.21.4 MPIOSM Timing Characteristics Table G-25 MPIOSM Timing Characteristics
(All delays are in IMB clock periods.) Characteristic Symbol Input Mode MPIOSM Input Pin Period MPIOSM Pin Low Time MPIOSM Pin High Time Input Pin to MPIOSM_DR Delay tPPER tPLO tPHI tPDR Output Mode 1 1 1 0 1 Min Max
Output Pulse Width2
tPULW
NOTES: 1. The minimum input pin period, pin low and pin high times depend on the rate at which the MPIOSM_DR register is polled. 2. The minimum output pulse width depends on how quickly the CPU updates the value inside the MIOPSM_DR register. The MPC555 RCPU core takes six clock cycles to access the MIOPSM_DR register, therefore the minimum output pulse will be 12 IMB clocks.
tPDR
fSYS
MPIOSM input pins FFA5 005A
MPIOSM_DR
FFA5
005A
Figure G-50 MPIOSM Input Pin to MPIOSM_DR (Data Register) Timing Diagram
MOTOROLA G-68
APPENDIX H FLASH ELECTRICAL CHARACTERISTICS FOR ALL J76N MASK SETS AND 0K02A AND 1K02A ONLY
H.1 Electrical Characteristics Table H-1 Program and Erase Characteristics
(VDDF = 3.3 V 0.3 V, VPP= 4.75 V to 5.25 V, TA = TL to TH) Value
Symbol EPULSE TERASE PPULSE(4.75 Vpp) PPULSE(5.0 Vpp)
Meaning Minimum Number of Erase Pulses Erase Pulse Time Number of Program Pulses @VPP = 4.75 Number of Program Pulses @VPP = 5.00 1 0.9 21.2 1 1 1 0.98 1 1 1 0.98 Typical 1 1 12001 3004 1257 25.6 1 1 1 18 1 1 1 18 Maximum 1 1.1 35002,3,5 10005 5005 32.0 38 38 38 1.18 38 38 38 1.18
Units
S Pulses Pulses Pulses S Pulses Pulses Pulses S Pulses Pulses Pulses S
PPULSE (5.25 Vpp) Number of Program Pulses6 @V = 5.25 PP TPROG CPULSE(4.75 Vpp) CPULSE(5.0 Vpp) CPULSE(5.25 Vpp) TCLEAR SPULSE(4.75 Vpp) SPULSE(5.0 Vpp) SPULSE(5.25 Vpp) TSET Program Pulse Time Number of CENSOR Clear Pulses @VPP = 4.75 Number of CENSOR Clear Pulses @VPP = 5.00 Number of CENSOR Clear Pulses @VPP = 5.25 CENSOR Clear Pulse Time Number of CENSOR Set Pulses @VPP = 4.75 Number of CENSOR Set Pulses @VPP = 5.00 Number of CENSOR Set Pulses @VPP = 5.25 CENSOR Set Pulse Time
NOTES: 1. The typical number of pulses at VPP = 4.75 V and TA = 25C. 2. The worst case programming time occurs at VPP = 4.75 V and TA = -40 C. 3. This value is based on initial device characterization and is not tested in production. 4. The typical number of pulses is at VPP = 5.00 v and TA = 25C. 5. Assumes pulse width = 25.6 s. 6. The best case (fastest) programming time of < 50 pulses is at VPP = 5.25 V and TA = 125C. 7. The typical number of pulses is at VPP = 5.25 V and TA = 25C. 8. After characterization this value may be improved.
MPC555 / MPC556FLASH ELECTRICAL CHARACTERISTICS FOR ALL J76N MASK SETS AND 0K02A AND 1K02A ONLY USERS MANUAL MOTOROLA For More Information On This Product, Go to:15 October 2000 Rev. www.freescale.com H-1
Program Time vs VPP & Temperature

10000 Estimated # Pulses Required to Program (25 S Pulse Width)
2325
1000
1180 438
447
270 117
140
100
81 46
10
1 4.7 4.8 4.9 5 5.1 5.2 5.3
VPP (V)
Temp = -40C Temp = 25C Temp = 150C
Figure H-1 Typical Program Time vs. VPP and Temperature (for CDR1 Target Process)
Table H-2 CMF AC and DC Power Supply Characteristics

Symbol VDDF IDDF Operating Voltage Read, Program or Erase Operating Current at 40.0MHz, VDDF = 3.3 V for a 256K-byte Module Read, Program or Erase Operation Disabled External Program or Erase voltage Read Program or Erase External Program and Erase Current1 Read, VPP = 5 V Program, VPP = 5.25 V Erase, VPP = 5.25 V Meaning Min. Value 3.0 Max Value 3.6 V Unit V
VDDF -0.35 4.75
22 5 5.5 5.25 <1001 301 301
mA
VPP
IDDPP
A1 mA1 mA1
NOTES: 1. Average current is less than 30 mA when programming both modules simultaneously.

H.1.1 Flash Module Life
Table H-3 Flash Module Life

Symbol P/E Cycles1 Retention Meaning Maximum Number of Program/ Erase cycles2 to Guarantee Data Retention Data Retention at Average Operating Temperature of 85 C Value 1003,4 Minimum 10 years
NOTES: 1. Target failure rate at specified number of program/erase cycles of 2ppm pending characterization of production silicon. 2. A program/erase cycle is defined as switching the bits from 1 0 1. 3. Reprogramming of a CMF array block prior to erase is not required. 4. Number of program/erase cycles to be adjusted pending characterization of production silicon.
H.2 Programming and Erase Algorithm Table H-4 CMF Programming Algorithm (v5)
No. of Pulses (Maximum) 3500 Pulse Width 25.6 s NVR X PAWs 000 GDB X PAWs Mode Normal Description
Table H-5 CMF Erase Algorithm (v5)

No. of Pulses (Maximum) 10 Pulse Width 1s NVR X PAWs 111 GDB X PAWs Mode Mode 7P Description Positive drain ramp

INDEX
A A(0 31), 9-4 ACKERR 16-31 Acknowledge error (ACKERR) 16-31 Address -mark wakeup 14-58 space 13-7 address type (AT0-AT3), 9-37 ALE 21-54 ALEE 21-56 alignment exception, 3-46 ALUBFU 3-5 AN 13-3, 13-5 Analog front-end multiplexer 13-14 input multiplexed 13-5 port A 13-3 port B 13-4 section contents 13-1 submodule block diagram 13-12 supply pins 13-5 arbitration, 9-30 AT(0 3), 9-4 atomic update primitives, 3-42 atomic, 9-31 B BAR 3-52 Base ID mask bits 16-30 Baud clock 14-51 BB, 9-7 BDIP, 9-5 BE bit 3-21 Beginning of queue 2 (BQ2) 13-39 BG, 9-7 BI, 9-6 Binary divider 13-25 -weighted capacitors 13-14 Bit stuff error (STUFFERR) 16-31 BITERR 16-31 BITS 14-17 Bits per transfer enable (BITSE) 14-23 field (BITS) 14-17 BITSE 14-23, 14-38
Bit-time 14-50 BKPT (TPU asserted) 17-14 BLC 17-13 BOFFINT 16-31 Boundary conditions 13-17 Boundary scan cells 22-1 descriptor language 22-7 register 22-1 BPU 3-5 BQ2 13-17, 13-39 BR, 9-7 Branch prediction 3-5 processing unit 3-5 trace enable 3-21 Branch latch control (BLC) 17-13 Branch processing unit 3-5 Break frame 14-51 Breakpoint asserted flag (BKPT) 17-14 flag (PCBK) 17-14 Breakpoint counter A value and control register 21-52 Breakpoint counter B value and control register 21-53 BRKNOMSK 21-51 BSC 22-1 BSR 22-1 burst indicator (BURST), 9-36 burst inhibit (BI), 9-39 burst read cycle (illustration), 9-18 burst transfer, 9-15 burst write cycle (illustration), 9-23 BURST, 9-4 Bus monitor 6-12 off interrupt (BOFFINT) 16-31 bus busy (BB), 9-32 bus exception control cycles, 9-43 bus grant (BG), 9-32 bus interface bus control signals, 9-2 bus operation address transfer phase related signals, 9-35 arbitration phase, 9-30 basic transfer protocol, 9-8 burst mechanism, 9-16 burst transfer, 9-15 bus exception control cycles, 9-43 single beat transfer single beat read flow, 9-8
INDEX Rev. 15 October 2000
MOTOROLA Index-1

single beat write flow, 9-8, 9-11 single beat transfer, 9-8 storage reservation, 9-40 termination signals, 9-38 bus operations, 9-7 bus transfer signals, 9-1 features, 9-1 signal descriptions, 9-3 bus request (BR), 9-31 bus signals (illustration), 9-3 BUSY 16-5, 16-15 BYP 13-13, 13-47 Bypass mode 13-13 BYTES field 3-18 C C bit 3-14 CA bit 3-18 cache control instructions, 3-42 CAN2.0B system 16-3 CANCTRL0 16-25 CANCTRL1 16-26 CANCTRL2 16-28 CANICR 16-24 Carry 3-18 CCL 17-13 CCW 13-1, 13-46 CF1 13-41 CF2 13-41 CFSR 17-15 CGBMSK 21-50 CH 17-15, 17-18, 17-19 CHAN 13-47 CHANNEL 17-16 Channel assignments multiplexed 13-48 nonmultiplexed 13-48 conditions latch (CCL) 17-13 interrupt enable /disable field (CH) 17-15 request level (CIRL) 17-15 status (CH) 17-19 invalid 13-47 number (CHAN) 13-47 orthogonality 17-3 priority registers 17-18 register breakpoint flag (CHBK) 17-14 reserved 13-47 CHBK 17-14 CHBMSK 21-50 checkstop state, 3-45 CHSTP bit 21-54 CHSTPE 21-55 CIE1 13-37 CIE2 13-39 CIER 17-15, 17-19 CIRL 17-15 CISR 17-8, 17-19 class, instruction, 3-38 CLKOUT to TA, BI assertion (when driven by the Memory Controller) G-18 CLKOUT, 9-7 CLKS 17-13 Clock block diagram 13-26 frequency 13-26 generation 13-24 phase (CPHA) 14-17 polarity (CPOL) 14-17 CMPACMPD 21-45 CMPECMPF 21-46 CMPGCMPH 21-46 CNRX/TX pins 16-2 CNTC 21-52 CNTV 21-52 Code 16-5 Coherency 13-6, 13-22, 17-4 COMM D-18 Command RAM 14-22 word pointer (CWP) 13-42 Comparator 13-14 Comparator AD value registers 21-45 Comparator EF value registers 21-46 Comparator GH value registers 21-46 Compare instructions 3-17 Compare size 21-50 Compare type 21-48, 21-50 Completed queue pointer (CPTQP) 14-21 Condition register 3-15, 3-17 CONT 14-23 contention, 9-36 Continue (CONT) 14-23 Continuous transfer mode 14-15 Control registers 1 (QACR1) 13-36 2 (QACR2) 13-38 controlling termination of a bus cycle for a bus error, 9-43 Conversion command word table (CCW) 13-1, 13-14 cycle times 13-12 stages 13-45 Count register 3-19 COUNTA 21-52 COUNTB 21-53 CPHA 14-17, 14-34 CPOL 14-17, 14-34 CPR 17-18 CPTQP 14-21, 14-24 CR 3-5, 3-15, 3-19 and compare instructions 3-17 CR, 9-5 CR0 field 3-16 CR1 field 3-16 CRCERR 16-31 CRWE 21-50 CRWF 21-50
INDEX Rev. 15 October 2000 For More Information On This Product, Go to: www.freescale.com
MOTOROLA Index-2

CSG 21-50 CSH 21-50 CTA 21-48 CTB 21-48 CTC 21-48 CTD 21-48 CTE 21-50 CTF 21-50 CTG 21-50 CTH 21-50 CTR 3-5 CWP 13-42 Cyclic redundancy check error (CRCERR) 16-31 D D(0 31), 9-6 D0 20-3 DAC 13-1 DAE/source instruction service register 3-22 DAR 3-22, 3-46, 3-51, 3-52 DAR, 3-46, 3-51 Data field for RX/TX frames (TOUCAN) 16-5 frame 14-50 Data address register 3-22 Data space only 20-3 data storage interrupt, 3-45 DCNR 17-19 DDRQA 13-33, 13-35 DDRQS 14-9, 14-33, 14-37 Debug enable register 21-55 debug mode disable, 3-45 DEC 3-23 DECE 21-54 DECEE 21-56 Decrementer register 3-23 Delay after transfer (DT) 14-23, 14-35 before SCK (DSCKL) 14-18 DER 21-55 Development Port trap enable selection 21-48 Digital control section contents 13-1, 13-1413-29 input /output port (PQA) 13-3 port (PQB) 13-4 to analog converter (DAC) 13-14 DIO D-38 DIS 20-3 Disable TPU2 pins field (DTPU) 17-20 Disabled mode 13-18 Discrete input/output (DIO) D-38 DIV2 17-20 DIV8 clock 17-7 Divide by two control field (DIV2) 17-20 DIW0EN 21-48 DIW1EN 21-48 DIW2EN 21-48 DIW3EN 21-48 DLW0EN 21-52 DLW1EN 21-52 Double -buffered 14-52, 14-56 DPI 21-55 DPTRAM 18-4 DSCK 14-23 DSCKL 14-18 DSCR 17-12 DSISR 3-22, 3-46, 3-51, 3-52 DSSR 17-14 DT 14-23 DTL 14-18 DTPU 17-20 E EA 3-33 EBRK 21-55 ECR 21-53 EE bit 3-21, 3-26 Effective address 3-33 EID 3-26 EIE 3-26 eieio, 3-43 ELE bit 3-21 EMPTY 16-5 EMU 17-4, 17-11 Emulation control (EMU) 17-11 support 17-4 Encoded one of three channel priority levels (CH) 17-18 time function for each channel (CHANNEL) 17-16 type of host service (CH) 17-18 Ending queue pointer (ENDQP) 14-19 End-offrame (EOF) 16-16 End-of-queue condition 13-45 ENDQP 14-19, 14-24 Entry table bank select field (ETBANK) 17-20 EOF 16-16 EOQ 13-17 EP bit 3-21 ERRINT 16-32 Error conditions 14-56 counters 16-9 interrupt (ERRINT) 16-32 ESTAT 16-30 ETBANK 17-20 ETRIG 13-4 Event timing 17-3 Exception cause register 21-53 Exception prefix 3-21 Exceptions 3-34 classes 3-34
MOTOROLA Index-3

little endian mode 3-21 ordered 3-34 precise 3-35 unordered 3-34 vector table 3-35, 3-36 Execution units 3-4 Extended message format 16-1 frames 16-5 External digital supply pin 13-5 interrupt disable 3-26 enable 3-26 multiplexing 13-9 trigger pins 13-4 trigger single-scan mode 13-20 External interrupt enable 3-21, 3-26 Externally multiplexed mode (MUX) 13-36 EXTEST 22-5 EXTI 21-54 EXTIE 21-56 F Fast quadrature decode TPU function (FQD) D-29 Fault confinement state (FCS) 16-10, 16-31 FCS 16-10, 16-31 FE 14-49, 14-56 FE bits 3-21, 3-22 FE flag 3-14 features bus interface, 9-1 Fetch serialized 21-1 FEX bit 3-14 FG bit 3-14 FI bit 3-14 Final sample time 13-12 FL bit 3-14 Floating-point available 3-21 condition code 3-14 enabled exception summary 3-14 equal or zero 3-14 exception mode 3-21, 3-22 exception summary 3-14 fraction inexact 3-14 fraction rounded 3-14 greater than or positive 3-14 inexact exception 3-14 enable 3-15 invalid operation exception enable 3-15 for *0 3-14 for / 3-14 for - 3-14 for 0/0 3-14 for invalid compare 3-14 for invalid integer convert 3-15 for invalid square root 3-15 for SNaN 3-14 for software request 3-15 summary 3-14 less than or negative 3-14 overflow exception 3-14 enable 3-15 registers 3-12 result class descriptor 3-14 result flags 3-14 rounding control 3-15 status and control register 3-12 underflow exception 3-14 unit 3-5 unordered or NaN 3-14 zero divide exception 3-14 enable 3-15 floating-point unavailable interrupt, 3-47 FORMERR 16-31 FP bit 3-21 FPCC bit 3-14 FPRF field 3-14 FPRs 3-12 FPSCK 17-20 FPSCR 3-12 FPU 3-5 FPUVE 21-54 FPUVEE 21-56 FQCLK 13-25 FQD D-29 FQM D-11 FR 3-14 Frame 14-50 size 14-57 Frames overload 16-16 remote 16-15 Framing error (FE) flag 14-49, 14-56 FREEZ ACK 16-17 FREEZE assertion response (FRZ) QADC 13-6, 13-33 QSM 14-5 TPU 17-13 FREEZE (internal signal) 13-46 Frequency measurement (FQM) D-11 FRZ 13-7, 13-33, 16-11, 17-13 FRZACK 16-11 FU bit 3-14 FULL 16-5 Function library for TPU 17-4 FX bit 3-14 G General SPRs 3-25 General-purpose registers (GPRs) 3-12 Global registers 13-32
MOTOROLA Index-4

H Hall effect decode (HALLD) D-20 HALLD D-20 HALT 14-20, 16-11 Halt acknowledge flag (HALTA) 14-21 QSPI (HALT) 14-20 HALTA 14-21 HALTA and MODF Interrupt Enable (HMIE) 14-41 HALTA/MODF interrupt enable (HMIE) bit 14-20 Hang on T4 (HOT4) 17-13 HMIE 14-20 HOT4 17-13 HSQR 17-16 HSSR 17-17 Initial sample time 13-12 Input sample time (IST) 13-28, 13-47 Instruction pipeline 3-36 sequencer 3-3 set summary 3-29 timing 3-36 Instruction fetch show cycle control 21-1 instruction storage interrupt, 3-46 instructions cache control, 3-42 storage control, 3-44 instructions, partially executed, 3-52 Integer exception register 3-17 Integer unit 3-5 Interchannel communication 17-4 Intermission 16-16 Intermodule bus (IMB) 13-1 Interrupt sources 13-30 Interrupt Level of SCI (ILSCI) 14-8, 14-9 Interrupts QADC 13-29 TOUCAN 16-19 TPU 17-5 interrupts, 3-44 Inter-transfer delay 14-14 invalid and preferred instructions, 3-39 Invalid channel number 13-47 IPT 16-9 IRQ 17-5 ISCTL 21-1 IST 13-28, 13-47 isync, 3-42 IU 3-5 IW 21-48 J Joint test action group. See JTAG JTAG 22-1 instruction register 22-4 non-IEEE 1149.1-1990 operation 22-7 signals 22-1, 22-2 K KR/RETRY, 9-5 L LBRK 21-55 LBUF 16-27 L-bus support control register 1 21-49 control register 2 21-50 LCK 20-3 LCTRL1 21-49 LCTRL2 21-50
I I/O port operation 13-7 IBRK 21-55 I-bus watchpoint programming 21-48 I-bus support control register 21-47 ICTRL 21-47 ID Extended (IDE) field 16-6 HIGH field 16-6 LOW field 16-6 IDE 16-6 Identifier (ID) 16-1 bit field 16-6 IDLE 14-48, 14-57, 16-31 Idle CAN status (IDLE) 16-31 frame 14-50 -line detect type (ILT) 14-46 detected (IDLE) 14-48, 14-57 detection process 14-57 interrupt enable (ILIE) 14-46, 14-57 type (ILT) bit 14-57 IEEE 1149.1-1990 standard. See JTAG IFLAG 16-33 Ignore first match 21-48 IIFM 21-48 ILIE 14-46, 14-57 illegal and reserved instructions, 3-38 ILSCI 14-8, 14-9 ILT 14-46, 14-57 IMASK 16-32 IMB 13-1, 13-24 implementation dependent software emulation interrupt, 3-48 implementation specific data TLB error interrupt, 3-50 implementation specific debug interrupt, 3-51 implementation specific instruction TLB error interrupt, 3-49 IMULIDIV 3-5 Information processing time (IPT) 16-9
MOTOROLA Index-5

LE bit 3-22 Least significant bit (LSB) 13-14 Left justified signed result word table (LJSRR) 13-49 unsigned result word table (LJURR) 13-49 Length of delay after transfer (DTL) 14-18 Link register 3-18 Little endian mode 3-22 LJSRR 13-49 LJURR 13-49 Load/store unit 3-5, 3-6 Lock /release/busy mechanism 16-15 Loop mode (LOOPS) 14-46 LOOPQ 14-20 LOOPS 14-46 Low power stop (LPSTOP) QADC 13-6 QSM 14-5 Lowest buffer transmitted first (LBUF) 16-27 Low-power stop mode enable (STOP) QADC 13-33 TPU 17-11 LR 3-5, 3-18, 17-19 LSB 13-14 LSU 3-5, 3-6 LW0EN 21-51 LW0IA 21-51 LW0IADC 21-51 LW0LA 21-51 LW0LADC 21-51 LW0LD 21-51 LW0LDDC 21-51 LW1EN 21-51 LW1IA 21-51 LW1IADC 21-51 LW1LA 21-51 LW1LADC 21-51 LW1LD 21-51 LW1LDDC 21-51 M M 14-46, 14-51 Machine check enable 3-21 state register 3-20 status save/restore register 0 3-24 status save/restore register 1 3-24 machine check interrupt, 3-45 Machine status save/restore register 1 3-24 Mask examples for normal/extended messages 16-8 registers (RX) 16-7 Master /slave mode select (MSTR) 14-17 master external arbitration phase, 9-30 MCE 21-54 MCEE 21-55 MCPWM D-22 ME bit 3-21 Message buffer address map 16-22 code for RX/TX buffers 16-5 deactivation 16-13 structure 16-3 format error (FORMERR) 16-31 Mid-analog supply voltage 13-14 MISO 14-33, 14-37 Mode fault flag (MODF) 14-21, 14-26 select (M) 14-46 Mode Fault Flag (MODF) 14-41 Modes disabled 13-18 reserved 13-18 scan. See Scan modes MODF 14-21, 14-26, 14-41 Modulus counter 14-51 MOSI 14-33, 14-37 Most significant bit (MSB) 13-14 MQ1 13-37 MQ2 13-39 MSB 13-14 MSR 3-20, 3-45, 3-47, 3-48, 3-49, 3-50, 3-51, 3-52 MSR, 3-44 MSTR 14-17 Multichannel pulse-width modulation (MCPWM) D-22 parameters slave channel A non-inverted center aligned mode D-25, D-41 slave edge-aligned mode D-24 Multimaster operation 14-26 Multiphase motor commutation (COMM) D-18 parameters D-19 Multiple end-of-queue 13-17 Multiplexed analog inputs 13-5 MUX 13-8, 13-36 N New queue pointer value (NEWQP) 14-19 New input capture/transistion counter (NITC) D-16 parameters D-17 NEWQP 14-19, 14-24 NF 14-49, 14-56 NI bit 3-15 NITC D-16 Noise error flag (NF) 14-49 errors 14-56 flag (NF) 14-56 Non-IEEE 1149.1-1990 operation 22-7
MOTOROLA Index-6

Non-IEEE floating-point operation 3-15 nonoptional instructions, 3-38 Non-recoverable interrupt 3-26 NOT ACTIVE 16-5 Not ready (NOTRDY) 16-20 NOTRDY 16-16, 16-20 NRI 3-26 O OC D-34 OE bit 3-15 OP0, 9-28 OP1, 9-28 OP2, 9-28 OP3, 9-28 operand placement (effects), 3-42 operand representation (illustration), 9-28 optional instructions, 3-38 OR 14-48 Ordered exceptions 3-34 Output compare (OC) D-34 OV (overflow) bit 3-18 Overload frames 16-16 OVERRUN 16-5 Overrun error (OR) 14-48 OX bit 3-14 P P 13-47 Parity (PF) flag 14-56 checking 14-52 enable (PE) 14-46 error (PF) bit 14-49 errors 14-56 type (PT) 14-46 type (PT) bit 14-52 Pause (P) 13-15, 13-47 PCBK 17-14 PCS 14-23 to SCK delay (DSCK) 14-23 PCS0/SS 14-38 PCS3-PCS0/SS 14-41 PE 14-46 Period /pulse-width accumulator (PPWA) D-32 Periodic /interval timer 13-29 Periodic interrupt timer 6-14 Peripheral chip-selects (PCS) 14-23, 14-36 Peripheral Chip-Select 3-0/Slave Select (PCS3-PCSO/SS) 14-41 PF 14-49, 14-56 PF1 13-41 PF2 13-41 Phase buffer segment 1/2 (PSEG1/2) bit field 16-28 phase-lock loop, 9-7 PIE1 13-37 PIE2 13-39 PIT 6-14 PLL, 9-7 Pointer 14-15 port size device interfaces (illustration), 9-29 port width, 9-1 PORTQA 13-33, 13-34 PORTQB 13-33, 13-34 PORTQS 14-10 PowerPC standards PowerPC Operating Environment Architecture (Book 3) branch processor, 3-43 fixed-point processor special purpose registers, 3-43 fixed-point processor, 3-43 interrupts, 3-44 optional facilities and instructions, 3-53 storage control instructions, 3-44 timer facilities, 3-53 PowerPC Operating Environment Architecture (Book 3), 3-43 PowerPC User Instruction Set Architecture (Book 1) branch instructions, 3-39 branch processor, 3-39 computation modes, 3-38 exceptions, 3-39 fixed point-processor, 3-39 instruction classes, 3-38 load/store processor, 3-40 reserved fields, 3-38 PowerPC User Instruction Set Architecture (Book 1), 3-38 PowerPC Virtual Environment Architecture (Book 2) operand placement effects, 3-42 storage control instructions, 3-42 timebase, 3-43 PowerPC Virtual Environment Architecture (Book 2), 3-42 PowerPC User Instruction Set Architecture Book 1 instruction fetching, 3-39 PPWA D-32 PQA 13-8 PQB 13-4, 13-8 PQSPAR 14-9, 14-33, 14-37 PR bit 3-7, 3-21 PRE 21-54 Precise exceptions 3-35 PREE 21-56 Prescaler 13-26 clock (PSCK) 17-11 high time (PSH) 13-36 low time (PSL) 13-36 clock high time (PSH) 13-26 control for TCR1 17-5 for TCR2 17-7
MOTOROLA Index-7

divide factor field 16-28 register (PRESDIV) 16-8, 16-27 PRESDIV (bit field) 16-28 PRESDIV (register) 16-8, 16-9, 16-27 Privilege level 3-7, 3-21 Processor version register 3-25 Programmable channel service priority 17-4 transfer length 14-14 Programmable time accumulator (PTA) D-4 parameters D-5, D-44, D-46 Propagation segment time (PROPSEG) 16-27 PROPSEG 16-11, 16-27 PSCK 17-11 PSEG1 16-28 PSEG2 16-9, 16-11, 16-28 PSEGS1 16-11 PSH 13-26, 13-36 PSL 13-36 PT 14-46, 14-52 PTA D-4 PTR, 9-4, 9-37 Pulse-width modulation (PWM) D-36 parameters D-37 PVR 3-25 PWM D-36 Q QACR0 13-35 QACR1 13-36 QACR2 13-38, 13-39 QADC features 13-2 pin functions diagram 13-2 registers control register 0 (QACR0) 13-35 control register 1 (QACR1) 13-36 control register 2 (QACR2) 13-39 conversion command word table (CCW) 13-46 interrupt register (QADCINT) 13-32, 13-33 module configuration register (QADCMCR) 13-6, 13-32, 13-33 port A data register (PORTQA) 13-33 B data register (PORTQB) 13-33 data direction register (DDRQA) 13-33 QA data direction register (DDRQA) 13-35 QA data register (PORTQA) 13-34 QB data register (PORTQB) 13-34 status register (QASR) 13-41, 13-42 test register (QADCTEST) 13-32, 13-33 QADCINT 13-32, 13-33 QADCMCR 13-6, 13-32, 13-33 QADCTEST 13-32, 13-33 QASR 13-40 QASR0 13-41 QASR1 13-42 QCLK 13-21, 13-24 frequency 13-25 QDDR 14-12, 14-41 QILR 14-8 QOM D-6 QPAR 14-11 QPDR 14-10, 14-41 QS 13-42 QSM pin function 14-10 QSPI 14-13 operating modes 14-26 operation 14-24 RAM 14-21 registers pin control registers 14-9 port QS data direction register (DDRQS) 14-9 data register (PORTQS) 14-10 QSPI control register 0 (SPCR0) 14-16 control register 1 (SPCR1) 14-18 control register 2 (SPCR2) 14-18 control register 3 (SPCR3) 14-19 status register (SPSR) 14-19 SCI control register 0 (SCCR0) 14-45 control register 1 (SCCR1) 14-45 data register (SCDR) 14-49 status register (SCSR) 14-47 SCI 14-41 operation 14-50 pins 14-50 registers 14-44 QSM Data Direction Register (QDDR) 14-12, 14-41 QSM Interrupt Level Register (QILR) 14-8 QSM Pin Assignment Register (QPAR) 14-11 QSM Port Data Register (QPDR) 14-10, 14-41 QSPI 14-13 block diagram 14-14 enable (SPE) 14-18 finished flag (SPIF) 14-21 initialization operation 14-27 loop mode (LOOPQ) 14-20 master operation flow 14-28 operating modes 14-26 master mode 14-26, 14-33 wraparound mode 14-37 slave mode 14-26, 14-37 operation 14-24 peripheral chip-selects 14-36 RAM 14-21, 14-22 command RAM 14-22 receive RAM 14-22 transmit RAM 14-22 QSPI Enable (SPE) 14-41 QSPI Status Register (SPSR) 14-41 Queue 13-14 pointers completed queue pointer (CPTQP) 14-24 end queue pointer (ENDQP) 14-24 new queue pointer (NEWQP) 14-24
MOTOROLA Index-8

status (QS) 13-42 Queue 1 completion flag (CF1) 13-41 interrupt enable (CIE1) 13-37 operating mode (MQ1) 13-37 pause flag (PF1) 13-41 interrupt enable (PIE1) 13-37 single-scan enable (SSE1) 13-37 trigger overrun (TOR1) 13-41 Queue 2 completion flag (CF2) 13-41 interrupt enable (CIE2) 13-39 operating mode (MQ2) 13-39 pause flag (PF2) 13-41 interrupt enable (PIE2) 13-39 resume (RES) 13-39 single-scan enable bit (SSE2) 13-39 trigger overrun (TOR2) 13-41 Queued analog-to-digital converter. See QADC 13-1 serial peripheral interface (QSPI) 14-13 Queued output match TPU function (QOM) D-6 R R0 20-3 RAF 14-48 RD/WR, 9-4 RDRF 14-48, 14-56 RE 14-44, 14-46, 14-56 RE bit 3-22, 3-26 read cycle, data bus requirements, 9-30 Read only, SRAM 20-3 read/write (RD/WR), 9-36 Receive data register full (RDRF) 14-48 error status flag (RXWARN) 16-31 RAM 14-22 time sample clock (RT) 14-52, 14-56 Receiver active (RAF) 14-48 data register (RDRF) flag 14-56 enable (RE) 14-46, 14-56 interrupt enable (RIE) 14-46 wakeup (RWU) 14-47, 14-58 Receiver Enable (RE) 14-44 Reception of transmitted frames 16-13 Recoverable exception 3-22, 3-26 Registers CMPACMPD 21-45 CMPECMPF 21-46 CMPGCMPH 21-46 COUNTA 21-52 COUNTB 21-53 DER 21-55 ECR 21-53 ICTRL 21-47 LCTRL1 21-49 LCTRL2 21-50 MI_RA 0-3 region attribute register 4-21 supervisor level 3-20 test (RAMTST) 18-4 user level 3-11 registers special purpose added registers, 3-44 unsupported registers, 3-43 special purpose, 3-43 Remote frames 16-15 transmission request (RTR) 16-5, 16-6 RES 13-39 reservation protocol for a multi-level (local) bus, 9-41 Reserved channel number 13-47 mode 13-18 Reset status register 7-5 Resistor-divider chain 13-14 Resolution time 13-12 Result word table 13-1, 13-15, 13-49 Resynchronization jump width (RJW) bit field 16-28 RETRY, 9-43 RIE 14-46 Right justified, unsigned result word table (RJURR) 13-49 RJURR 13-49 RJW 16-11, 16-28 RN field 3-15 RSR 7-5 RSV, 9-37 RT 14-56 RTR 16-5, 16-6, 16-15 RWU 14-47, 14-58 RX Length 16-5 RX14MSKHI 16-30 RX14MSKLO 16-30 RX15MSKHI 16-30 RX15MSKLO 16-30 RXECTR 16-33 RXGMSKHI 16-29 RXGMSKLO 16-29 RXWARN 16-31 S S0 14-8, 20-3 SAMP 16-27 Sample amplifier bypass (BYP) 13-47 Sampling mode (SAMP) 16-27 SAR 13-14 SBK 14-47, 14-53 Scan modes single-scan modes external trigger 13-20 SCBR 14-45
MOTOROLA Index-9

SCCR0 14-45 SCCR1 14-45 SCDR 14-49 SCI 14-33, 14-41 baud clock 14-51 rate (SCBR) 14-45 equation 14-45 idle-line detection 14-57 internal loop 14-58 operation 14-50 parity checking 14-52 pins 14-50 receiver block diagram 14-43 operation 14-56 wakeup 14-58 registers 14-44 SCCR0 14-44 SCCR1 14-44 SCI Baud Rates 14-52 SCI SUBMODULE 14-12 SCSR 14-44 transmitter block diagram 14-42 operation 14-52 SCI Control Register 0 (SCCR0) 14-44 SCI Control Register 1 (SCCR1) 14-44 SCI Status Register (SCSR) 14-44 SCK 14-11, 14-32, 14-37 actual delay before SCK (equation) 14-35 baud rate (equation) 14-34 S-clock 16-9 SCSR 14-47 SE bit 3-21 SEE 21-54 Send break (SBK) 14-47, 14-53 Sequencer, instruction 3-3 Serial clock baud rate (SPBR) 14-17 communication interface (SCI) 14-41 formats 14-51 mode (M) bit 14-51 shifter 14-52 Serial Clock (SCK) 14-11 Serialization fetch 21-1 Service request breakpoint flag (SRBK) 17-14 SGLR 17-19 Simplified mnemonics 3-33 Single-step trace enable 3-21 SIU module configuration register 6-18 SIU signals, 9-4 SIUMCR 6-18 SIW0EN 21-48 SIW1EN 21-48 SIW2EN 21-48 SIW3EN 21-48 Slave Select (SS) 14-41 Slave select signal (SS) 14-37, 14-38 SLW0EN 21-52 SLW1EN 21-52 snooping external bus activity, 3-42 SO bit 3-18 SOF 16-9 Soft reset control field (SOFT_RST) 17-20 SOFT_RST 17-20 SOFTRST 16-11 Software trap enable selection 21-48 SPBR 14-17 SPCR0 14-16 SPCR1 14-18 SPCR2 14-18 SPCR3 14-19 SPE 14-18, 14-41 Special-purpose registers, general 3-25 SPI finished interrupt enable (SPIFIE) 14-19 TSBD 14-8 SPI Test Scan Path Select (TSBD) 14-8 SPIF 14-21 SPIFIE 14-19 SPRG0SPRG3 3-25 SPRGs 3-25 SPRs general 3-25 SPSR 14-19, 14-41 SPWM D-40 SRAM data space only 20-3 disabling 20-3 locking 20-3 read only 20-3 registers 20-2 supervisor space only 14-8, 20-3 two-cycle mode 20-3 SRAMMCR 20-3 SRBK 17-14 SRR 16-6 SRR0 3-24, 3-44, 3-45, 3-47, 3-48, 3-49, 3-50, 3-51, 3-52 SRR1 3-24, 3-44, 3-45, 3-47, 3-48, 3-49, 3-50, 3-51, 3-52 SS 14-41 SS 14-37, 14-38 SSE1 13-37 SSE2 13-39 Standard message format 16-1 frames 16-5 Start bit (beginning of data frame) 14-50 -of-frame (SOF) symbol 16-9 State machine 13-25, 14-56 Status register (QASR) 13-40 STF 17-11 STOP 13-33, 16-17, 17-11 Stop clocks to TCRs (CLKS) 17-13 enable (STOP) bit
MOTOROLA Index-10

QADC 13-6 QSM 14-5 TOUCAN 16-17 TPU 17-11 flag (STF) 17-11 SCI end of data frame bit 14-50 storage control instructions, 3-44 storage reservation, 9-40 STS, 9-5 STUFFERR 16-31 Subqueue 13-15 Substitute remote request (SRR) 16-6 Successive approximation register (SAR) 13-14 Summary overflow 3-18 Supervisor /unrestricted data space (SUPV) QADC 13-33 TPU 17-11 Supervisor mode 3-20 and SRAM 14-8, 20-3 SUPV 13-7, 13-33 SUSG 21-50 SUSH 21-50 Synchronized pulse-width modulation (SPWM) D-40 SYSE 21-54 SYSEE 21-56 system clock output, 9-7 system reset interrupt, 3-44 T T2CFILTER 17-20 T2CG 17-7, 17-11 T2CLK pin filter control (T2CFILTER) 17-20 T2CSL 17-11 TA, 9-6 Table stepper motor (TSM) D-8 TAP controller 22-3 TB 3-19 TBL 3-19, 3-23 TBU 3-19, 3-23 TC 14-48, 14-53 TCIE 14-46, 14-54 TCK 22-3 TCNMCR 16-22 TCR 17-12 TCR1P 17-11 TCR2 clock/gate control (T2CG) 17-11 TDI 22-3 TDO 22-3 TDRE 14-48 TE 14-44, 14-46 TEA, 9-6 termination signals, 9-38 Test access port controller. See TAP controller clock 22-3 data input 22-3 data output 22-3 mode select 22-3 reset 22-3 test register (RAMTST) 18-4 TICR 17-14, 17-21 TIE 14-46, 14-54 Time quanta clock 16-9 stamp 16-5, 16-10 Time base 3-19 timebase, 3-43 TIMER 16-29 Timer count register 1 prescaler control (TCR1P) 17-11 synchronize mode (TSYNC) 16-27 Timing, instruction 3-36 TMS 22-3 TOR1 13-41 TOR2 13-41 TOUCAN address map 16-20 bit timing configuration 16-8 operation 16-9 external pins 16-2 initialization sequence 16-11 interrupts 16-19 message buffer address map 16-22 operation 16-3 receive process 16-13 registers control register 0 (CANCTRL0) 16-25 control register 1 (CTRL1) 16-8 control register 1(CANCTRL1) 16-26 control register 2 (CANCTRL2) 16-28 control register 2 (CTRL2) 16-8 error and status register (ESTAT) 16-30 free running timer register (TIMER) 16-29 interrupt configuration register (CANICR) 16-24 flag register (IFLAG) 16-33 mask register (IMASK) 16-32 module configuration register (TCNMCR) 16-22 receive buffer 14 mask registers (RX14MSKHI/LO) 16-30 buffer 15 mask registers (RX15MSKHI/LO) 16-30 global mask registers (RXGMSKLO/HI 16-29 RX/TX error counter registers (RXECTR/TXECTR) 16-33 test configuration register (CANTCR) 16-24 special operating modes 16-16 auto power save mode 16-18 debug mode 16-16 low-power stop mode 16-17 transmit process 16-12 TPU address map 17-8 components 17-2 FREEZE flag (TPUF) 17-14
MOTOROLA Index-11

function library 17-4 host interface 17-2 interrupts 17-5 microengine 17-2 operation 17-3 coherency 17-4 emulation support 17-4 event timing 17-3 interchannel communication 17-4 programmable channel service priority 17-4 parameter RAM 17-2, 17-22 address map 17-22 registers channel function select registers (CFSR) 17-15 interrupt enable register (CIER) 17-5, 17-15 status register (CISR) 17-5, 17-19 priority registers (CPR) 17-18 decoded channel number register (DCNR) 17-19 development support control register (DSCR) 17-12 support status register (DSSR) 17-14 host sequence registers (HSQR) 17-16 service request registers (HSSR) 17-17 link register (LR) 17-19 module configuration register (TPUMCR) 17-10 service grant latch register (SGLR) 17-19 test configuration register (TCR) 17-12 TPU interrupt configuration register (TICR) 17-14, 17-21 scheduler 17-2 time bases 17-2 timer channels 17-2 TPU Reference Manual 17-3, 17-17 TPU2 module configuration register 2 (TPUMCR2) 17-20 TPUF 17-14 TPUMCR 17-10 TPUMCR2 17-20 TR 21-54 trace interrupt, 3-47 transaction (bus), 9-8 Transfer length options 14-36 transfer acknowledge (TA), 9-38 transfer error acknowledge (TEA), 9-39 transfer size (TSIZ), 9-37 transfer start (TS), 9-36 transfers, alignment and packaging, 9-28 transfers, burst-inhibited, 9-16 transfers, termination signals, 9-39 Transmission complete (TC) flag 14-53 interrupt enable (TCIE) 14-54 Transmit /receive status (TX/RX) 16-31 bit error (BITERR) 16-31 complete bit (TC) 14-48 interrupt enable (TCIE) 14-46 data register empty (TDRE) flag 14-48 error status flag (TXWARN) 16-31 interrupt enable (TIE) 14-46, 14-54 pin configuration control (TXMODE) 16-25 RAM 14-22 Transmitter Enable (TE) 14-44 Transmitter enable (TE) 14-46, 14-52 TRE 21-56 Trigger event 13-44 TRST 22-3 TS, 9-5 TSIZ(0 1), 9-4 TSIZ0, 9-1 TSIZ1, 9-1 TSM D-8 TSR 13-6 TSYNC 16-27 Two-cycle mode, SRAM 20-3 TX Length 16-5 TX/RX 16-31 TXECTR 16-33 TXMODE 16-25 TXWARN 16-31 U UART D-13 UISA register set 3-11 Universal asynchronous receiver/transmitter (UART) D-13 parameters receiver parameters D-15 transmitter parameters D-14 Unordered exceptions 3-34 User level registers 3-11 Using the TPU Function Library and TPU Emulation Mode 17-4 UX bit 3-14 V VDD 13-5 VDDA 13-5 VDDA/2 13-14 VE bit 3-15 Vector table, exception 3-36 Vector table, exceptions 3-35 VIH 13-8 VIL 13-8 Voltage reference pins 13-5 VRH 13-5, 13-14, 13-47 VRL 13-5, 13-14, 13-47
MOTOROLA Index-12

VSS 13-5 VSSA 13-5 VX bit 3-14 VXCVI bit 3-15 VXIDI 3-14 VXIMZ bit 3-14 VXISI 3-14 VXSNAN 3-14 VXSOFT bit 3-15 VXSQRT bit 3-15 VXVC bit 3-14 VXZDZ bit 3-14 W WAKE 14-46, 14-58 Wake interrupt (WAKEINT) 16-32 WAKEINT 16-17, 16-32 WAKEMSK 16-17 Wakeup address mark (WAKE) 14-46, 14-58 Wired-OR mode for QSPI pins (WOMQ) 14-17 for SCI pins (WOMS) 14-46, 14-53 WOMQ 14-17 WOMS 14-46, 14-53 Wrap enable (WREN) 14-19 to (WRTO) 14-19 Wraparound mode 14-15 master 14-37 WREN 14-19 write cycle data bus contents, 9-30 WRTO 14-19 X XE bit 3-15 XER 3-17 XX bit 3-14 Z ZE bit 3-15 ZX bit 3-14
MOTOROLA Index-13

MOTOROLA Index-14
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola is a registered trademark of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
To obtain additional product information: USA/EUROPE: JAPAN: HONG KONG: MFAX: INTERNET: http://www.mot.com
Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609

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Freescale Semiconductor, Inc.

Revised 15 October 2000

Copyright 2000 MOTOROLA; All Rights Reserved

For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc.

Revised 15 October 2000

Copyright 2000 MOTOROLA; All Rights Reserved

For More Information On This Product, Go to: www.freescale.com

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc...

Section 2 SIGNAL DESCRIPTIONS

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Section 3 CENTRAL PROCESSING UNIT

MPC555 / MPC555 USERS MANUAL

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Section 4 BURST BUFFER

MPC555 / MPC555 USERS MANUAL

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Section 5 UNIFIED SYSTEM INTERFACE UNIT

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Section 6 SYSTEM CONFIGURATION AND PROTECTION

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Section 8 CLOCKS AND POWER CONTROL

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Section 9 EXTERNAL BUS INTERFACE

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MPC555 / MPC555 USERS MANUAL

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Section 11 L-BUS TO U-BUS INTERFACE (L2U)

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Section 12 U-BUS TO IMB3 BUS INTERFACE (UIMB)

Section 13 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64

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Section 14 QUEUED SERIAL MULTI-CHANNEL MODULE

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MPC555 / MPC555 USERS MANUAL

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14.9.12 Example QSCI1 Receive Operation of 17 Data Frames . . . . . . . . . . . . . . . . . . . . . 14-73

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MPC555 / MPC555 USERS MANUAL

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