Department Of Computer Science and Engineering

(Approved by AICTE and Affiliated to JNT University, Hyderabad)

Course File

COMPUTER ORGANIZATION AND ARCHITECTURE

For

II Year [Link] I Sem(A & C Sections/R18)

By

[Link] Babu

Asst Prof., CSE Department

CONTENTS

Sl. No. PARTICULARS PAGE NO.

1 Vision and Mission of the Institute 1

 2 Vision & Mission and PEO’S of the Department 2

3 Program Outcomes & Program Specific Outcomes 3

4 Course Outcomes 4-5

5 Mapping of Course outcomes with PO’S and PSO’s 6

6 University Syllabus copy, Text Book References 7

7 Lecture Schedule (60to 6 5 pe1·iods) 8

8 Unit Wise Lecture Notes 9-12

9 Assignment questions with solutions 13

10 Multiple Choice Questions 14

11 Unit wise Question Bank 15

12 Previous Question papers , Internal & External (last 3 years) 16-19

13 Result Analysis & Attainment level 20-31

14 Course Survey 32-33

VISION AND MISSION OF THE INSTITUTE

VISION

“To be a Centre of Excellence in Technical Education and to become an Epic centre of Research for Creative solutions”
 MISSION

“To address the Emerging needs through Quality Technical Education with an Emphasis on Practical Skills and Advanced Research with Social Relevance”

COMPUTER SCIENCE AND ENGINEERING

VISION, MISSION AND PROGRAM EDUCATIONAL OBJECTIVES (PEOS) OF THE DEPARTMENT

VISION

To become a center of excellence in the field of Computer Science and Engineering, keeping in view of advanced developments that produces innovative, skillful, Socially re-

sponsible professionals who can contribute significantly to Industry and Research.

MISSION

DM1: To provide the skilled manpower with state-of-art knowledge in Computer Science and Engineering

DM2: To provide the Professionals to the nation with innovations and ideas in the area of advanced Computing Technologies through research and graduate studies

DM3: To provide the professionals for aiding in the design and development process of industries and society

Program Educational Objectives (PEOs)

PEO 1 : Graduates will be able to comprehend mathematics, science, engineering fundamentals; laboratory and work-based experience to formulate and solve problems in

Computer Science and Engineering and other related domains and will develop proficiency in computer-based engineering and the use of computation tools.

PEO 2: Graduates will be prepared to communicate and work effectively on the multi disciplinary engineering projects practicing the ethics of their profession with a sense of so-

cial responsibility.

PEO 3: Graduates will recognize the importance of lifelong learning to become experts either as entrepreneurs or employees and to widen their knowledge in their domain.

COMPUTER SCIENCE AND ENGINEERING

PROGRAMME OUTCOMES (POs) AND PROGRAM SPECIFIC OUTCOMES (PSOs)

PROGRAMME OUTCOMES :

PO1 : Engineering knowledge – Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and an engineering specialization to the

solution of complex engineering problems.

PO2: Problem analysis – Identify, formulate, review research literature, and analyze complex engineering problems reaching substantiated conclusions using first principles

of mathematics, natural sciences, and engineering sciences.

PO 3: Design/ development of solutions – Design solutions for complex engineering problems and design system components or processes that meet the specified needs

with appropriate consideration for the public health and safety, and the cultural, societal, and environmental considerations.

PO 4: Conduct investigations of complex problems – Use research-based knowledge and research methods including design of experiments, analysis and interpretation of

data, and synthesis of the information to provide valid conclusions.

PO 5 : Modern tool usage – Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern engineering and IT tools including prediction and

modeling to complex engineering activities with an understanding of the limitations.

PO 6 : The engineer and society – Apply reasoning informed by the contextual knowledge to assess societal, health, safety, legal and cultural issues and the consequent

responsibilities relevant to the professional engineering practice.

PO 7 : Environment and sustainability – Understand the impact of the professional engineering solutions in societal and environmental contexts, and demonstrate the

knowledge of, and need for sustainable development.

PO 8 : Ethics – Apply ethical principles and commit to professional ethics and responsibilities and norms of the engineering practice.

PO 9 : Individual and team work – Individual and team work: Function effectively as an individual, and as a member or leader in diverse teams, and in multidisciplinary

settings.

PO 10 : Communication – Communicate effectively on complex engineering activities with the engineering community and with society at large, such as, being able to

comprehend and

write effective reports and design documentation, make effective presentations, and give and receive clear instructions.

PO 11 : Project management and finance – Demonstrate knowledge and understanding of the engineering and management principles and apply these to one’s own work, as a

member and leader in a team, to manage projects and in multidisciplinary environments.

PO 12 : Life-long learning – Life-long learning: Recognize the need for, and have the preparation and ability to engage in independent and life-long learning in the broadest

context of technological change.

PROGRAM SPECIFIC OUTCOMES :

PSO 1: Ability to adapt to a rapidly changing environment by learning and employing new programming skills and technologies.

PSO 2: Ability to use design and develop systems in a range of domains.

 COURSE COUTCOMES

C204.1 Understand the basics of instructions sets and their impact on processor design.

C204.2 Demonstrate an understanding of the design of the functional units of a digital computer
system.

C204.3 Evaluate cost performance and design trade-offs in designing and constructing a computer
processor including memory

C204.4 Design a pipeline for consistent execution of instructions with minimum hazards.

C204.5 Recognize and manipulate representations of numbers stored in digital computers

 JNTUH SYLLABUS (R18 REGULATION)

UNIT - I
Digital Computers: Introduction, Block diagram of Digital Computer, Definition of Computer
Organization, Computer Design and Computer Architecture.
Register Transfer Language and Micro operations: Register Transfer language, Register Transfer,
Bus and memory transfers, Arithmetic Micro operations, logic micro operations, shift micro operations,
Arithmetic logic shift unit.
Basic Computer Organization and Design: Instruction codes, Computer Registers Computer
instructions, Timing and Control, Instruction cycle, Memory Reference Instructions, Input – Output and
Interrupt.

UNIT - II
Microprogrammed Control: Control memory, Address sequencing, micro program example, design
of control unit.
Central Processing Unit: General Register Organization, Instruction Formats, Addressing modes,
Data Transfer and Manipulation, Program Control.

UNIT - III
Data Representation: Data types, Complements, Fixed Point Representation, Floating Point
Representation.
Computer Arithmetic: Addition and subtraction, multiplication Algorithms, Division Algorithms,
Floating – point Arithmetic operations. Decimal Arithmetic unit, Decimal Arithmetic operations.

UNIT - IV
Input-Output Organization: Input-Output Interface, Asynchronous data transfer, Modes of Transfer,
Priority Interrupt Direct memory Access.
Memory Organization: Memory Hierarchy, Main Memory, Auxiliary memory, Associate Memory,
Cache Memory.
.
UNIT - V
Reduced Instruction Set Computer: CISC Characteristics, RISC Characteristics.
Pipeline and Vector Processing: Parallel Processing, Pipelining, Arithmetic Pipeline, Instruction
Pipeline, RISC Pipeline, Vector Processing, Array Processor.
Multi Processors: Characteristics of Multiprocessors, Interconnection Structures, Interprocessor
arbitration, Interprocessor communication and synchronization, Cache Coherence.

TEXT BOOK:
1. Computer System Architecture – M. Moris Mano, Third Edition, Pearson/PHI.

REFERENCES:
1. Computer Organization – Car Hamacher, Zvonks Vranesic, Safea Zaky, Vth Edition, McGraw
Hill.
2. Computer Organization and Architecture – William Stallings Sixth Edition, Pearson/PHI.
3. Structured Computer Organization – Andrew S. Tanenbaum, 4th Edition, PHI/Pearson

COURSE OBJECTIVES

1) The purpose of the course is to introduce principles of computer organization and the basic architectural concepts.
 2)It begins with basic organization, design, and programming of a simple digital computer and introduces simple register transfer language to specify various computer operations.
3) Topics include computer arithmetic, instruction set design, microprogrammed control unit,pipelining and vector processing, memory organization and I/O systems, and multiprocessors

LECTURE PLAN

o Topic Hours Teaching Mode

UNIT – I

Digital Computers, Register Transfer Language and Micro operations, Basic Computer Organization and Design,

omputers:

Introduction 1 Black Board/PPT

Block diagram of Digital Computer 1 Black Board/PPT

Definition of Computer Organization, Computer Design and Computer Architecture 1 Black Board/PPT

Bus Structures ,Software 1 Black Board/PPT

Transfer Language and Micro operations:

Register Transfer language, Register Transfer 1 Black Board/PPT

Bus and memory transfers 1 Black Board/PPT

Arithmetic Micro operations 1 Black Board/PPT

logic micro operations 1 Black Board/PPT

shift micro operations 1 Black Board/PPT

Arithmetic logic shift unit 1 Black Board/PPT

mputer Organization and Design:

Instruction codes 1 Black Board/PPT

Computer Registers 1 Black Board/PPT

Computer instructions 1 Black Board/PPT

Timing and Control, Instruction cycle 1 Black Board/PPT

Memory Reference Instructions 1 Black Board/PPT

Input – Output and Interrupt 1 Black Board/PPT

MENT on UNIT – I Mode: Offline/Online

TOTAL HOURS FOR UNIT – I 16

n No Topic Hours Teaching Mode

UNIT – II

Micro Programmed Control , Central Processing Unit

ogrammed Control:

Control memory 1 Black Board/PPT

Address sequencing 1 Black Board/PPT

micro program example 1 Black Board/PPT

Symbolic Microinstructions 1 Black Board/PPT

design of control unit 1 Black Board/PPT

Microprogram Sequencer 1 Black Board/PPT

rocessing Unit:

General Register Organization 1 Black Board/PPT

Instruction Formats 1 Black Board/PPT

Addressing modes 1 Black Board/PPT

Data Transfer and Manipulation 1 Black Board/PPT

Program Control 1 Black Board/PPT

MENT on UNIT – II Mode: Mode:

TOTAL HOURS FOR UNIT – II 11

o Topic Hours Teaching Mode

UNIT – III

Data Representation, Computer Arithmetic

resentation:
 Data types: Number systems 1 Black Board/PPT

Number systems, complements 1 Black Board/PPT

Fixed Point Representation 1 Black Board/PPT

Floating Point Representation. 1 Black Board/PPT

r Arithmetic:

Addition and subtraction with signed magnitude numbers 1 Black Board/PPT

Addition and subtraction with signed 2’s complement numbers 1 Black Board/PPT

Multiplication algorithms 1 Black Board/PPT

Division algorithms 1 Black Board/PPT

Floating point Arithmetic operations 1 Black Board/PPT

Decimal Arithmetic unit 1 Black Board/PPT

Decimal Arithmetic operations 1 Black Board/PPT

MENT on UNIT – III Mode: Offline / Online

TOTAL HOURS FOR UNIT – III 11

o Topic Hours Teaching Mode

UNIT – IV

Computer Arithmetic, Input-Output Organization

tput Organization:

Peripheral Devices, Input-Output Interface 1 Black Board/PPT

Asynchronous data transfer 1 Black Board/PPT

Asynchronous data transfer 1 Black Board/PPT

Modes of Transfer 1 Black Board/PPT

Priority Interrupt 1 Black Board/PPT

Direct memory Access 1 Black Board/PPT

Organization:

Memory Hierarchy 1 Black Board/PPT

Main Memory: RAM and ROM chips 1 Black Board/PPT

 Memory Address Map, Auxiliary memory 1 Black Board/PPT

Associate Memory 1 Black Board/PPT

Cache Memory-Mapping Techniques, writing into cache 1 Black Board/PPT

MENT on UNIT – IV Mode: Offline / Online

TOTAL HOURS FOR UNIT – IV 11

n No Topic Hours Teaching Mode

UNIT – V

Memory Organization, Pipeline and Vector Processing, Multi Processors

nd Vector Processing:

RISC and CISC 1 Black Board/PPT

Parallel Processing, Pipelining 1 Black Board/PPT

Arithmetic Pipeline 1 Black Board/PPT

Instruction Pipeline 1 Black Board/PPT

RISC PIPELINE 1 Black Board/PPT

Vector Processing, Array Processors 1 Black Board/PPT

cessors:

Characteristics of Multiprocessors, 1 Black Board/PPT

Interconnection Structures 1 Black Board/PPT

Inter processor arbitration 1 Black Board/PPT

Inter processor communication, and synchronization 1 Black Board/PPT

Cache coherence 1 Black Board/PPT

TOTAL HOURS FOR UNIT – V 11

GRAND TOTAL NUMBER OF HOURS 60

[Link] QUESTION BANK

 Descriptive Questions

UNIT – I

QNO Description of Question Marks Course Program BTL

outcome Outcome(P

(CO) O)

a Define Computer Organization and Computer Architecture 2 CO1 PO1 L1

b Differentiate between Von Neumann Architecture and Harvard Architecture 3 CO1 PO1 L4

c Explain the functional units of digital computer with block diagram 10 CO1 PO1 L2

a Explain RTL and its control function. 2 CO1 PO1 L2

b Define Micro operations? List out the types of Micro operations? 3 CO1 PO1 L1

c Design a common bus system for 4 registers of 4 bits using Multiplexers 5 CO1 PO3 L3

d Design a common bus system for 4 registers of 1 bit each using three state buffers 5 CO1 PO3 L3

a What is Full Adder 2 CO1 PO1 L1

b Describe the Arithmetic Micro operations 3 CO1 PO1 L2

c Explain the 4 bit Arithmetic Circuit 5 CO1 PO1 L2

d Explain the 4bit binary adder- subtractor 5 CO1 PO1 L2

a Define Instruction code [ 2 CO1 PO1 L1

A digital computer has a common bus system for 16 registers of 32bit each. The bus constructed with CO1 PO3 L1

multiplexers.

i) How many multiplexer are there in the bus??

b 3

ii)What size of Multiplexer are needed?

iii) How many selection inputs are there in each multiplexer?

c What are the Logical Micro operations and Explain the applications of Logical Micro operations 5 CO1 PO1 L3

d Describe shift Micro operations 5 CO1 PO1 L2

a List out the Basic Computer Registers 2 CO1 PO1 L1

b Define Direct addressing mode and Indirect addressing mode 3 CO1 PO1 L1

c Explain the different types of basic computer instructions with their formats 10 CO1 PO3 L2

a What is interrupt cycle 2 CO1 PO1 L2

b Describe the Register Reference Instructions 3 CO1 PO1 L2

 c Describe the Memory Reference instructions 5 CO1 PO1 L2

d What is instruction cycle and explain the basic computer instruction cycle 5 CO1 PO1 L1

UNIT-2

QNO Description of Question Marks Course Program BTL

outcome Outcome(P

(CO) O)

a What is a pipeline register in micro programmed control unit 2 CO2 PO1 L1

b Discuss about control memory and its organization 3 CO2 PO1 L2

Differentiate between hardwired control unit and Microprogrammed control unit. Hardwired control CO2 PO2 L4
c 10
unit is faster than micro programmed control unit. Justify this statement

a Discuss about mapping process in microprogrammed control unit 2 CO2 PO1 L2

b Explain symbolic microinstruction format with example 3 CO2 PO1 L2

c With the help of a block diagram , explain how do we select the address of control memory 10 CO2 PO2 L2

a Why do we need subroutine register in a control unit?[ 2 CO2 PO2 L1

Define the following: CO2 PO1 L1

b 3
i)Microoperation ii)Microinstruction iii) Microprogram iv)Control Address Register

c Explain the decoding of microoperation fields in control unit?[ 5 CO2 PO3 L2

Show the general block diagram of a micro program sequencer and also explain the inputs and outputs CO2 PO3 L2
d 5
along with their functioning

a What is stack pointer 2 CO2 PO1 L1

b Explain about data transfer instructions 3 CO2 PO1 L2

c What is an addressing mode? Explain various addressing modes with examples 10 CO2 PO1 L2

a Write the generic instruction types present in a computer system 2 CO2 PO1 L1

b Explain about shift instructions 3 CO2 PO1 L2

c Explain the General Register Organization 5 CO2 PO1 L2

d What is an interrupt? What are the uses of interrupts? Explain about the different type of interrupts?. 5 CO2 PO1 L1

a Give an example each of Zero-address, One-address, two-address and three-address instruction 2 CO2 PO2 L1

b Explain about Logical and Bit Manipulation Instructions 3 CO2 PO1 L2

c Explain about Program Control Instructions 5 CO2 PO1 L2

d Evaluate the following arithmetic statement using zero, one, two and three address instructions. Use the 5 CO2 PO3 L2
 conventional symbols and instructions. X = (A+B) * (C+D).

UNIT-3

QNO Description of Question Marks Course Program BTL

outcome Outcome(P

(CO) O)

a Solve for X in the equation (19.125)10 =(X)8 2 CO3 PO1 L3

b Using 2’s complement perform (42)10 –( 68)10 3 CO3 PO2 L3

Explain about sign magnitude and 2’s complement approaches for representing the fixed point CO3 PO1 L2
c 5
numbers. Why 2’s complement is preferable.

What is the use of complements? Perform subtraction using 7's complement for the given Base-7 CO3 PO1 L1
d 5
numbers (565)-(666).

a Using 10’s complement subtract 72532-3250 2 CO3 PO1 L3

Give the 2's complement notation for the following signed decimal numbers CO3 PO1 L3
b 3
for 8 bit word i.) +1 ii) +127 iii) -1 iv) -64.

Solve for x CO3 PO3 L3

c i) (367)8=(x)2 ii) (323)4 = ( )5 10

iii) (B9F. AE)16 = (x)8 iv) (16)10 = (100) x

a Represent the decimal number 46.5 as a floating point number with 16 bit mantissa and 8 bit exponent 2 CO3 PO1 L3

b Convert the following (527)10=(?)Gray=(?)BCD=(?)XS-3 3 CO3 PO1 L3

Explain 2's complement method of representing numbers. When can you say that an overflow has CO3 PO1 L2
c 5
occurred when adding or subtracting two fixed point numbers.

Represent 32.75 and 18.125 in single precision IEEE 754 Representation 5 CO3 PO1 L2

d
____

a Show the hardware to be used for Multiplication with signed magnitude numbers 2 CO3 PO3 L2

b Define Divide overflow? 3 CO3 PO1 L1

c Explain in detail with neat sketch Booth Multiplication Algorithm with example 10 CO3 PO3 L2

Perform the operation (-9)+(-6)= -15 with binary numbers in signed 2’s complement representation CO3 PO1 L3
a 2
using only five bits to represent each number (including the sign).

b Give Register configuration for floating point arithmetic operations 3 CO3 PO3 L2

c Explain in detail addition and subtraction with signed magnitude numbers 5 CO3 PO3 L2
 d Explain different methods of decimal addition 5 CO3 PO1 L2

a What is an array multiplier and give example 2 CO3 PO1 L1

b Define overflow and underflow 3 CO3 PO1 L1

c Explain Division Algorithms 5 CO3 PO1 L2

d Explain the floating point additions and subtractions operations With a flow chart 5 CO3 PO1 L2

UNIT-4

QNO Description of Question Marks Course Program BTL

outcome Outcome(P

(CO) O)

a What is an I/O interface 2 CO4 PO1 L1

b Differentiate isolated I/O and memory mapped I/O 3 CO4 PO1 L4

c Explain different types of modes of transfer (or) I/O communication techniques 10 CO4 PO1 L2

What is the basic advantage of using interrupt-initiated data transfer over transfer under program control CO4 PO2 L1
a 2
without an interrupt?

b Explain about Source-initiated transfer using handshaking 3 CO4 PO1 L2

What is Direct Memory Access? Explain the working of DMA. What are the different kinds of DMA CO4 PO1 L1
c 10
transfers?[

a Differentiate vectored and non vectored interrupt 2 CO4 PO1 L4

b Explain daisy-chain priority interrupt 3 CO4 PO1 L2

c Explain parallel priority interrupt? 5 CO4 PO1 L2

d Explain Asynchronous serial transfer 5 CO4 PO1 L2

How many characters per second can be transmitted over a 1200 baud line in Synchronous serial CO4 PO2 L3
a 2
transmission?[

b Give a neat sketch that illustrate the components in a typical memory Hierarchy 3 CO4 PO3 L4

c Explain the different types mapping techniques are used in usage of the cache memory 10 CO4 PO1 L2

a Define hit ratio and miss ratio 2 CO4 PO1 L1

b Differentiate between SRAM and DRAM 3 CO4 PO1 L4

c Explain about types of ROM 5 CO4 PO1 L2

d What is memory address map table ? Explain with example? 5 CO4 PO1 L1

a What is an Auxilary Memory 2 CO4 PO1 L1

 b Differentiate write through and write back 3 CO4 PO1 L4

How many 128 × 8 RAM chips are needed to provide a memory capacity of 2048 bytes? How many CO4 PO2 L2

c lines of address bus must be used to access 2048 bytes of memory? How many of these lines will be 5

common to all chips?

d With the help of a neat diagram explain the match logic for one word of Associative Memory 5 CO4 PO3 L2

UNIT-5

QNO Description of Question Marks Course Program BTL

outcome Outcome(P

(CO) O)

a What is space time diagram and give example 2 CO5 PO1 L1

b Differentiate between RISC and CISC 3 CO5 PO2 L4

c Explain array processor in detail 10 CO5 PO1 L2

d What is pipeline and explain with example CO5 PO1 L1

a What are the pipeline conflicts 2 CO5 PO1 L1

b What is delayed branch? Explain with example 3 CO5 PO1 L2

c Explain RISC pipeline or three segment instruction pipeline 10 CO5 PO1 L2

a What are the applications of vector processing 2 CO5 PO1 L1

b Define memory interleaving 3 CO5 PO1 L1

c Explain arithmetic pipeline with example 5 CO5 PO1 L2

Explain the various hardware techniques to minimize the performance degradation caused by CO5 PO2 L2
d 5
instruction branching

a Draw the system bus structure for multiprocessors 2 CO5 PO1 L2

b Differentiate between tightly coupled multiprocessor and loosely coupled multiprocessor 3 CO5 PO2 L4

i)Explain the functioning of omega switching network with a neat sketch. CO5 PO3 L2

ii) In 8 X 8 omega switching network how many stages are there and in each stage how many

c Switches are there. 10

iii) How many stages and how many Switches in each stage are needed in a n x n omega switching

network.

a Explain the cache incoherence 2 CO5 PO1 L2

b Explain multiport memory organization with a neat sketch 3 CO5 PO1 L2

c Explain static arbitration and dynamic arbitration algorithms 5 CO5 PO1 L2

 a Define critical section 2 CO5 PO1 L1

How many switch points are there in a crossbar switch network that connects p processors to m memory CO5 PO1 L2
b 3
modules

What are the various forms available for establishing an interconnection network in a multi processor CO5 PO1 L2
c 5
system?

d What is cache coherence? Explain different solutions to the cache coherence problem 5 CO5 PO1 L2

Objective Questions

UNIT – I

Multiple Choice Questions:

[Link] Organization is concerned with [ ]

a. The way hardware components operate and connected together to form Computer system.
b. The determination of what hardware should be used and how the parts be connected.
c. The structure and behavior of the computer as seen by the user.

d. Design of electronic components of computer.

2. The part of the hardware of computer that controls the transfer of information between
computer and the outside word is [ ]

a)CPU b)Memory c)IOP d)Microprocessor

3. In direct addressing mode address part of instruction specifies [ ]

a)Address of next instruction b)Address of register

c)Address of operand in memory d)Operand itself
4. In indirect addressing mode address part of instruction specifies [ ]

a)Address of next instruction b)Address of current instruction

c)Address of operand d)Address of memory location containing address of operand

5. The memory reference instruction that denotes operation PC 🡨AR is [ ]

a) AND b) BSA c) BUN d)STA

6. The transfer of information from a memory word to the outside environment is called a ________ operation. [ ]
a) Read b) write c) both d) none

7. To design a common bus system for 4 register of 4-bits each, by using tristate buffers and a decoder, what is the size of the decoder? [ ]
a) 2 to 4 Decoder b) 3 to 8 Decoder c) 4 to 16 Decoder d)5 to 32 decoder

8. If the address field of an instruction specifies the effective address, then the instruction is
[ ]
a) Immediate Instruction b) Direct Instruction c) Indirect Instruction d) None
9 There are ___________ different logical operations that can be performed with 2 binary variables
[ ]
a) 2 b) 4 c) 8 d) 16.
10. In the Binary Adder/subtractor if M=0 the circuit is __________ [ ]
a) adder b) subtractor c) both adder & subtractor d) exclusive Binary Operation.

11. The _________ operation is similar to the selective clear operation except that the bits of A are cleared only where there are corresponding 0's in B. [ ]
a) Selective – set b) Selective – complement c) Mask d) Insert .

Fill in the blanks:

12. The type of shift used to shift the contents of a register which contains a signed binary number is called ___________
13. If the memory size is 4096*16, then ___ address lines are required to address any memory location
14. The ______________ operation sets to 1 bit in register A where there are corresponding 1’s in register B.
15. Description of SPA instruction ______________________________

16. An _____________ is s a group of bits that instruct the computer to perform a specific operation.
17. A _______________ is a fast electronic calculating machine that accepts digitized input information, processes it according to a list of internally stored instructions and the resulting output information.
18. The ____________ holds the address of the next instruction to be read from memory after the current instruction is executed.

19. An elementary operation performed on the information stored in one or more registers is referred as ___________
20. A common bus for eight registers of 16 bits each requires _______ number of multiplexers.
21. An arithmetic shift right ________ the signed binary number by 2. An arithmetic shift left _______ a signed binary number by 2.

22.__________ holds the address of the memory location to be accessed

23. ______________ holds the instruction code that is currently being executed.

UNIT – 2

1. The control logic is implemented with gates, flip-flops, decoders, and other digital circuits. [ ]

a) Hardwired control b) Microprogrammed c)Control logic d)None

2. If the control signals are generated using hardware with conventional logic design techniques then the control unit is said to be [ ]

a)Micro programmed b)Hardwired

c)Nano programmed d)Programmed
3. The register used to store return address of sub routine is [ ]

a)Control address Register (CAR) b)Sub routine register (SBR)

c)Instruction register (IR) d)Program counter (PC)
4. Micro instructions are stored in [ ]

a)Main memory b)Secondary memory c)Control memory d)Virtual memory

5. The memory reference instruction that denotes operation AC 🡨M[AR] is [ ]

a)AND b)BSA c)BUN d)LDA

6. RPN is also called as [ ]

a) Infix Notation b) Polish Notation c) Prefix Notation d) Postfix Notation

7 _________ refer to the transfer of program control from a currently running program to another service program as result of external or internal generated request. [ ]

a)Program Interrupt b) Internal Interrupt c) External Interrupt d) Software Interrupt

8. Postfix notation of (A+B)*C is [ ]

a. AB+*C b. AB*+C c . ABC+* d. AB+C*

9 Stack follows the __________ operation [ ]

a) L I F O b) F I F O c) S J F d) none

10 Which of the following is shift instruction [ ]

a) RORC b) CALL C) SKP d) SETC

Fill in the blanks:

11. The next address generator is also called as ______________________

12 In the Micro instruction code Format the condition field consists of two bits which are encoded to specify_______ status bit conditions
13 A _____________ requires changes in the wiring among the various components if the design has to be modified (or) changed.
14. The transformation from the instruction code bits to an address in control memory where the routine located is referred as __________
15. In Micro programmed organization, the control information is stored in _______________
16. A control unit whose binary control variables are stored in memory is called _____________ control unit
17 The register that holds the address for the stack is called __________
18 Internal interrupts are also called as ___________
19 The implied operand of an operation in a single accumulator organization is _____________
[Link] a memory stack, after the pop operation, the stack pointer will be ____________

UNIT – 3

[Link] coded decimal number for 99 is ________ [ ]

a) 1100011 b) 00110101 c) 10011001 d) 00100000.

2. In the Hardware for Signed –Magnitute addition and subtraction two magnitudes are subtracted if the sign are different for an ________ Operation (or) identical for an ________ operation. [ ]

a) add , subtract b) add , Multiply c) subtract , add d) Multiply , add.

3. Convert the following binary number into decimal 101110 [ ]
a) 55 b) 45 c)46 d)56
4. Obtain the 10’s complement of the following 6-bit decimal number 100000 [ ]
a. 999999 b. 899999 c. 900000 d. 100000

5. What is the description about following decimal arithmetic microoperation? QL QL+1 [ ]

[Link] QL register b. Increment BCD number in QL

c. Increment decimal number in QL d. All the above

6. Convert the hexadecimal number F3A7C2 to binary [ ]

a.111101101101100010101001 b. 111111000101101101011110

c. 111100111010011111000010 d. 111110011001100000010010
7. Perform the subtraction with the following unsigned decimal number by [ ]

taking the 10’s complement of the subtrahend 1200-250.

a. 450 b. 750 c. 749 d. 449

8. N-bit sign magnitude numbers can represent quantities from [ ]

(n-1) (n-1) (n-1) (n-1) n n n n
a) –(2 -1) to +(2 ) b) –(2 -1) to +(2 -1) c) –(2 -1) to +(2 -1) d) –(2 -1) to +2
[Link] is the 8-bit 2’s complement of -12 [ ]

a. 1111 0100 b. 1000 1100 c. 0000 0100 d. 0000 0011

10. If (123)5=(x3)y, then the number of possible values of x is [ ]

a. 4 b. 1 c. 3 d. 2

Fill in the blanks:

11. A floating- point number is said to be _____________if the most- significant digit of the mantissa is nonzero.

12The Divisor is shifted once to the right and subtracted from the dividend. That difference is called a ______________.

13The r’s complement of an n-digit number N in base r is defined as _____________

14. The decimal equivalent of the binary number 101.101 is _____________

15. The 9’s complement of BCD (1001) is _____________

16. In BCD addition, when the binary sum is greater than 1001, then addition of _______ converts the binary sum to correct BCD representation

17 An n-bit 2’s complement number can represent values _____________

18. In a Array multiplier circuit with ‘j’ multiplier bits and ‘k’ multiplicand bits, the number of

AND gates required are ___________

19. A divide overflow condition occurs, if the high order half bits of the dividend is __________________
20. ___________ algorithm specifies a procedure for multiplying two binary integers in Signed 2’s complement.

UNIT-4
1. Machines whose instructions generate 32-bit address can utilize a memory that contains up to _______ memory locations [ ]

8 16 32 48
A. 2 B. 2 C. 2 D. 2
2. The CPU has distinct i/p and o/p instructions and each of these instructions is associated with the address of an interface register. [ ]
A. Memory Mapped I/O B. I/O Port C. Isolated I/O D. I/O Command
3. Backup storage is called as [ ]
A. Cache Memory B. Main Memory C. Auxiliary Memory D. Virtual Memory
4. Baud rate is data transfer in [ ]
[Link] per second B. bytes per second C. words per second D. all the above
5. During a _________ operation, the sense/read circuits, the information stored in the cells selected by a word line and transmit this information to the o/p data lines [ ]
A. Write B. Read C. Read/Write D. Write & Read/Write
6. The interface transfer s data into and out of the memory unit through the memory bus. [ ]
A. Programmed-I/O B. Interrupted-Initiated I/O C. Direct Memory Access D. all the above
7In the ____________ only the cache is updated and the location is marked so that it can be copied later into main memory. [ ]

A. Write through policy B. Cache Coherence C. Write- back policy D. Cache Incoherence
8. Many instructions in localized areas of the program are executed repeatedly during some time period, and the remainder of the program is accessed relatively infrequently . [ ]
A. Locality reference B. spatial C. temporal D. cache
9. Which of the following is volatile? [ ]

A) Bubble memory B) RAM C) ROM D) Magneticdisk

10. In a non-vectored interrupt [ ]

A) The branch address is assigned to a fixed location in memory

B)The interrupting source supplies the branch information to the processor through an interrupt vector
C)The branch address is obtained from a register in the process
D)Both The interrupting source supplies the branch information to the processor through an interrupt vector & The branch address is obtained from a register in the process

Fill in the blanks:

11 In an _____________ different sets of addresses are assigned to different memory locations.

12. The bus grant signal is replaced by a set of lines called poll lines which are connected to all units is called as ____________
13 Expand UART: _______________________
14 The number of hits stated as a fraction of all attempted accesses is called ____________
15. In the _____________ policy, both cache and main memory are updated with every write operation.
16Input-Output interface provides a method for transferring information between _______________
17The DMA controller to transfer one data word at a time, after which it must return control of the buses to the cpu, this technique is called as ____________
18. Associative memory is called ______________
19 A serial transmission technique which employs special bits to mark the ends of character is called _______________
20 If the branch address of the interrupt routine is supplied by the source it is called ____________ interrupt.
UNIT-5
1. The speed up of a pipeline processing over an equivalent non-pipeline processing is defined by the ratio S =_________ [ ]
A. ntn /(k+n-1)tp B. ntp/(k+n-1)tn [Link] /(k+n+1)tp [Link]/(k-n-1)tn

2 The ______ organization consists of a number of cross points that are placed at intersections between processors buses and memory module paths. [ ]
A. Multiport memory B. Hypercube system C. Crossbar Switch D. Time –shared common bus

3. Application of Vector Processing is [ ]

A. Library System B. Medical Diagnosis C. Seismic Wave Analysis D. Space Research
4 An __________ is an auxiliary processor attached to a general purpose computer . [ ]
A. SIMD array Processor B. Attached array Processor C. Vector Processor D. All the above
5. An ______________is a processor that as single instruction multiple data organization [ ]
A. SIMD array Processor B. Attached array Processor C. Vector Processor D. All the Above
6. To compute n-tasks using a k-segments pipeline requires ______ clock cycles [ ]
A. k-(n+1) B. k-(n-1) C. k+ (n-1) D. k+ (n+1)
7. The _________ algorithm allocates a fixed –length time slice of bus time that is offered sequentially to each processor. [ ]

A. FIFO B. LRU C. Time slice D. Polling

8. _________ arise from branch and other instructions that change the value of pc [ ]

A. Data Dependency B. Resource conflict C. Branch difficulties D. NONE

9________________ caused by access to memory by two segments at the same time [ ]

A. Data dependency B. Resource Conflict C. Branch difficulties D. Delay load

10The ______algorithm gives the highest priority to the requesting device that has not used the bus for the longest interval. [ ]
A. Round - robin [Link] C. LRU D. rotating daisy-chain
Fill in the blanks:

11 ____________ is a technique of decomposing a sequential process into sub operations, with each sub process being executed in a special dedicated segment that operates concurrently with all other segments.
12 An ________________ operates on a stream of instructions by overlapping the fetch, decode and execute phases of the instruction cycle.
13A ___________________ is a program sequence that, once begun, must complete execution before another processor access the same shared resource.
14Expand SIMD _____________________________
15. Multi processors and Multi computer system come into ____________ category
16 A hyper cube with 2-dimensions contain _________ number of processors.
17 An 8x8 omega switching network contains _________ number of switches
18 The number of stages in nxn omega switching network is _________
19. The bus controller that monitors the cache coherence problem is referred as _____________

20 Each processor element in a _______________ system has its own private local memory

UNIT WISE LEARNING OBJECTIVES

UNIT-I

Digital Computers,Register Transfer Language and Micro operations

Learning Objectives:

After completion of this unit the student would be able to:

●
Able to Understand what is computer organization,computer design and computer architecture.
●
Identify the major parts in digital computer
●
RTL and different types of micro operations
●
Able to understand instruction codes and computer registers
●
Able to understand different types of instructions.
●
Able to Understand the instruction cycle

UNIT-II

Microprogrammed Control,Central Processing Unit

Learning Objectives:

After completion of this unit the student would be able to:

● Understanding the design of control unit

● Understanding the control memory

● Understanding the instruction formats

● Understanding the micro programs

● Understanding the register organization

● Understanding the addressing modes

● Understanding the types of instructions

UNIT-III
Data Representation,Computer Arithmetic

Learning Objectives:

After completion of this unit the student would be able to:

● Understanding data types

●
Learning about complements
●
Learning fixed point and floating point representation
●
Understanding addition,subtraction,multiplication and division algorithms
●
Understanding floating – point and arithmetic operations

UNIT-IV

Input-Output Organization,Memory Organization

Learning Objectives:

After completion of this unit the student would be able to:

●
Understanding input output interface
●
Learning asynchronous data transfer
●
Learning modes of transfer
●
Learning priority interrupt
●
Understanding Direct Memory Access
●
Understanding memory hierarchy
●
Understanding types of memories
●
Understanding associate memory
●
Learning cache mappings

UNIT-V

RISC,Pipeline and Vector Processing,Multi Processors

Learning Objectives:

After completion of this unit the student would be able to:

●
Understanding RISC and CISC characterestics.
●
Understanding parallel processing
●
Understanding pipelining and different types of pipelining
●
Understanding characterestics of multi processors,interconnection structures and cache coherence
●
Understanding interprocessor communication and synchronization

IMPORTANT QUESTIONS FOR MID-I

 Course: B. Tech Branch: CSE Year/Semester: II/I
Subject: Computer Organization and Architecture

Answer ANY TWO of the following 2 x 15 = 30 Marks

S. No. DESCRIPTION OF QUESTION MARKS CO PO BTL

1. a) Give an example each of Zero-address, One-address, two-address and three-address 2 PO2 L1

2
instruction

b) Explain about Logical and Bit Manipulation Instructions 3 2 PO1 L2

c) Explain about Program Control Instructions 5 2 PO1 L2

d) Evaluate the following arithmetic statement using zero, one, two and three address 2 PO3 L2
5
instructions. Use the conventional symbols and instructions. X = (A+B) * (C+D).

2. a) List out the Basic Computer Registers 2 1 PO1 L1

b) Define Direct addressing mode and Indirect addressing mode 3 1 PO1 L1

Explain the different types of basic computer instructions with their formats 10 1 PO3 L2

3. a) Explain RTL and its control function. 2 1 PO1 L2

b) Define Micro operations? List out the types of Micro operations? 3 1 PO1 L1

c) Design a common bus system for 4 registers of 4 bits using Multiplexers 5 1 PO3 L3

d) Design a common bus system for 4 registers of 1 bit each using three state buffers 5 1 PO3 L3

4. a) What is a pipeline register in micro programmed control unit 2 2 PO1 L1

b) Discuss about control memory and its organization 3 2 PO1 L2

c) Differentiate between hardwired control unit and Microprogrammed control unit. Hardwired 2 PO2 L4
10
control unit is faster than micro programmed control unit. Justify this statement

IMPORTANT QUESTIONS FOR MID-II

1 Answer any two of the following(2 * 15 M = 30 M)

1.1 1

1.1.1 A) Explain parallel priority interrupt? (8.00 Marks)

Bloom's Level : Evaluate,Understand Course Outcome : C204.4

1.1.2 B) Explain Asynchronous serial transfer (7.00 Marks)

Bloom's Level : Evaluate,Understand Course Outcome : C204.4

1.2 2

1.2.1 Explain RISC pipeline or three segment instruction pipeline (15.00 Marks)

Bloom's Level : Evaluate,Understand Course Outcome : C204.5

1.3 3

1.3.1 A) Explain about types of ROM (8.00 Marks)

Bloom's Level : Evaluate,Understand Course Outcome : C204.4

1.3.2 B) What is memory address map table ? Explain with example? (7.00 Marks)

Bloom's Level : Evaluate,Understand,Remember Course Outcome : C204.4

1.4 4

1.4.1 A) Explain Division Algorithms (8.00 Marks)

Bloom's Level : Evaluate,Understand Course Outcome : C204.3

1.4.2 B) Explain the floating point additions and subtractions operations With a flow chart (7.00 Marks)

Bloom's Level : Evaluate,Understand Course Outcome : C204.3

[Link]-I & MID-II SCHEME OF EVALUATION

MID -1 SCHEME OF EVALUATION

1A) Give an example each of Zero-address, One-address, two-address and three-address instruction. [2M]

Zero address instruction Ex --- 1/2 M

One address instruction Ex --- 1/2 M
Two address instruction Ex --- 1/2 M
Three address instruction Ex – 1/2 M

Zero-address instruction
ADD
One-address instruction
LOAD A
Two-address instruction
MOV R1, A
Three-address instruction.
ADD R1, A, B

B) Explain about Logical and Bit Manipulation Instructions.[3M]

Logical and Bit Manipulation Instructions Table – 3 M

D) Explain about Program Control Instructions.[5M]

PC explanation ------------- 2 M
Instructions table ---------- 3 M
D) Evaluate the following arithmetic statement using zero, one, two and three address instructions. Use the conventional symbols and instructions. X = (A+B) * (C+D). [5M]

Zero address instruction --- 2 M

One address instruction --- 1 M
Two address instruction --- 1 M
Three address instruction –- 1 M

Zero address instruction

X = (A+B) * (C+D)
PUSH A /* TOS 🡨A */

PUSH B /* TOS 🡨 B */

ADD /* TOS 🡨 (A + B) */

PUSH C /* TOS 🡨 C */

PUSH D /* TOS 🡨 D */

ADD /* TOS 🡨 (C + D) */

MUL /* TOS 🡨 (C + D) * (A + B) */

POP X /* M[X] 🡨 TOS */

One address instruction

X = (A+B) * (C+D)
LOAD A /* AC 🡨 M[A] */

ADD B /* AC 🡨 AC + M[B] */

STORE T /* M[T] 🡨 AC */

LOAD C /* AC 🡨 M[C] */

ADD D /* AC 🡨 AC + M[D] */

MUL T /* AC 🡨 AC * M[T] */

STORE X /* M[X] 🡨AC */

Two address instruction
X = (A+B) * (C+D)
MOV R1, A /* R1 🡨 M[A] */

ADD R1, B /* R1 🡨 R1 + M[A] */

MOV R2, C /* R2 🡨M[C] */

ADD R2, D /* R2 🡨 R2 + M[D] */

MUL R1, R2 /* R1 🡨 R1 * R2 */

MOV X, R1 /* M[X] 🡨R1 */

Three address instruction

X = (A+B) * (C+D)
ADD R1, A, B /* R1 🡨 M[A] + M[B] */

ADD R2, C, D /* R2 🡨 M[C] + M[D] */

MUL X, R1, R2 /* M[X] 🡨 R1 * R2 */

2A)List out the Basic Computer Registers[2M]

Basic Computer Registers Table – 2M

B)Define Direct addressing mode and Indirect addressing mode[3M]

Direct Addressing Mode ----------- 1 ½ M

Indirect Addressing Mode --------- 1 ½ M

• Direct Addressing Mode

Instruction specifies the memory address which

can be used directly to access the memory
- Faster than the other memory addressing modes
- Too many bits are needed to specify the address
for a large physical memory space
- EA = IR(addr) (IR(addr): address field of IR)
• Indirect Addressing Mode
The address field of an instruction specifies the address of a memory location that contains the address of the operand
- When the abbreviated address is used large physical memory can be
addressed with a relatively small number of bits
- Slow to acquire an operand because of an additional memory access
- EA = M[IR(address)]
 C)Explain the different types of basic computer instructions with their formats[10M]
Instruction Formats – 3 M
Instructions Table ---- 7 M

3 A) Explain RTL and its control function.[2M]

RTL Definition ------------ 1 M
Control Function --------- 1 M
Register Transfer Language (RTL) : a symbolic notation to describe the microoperation transfers among registers.
• Conditional transfer occurs only under a control condition
• Representation of a (conditional) transfer
P: R2 ← R1
• A binary condition (P equals to 0 or 1) determines when the transfer occurs
• The content of R1 is transferred into R2 only if P is 1

B)Define Micro operations? List out the types of Micro operations? [3M]

Microoperations Definition – 1 M
Listing---------------------------- 2 M

Microoperations: operations executed on data stored in one or more registers.

⮚ Register transfer microoperations

⮚ Arithmetic microoperations
⮚ Logic microoperations
⮚ Shift microoperations

C)Design a common bus system for 4 registers of 4 bits using Multiplexers[5M]

Explanation – 2 M
Diagram ----- 3 M

D)Design a common bus system for 4 registers of 1 bit each using three state buffers[5M]
 Explanation – 2 M
Diagram ------ 3 M

4 A) What is a pipeline register in micro programmed control unit [2M]

Pipeline Reg def and explanation – 2 M

The data register is sometimes called pipeline register. It allows the execution of the microoperations specified by the control word simultaneously with the generation of the next micro instruction.

B) Discuss about control memory and its organization?[3M]

Control Memory explanation – 3 M

– Memory contains control words

• Read-only memory (ROM)

• Content of word in ROM at given address specifies microinstruction
• Each computer instruction initiates series of microinstructions (microprogram) in control memory
• These microinstructions generate microoperations to
Fetch instruction from main memory
Evaluate effective address
Execute operation specified by instruction
Return control to fetch phase for next instruction

C) Differentiate between hardwired control unit and Microprogrammed control unit. Hardwired control unit is faster than micro programmed control unit. Justify this statement.[10M]

Differences ---------- 7 M
Stmt Justification -- 3 M
 MID 2 SCHEME OF EVALUATION

1.A) Explain parallel priority interrupt? (8 M)

Explanation – 3 M

Diagrams – 5M
Priority Encoder:

B) Explain Asynchronous serial transfer (7 M)

Explanation – 5 M

Diagrams – 2 M
[Link] RISC pipeline or three segment instruction pipeline.(15 M)

Explanation – 8 M

Diagrams – 7M
3.A) Explain about types of ROM.(8 M)

Definition – 1M

Explanation – 5 M

Advantages – 1 M

ROM stands for Read Only Memory. The memory from which we can only read but cannot write on it. This type of memory is non-volatile. The information is stored permanently in such memories during manufacture. A ROM

stores such instructions that are required to start a computer. This operation is referred to as bootstrap. ROM chips are not only used in the computer but also in other electronic items like washing machine and microwave oven.

MROM (Masked ROM)

The very first ROMs were hard-wired devices that contained a pre-programmed set of data or instructions. These kind of ROMs are known as masked ROMs, which are inexpensive.

PROM (Programmable Read Only Memory)

PROM is read-only memory that can be modified only once by a user. The user buys a blank PROM and enters the desired contents using a PROM program. Inside the PROM chip, there are small fuses which are burnt open during
programming. It can be programmed only once and is not erasable.

EPROM (Erasable and Programmable Read Only Memory)

EPROM can be erased by exposing it to ultra-violet light for a duration of up to 40 minutes. Usually, an EPROM eraser achieves this function. During programming, an electrical charge is trapped in an insulated gate region. The
charge is retained for more than 10 years because the charge has no leakage path. For erasing this charge, ultra-violet light is passed through a quartz crystal window (lid). This exposure to ultra-violet light dissipates the charge.
During normal use, the quartz lid is sealed with a sticker.

EEPROM (Electrically Erasable and Programmable Read Only Memory)

EEPROM is programmed and erased electrically. It can be erased and reprogrammed about ten thousand times. Both erasing and programming take about 4 to 10 ms (millisecond). In EEPROM, any location can be selectively erased
and programmed. EEPROMs can be erased one byte at a time, rather than erasing the entire chip. Hence, the process of reprogramming is flexible but slow.

Advantages of ROM

The advantages of ROM are as follows

● Non-volatile in nature

● Cannot be accidentally changed

● Cheaper than RAMs

● Easy to test

● More reliable than RAMs

● Static and do not require refreshing

● Contents are always known and can be verified

B)What is memory address map table?Explain with example?(7 M)

Definition – 1 M
Table – 2M

Diagram – 4 M

The addressing of memory can be established by means of a table that specifies the memory address assigned to each [Link] table,called a Memory Address Map,is a pictoral representation of assigned address space for each chip in

the system.

To demonstrate with an example,assume that a system needs 512 bytes of RAM and 512 bytes of [Link] memory address map for this configuration is shown in the below table.
Memory Connection to CPU

Memory Address Map Table:

4.A) Explain Division algorithms (8 M)

Flow chart – 6 M

Problem – 2 M
B)Explain the floating point additions and subtractions operations with a flow chart.(7 M)

Explanation – 1 M

Example – 1M
Flow chart – 5 M

Floating point Addition Eg:

Floating point subtraction Eg:

 20. PREVIOUS YEAR UNIVERSITY QUESTION PAPERS

Code No: 153AG

R18
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

[Link] II Year I Semester Examinations, October – 2020

COMPUTER ORGANIZATION AND ARCHITECTURE

(Computer Science and Engineering)

Time: 3 hours Max. Marks: 75

Answer any five questions All questions carry equal marks

---

1. a) Draw the bus system for four registers and explain.

b) An 8-bit register contains the binary value 10011100. What is the register value after an Arithmetic Shift Right? Starting from the initial number 10011100, determine the register value after an

arithmetic Shift Left, and state whether there is an overflow. [7+8]

2. Draw block diagram of a control memory and the associated hardware needed for selecting the next micro instruction address. [15]

3. Perform the arithmetic operation (+42)+(-13) and (-42)-(-13) in binary using signed 2’s complement representation for negative numbers. [15]

4. a) Differentiate between Isolated I/O and memory-mapped I/O.

b) Explain programmed-I/O in detail. [8+7]

5. a) Write the major characteristics of RISC processors.

b) Draw a space-time diagram for a four-segment pipeline showing the time it takes to process six tasks and explain. [7+8]

6. a) Draw the flowchart for instruction cycle and explain.

b) Explain the following instructions: BUN, ISZ, BSA, LDA, STA. [7+8]

7. Explain various Data Manipulation instructions with examples. [15]

8. With an example, explain Booth Multiplication algorithm. [15]