The list of optimal irreducible polynomial m 10

m=3 m=4 m=5 m=6 m=7 m=8 m=9 m = 10 x3 + x + 1 x4 + x + 1 x5 + x2 + 1 x6 + x + 1 x7 + x + 1 x8 + x4 + x3 + x2 + 1 x9 + x4 + 1 x10 + x3 +1

98

Polynomial, dual and normal basis representations of GF(24), generated by the irreducible polynomial p(x)= 1 + x + x4
power of 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Standard basis 1, , 2, 3 0000 1000 0100 0010 0001 1100 0110 0011 1101 1010 0101 1110 0111 1111 1011 1001 Dual basis 1, 3, 2, 0000 1000 0001 0010 0100 1001 0011 0110 1101 1010 0101 1011 0111 1111 1110 1100 Normal basis 3, 6, 12, 9 0000 1111 1001 1100 1000 0110 0101 0100 1110 0011 0001 1010 1101 0010 1011 0111

99

Optimal dual basis to polynomial basis conversions

Irreducible polynomials p(x) for GF(2m) are given in Appendix A b dual basis coefficients a - polynomial basis coefficients [38] {b0 0 + b1 1 + ... + bm-1 m-1} {a0 + a1 + ... + am-1 m-1} a1 a2 a3 a4 a5 a6 a7 a8 b2 b1 b3 b2 b1 b0 b4 b3 b2 b5 b4 b3 b2 b1 b6 b5 b4 b3 b2 b1 b1 b0+b2 b3+b7 b6 b5 b4 b3 b2 b1 b0 b8 b7 b6 b5 b4 b1 b0 b9 b8 b7 b6 b5 b4

m a0 3 b0 4 b0 5 b1 6 b0 7 b0 8 b2 9 b3 10 b2 In general for: an irreducible trinomial of the form: xm + xp + 1 a0, a1, a2, ..., am-1 bp-1, bp-2, ..., b0, bm-1, bm-2, ... , bp an irreducible pentanomial of the form: xm + xp+2 + xp+1 + xp + 1 a0, a1, a2, ..., am-1 bp, bp-1, ..., b1, b0 + bp, bp+1 + bm-1, bm-2, ... , bp+1

a9

b3

m 3 4 5 6 7 8 9 10

a - polynomial basis coefficients b - dual basis coefficients {a0 + a1 + ... + am-1 m-1} {b0 0 + b1 1 + ... + bm-1 m-1} b0 b1 b2 b3 b4 b5 b6 b7 b8 a0 a2 a1 a0 a3 a2 a1 a1 a0 a4 a3 a2 a0 a5 a4 a3 a2 a1 a0 a6 a5 a4 a3 a2 a1 a0+a2 a1 a0 a7 a6 a5 a4 a3+a7 a3 a2 a1 a0 a8 a7 a6 a5 a4 a2 a1 a0 a9 a8 a7 a6 a5 a4

Polynomial basis to dual basis conversions

b9

a3

In general for: an irreducible trinomial of the form: xm + xp + 1 b0, b1, b2, ..., bm-1 ap-1, ap-2, ..., a0, am-1, am-2, ... , ap an irreducible pentanomial of the form: xm + xp+2 + xp+1 + xp + 1 b0, b1, b2, ..., bm-1 a0 + ap, ap-1, ..., a0, am-1, am-2, ... , ap+2, ap+1 + am-1

100

BCH codes generated by primitive elements for m 10

(n, k, t) n k t m= 3 (7, 4, 1) m= 4 (15, 11, 1) m= 5 (31, 26, 1) (31, 6, 7) m= 6 (63, 57, 1) (63, 36, 5) (63, 16, 11) m= 7 (127, 120, 1) (127, 92, 5) (127, 64, 10) (127, 36, 15) (127, 8, 31) m= 8 (255, 247, 1) (255, 215, 5) (255, 187, 9) (255, 155, 13) (255, 123, 19) (255, 91, 25) (255, 63, 30) (255, 37, 45) (255, 9, 63) m= 9 (511, 502, 1) (511, 466, 5) (511, 430, 9) (511, 394, 13) (511, 358, 18) (511, 322, 22) (511, 286, 27) (511, 250, 31) (511, 220, 39) (15, 7, 2) (31, 21, 2) (15, 5, 3) (31, 16, 3) (31, 11, 5) length of a codeword in bits number of information bits in a codeword the maximum number of errors that can be corrected

(63, 51, 2) (63, 30, 6) (63, 10, 13) (127, 113, 2) (127, 85, 6) (127, 57, 11) (127, 29, 21)

(63, 45, 3) (63, 24, 7) (63, 7, 15) (127, 106, 3) (127, 78, 7) (127, 50, 13) (127, 22, 23)

(63, 39, 4) (63, 18, 10)

(127, 99, 4) (127, 71, 9) (127, 43, 14) (127, 15, 27)

(255, 239, 2) (255, 231, 3) (255, 223, 4) (255, 207, 6) (255, 199, 7) (255, 191, 8) (255, 179, 10) (255, 171, 11) (255, 163, 12) (255, 147, 14) (255, 139, 15) (255, 131, 18) (255, 115, 21) (255, 107, 22) (255, 99, 23) (255, 87, 26) (255, 79, 27) (255, 71, 29) (255, 55, 31) (255, 47, 42) (255, 45, 43) (255, 29, 47) (255, 21, 55) (255, 13, 59)

(511, 493, 2) (511, 457, 6) (511, 421, 10) (511, 385, 14) (511, 349, 19) (511, 313, 23) (511, 277, 28) (511, 241, 36) (511, 211, 41)

(511, 484, 3) (511, 448, 7) (511, 412, 11) (511, 376, 15) (511, 340, 20) (511, 304, 25) (511, 268, 29) (511, 238, 37) (511, 202, 42) 101

(511, 475, 4) (511, 439, 8) (511, 403, 12) (511, 367, 17) (511, 331, 21) (511, 295, 26) (511, 259, 30) (511, 229, 38) (511, 193, 43)

(511, 184, 45) (511, 148, 53) (511, 112, 59) (511, 76, 85) (511, 40, 95) (511, 10, 127) m= 10 (1023, 1013, 1) (1023, 973, 5) (1023, 933, 9) (1023, 893, 13) (1023, 858, 17) (1023, 818, 21) (1023, 778, 25) (1023, 738, 29) (1023, 698, 35) (1023, 658, 39) (1023, 618, 44) (1023, 578, 49) (1023, 543, 53) (1023, 503, 58) (1023, 463, 62) (1023, 423, 75) (1023, 383, 82) (1023, 348, 87) (1023, 308, 93) (1023, 268, 103) (1023, 228, 110) (1023, 193, 118) (1023, 153, 125) (1023, 121, 171) (1023, 86, 183) (1023, 46, 219) (1023, 11, 255)

(511, 175, 46) (511, 166, 47) (511, 157, 51) (511, 139, 54) (511, 130, 55) (511, 121, 58) (511, 103, 61) (511, 94, 62) (511, 85, 63) (511, 67, 87) (511, 58, 91) (511, 49, 93) (511, 31, 109) (511, 28, 111) (511, 19, 119)

(1023, 1003, 2) (1023, 963, 6) (1023, 923, 10) (1023, 883, 14) (1023, 848, 18) (1023, 808, 22) (1023, 768, 26) (1023, 728, 30) (1023, 688, 36) (1023, 648, 41) (1023, 608, 45) (1023, 573, 50) (1023, 533, 54) (1023, 493, 59) (1023, 453, 63) (1023, 413, 77) (1023, 378, 83) (1023, 338, 89) (1023, 298, 94) (1023, 258, 106) (1023, 218, 111) (1023, 183, 119) (1023, 143, 126) (1023, 111, 173) (1023, 76, 187) (1023, 36, 223)

(1023, 993, 3) (1023, 953, 7) (1023, 913, 11) (1023, 873, 15) (1023, 838, 19) (1023, 798, 23) (1023, 758, 27) (1023, 718, 31) (1023, 678, 37) (1023, 638, 42) (1023, 598, 46) (1023, 563, 51) (1023, 523, 55) (1023, 483, 60) (1023, 443, 73) (1023, 403, 78) (1023, 368, 85) (1023, 328, 90) (1023, 288, 95) (1023, 248, 107) (1023, 208, 115) (1023, 173, 122) (1023, 133, 127) (1023, 101, 175) (1023, 66, 189) (1023, 26, 239)

(1023, 983, 4) (1023, 943, 8) (1023, 903, 12) (1023, 863, 16) (1023, 828, 20) (1023, 788, 24) (1023, 748, 28) (1023, 708, 34) (1023, 668, 38) (1023, 628, 43) (1023, 588, 47) (1023, 553, 52) (1023, 513, 57) (1023, 473, 61) (1023, 433, 74) (1023, 393, 79) (1023, 358, 86) (1023, 318, 91) (1023, 278, 102) (1023, 238, 109) (1023, 203, 117) (1023, 163, 123) (1023, 123, 170) (1023, 91, 181) (1023, 56, 191) (1023, 16, 247)

bold - n < (m+2) * t -2: interleave = 2 (see Section 4.4.3.1) bold italic - 2n < (m+2) * t -2: interleave = 3

102

Encoder control system - the illustration how the C program, templates and VHDL files work together
C program
/* The function for coping a template into a VHDL file. */ void CopyFile(fin, fout) /* fin -an input (template) file, fout -an output (VHDL) file*/ FILE *fin, *fout; /* variable declarations */ { char c; c=getc(fin); /* read a character from the input file */ while(c!='#' && c!=EOF) /* while the read character is not # or End Of File*/ { putc(c,fout); c= getc(fin); } /* copy the input file into the output file */ }

/* Print an And statement that =1 if cout== i for a finite field counter */ void PrintAndCout(fo, i) FILE *fo; int i; { int f, mask, lx; lx=LPow(i); /* lx=i =a0 , a11,... , am-1m-1 */ mask=one; /* the mask equals 0 */ if((mask & lx)==0) fprintf(fo," NOT"); /* if a0 bit of lx is zero print NOT */ fprintf(fo, " cout(0)"); /* print to the file cout(0) */ mask>>=1; /* shift the mask to represent the j+1 bit */ for(f=1; f<m; f++) { fprintf(fo," AND"); if((mask & lx)==0) fprintf(fo," NOT"); /* if the af bit of lx is zero print NOT */ fprintf(fo, " cout(%d)",f); /* print to the file cout(f) */ mask>>=1; /* shift the mask to represent the j+1 bit */ } } /* Print a LFSR for a counter */ void PrintCoutRing(fo) FILE *fo; { int f, mask; mask=one; mask>>=1; /* the mask =x1 */ for(f=1; f<m; f++) { if(mask & gen_basis)/*gen_basis -the irreducible polynomial in GF(2m) (Appendix A)*/ fprintf(fo,"\tcout(%d)<= (cout(%d) XOR cout(m-1)) AND NOT reset;\n",f,f-1); else fprintf(fo,"\tcout(%d)<= cout(%d) AND NOT reset;\n",f,f-1); mask>>=1; /* mask = xf+1 */ }}

103

Fragment of C executable program ... CopyFile(fi,fo); PrintAndCout(fo,k-1); CopyFile(fi,fo); PrintAndCout(fo,n-1); CopyFile(fi,fo); PrintCoutRing(fo); CopyFile(fi,fo); ... /* the beginning ecount*/ /* for the vdinR signal the AND statement */ /* for the vdinS signal the AND statement */ /* for a LFSR in a counter */ /* finishing ecount and beginning enc */

Template
The fragment of the bch.vht template for a counter modulo 15 (using multiplication by ) for the (15, 5) BCH code encoder. -- COUNTER MODULO n FOR the (n,k) BCH ENCODER USE WORK.const.ALL; ENTITY ecount IS PORT (clk, reset: IN BIT; vdin: OUT BIT); --vdin - valid data in - vdin=1 if 0 count < k END ecount; ARCHITECTURE ecounta OF ecount IS SIGNAL cout: BIT_VECTOR(0 TO m-1); -- cout in GF(2^m); cout= L^count SIGNAL vdinR, vdinS, vdin1: BIT; BEGIN vdinR<=#; -- Run PrintAndCout(fo,k-1) C function -- synchronous reset of vdin1 register if cout==k-1 vdinS<= (#) OR reset; -- Run PrintAndCout(fo,n-1) C function -- synchronous set vdinS=1 if cout==n-1 vdin<= vdin1 AND NOT reset; -- output signal vdin is related with vdin1 register PROCESS BEGIN -- vdin1 register circuit WAIT UNTIL clk'EVENT AND clk='1'; IF vdinR='1' THEN vdin1<= '0'; ELSIF vdinS='1' THEN vdin1<= '1'; END IF; END PROCESS; PROCESS BEGIN -- increment or reset the cout in the LFSR, cout=L^count WAIT UNTIL clk'EVENT AND clk='1'; cout(0)<= cout(m-1) OR reset; # END PROCESS; -- run PrintCoutRing(fo) C function END ecounta; 104

VHDL
The fragment of the enc.vhd file for the control system for an encoder -- COUNTER MODULO n FOR the (n,k) BCH ENCODER USE WORK.const.ALL; ENTITY ecount IS PORT (clk, reset: IN BIT; vdin: OUT BIT); --vdin - valid data in - vdin=1 if 0 count < k END ecount; ARCHITECTURE ecounta OF ecount IS SIGNAL cout: BIT_VECTOR(0 TO m-1); -- cout in GF(2^m); cout= L^count SIGNAL vdinR, vdinS, vdin1: BIT; BEGIN vdinR<= cout(0) AND cout(1) AND NOT cout(2) AND NOT cout(3); -- the synchronous reset of the vdin1 register if cout==k-1 vdinS<= ( cout(0) AND NOT cout(1) AND NOT cout(2) AND cout(3)) OR reset; -- the synchronous set of the vdinS=1 if cout==n-1 vdin<= vdin1 AND NOT reset; -- output signal vdin is related with vdin1 register PROCESS BEGIN -- the vdin1 register circuit WAIT UNTIL clk'EVENT AND clk='1'; IF vdinR='1' THEN vdin1<= '0'; ELSIF vdinS='1' THEN vdin1<= '1'; END IF; END PROCESS; PROCESS BEGIN -- increment or reset the cout in the LFSR, cout=L^count WAIT UNTIL clk'EVENT AND clk='1'; cout(0)<= cout(m-1) OR reset; cout(1)<= (cout(0) XOR cout(m-1)) AND NOT reset; cout(2)<= cout(1) AND NOT reset; cout(3)<= cout(2) AND NOT reset; END PROCESS; END ecounta;

105

Constant values file: const.vhd

for a (15, 5) triple error correcting BCH code. -- File generated by bch.exe program. -- The constant package for BCH code (15,5), t=3 -- Option= 3, Interleave= 2, -- with optimisation. -- GF(2^4) is generated by polynomial [1+x+...] - 11001; -- Constants necessary for the decoder and encoder PACKAGE const IS CONSTANT m: INTEGER:= 4; CONSTANT n: INTEGER:= 15; -- n= 2^m -1 -size of block CONSTANT k: INTEGER:= 5; -- BCH code (n,k) -no. of information bits CONSTANT nk: INTEGER:= 10; -- nk=n-k CONSTANT t: INTEGER:= 3; -- no. of errors to be corrected CONSTANT sizea: INTEGER:= 3; -- size of counter ca CONSTANT sizeb: INTEGER:= 3; -- size of counter cb -- count = iteration* cb + ca CONSTANT sizel: INTEGER:= 3; -- size of l register (degree of error polynomial in the BMA) END const;

106

The (15,5) BCH code encoder

LFSR for the encoder USE WORK.const.ALL; ENTITY ering IS PORT (clk, rll, din: IN BIT; -- rll - ring loop lock (feedback enable) dout: OUT BIT); --output serial data END ering; ARCHITECTURE eringa OF ering IS SIGNAL rin, rout: BIT_VECTOR(0 TO nk-1); -- ring register SIGNAL rin0: BIT; BEGIN dout<= rout(nk-1); rin0 <= (din XOR rout(nk-1)) AND rll; rin(0)<= rin0; rin(1)<= rout(0) XOR rin0; rin(2)<= rout(1) XOR rin0; rin(3)<= rout(2); rin(4)<= rout(3) XOR rin0; rin(5)<= rout(4) XOR rin0; rin(6)<= rout(5); rin(7)<= rout(6); rin(8)<= rout(7) XOR rin0; rin(9)<= rout(8); -- Polynomial generating encoder: a0+a1*x+a2*x^2+... -- 11101100101 -- Number of XOR gates= 5 PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk='1'; rout<= rin; END PROCESS; END eringa; Ecount entity has been presented in Appendix E. -----------------------------------------------------------------ENCODER USE WORK.const.ALL; ENTITY enc IS PORT (clk, reset, din: IN BIT; vdin, dout: OUT BIT); --dout- serial data output to be transmitted END enc; -- vdin - valid data in (input of information bits is enable)-- to enable external data shifting 107

ARCHITECTURE enca OF enc IS SIGNAL vdin1, rin, rout, rll: BIT; -- rll-ring loop lock, rin -ring (LFSR) in, rout - ring out COMPONENT ecount --counter encoder PORT(clk, reset: IN BIT; vdin: OUT BIT); END COMPONENT; FOR ALL: ecount USE ENTITY WORK.ecount (ecounta); COMPONENT ering --ring for encoder (LFSR) PORT(clk, rll, din: IN BIT; dout: OUT BIT); END COMPONENT; FOR ALL: ering USE ENTITY WORK.ering (eringa); BEGIN c1: ecount PORT MAP (clk, reset, vdin1); r1: ering PORT MAP (clk, rll, rin, rout); rin<= din AND NOT reset; rll<= vdin1 AND NOT reset; vdin<= vdin1; PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk='1'; dout<= (NOT vdin1 AND rout) OR (vdin1 AND rin); -- the output register END PROCESS; END enca;

108

Calculation of the syndromes for the (15, 5) BCH code

USE WORK.const.ALL; -- syndromes S1, S2, S4 - calculated in the -- the second way -- the minimal polynomial f1(x) = 1 + x + x4.

ENTITY dsyn1 IS PORT (clk, ce, pe ,din: IN BIT; dout1, dout2, dout4: OUT BIT_VECTOR(0 TO m-1)); END dsyn1; ARCHITECTURE dsyn1a OF dsyn1 IS SIGNAL syn: BIT_VECTOR(0 TO 5); BEGIN syn(4)<= syn(1) XOR syn(3); -- 2 syn(5)<= syn(0) XOR syn(2); -- 1 -- Saving due to optimisation = 3 dout1(0 TO m-1)<= syn(0 TO m-1); dout2(0)<= syn(5); dout2(1)<= syn(2); dout2(2)<= syn(4); dout2(3)<= syn(3); dout4(0)<= syn(4) XOR syn(5); dout4(1)<= syn(4); dout4(2)<= syn(2) XOR syn(3); dout4(3)<= syn(3); PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk='1'; IF pe='1' THEN syn(0)<= din; syn(1 TO 3)<= "000"; ELSIF ce='1' THEN syn(0)<= syn(3) XOR din; syn(1)<= syn(0) XOR syn(3); syn(2)<= syn(1); syn(3)<= syn(2); END IF; END PROCESS; END dsyn1a; USE WORK.const.ALL; -- S3 - calculated in the first way *3 ENTITY dsyn3 IS PORT (clk, ce, pe ,din: IN BIT; dout3: OUT BIT_VECTOR(0 TO m-1)); END dsyn3; ARCHITECTURE dsyn3a OF dsyn3 IS SIGNAL syn: BIT_VECTOR(0 TO 3); 109

BEGIN dout3<= syn; PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk='1'; IF pe='1' THEN syn(0)<= din; syn(1 TO 3)<= "000"; ELSIF ce='1' THEN syn(0)<= din XOR syn(1); syn(1)<= syn(1) XOR syn(2); syn(2)<= syn(2) XOR syn(3); syn(3)<= syn(0) XOR syn(3); END IF; END PROCESS; END dsyn3a; USE WORK.const.ALL; -- S5 - in the second way -- the minimal polynomial f3(x) = 1 + x - the degree of the polynomial -- is less than m thus only 2 (not 4) registers are required, -- and the second way of the syndrome calculation is selected ENTITY dsyn5 IS PORT (clk, ce, pe ,din: IN BIT; dout5: OUT BIT_VECTOR(0 TO m-1)); END dsyn5; ARCHITECTURE dsyn5a OF dsyn5 IS SIGNAL syn: BIT_VECTOR(0 TO 1); BEGIN -- Saving due to optimisation = 0 dout5(0)<= syn(0); dout5(1)<= syn(1); dout5(2)<= syn(1); dout5(3)<= '0'; PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk='1'; IF pe='1' THEN syn(0)<= din; syn(1 TO 1)<= "0"; ELSIF ce='1' THEN syn(0)<= syn(1) XOR din; syn(1)<= syn(0) XOR syn(1); END IF; END PROCESS; END dsyn5a;

110

Chien search for the (15,5) BCH code

USE WORK.const.ALL; ENTITY dch1 IS -- for x^1 PORT (clk, ce, pe: IN BIT; din: IN BIT_VECTOR(0 TO m-1); dout: OUT BIT_VECTOR(0 TO m-1)); END dch1; ARCHITECTURE dch1a OF dch1 IS SIGNAL chin: BIT_VECTOR(0 TO m-1); -- registers input SIGNAL ch: BIT_VECTOR(0 TO 3); -- ch registers and optimisation BEGIN dout<= ch(0 TO m-1); chin(0)<= ch(3); chin(1)<= ch(0) XOR ch(3); chin(2)<= ch(1); chin(3)<= ch(2); PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk='1'; IF pe='1' THEN ch(0 TO m-1)<= din; ELSIF ce='1' THEN ch(0 TO m-1)<= chin; END IF; END PROCESS; -- the number of XOR gates= 1; END dch1a; USE WORK.const.ALL; ENTITY dch2 IS -- for x^2 PORT (clk, ce, pe: IN BIT; din: IN BIT_VECTOR(0 TO m-1); dout: OUT BIT_VECTOR(0 TO m-1)); END dch2; ARCHITECTURE dch2a OF dch2 IS SIGNAL chin: BIT_VECTOR(0 TO m-1); -- registers input SIGNAL ch: BIT_VECTOR(0 TO 3); -- ch registers and optimisation BEGIN dout<= ch(0 TO m-1); chin(0)<= ch(2); chin(1)<= ch(2) XOR ch(3); chin(2)<= ch(0) XOR ch(3); chin(3)<= ch(1); PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk='1'; IF pe='1' THEN ch(0 TO m-1)<= din; ELSIF ce='1' THEN 111

ch(0 TO m-1)<= chin; END IF; END PROCESS; -- the number of XOR gates= 2; END dch2a; USE WORK.const.ALL; ENTITY dch3 IS PORT (clk, ce, pe: IN BIT; din: IN BIT_VECTOR(0 TO m-1); dout: OUT BIT_VECTOR(0 TO m-1)); END dch3; ARCHITECTURE dch3a OF dch3 IS SIGNAL chin: BIT_VECTOR(0 TO m-1); -- registers input SIGNAL ch: BIT_VECTOR(0 TO 3); -- ch registers and optimisation BEGIN dout<= ch(0 TO m-1); chin(0)<= ch(1); chin(1)<= ch(1) XOR ch(2); chin(2)<= ch(2) XOR ch(3); chin(3)<= ch(0) XOR ch(3); PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk='1'; IF pe='1' THEN ch(0 TO m-1)<= din; ELSIF ce='1' THEN ch(0 TO m-1)<= chin; END IF; END PROCESS; -- the number of XOR gates= 3; END dch3a; -----------------------------------------------------------------------USE WORK.const.ALL; ENTITY dcheq IS -- Find if chien search circuit equals 0 PORT (din1, din2, din3: IN BIT_VECTOR(0 TO m-1); dout: OUT BIT); -- dout=1 if equals zero END dcheq; ARCHITECTURE dcheqa OF dcheq IS SIGNAL eq: BIT_VECTOR(0 TO m-1); BEGIN eq(0)<= NOT din1(0) XOR din2(0) XOR din3(0); --NOT because ch0=1000 eq(1)<= din1(1) XOR din2(1) XOR din3(1); eq(2)<= din1(2) XOR din2(2) XOR din3(2); eq(3)<= din1(3) XOR din2(3) XOR din3(3); dout<= NOT (eq(0) OR eq(1) OR eq(2) OR eq(3)); END dcheqa;

112

Raising to the power three in GF(25) with design optimisation

VHDL entity for exponentiation to the power 3 in GF(25) with design optimisation
ENTITY dpow3 IS PORT (din: IN BIT_VECTOR(0 TO m-1); dout: OUT BIT_VECTOR(0 TO m-1)); END dpow3; ARCHITECTURE dpow3a OF dpow3 IS SIGNAL dxor: BIT_VECTOR(0 TO 21); BEGIN dxor(0 TO m-1)<= din; dxor(5)<= din(0) AND din(1); dxor(6)<= din(0) AND din(2); dxor(7)<= din(0) AND din(3); dxor(8)<= din(0) AND din(4); dxor(9)<= din(1) AND din(2); dxor(10)<= din(1) AND din(3); dxor(11)<= din(1) AND din(4); dxor(12)<= din(2) AND din(3); dxor(13)<= din(2) AND din(4); dxor(14)<= din(3) AND din(4); dxor(15)<= dxor(8) XOR dxor(9); -- 2 dxor(16)<= dxor(2) XOR dxor(3); -- 1 dxor(17)<= dxor(4) XOR dxor(5); -- 1 dxor(18)<= dxor(6) XOR dxor(13); -- 1 dxor(19)<= dxor(10) XOR dxor(12); -- 1 dxor(20)<= dxor(14) XOR dxor(15); -- 1 dxor(21)<= dxor(18) XOR dxor(20); -- 1 -- optimisation saving = 8 XOR gates dout(0)<= dxor(0) XOR dxor(15) XOR dxor(19); dout(1)<= dxor(7) XOR dxor(14) XOR dxor(16) XOR dxor(17); dout(2)<= dxor(17) XOR dxor(21); dout(3)<= dxor(1) XOR dxor(4) XOR dxor(8) XOR dxor(12) XOR dxor(13) XOR dxor(16); dout(4)<= dxor(3) XOR dxor(11) XOR dxor(19) XOR dxor(21); -- 21 XOR gates END dpow3a;

113

Bit-parallel multiplications
Common SDBM, VHDL (the serial dual basis multiplier) USE WORK.const.ALL; ENTITY dsdbm IS PORT (dbin, sbin: IN BIT_VECTOR(0 TO m-1); -- standard & dual basis input dout: OUT BIT); -- serial output END dsdbm; ARCHITECTURE dsdbma OF dsdbm IS SIGNAL dxor: BIT_VECTOR(0 TO m-1); -- xor gates signals BEGIN dout<= dxor(m-1); dxor(0)<= sbin(0) AND dbin(0); gen: FOR i IN 1 TO m-1 GENERATE dxor(i)<= dxor(i-1) XOR (sbin(i) AND dbin(i)); END GENERATE; END dsdbma; Parallel Dual basis multiplier in GF(24) USE WORK.const.ALL; ENTITY dpdbm IS PORT (ddin, dsin: IN BIT_VECTOR(0 TO m-1); dout: OUT BIT_VECTOR(0 TO m-1)); END dpdbm; ARCHITECTURE dpdbma OF dpdbm IS SIGNAL a: BIT_VECTOR(0 TO 2*m-2); COMPONENT dsdbm -- Serial Dual Basis Multiplier without registers PORT (dbin, sbin: IN BIT_VECTOR(0 TO m-1); -- dual & standard basis in dout: OUT BIT); END COMPONENT; FOR ALL: dsdbm USE ENTITY WORK.dsdbm (dsdbma); BEGIN a(0 TO m-1)<= ddin; a(4)<= a(0) XOR a(1); a(5)<= a(1) XOR a(2); a(6)<= a(2) XOR a(3); m0: dsdbm PORT MAP (a(0 TO 3), dsin, dout(0)); m1: dsdbm PORT MAP (a(1 TO 4), dsin, dout(1)); m2: dsdbm PORT MAP (a(2 TO 5), dsin, dout(2)); m3: dsdbm PORT MAP (a(3 TO 6), dsin, dout(3)); 114

END dpdbma;

Standard basis multiplier, PSBML in GF(24)

USE WORK.const.ALL; ENTITY dpm IS PORT (din1, din2: IN BIT_VECTOR(0 TO m-1); dout: OUT BIT_VECTOR(0 TO m-1)); END dpm; ARCHITECTURE dpma OF dpm IS COMPONENT dsdbm -- the Serial Dual Basis Multiplier (without registers) PORT (dbin, sbin: IN BIT_VECTOR(0 TO m-1); -- dual & standard basis in dout: OUT BIT); END COMPONENT; FOR ALL: dsdbm USE ENTITY WORK.dsdbm (dsdbma); SIGNAL b: BIT_VECTOR(0 TO 6); -- in the approach presented in Section 2.5.3 -- m bit_vectors(0 to m-1) are required. But it can be seen that most of this signals -- are the same. Therefore in this approach only different signals are considered. -- Therefore the number of the b signal bits is m+(m-1)*(H(pp)-2) SIGNAL c0, c1, c2, c3: BIT_VECTOR(0 TO m-1); BEGIN b(0 TO m-1)<= din1; b(4)<= b(0) XOR b(3); b(5)<= b(3) XOR b(2); b(6)<= b(2) XOR b(1); c0<= b(0) & b(3) & b(2) & b(1); m0: dsdbm PORT MAP (din2, c0, dout(0)); c1<= b(1) & b(4) & b(5) & b(6); m1: dsdbm PORT MAP (din2, c1, dout(1)); c2<= b(2) & b(1) & b(4) & b(5); m2: dsdbm PORT MAP (din2, c2, dout(2)); c3<= b(3) & b(2) & b(1) & b(4); m3: dsdbm PORT MAP (din2, c3, dout(3)); END dpma;

115

Finite field inversion

q1: qsq drdce x1: din dmul21 q2: drdrDualOne msin sq s1: dsq m1: dpdbm mout

mdin

dout

The circuit for carrying out the Fermat inversion and bit-parallel multiplication. q1: drdce - m * registers with clock enable s1: dsq - squaring in the polynomial basis x1: dmul21 - m * (2:1 multiplexer) m1: dpdbm -the bit-parallel dual basis multiplier (see Appendix K). q2: drsrDualOne- m* registers with clock enable, synchronous reset to the dual basis value 1, e.g. for m=5, reset value = 01000. clock 0 1- m-2 m-1 m algorithm mdin 1; msin= dinr; qsq dinr2 msin = qsq; qsq qsq2; mdin mdin * msin msin = qsq; mdin mdin * msin, dout= dinr-1 msin = dinr+1; qsq dinr+12 ; mdin= dinr-1; dout = dinr-1 * dinr+1; mdin 1;

116

Single error correcting decoders

b1: dbuf err din syn1 s1: dsyn1 ch1 h1: dch1

dout count: dcount reset

The block diagram for SEC decoders. The fragment of sim.txt file for a (15, 11) BCH code decoder: entity name - description the numbers of used registers and 2 input XOR gates dcount - counter - control system Reg= 4 XOR= 1 dsyn1 - syndromes 1 Reg= 4 XOR= 2 dch1 - Chien Search for x^1 Reg= 4 XOR= 1 dbuf - buffer for data to be corrected Reg= 17 XOR= 1 dec - DECODER total Reg= 29 XOR= 5

117

Double error correcting decoders

din b1: dbuf dout

s1: dsyn1 s3: dsyn3

syn1

h1: dch1 h3: dch3

ch1 e1: deq neq

f1: ffce f2: ffce c1: dcount

syn3

ch3

The block diagram for DEC decoders. The fragment of sim.txt file for a (15, 7) BCH code decoder: ffce - flip flop register Reg= 1 XOR= 0 dcount - counter - control system Reg= 4 XOR= 1 dbuf - buffer for data to be corrected Reg= 17 XOR= 1 ----SYNDROMES---dsyn1 - syndromes 1 Reg= 4 dsyn3 - syndromes 3 Reg= 4 SYNDROMES -- total total Reg= 8

XOR= 2 XOR= 4 XOR= 6

---- Chien search ---dpow3 - dout<= din^3 Reg= 0 XOR= 13 deq - comparison dout<= 1 if (ch1)^3== ch3 - this entity includes dpow3 entity Reg= 0 XOR= 4 total Reg= 0 XOR= 17 dch1 - Chien Search for x^1 Reg= 4 XOR= 1 dch3 - Chien Search for x^3 Reg= 4 XOR= 3 CHIEN SEARCH - total including dcheq total Reg= 8 XOR= 21 ------ DECODER -----total Reg= 38 XOR= 29

Fragment of VHDL for (15,7) DEC code.

118

Chien search - this circuit is similar as for general case, but requires two additional input signals, for assumption that an error has occurred (errcheck) and for correction the error if it has been found (err). USE WORK.const.ALL; ENTITY dch3 IS PORT (clk, err, errcheck, pe: IN BIT; din: IN BIT_VECTOR(0 TO m-1); dout: OUT BIT_VECTOR(0 TO m-1)); END dch3; ARCHITECTURE dch3a OF dch3 IS SIGNAL ch0reg: BIT; SIGNAL chin: BIT_VECTOR(0 TO m-1); -- registers input SIGNAL ch: BIT_VECTOR(0 TO 3); -- ch registers and optimisation BEGIN ch0reg<= ch(0) XOR err; -- error was found so correct it dout(0)<= ch(0) XOR errcheck; -- suppose that an error has occurred dout(1 TO m-1)<= ch(1 TO m-1); chin(0)<= ch(1); chin(1)<= ch(1) XOR ch(2); chin(2)<= ch(2) XOR ch(3); chin(3)<= ch0reg XOR ch(3); PROCESS BEGIN WAIT UNTIL clk'EVENT AND clk='1'; IF pe='1' THEN ch(0 TO m-1)<= din; ELSE ch(0 TO m-1)<= chin; END IF; END PROCESS; -- number XOR gates= 3; END dch3a; The main entity -- the decoder circuit USE WORK.const.ALL; ENTITY dec IS PORT (clk, reset, din: IN BIT; vdout, dout: OUT BIT); END dec;

--vdout - valid data out

ARCHITECTURE deca OF dec IS SIGNAL pe, cef, cefa, vdout1, din_reset: BIT; --pe -parallel enable for Chien search and reset for dsyn; -- cef- ce SIGNAL ff1, ff3, err, err1, err2, errcheck, neq: BIT; -- ff1, ff3 registers to remember previous number of errors -- err - correct error, err1 - single error found, err2- double -- errcheck - assumption that an error has occurred (should be zero for initialisation) SIGNAL syn1, syn3: BIT_VECTOR(0 TO m-1); -- syndromes 119

SIGNAL ch1, ch3: BIT_VECTOR(0 TO m-1); -- Chien search output SIGNAL ch1_or: BIT_VECTOR(0 TO m-1); -- for sum of ch1 ... declaration of components ... BEGIN c1: dcount PORT MAP (clk, reset, cef, pe, vdout, vdout1); b1: dbuf PORT MAP (clk, err, vdout1, din_reset, dout); e1: deq PORT MAP (ch1, ch3, neq); f1: ffce PORT MAP (clk, cefa, ch1_or(m-1), ff1); f2: ffce PORT MAP (clk, cefa, neq, ff3); s1: dsyn1 PORT MAP (clk, pe, din_reset, syn1); s3: dsyn3 PORT MAP (clk, pe, din_reset, syn3); h1: dch1 PORT MAP (clk, err, errcheck, pe, syn1, ch1); h3: dch3 PORT MAP (clk, err, errcheck, pe, syn3, ch3); din_reset<= din AND NOT reset; -- ch1_or eq_or gates ch1_or(0)<= ch1(0); gen: FOR i IN 1 TO m-1 GENERATE ch1_or(i)<= ch1_or(i-1) OR ch1(i); END GENERATE; -- cefa - clock enable p1, p3 - cefa=1 if start of a new word or err cefa <= cef OR err; -- error decision circuit err1<= NOT ff3 AND NOT neq AND ff1 AND NOT ch1_or(m-1); --single err err2<= ff1 AND ch1_or(m-1) AND ff3 AND NOT neq; -- double error err<= err1 OR err2; -- error has been found errcheck<= NOT cef; -END deca;

120

TMEC decoders and the BMA with inversion

xdr: dmul21 dra inv: dinv drpd mli: dmli qd dli xdm: dmul21 dmi dring: dsdbmRing

syn1

dr
msm: dssbm cs(m-1) ms(m-1): dxort sn(t)en

qdd: drdce

dm
cc(t-2)out b(t-2)out dm mb(t): b(t)out dsdbm xb(t): dmul21 b(t)in b(t): drdce

sn(t): dandm

c(t)out

c(t): dshr

cin(t)

sn(t)out dm(0) b2out cc2: drdce b2: drd1ce cc2out

c2out cs(1) c1out

c2: dshr

cin(2)

mb(2) and

ms1: dxort cs(0) ms0: dxort

sn1e: dandm

c1: dshpe

syn1

sn0: dandm

c0first

Berlekamp Massey Algorithm

sn0out sn0: drdce sn0in x0: dmul21 sn(2t-3)out syn1

sn1out sn1: drdce sn1in x1: dmul21 syn2

sn2out sn2: drdce sn2in x2: dmul21 syn3

syndromes rearranging

sn(2t-2)out sn(2t-2): drdce sn(2t-2)in x(2t-2): dmul21

sn(2t-4)out syn(2t-1)

The circuit for the BMA with inversion

121

The description of the BMA entities. xdr - 2:1 multiplexer to initialise the inverter with S1 value (if S1 0) (see equ(3.17)) inv - inverter /division drpd<= dra current/dra previous (see Appendix L) drpd- the dual basis representation, drpd- the polynomial basis representation. mli, qdd, xdm, dring - the basis rearranging circuit (see Fig. 2.9) for m 8 b(i) - registers to store value (x)= b2x2 + ... +bixi + ... btxt (see equ(3.18)) xb(i) - 2:1 multiplexer for selecting the new value of (r+1)(x) mb(i) - the SDBM (without registers) (see Fig. 2.9) for multiplication drp i(x) (equ(4.3)) c(i) - registers to store values i (similar to registers C0-3 on Fig. 2.9) with summation cc(i) - registers to store the previous value of the ci registers sn(i) - m 2-input AND gates for the multiplication Sj i. ms(i) - (t-1) XOR gates for the summation in the Sum of Products architecture (see Fig2.6) msm - the LFSR for the Sum of Products (part A)

The fragment of the sim.txt file for a decoder of the (63, 18) 10 error correction BCH code option 3 with inversion (with design optimisation):
--------------- Syndromes calculation -----------dsyn1 - syndromes 1 2 4 8 16 Reg= 6 XOR= 15 dsyn3 - syndromes 3 6 12 Reg= 6 XOR= 14 dsyn5 - syndromes 5 10 17 Reg= 6 XOR= 14 dsyn7 - syndromes 7 14 Reg= 6 XOR= 12 dsyn9 - syndromes 9 18 Reg= 3 XOR= 4 dsyn11 - syndromes 11 Reg= 6 XOR= 9 dsyn13 - syndromes 13 19 Reg= 6 XOR= 13 dsyn15 - syndromes 15 Reg= 6 XOR= 15 total Reg= 45 XOR= 96 --------------- Chien Search -----------dcheq - check if Chien search equal zero - found an error Reg= 0 XOR= 54 dch1 - Chien Search for x^1 Reg= 6 XOR= 1 dch2 - Chien Search for x^2 Reg= 6 XOR= 2 dch3 - Chien Search for x^3 Reg= 6 XOR= 3 dch4 - Chien Search for x^4 Reg= 6 XOR= 4 dch5 - Chien Search for x^5 Reg= 6 XOR= 5 dch6 - Chien Search for x^6 Reg= 6 XOR= 6 dch7 - Chien Search for x^7 Reg= 6 XOR= 7 dch8 - Chien Search for x^8 Reg= 6 XOR= 7

122

dch9 - Chien Search for x^9 Reg= 6 XOR= 7 dch10 - Chien Search for x^10 Reg= 6 XOR= 7 total Reg= 60 XOR= 103 --------------- Syndromes rearranging -----------dmul21 - 2 to 1 multiplexers Reg= 0 * 19 = 0 XOR= 0 * 19 = 0 drdce - m registers with clock enable Reg= 6 * 19 = 114 XOR= 0 * 19 = 0 total Reg= 114 XOR= 0 --------------- the Berlekamp-Massey Algorithm ---dmul21 - 2 to 1 multiplexers Reg= 0 * 8 = 0 XOR= 0 * 8 = 0 dmli - multiply by L^i Reg= 0 XOR= 1 dinv - inversion/division Reg= 12 XOR= 38 dsdbmRing - bit-Serial Dual Basis Multiplier Ring Reg= 6 XOR= 1 drdce - m registers with clock enable Reg= 6 * 14 = 84 XOR= 0 * 14 = 0 drdceSOne - m registers with set to one Reg= 6 * 2 = 12 XOR= 0 * 2 = 0 drd1ce - single register with clock enable Reg= 1 * 2 = 2 XOR= 0 * 2 = 0 dsdbm - bit-serial dual basis multiplier Reg= 0 * 8 = 0 XOR= 5 * 8 = 40 dshpe - m shift registers (ring) with parallel enable Reg= 6 XOR= 0 dshr - m shift registers (ring) with reset and addition Reg= 6 * 9 = 54 XOR= 1 * 9 = 9 dandm - m AND gates Reg= 0 * 11 = 0 XOR= 0 * 11 = 0 dxort - t XOR gates Reg= 0 * 6 = 0 XOR= 10 * 6 = 60 dssbm - bit-serial standard basis multiplier Reg= 6 XOR= 7 total Reg= 182 XOR= 156 --------------- The buffer ---dbuf - buffer for storing data to be corrected Reg= 37 XOR= 1 total Reg= 37 XOR= 1 --------------- The control system ---dci - interleave counter Reg= 1 XOR= 0 dca - less significant control counter Reg= 3 XOR= 2 dcb - more significant control counter Reg= 4 XOR= 3 dcl - degree of error polynomial Reg= 4 XOR= 5 drd1ce - single register Reg= 1 * 5 = 5 XOR= 0 * 5 = 0

123

dcount - control system total Reg= 17 DECODER total Reg= 455

XOR= 10 XOR= 366

124

TMEC decoders and the inversionless BMA

xqdp: dmul21

qdpIn

qdp: drdceSOne

dp c(t)out b(t-2)out xb(t): dmul21 b(t)in b(t): drdcer mc(t): dpm b2: drdceSOne mc2: dpm mc1: dpm dp

syn1

dr
msm: drdce cs(m-1) ms(m-1): dxort m(t)out c(t)out dr mb(t): dpm

b(t)out

m(t): dpm

c(t): drdcer

c(t)in

mb(t)out mc(t)out cs(t): dxorm mb2: dpm b2out

sn(t)out

dr

c0out

cs(1) ms1: dxort cs(0) ms0: dxort m0: dpm m1: dpm

c2out c1out

c2: drdcer

c2in

mb2out mc2out cs2: dxorm xc1: dmul21 mc1out syn1

dp

c1: drdcer

c1in

dp

c0out

c0: drdceSOne

mc0out

mc0: dpm

dp

Berlekamp Massey Algorithm

sn(2t-2)out sn(2t-2): drdce sn(2t-2)in x(2t-2): dmul21

sn0out sn0: drdce sn0in x0: dmul21 sn(2t-3)out syn1

sn1out sn1: drdce sn1in x1: dmul21 syn2

sn2out sn2: drdce sn2in x2: dmul21 syn3

Syndromes rearranging

sn(2t-4)out syn(2t-1)

The circuit for the inversionless BMA.

125

The fragment of the sim.txt file for the decoder of the (63, 18) 10 error correction BCH code option 2 without inversion (with design optimisation):
--------------- Syndromes calculation -----------dsyn1 - syndromes 1 2 4 8 16 Reg= 6 XOR= 15 dsyn3 - syndromes 3 6 12 Reg= 6 XOR= 14 dsyn5 - syndromes 5 10 17 Reg= 6 XOR= 14 dsyn7 - syndromes 7 14 Reg= 6 XOR= 12 dsyn9 - syndromes 9 18 Reg= 3 XOR= 4 dsyn11 - syndromes 11 Reg= 6 XOR= 9 dsyn13 - syndromes 13 19 Reg= 6 XOR= 13 dsyn15 - syndromes 15 Reg= 6 XOR= 15 total Reg= 45 XOR= 96 --------------- Chien Search -----------dcheq - check if Chien search equal zero - found an error Reg= 0 XOR= 60 drdce - m registers for x^0 Reg= 6 XOR= 0 dch1 - Chien Search for x^1 Reg= 6 XOR= 1 dch2 - Chien Search for x^2 Reg= 6 XOR= 2 dch3 - Chien Search for x^3 Reg= 6 XOR= 3 dch4 - Chien Search for x^4 Reg= 6 XOR= 4 dch5 - Chien Search for x^5 Reg= 6 XOR= 5 dch6 - Chien Search for x^6 Reg= 6 XOR= 6 dch7 - Chien Search for x^7 Reg= 6 XOR= 7 dch8 - Chien Search for x^8 Reg= 6 XOR= 7 dch9 - Chien Search for x^9 Reg= 6 XOR= 7 dch10 - Chien Search for x^10 Reg= 6 XOR= 7 total Reg= 66 XOR= 109 --------------- Syndromes rearranging -----------dmul21 - 2 to 1 multiplexers Reg= 0 * 19 = 0 XOR= 0 * 19 = 0 drdce - m registers with clock enable Reg= 6 * 19 = 114 XOR= 0 * 19 = 0 total Reg= 114 XOR= 0 --------------- Berlekamp-Massey Algorithm ---dmul21 - 2 to 1 multiplexers

126

Reg= 0 * 9 = 0 XOR= 0 * 9 = 0 drdceSOne - m registers with set to one Reg= 6 * 4 = 24 XOR= 0 * 4 = 0 drdcer - m registers with reset Reg= 6 * 16 = 96 XOR= 0 * 16 = 0 dxorm - m * XOR - modulo 2 addition Reg= 0 * 9 = 0 XOR= 6 * 9 = 54 dpm - bit-parallel standard basis multiplier option L Reg= 0 * 31 = 0 XOR= 35 * 31 = 1085 dxort - modulo 2 addition Reg= 0 * 6 = 0 XOR= 9 * 6 = 54 drdce - m registers Reg= 6 * 2 = 12 XOR= 0 * 2 = 0 total Reg= 132 XOR= 1193 --------------- The buffer ---dbuf - buffer for storing data to be corrected Reg= 37 XOR= 1 total Reg= 37 XOR= 1 --------------- The control system ---dca - less significant control counter Reg= 2 XOR= 1 dcb - more significant control counter Reg= 5 XOR= 4 dcl - degree of error polynomial Reg= 4 XOR= 5 drd1ce - single register Reg= 1 * 5 = 5 XOR= 0 * 5 = 0 dcount - control system total Reg= 16 XOR= 10 DECODER total Reg= 410

XOR= 1409

127

The design simulation

din encB: encBuf input data buffor encIn vdin e1: enc encoder encOut error errB: errBuf error buffor err d1: dec decoder dout decB: decBuf output data buffor vdout decOut wrong compare comB: comBuf buffor for comparision comBOut wrong now

decIn

The circuit for simulation included in the sim.vhd file. The din and error vectors are generated by the C program and exported into the sim.cmd and sim.cme simulation command file. Then these vectors are converted into serial form in encBuf and errBuf circuit. Accordingly the decBuf converts serial data corrected by the decoder into the parallel output vector. There are two different signals indicating a faulty circuit: - wrongNow - the high state indicates that signal decOut is faulty at the time - wrong - the high state indicates that at least one state of the decOut signal has been faulty.

128