2010 International Conference on Reconfigurable Computing

FPGA Implementation of OFDM Transceiver for a 60GHz Wireless Mobile Radio System
Khaled Sobaihi, Akram Hammoudeh, David Scammell Faculty of Advanced Technology University of Glamorgan, UK Email: {ksobaihi, amhammou, dscammel}@glam.ac.uk

AbstractOrthogonal Frequency Division Multiplexing (OFDM) has been adopted by most wireless and wired communication standards; these include wireless Local Area Networks (LANs) HyperLan2, 802.11a, broadband wireless (802.16) and lately the 802.15.3c for millimetre wave communications. In parallel, Field-Programmable Gate Arrays (FPGAs) have become an alternative for the implementation of those standards, due to their increased capabilities (speed and resources). This work introduces the design and performance evaluation of an OFDM transceiver, implemented on a FPGA platform for applications on a wireless millimetre wave radio system, operating around 60GHz. KeywordFPGA, HDL, Millimetre Wave, Mobile Radio, OFDM, Xilinx System Generator.

I.

INTRODUCTION

only experience the effects of flat fading. The orthogonality of the subcarriers ensures the OFDM modulation scheme is spectrum efficient. In recent years, Field-Programmable Gate Arrays (FPGAs) have become a key component for implementing high performance digital signal processing (DSP) designs particularly for digital communication systems. The logic fabric of todays FPGAs consists not only of look-up tables, registers, multiplexers, distributed and block memory, but also, dedicated circuitry for fast adders and multipliers. The memory bandwidth of modern FPGAs far exceed that of a microprocessor or a DSP processor running at clock rates two to ten times that of the FPGA. However, this DSP performance combined with the parallelism aspect of the FPGA allow the implementation of complex digital communication systems such as OFDM. II. RELATED WORKS

The interest in the unlicensed millimetre wave band, particularly the oxygen absorption zone around 60GHz, for wireless communication systems has increased dramatically. This is because of the large bandwidth available to accommodate high data-rates; and the fact that radiated power is limited to some tens of mW, lead to a good frequency reuse factor [1]. The task group TG3c under IEEE802.15.3c working group, responsible for of standardizing Wireless Personal Area Network (WPAN) systems, is now working on future WPAN systems, IEEE802.15.3c, which operates in the 60GHz millimetre-wave band. WPAN systems will support high data rate at least 1 Gbps for applications such as high speed internet access and a streaming content download (video on demand, home theatre, etc.) [2]. Orthogonal Frequency Division Multiplexing (OFDM) has been proposed for use in millimetre-wave transmission systems. This is due to OFDM having superior performance over single carrier system in multi-path wireless channels. The OFDM allows the transmission of the data over multiple orthogonal subcarriers, created by the mean of a Fourier Transform; each subcarrier is modulated independently resulting in a narrow band signal that will
978-0-7695-4314-7/10 $26.00 2010 IEEE DOI 10.1109/ReConFig.2010.40 185

There are limited publications related to the design and implementation of complete OFDM transceivers on FPGA platforms along with their performance evaluation over real wireless channels operating at millimetre waves. Work presented in [3] and [4] focused on the FPGA suitability and the resource availability to design an OFDM transceiver, without evaluating its performance under real conditions. Research published in [5] reported the implementation of an OFDM transceiver on a FPGA prototype to validate its suitability for implementation as an Application-Specific Integrated Circuit (ASIC). In contrast, work presented in [6], [7], [8] and [9] have reported the design and implementation of the transmitter part only of the OFDM system, by either using pure HDLs coding or System Generator block-set. The simulation of the OFDM system operating at millimetre waves has been emphasised in [10], [11], [12] and [13]. Those simulations demonstrated the possibility to use a high bit-rate communication system in a 60 GHz indoor wireless channel. The use of 16-QAM/OFDM for the transmission of Digital Terrestrial Broadcasting (ISDB-T) over 60GHz

channel has been reported in [14]. It has been shown that the ISDB-T signal, characterised by a low bit-rate of 6.39Mbps, was successfully transferred with a BER less than 10-6 without using forward error correction. III. OFDM TRANSCEIVER ARCHITECTURE

Simulink modelling environment using a Xilinx specific block-set. All of the downstream FPGA implementation steps including synthesis and place and route are automatically performed to generate an FPGA programming file [15].
DAC1
I Re in Re out I I

OFDM splits a data-bearing radio signal into multiple smaller signal sets and modulates each onto a different subcarrier, transmitting them simultaneously at different frequencies, by using a number of parallel subcarriers spaced orthogonally as closely as possible in frequency without overlapping or interfering [1]. Fig 1 shows the block diagram of a basic OFDM Transceiver, the input bits stream are grouped into parallel format in order to be mapped into M-QAM or M-PSK constellation (Example: 2 bits for QPSK, 4 bits for 16QAM etc...). The output of the mapping is a complex number that locates the sample on the I-Q constellation. The Inverse Fourier Transform (IFFT) block takes N samples and performs the inverse Fourier transform, the result is N-Points time domain signal that sums up N subcarriers. Those N point samples are serialised and converted to analogue format to be up-converted and sent through the channel. At the receiver, the inverse process is applied, after down-conversion the signal is converted to digital format. Those points are framed in the same order as the ones sent; in order to apply an N point Fourier transform to recover the N subcarriers. Those subcarriers are demodulated by using the corresponding de-mapping
Up-Conversion fc In bits Stream
Serial /Parallel QAM/PSK Mapping N Pts IFFT Parallel /Serial

Re

dout

Tx

-1

B Q Im in Im out Q Q

Serial to Parallel LFSR PSEUDO RANDOM GENERATOR

Im

16QAM MAPPING

Start 1
Start Done

DAC2

IFFT Tx
Tx

Out Out
Rx

Tx

Rx

Error Rate Calculation Rx

AWGN Channel

AWGN

16QAM DEMAPPING I
Re out Re in

ADC1
I

Re

B QAM16_DEM Q

Im out

Im in

Im

Parallel to Serial Thrd 0.32501220 threshold FFT

ADC2

Figure 2. System Generator implementation of an OFDM Transceiver

Fig 2 shows the block diagram of the OFDM transceiver to be implemented on the FPGA board by using the Xilinx block-set. This OFDM has 64 subcarriers modulated with 16-QAM scheme. The main blocks are: A. 16-QAM Mapping Each four bits generated by the pseudo random generator are mapped using the 16-QAM constellation. The In-phase and Quadrature signals are generated from the first and the last two bits respectively according to Table I. The four coding values (-3, -1, +1 and +3) are stored in a ROM memory block. The block diagram of 16-QAM mapping is demonstrated in Fig 3.

Transmitter
Channel
Down-Conversion
1 B [a:b] B2B3 addr z-1 Q ROM 2 Q [a:b] B0B1 addr z-1 I ROM 1 I

Out bits Stream

Parallel /Serial

QAM/PSK DeMapping

N Pts FFT

Serial /Parallel

Receiver Figure 1. Basic OFDM Transceiver

ADC fc

DAC

Figure 3. 16-QAM Mapping

scheme to get the correct samples, the samples are serialised back to get the bits stream initially transmitted.
TABLE I. 16-QAM Mapping Table

IV.

OFDM SIMULATION USING XILINX SYSTEM GENERATOR

B0B1 00 01 10 11

In Phase (I) -3 -1 1 3

B2B3 00 01 10 11

Quadrature (Q) -3 -1 1 3

System Generator is a DSP design tool from Xilinx that enables the use of The Mathworks model-based design environment Simulink for FPGA design. Previous experience with Xilinx FPGAs or Hardware Description Languages (HDLs) is not required when using System Generator. Designs are captured in the DSP friendly

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B. Direct/Inverse Fast Fourier Transform The FFT and IFFT are the most important blocks in the OFDM system and their performances have a big effect on the whole system; therefore, Xilinx Intellectual Property (IP) Core is used to perform a 64 Point (number of subcarriers employed) FFT or IFFT. This IP core is well optimised for a given device and can be configured to work in pipelined streaming I/O which means that the input data and output results are continuously fetched in and out respectively; Fig 4 shows an example using this IP core block.

V.

SOFTWARE SIMULATION

The input data stream is generated from a pseudo random generator implemented by a Linear Feedback Shift Register (LFSR) block. At the receiver, and in order to recover the subcarriers, the FFT should be applied on the received samples which must have the same order as the ones transmitted. To perform this synchronisation the Done output of the IFFT block is set high upon the completion of the inverse Fourier transform. This is turn will set the Start input of the FFT block to start receiving the transmitted samples. The performance of the simulated OFDM has been evaluated over Additive White Gaussian Noise (AWGN) channel to estimate the BER for a given Signal to Noise ratio. Fig 6 compares the BER obtained from floating point simulation of the OFDM by using MATLAB Simulink and the 16-bits fixed point Xilinx block-set. The results obtained from both simulations are very similar. The floating point performs slightly better than fixed point, this is the result of the limited 16-bits word length compared to 64-bits floating point.
1.E+00

Figure 4. IFFT/FFT Xilinx IP Core

C. 16-QAM De-Mapping
1.E-01

To perform the 16-QAM demodulation of the recovered sub-carriers the Xilinx M-Code is used. The Xilinx MCode block contains MATLAB code to be executed within Simulink to calculate the block outputs during simulation. The same code is translated into equivalent behavioural HDL code when hardware is generated. The M-Code block supports a limited subset of the MATLAB language (Finite state machines and control logic). The De-Mapping is performed by assigning the received I-Q signals location to the nearest point in the I-Q constellation; therefore, I and Q signals are compared to a predefined threshold defined at the mid-way between two neighbouring points. Fig 5 illustrates this principle.
B0B1B2B3 0011 X 0010 X -3 0001 X 0000 X 0111 X +3 0110 X +1 -1 0101 X -1 0100 X -3

Bit Error Rate (BER)

1.E-02

1.E-03

1.E-04

Matlab Floating Point FPGA Fixed Point

1.E-05

-20

-15

-10

-5

10

Signal To Noise Ratio SNR (dB) Figure 6. Bit Error Rate vs SNR Ratio

Q
1011 X Threshold 1010 X +1 1001 X 1000 X 1111 X 1110 X +3 1101 X 1100 X

VI.

HARDWARE CO-SIMULATION

The implementation of the OFDM system has been performed on Xilinx XtremeDSP Developement Kit (Fig 7), the main features of this development board are:
I

a. Virtex-4 XC4VSX35 main FPGA which has a high amount of DSP blocks, b. 2 channels ADC (14-bits up to 105 MSPS), c. 2 channels DAC (14-bits up to 160 MSPS).

Figure 5. 16-QAM De-Mapping decision scheme

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Once the simulation is verified, a hardware cosimulation block along with a hardware configuration file are generated by the System Generator. During simulation, the configuration file is loaded into the XtremeDSP developement board and the co-simulation block behaves exactly as the subsystem from which it generated, except that the simulation data is processed in hardware instead of software.

transmitter and the receiver use common oscillators in order to achieve perfect frequency synchronization. Fig 9 illustrates the received I-Q 16-QAM constellation for line of sight transmission with the transmitter and receiver 1m apart. This I-Q constellation is very clean and errors-free transmission was achieved with a bit-rate up to 200Mbps.

Figure 7. XtremeDSP development kit

Rx
DOWN CONVERTER LNA ISOLATOR TRIPLER LNA DOUBLER I-Q Demodulator
I Q

UP CONVERTER

Figure 9. The received I-Q constellation with LOS Transmission and 1m distance VII.

CONCLUSION

POWER AMP ISOLATOR TRIPLER LNA DOUBLER SPLITTER

LNA

100MHz CRYSTAL SPLITTER

10MHz CRYSTAL

ITx FPGA Board Baseband OFDM

IRx

QTx

QRx

Control

Figure 8. OFDM baseband transceiver interfaced with 62.4 GHz radio system

Fig 8 shows the integration of the OFDM baseband transceiver with a 62.4 GHz wireless radio system. The upconversion of the baseband signal to the 64.2 GHz is done through a 2.4 GHz intermediate frequency. The inverse process is performed in the down-conversion, where the
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The capability to design, simulate and implement an OFDM transceiver was achieved in this work by exclusively using System Generator block-set provided by Xilinx. The design targets the Xilinx FPGA Virtex4 xc4sx35-10ff668 which packs 700 kgates, 3.5 Mbits of embedded memory, 192 dedicated DSP blocks, and up to 448 I/O lines. After the mapping and routing phase, the used area is summarised in Table II. This shows there are sufficient resources to improve the OFDM transceiver by adding the coding blocks, synchronisation and carrier recovery blocks. Such blocks are mandatory to make the system work in the real world. The timing constraints reported in Table III do not show any conflict and the maximum estimated frequency is 228MHz. This is directly related to the maximum achievable bit-rate of 228Mbps. In future work and in order to ensure the correct functionality of the OFDM system, frame synchronisation would need to be implemented. In addition, the OFDM transceiver will be further improved to allow a high order modulation scheme such as 256-QAM. Equalisation techniques will also be utilised to mitigate the effect of multipath fading, particularly over the 60 GHz wireless radio channel.

TABLE II. FPGA Resources Utilisation Device Utilisation Summary Virtex4 xc4vsx35-10ff668 Used Available 3,359 30,720 2,393 15,360 4 192 44 192 TABLE III. Timing Constraints Timing summary Minimum period: 4.370ns Maximum path delay: 4.152ns Maximum frequency: 228.833MHz

Resources Slice FFs Slices RAMB16s DSP48s

Utilisation 10% 15% 2% 22%

[12] D. Sommer, G.P. Fettweis, Fast frequency correction for DQPSK-OFDM in the 60 GHz indoor environment, in IEEE International Conference on Communications, (ICC apos; 99), vol.1, 1999, pp. 157 161. [13] F. Poegel, S. Zeisberg, A. Finger, Comparison of different coding schemes for high bit rate OFDM in a 60 GHz environment, in IEEE 4th International Symposium on Spread Spectrum Techniques and Applications Proceedings, vol.1, 22-25 Sep 1996, pp. 122 125. [14] Y. Shoji, M. Nagatsuka, K. Hamaguchi, H. Ogawa, 60 GHz band 64 QAM/OFDM terrestrial digital broadcasting signal transmission by using millimeter-wave selfheterodyne system, IEEE Transactions On Broadcasting, Vol. 47, No. 3, 2001, pp. 218-227. [15] Xilinx (2009), System Generator for DSP, Getting Started Guide, [Online]. Available: http://www.xilinx.com/support/sw_manuals/sysgen_gs.pdf

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