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Chapter3-Input Output Ports Programming

This document discusses input/output (I/O) ports and their programming on PIC microcontrollers. It explains that PICs have multiple I/O ports with registers to control the direction and output values of pins. Pins can be configured as inputs or outputs using these registers. It also notes that some pins have alternate functions or are multiplexed with other peripherals. The document provides details on initializing and programming specific ports (A-E) on PIC microcontrollers.

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adamwaiz
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© Attribution Non-Commercial (BY-NC)
1K views

Chapter3-Input Output Ports Programming

This document discusses input/output (I/O) ports and their programming on PIC microcontrollers. It explains that PICs have multiple I/O ports with registers to control the direction and output values of pins. Pins can be configured as inputs or outputs using these registers. It also notes that some pins have alternate functions or are multiplexed with other peripherals. The document provides details on initializing and programming specific ports (A-E) on PIC microcontrollers.

Uploaded by

adamwaiz
Copyright
© Attribution Non-Commercial (BY-NC)
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INPUT OUTPUT PORTS PROGRAMMING

Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

Each port has three registers for its operation. These registers are: TRIS register (data direction register) PORT register (reads the levels on the pins of the device) LAT register (output latch)

LATx is used for writing an output. PORTx is for reading an input.

TRISx is used to configure the direction; an output (=0) or an input (=1).

The corresponding Data Direction register is TRISx. Setting a TRISx bit (= 1) will make the corresponding PORTx pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISx bit (= 0) will make the corresponding PORTx pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATx) is also memory mapped. Readmodify-write operations on the LATx register read and write the latched output value for PORTx.

PORTA, TRISA and LATA Registers

Dual Role Port


The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. RA4 is also multiplexed with the USB module, it serves as a receiver input from an external USB transceiver. The RA6 pin is multiplexed with the main oscillator pin. Several PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the comparator voltage reference output. The operation of pins RA5 and RA3:RA0 as A/D converter inputs is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register 1).

INITIALIZING PORTA

PORTB, TRISB and LATB Registers


PORTB is an 8-bit wide, bidirectional port. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.

PORTC, TRISC and LATC Registers


PORTC is a 7-bit wide, bidirectional port. PORTC is primarily multiplexed with serial communication modules, including the EUSART, MSSP module and the USB module, Except for RC4 and RC5, PORTC uses Schmitt Trigger input buffers. The RC3 pin is not implemented in these devices. RC4 and RC5 do not have TRISC bits associated with them. As digital ports, they can only function as digital inputs.

INITIALIZING PORTC

PORTD, TRISD and LATD Registers


PORTD is an 8-bit wide, bidirectional port. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. Three of the PORTD pins are multiplexed with outputs, P1B, P1C and P1D, of the Enhanced CCP module. PORTD can also be configured as an 8-bit wide Streaming Parallel Port (SPP). In this mode, the input buffers are TTL.

INITIALIZING PORTD

PORTE, TRISE and LATE Registers


PORTE is a 4-bit wide port. Three pins (RE0/AN5/CK1SPP, RE1/AN6/CK2SPP and RE2/AN7/OESPP) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as 0s.

The fourth pin of PORTE (MCLR/VPP/RE3) is an input only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin; as such, it does not have TRIS or LAT bits associated with its operation. Otherwise, it functions as the devices Master Clear input. In either configuration, RE3 also functions as the programming voltage input during programming.

INITIALIZING PORTE

I/O Ports And Bit-addressability


Sometimes we need to access only I or 2 bits of the port instead of the entire 8 bits. A powerful feature of PIC i/o ports is their capability to access individual bits of the port without altering the rest of the bits in that port. For all PIC ports, we can access either all 8 bits or any single bit without altering the rest.

End chapter 2. Please read PIC18 datasheet for detail description assembly language

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