ARM 7

INTRODUCING EMBEDDED SYSTEMS AND THE MICROCONTROLLERS

Definition for: embedded system

A combination of hardware and software which together form a component of a larger machine.
An example of an embedded system is a microprocessor that controls an automobile engine. An embedded system is designed to run on its own without human intervention, and may be required to respond to events in real time.

Embedded system: is a system whose principal function is not computational, but which is controlled by a computer embedded within it.

Definition of Embedded Systems

Examples: Refrigerator

Examples: Car Door

Examples: Electronic Ping-pong

Application Areas
TV stereo remote control phone / mobile phone refrigerator microwave washing machine electric tooth brush oven / rice or bread cooker watch alarm clock electronic musical instruments electronic toys (stuffed animals,handheld toys, pinballs, etc.) medical home equipment (e.g. blood pressure, thermometer) [PDAs?? More like standard computer system] Consumer Products

System
application OS & middleware micro Processor Memory system peripherals controller
Size Power consumption Throughput Code Density Code Exe. Speed

SW system HW system

8051 and ARM 7

8051 :

4K ROM Internal, up to 64K external 128 Bytes User RAM Internal, up to 64K external (addressing shared with ROM) 2 Timers 32 I/O pins 1 Serial Port

6 Interrupt Sources
ARM 7(LPC2148) 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package 8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory

2 Timers(32 bit)
2 Serial Ports

Architecture Revisions
ARMv7 version ARM1156T2F-S ARM1136JF-S ARMv6 ARM102xE XScaleTM ARMv5
ARM7TDMI-S StrongARM

ARM1176JZF-S ARM1026EJ-S

ARM9x6E ARM926EJ-S SC200 ARM92xT

V4 SC100 ARM720T

1994

1996

1998

2000

2002

2004

2006 time

XScale is a trademark of Intel Corporation

ARM7 Block Diagram

ARM7 Functional Diagram

ARM7 TDMI-S

NXP LPC2148

ARM7TDMI Processor Core

Current low-end ARM core for applications like digital mobile phones etc TDMI
T: Thumb, 16-bit compressed instruction set D: on-chip Debug support, enabling the processor to halt in response to a debug request M: enhanced Multiplier, yield a full 64-bit result, high performance I: Embedded ICE hardware

Von Neumann architecture 3-stage pipeline

Data Sizes and Instruction Sets

The ARM is a 32-bit architecture. When used in relation to the ARM:

Byte means 8 bits Half word means 16 bits (two bytes) Word means 32 bits (four bytes)

Most ARMs implement two instruction sets

32-bit ARM Instruction Set 16-bit Thumb Instruction Set

Jazelle cores can also execute Java byte code

Processor Modes

The ARM has seven basic operating modes:

User : unprivileged mode under which most tasks run

FIQ : entered when a high priority (fast) interrupt is raised

IRQ : entered when a low priority (normal) interrupt is raised

Supervisor : entered on reset and when a Software Interrupt instruction is executed Abort : used to handle memory access violations Undef : used to handle undefined instructions System : privileged mode using the same registers as user mode

The ARM Register Set

Current Visible Visible Registers Registers Current
Abort Mode SVC Undef Mode Mode FIQ User IRQ Mode Mode Mode
r0 r1 r2 r3 r4 r5 r6

Banked Banked Bankedout out outRegisters Registers Registers

User
r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

FIQ
r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

IRQ

SVC

Undef

Abort

r7 r8 r9 r10 r11 r12 r13 (sp) (sp) r13 r14 (lr) (lr) r14 r15 (pc)
cpsr spsr spsr

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

spsr

spsr

spsr

spsr

spsr

Register Organization Summary

User
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

FIQ

IRQ

SVC

Undef

Abort

User mode r0-r7, r15, and cpsr

r8 r9 r10 r11 r12 r13 (sp) r14 (lr)

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

User mode r0-r12, r15, and cpsr

Thumb state Low registers

Thumb state High registers

r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr)

r15 (pc)
cpsr spsr spsr spsr spsr spsr

Note: System mode uses the User mode register set

The Registers

ARM has 37 registers all of which are 32-bits long.

1 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 30 general purpose registers

The current processor mode governs which of several banks is accessible. Each mode can access

a particular set of r0-r12 registers a particular r13 (the stack pointer, sp) and r14 (the link register, lr)

the program counter, r15 (pc)

the current program status register, cpsr

Privileged modes (except System) can also access

a particular spsr (saved program status register)

Program Status Registers

31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V Q

J U

I F T

mode

Condition code flags

N = Negative result from ALU Z = Zero result from ALU C = ALU operation Carried out V = ALU operation oVerflowed

Interrupt Disable bits.

I = 1: Disables the IRQ. F = 1: Disables the FIQ.

T Bit

Architecture xT only T = 0: Processor in ARM state T = 1: Processor in Thumb state

Sticky Overflow flag - Q flag

Architecture 5TE/J only

Indicates if saturation has occurred

Mode bits

J bit

Specify the processor mode

Architecture 5TEJ only J = 1: Processor in Jazelle state

Program Counter (r15)

When the processor is executing in ARM state:

All instructions are 32 bits wide All instructions must be word aligned Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be half word or byte aligned)

When the processor is executing in Thumb state:

All instructions are 16 bits wide All instructions must be half word aligned Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instruction cannot be byte aligned)

When the processor is executing in Jazelle state:

All instructions are 8 bits wide Processor performs a word access to read 4 instructions at once

Exceptions

Exceptions are usually used to handle unexpected events which arise during the execution of a program, such as interrupts or memory faults, also cover software interrupts, undefined instruction traps, and the system reset Three groups:

Exceptions generated as the direct effect of execution an instruction

Software interrupts, undefined instructions, and prefetch abort Data aborts Reset, IRQ and FIQ

Exceptions generated as a side effect of an instruction

Exceptions generated externally

Exception Entry (1/2)

When an exception arises

ARM completes the current instruction as best it can (except that reset exception) handle the exception which starts from a specific location (exception vector).

Processor performs the following sequence:

Change to the operating mode corresponding to the particular exception Stores the return address in LR_<mode> Copy old CPSR into SPSR_<mode> Set appropriate CPSR bits

If core currently in Thumb state then ARM state is entered. Disable IRQs by setting bit 7 If the exception is a fast interrupt, disable further faster interrupt by setting bit 6 of the CPSR

Exception Entry (2/2)

Force
Priority 1 2 3 4 5 6

PC to relevant vector address

Mode SVC Abort FIQ IRQ vector address 0x00000000 0x00000010 0x0000001C 0x00000018 0c0000000C 0x00000004 0x00000008

Exception Reset Data abort (data access memory fault) FIQ (fast interrupt ) IRQ (normal interrupt)

Prefetch abort (instruction fetch memory fault) Abort Undefined instruction Software interrupt (SWI) UND SVC

Normally the vector address contains a branch to the relevant routine Exception handler use r13_<mode> and r14_<mode> to hold the stack point and return address

On entry

1) completes the current instruction (except reset exception)

2) Changes to the operating mode corresponding to the 1) particular exception 3) Saves the address of the following instruction in r14 of new mode

4) Saves the old value of the CPSR in the SPSR of the new mode
5) Disables IRQ exception; set bit 7 of the CPSR 6) If it a FIQ exception, disable further FIQ; disables bit 6 of the CPSR 7) Forces the PC to the address of exception handler

Exception Return

Once the exception has been handled, the user task is normally resumed The sequence is
Any

modified user registers must be restored from the handlers stack CPSR must be restored from the appropriate SPSR PC must be changed back to the relevant instruction address

The last two steps happen atomically as part of a single instruction

On exit
1) Restores user registers 2) Restores the CPSR using the SPSR 3) set proper return address to PC

!! Conflict in performing step 2) and 3)

If step 2) is performed prior to step 3), then since lower bits of the CPSR determines the operating mode, restoring the CPSR makes it impossible to access the banked r14 If step 3) is performed prior to step 2), exception handler loses the control and the code to perform step 2) is never accessed

Conditional Execution

Most instruction sets only allow branches to be executed conditionally. However by reusing the condition evaluation hardware, ARM effectively increase number of instruction All instructions contain a condition field which determines whether the CPU will execute them Non-executed instruction still take up 1 cycle To allow other stages in the pipeline to complete This reduces the number of branches which would stall the pipeline Allows very dense in-line code The time penalty of not executing several conditional instructions is frequently less than overhead of the branch or instruction call that would otherwise be

Condition code
31 28 27 0

con d
Opcode [31:28] 0000 0001 Mnemonic extension EQ NE Interpretation Equal / equals zero Not equal Status flag state for execution Z set Z clear

0010
0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110

CS/HS
CC/LO MI PL VS VC HI LS GE LT GT LE AL

Carry set / unsigned higher or some

Carry clear / unsigned lower Minus / negative Plus / positive or zero Overflow No overflow Unsigned higher Unsigned lower or same Signed greater than or equal Signed less than Signed greater than Signed less than or equal Always

C set
C clear N set N clear V set V clear C set and Z clear C clear or Z set N equals V N is not equal to V Z clear and N equals V Z sets or N is not equal to V any

1111

NV

Never (do not use!)

none

Conditional execution examples

C source code if (r0 == 0) { r1 = r1 + 1; } else { r2 = r2 + 1; } ARM instructions unconditional conditional CMP r0, #0 CMP r0, #0 BNE else ADDEQ r1, r1, #1 ADD r1, r1, #1 ADDNE r2, r2, #1 B end ... else ADD r2, r2, #1 end ... 5 instructions 5 words 5 or 6 cycles 3 instructions 3 words 3 cycles

Examples of conditional execution

Use a sequence of several conditional instructions if (a==0) func(1); CMP MOVEQ BLEQ r0,#0 r0,#1 func

Set the flags, then use various condition codes if (a==0) x=0; if (a>0) x=1; CMP MOVEQ MOVGT r0,#0 r1,#0 r1,#1

Use conditional compare instructions if (a==4 || a==10) x=0; CMP CMPNE MOVEQ r0,#4 r0,#10 r1,#0

Example of Conditional Execution

An unusual feature of the ARM instruction set is that conditional execution applies no only to branches but to all CMP r0,#5 ARM instructions CMP r0,#5
BEQ Bypass ;if (r0!=5) ADDNE r1,r1,r0 SUBNE r1,r1,r2 ADD r1,r1,r0 ;{r1=r1+r0}

SUB r1,r1,r2
Bypass

Whenever the conditional sequence is 3 instructions for fewer it is better (smaller and faster) to exploit conditional CMP r0,r1 execution than to use a branch
if((a==b)&&(c==d)) e++; CMPEQ r2,r3 ADDEQ r4,r4,#1

Using and Updating the condition Field

To execute an instruction conditionally, simply postfix it with the appropriate condition:

For example and add instruction takes the form

ADD r0, r1, r2 ADDEQ r0, r1, r2 set

; r0 = r1 + r2 (ADDAL) ; r0 = r1 + r2 iff zero flag

To execute this only if the zero flag is set

By default, data processing operations do not affect the condition flags

With comparison instructions this is the only effect

To cause the condition flags to be updated, the S bit of the instruction needs to be set by postfixing the instruction (and any condition codes) with an S.

For example to add two numbers and set the condition flags:

ARM instruction set

ARM assembly language program

ARM

development board or ARM emulator

ARM instruction set

Standard

ARM instruction set A compressed form of the instruction set, a subset of the full ARM instruction set is encoded into 16-bit instructions Thumb instruction Some ARM cores support instruction set extensions to enhance signal processing capabilities

Features of the ARM Instruction Set

Load-store architecture
Process values which are in registers Load, store instructions for memory data accesses

3-address data processing instructions Conditional execution of every instruction Load and store multiple registers Shift, ALU operation in a single instruction Open instruction set extension through the coprocessor instruction Very dense 16-bit compressed instruction set (Thumb)

Instructions

Data processing instructions Data transfer instructions Control flow instructions

Data Processing Instruction (1/3)

Consist of

Arithmetic (ADD, SUB, RSB) Logical (BIC, AND) Compare (CMP, TST) Register movement (MOV, MVN)

All operands are 32-bit wide; come from registers or specified as literal in the instruction itself Second operand sent to ALU via barrel shifter 32-bit result placed in register; long multiply instruction produces 64-bit result 3-address instruction format

2 source operands and 1 destination register One source is always a register, the second may be a register, a

Data Processing Instruction (2/3)

Allows direct control of whether or not the condition codes are affected by S bit (condition code unchanged when S = 0)

N = 1 if the result is negative; 0 otherwise (i.e. N = bit 31 of the result) Z = 1 if the result is zero; 0 otherwise C = 1 carry out from the ALU when ADD, ADC, SUB, SBC, RSB, RSC, CMP, or CMN; carry out from the shifter V = 1 if overflow from bit 30 to bit 31; 0 if no overflow (V is preserved in non-arithmetic operations)

PC may be used as a source operand (address of the instruction plus 8) except when a register-specified shift amount is used PC may be specified as the destination register, the instruction is a form of branch (return from a subroutine)

Data Processing Instruction (3/3)

31 28 27 26 25 24 21 20 19 16 15 12 11 0

cond

00

opcode

Rn

Rd

operand 2

destination register first operand register set condition codes arithmetic/logic function
25 11 8 7 0

1
immediate alignment
11

#rot

8-bit immediate

5 4

#shift
25

Sh

Rm

immediate shift length shift type second operand register

11 8 7 6 5 4 3 0

Rs
register shift length

Sh

Rm

Simple Register Operands (1/2) Arithmetic Operations

ADD r0,r1,r2 ADC r0,r1,r2 SUB r0,r1,r2 SBC r0,r1,r2 RSB r0,r1,r2 subtraction RSC r0,r1,r2
By

;r0:=r1+r2 ;r0:=r1+r2+C ;r0:=r1r2 ;r0:=r1r2+C1 ;r0:=r2r1, reverse ;r0:=r2r1+C1

default data processing operations do no affect the condition flags

Bit-wise Logical Operations

AND r0,r1,r2 ORR r0,r1,r2 EOR r0,r1,r2 ;r0:=r1ANDr2 ;r0:=r1ORr2 ;r0:=r1XORr2

Simple Register Operands (2/2)

Register Movement Operations

Omit

1st source operand from the format

MOV r0,r2 ;r0:=r2 MVN r0,r2 ;r0:=NOT r2, move 1s complement

Comparison Operations
Not

produce result; omit the destination from the format Just set the condition code bits (N, Z, C and V) in CPSR

Immediate Operands

Replace the second source operand with an immediate operand, which is a literal constant, preceded by #
ADD r3,r3,#1 AND r8,r7,#&FF &:hexadecimal ;r3:=r3+1 ;r8:=r7[7:0],

Since the immediate value is coded within the 0 n 12 to 32 bits of the instruction, it is not possible enter every possible 32-bit value as an immediate.

Shift Register Operands

31 0 31 0

ADD r3,r2,r2,LSL#3 := r2 + 8 * r1

;r3
00000 00000

A single instruction executed in a single cycle

LSL #5
31 0 0 31 1

LSR #5
0

LSL: Logical Shift Left by 0 to 31 places, 0 filled at the lsb end LSR, ASL (Arithmetic Shift Left), ASR, ROR (Rotate Right), RRX (Rotate Right eXtended by 1 place) ADD r5,r5,r3,LSL r2 ; r5:=r5+r3*2r2 MOV r12,r4,ROR r3 ;r12:=r4 rotated right by value of r3

00000 0

11111 1

ASR #5 , pos itiv e operand

31 0 C

ASR #5 , negativ e operand

31 0

ROR #5

RRX

Using the Barrel Shifter: The Second Operand Register, optionally with shift operation
Operand 1
Operand 2

Barrel Shifter

Shift value can be either be: 5 bit unsigned integer Specified in bottom byte of another register. Used for multiplication by constant

ALU

Result

Immediate value 8 bit number, with a range of 0255. Rotated right through even number of positions Allows increased range of 32-bit constants to be loaded directly into registers

Multiply Instructions (1/2)

32-bit product (Least Significant) MUL{<cond>}{S} Rd,Rm,Rs MLA{<cond>}{S} Rd,Rm,Rs,Rn MUL r4,r3,r2; r4:=(r3*r2)[31:0] MLA r4,r3,r2,r1; r4:=(r3*r2+r1)[31:0]
64-bit Product <mul>{<cond>}{S} RdHi,RdLo,Rm,Rs <mul> is UMULL,UMLAL,SMULL,SMLAL
Mnemonic MUL MLA UMULL UMLAL SMULL SMLAL Meaning Multiply (32-bit result) Multiply-accumulate (32-bit result) Unsigned multiply long Unsigned multiply-accumulate long Signed multiply long Signed multiply-accumulate long Effect Rd := (Rm * Rs) [31:0] Rd := (Rm * Rs + Rn) [31:0] RdHi:RdLo := Rm * Rs RdHi:RdLo += Rm * Rs RdHi:RdLo := Rm * Rs RdHi:RdLo += Rm * Rs

Opcode [23:21] 000 001 100 101 110 111

Multiply Instructions (2/2)

Booths algorithm is used to perform integer multiplication

Instructions

will early terminate wherever possible On ARM7TDMI Mul will execute in minimum of 2 clock cycles and maximum of 5 clock cycles

Restrictions on use:
Rd

and Rm cannot be the same register (can be avoided by swapping over Rm and Rs multiplication is commutative)

Multiplication by a Constant

Multiplication by a constant equals to a ((power of 2) +/- 1) can be done in a single cycle

Using

MOV, ADD or RSB with an inline shift

Example: r0 = r1 * 5 Example: r0 = r1 + (r1 * 4)

ADD

r0,r1,r1,LSL #2 ;r0:=r1+r1*4

Can combine several instruction to carry out other multiplies Example: r2 = r3 * 119 Example: r2 = r3 * 17 * 7

Loading Constants (1/2)

No single ARM instruction can load a 32-bit immediate constant directly into a register

All ARM instructions are 32-bit long ARM instructions do not use the instruction stream as data

The data processing instruction format has 12 bits available for operand 2

If used directly, this would only give a range of 4096

Instead it is used to store 8-bit constants, give a range of 0255 These 8 bits can then be rotated right through an even number of positions This gives a much larger range of constants that can be directly loaded, through some constants will still need to be loaded from memory

Loading Constant (2/2)

To load a constant, simply move the required value into a register the assembler will convert to the rotate form for us MOV r0,#4096 ;MOV r0,#&1000 (0x40 ror 26) The bitwise complements can also be formed using MVN: MOV r0,#&FFFFFFFF ;MVN r0,#0 Value that cannot be generated in this way will cause an error

Loading 32-bit Constants

To allow larger constants to be loaded, the assembler offers a pseudo-instruction:

LDR Rd,=const Produce a MOV or MVN instruction to generate the value (if possible) or Generate a LDR instruction with a PC-relative address to read the constant from a literal pool (constant data area embedded in the code) MOV r0,=&FF LDR r0,=&55555555 ;MOV r0,#0xFF ;LDR r0,[PC,#Imm10]

This will either:

For example

As this mechanism will always generate the best

Data Transfer Instructions

Three basic forms to move data between ARM registers and memory

Single register load and store instruction

A byte, a 16-bit half word, a 32-bit word

Multiple register load and store instruction

To save or restore workspace registers for procedure entry and exit To copy blocks of data

Single register swap instruction

A value in a register to be exchanged with a value in memory To implement semaphores to ensure mutual exclusion on accesses

Single Register Data Transfer

Word transfer

LDR / STR
LDRB / STRB

Byte transfer

Halfword transfer

LDRH / STRH

Load singled byte or halfword-load value and sign extended to 32 bits

LDRSB / LDRSH

All of these can be conditionally executed by insert-ing the appropriate condition code after STR/LDR

LDREQB

Addressing mode

Register-indirect addressing Base-plus-offset addressing

Base register

r0 r15

Offset, and or subtract an unsigned number

Immediate Register (not PC) Scaled register (only available for word and unsigned byte instructions)

Stack addressing Block-copy addressing

Register-Indirect Addressing

Use a value in one register (base register) as a memory address

LDR r0,[r1] ;r0:=mem32[r1] STR r0,[r1] ;mem32[r1]:=r0

Other forms
Adding

immediate or register offsets to the base address

Initializing an Address Pointer

A small offset to the program counter, r15

ARM assembler has a pseudo instruction, ADR

As an example, a program which must copy data from TABLE1 to TABLE2, both of which are near to the code
Copy ADR r1,TABLE1 ;r1 points to TABLE1
ADR r2,TABLE2 ;r2 points to TABLE2 TABLE1

TABLE2

;<source>

;<destination>

Base-plus-offset Addressing (1/2)

Pre-indexing
LDR r0,[r1,#4] ;r0:=mem32[r1+4] Offset up to 4K, added or subtracted, (# -4)

Post-indexing
LDR r0,[r1],#4 ;r0:=mem32[r1], r1:=r1+4 Equivalent to a simple register-indirect load, but faster, less code space

Auto-indexing
LDR r0, [r1,#4]! ;r0:=mem32[r1+4], r1:=r1+4 No extra time, auto-indexing performed while the data is being fetched from memory

Base-plus-offset Addressing (2/2)

*Pre-indexed: STR r0,[r1,#12]
Updated Base Register

r1
0x20c

Offest
12
0x20c

r0
0x5 0x5
Source Register for STR 0x200

r1
Base Register 0x200

Auto-update from: STR r0,[r1,#12]! *Post-indexed: STR r0,[r1],#12

Updated Base Register

r1
0x20c

Offest
12
0x20c

Original Base Register

r1
0x200 0x200 0x5

r0
0x5
Source Register for STR

Multiple Register Data Transfer (1/2)

The load and store multiple instructions (LDM/STM) allow between 1 and 16 registers to be transferred to or from memory

Order of register transfer cannot be specified, order in the list is insignificant Lowest register number is always transferred to/form lowest memory location accessed Any subset of the current bank of registers (default) Any subset of the user mode bank of registers when in a privileged mode (postfix instruction with a ^)

The transferred registers can be either

Base register used to determine where memory access should occur

4 different addressing modes Base register can be optionally updated following the transfer (using !)

Multiple Register Data Transfer (2/2)

These instruction are very efficient for

Moving block of data around memory Saving and restoring context stack STMIA/LDMIA: Increment After STMIB/LDMIB: Increment Before STMDA/LDMDA: Decrement After STMDB/LDMDB: Decrement Before

The direction that the base pointer moves through memory is given by the postfix to the STM/LDM instruction

Allow any subset (or all, r0 to r15) of the 16 registers to be transferred with a single instruction
LDMIA r1,{r0,r2,r5} ;r0:=mem32[r1] ;r2:=mem32[r1+4] ;r5:=mem32[r1+8]

Stack Processing

The stack type to be used is given by the postfix to the instruction:

STMFD/LDMFD: Full Descending stack STMFA/LDMFA: Full Ascending stack STMED/LDMED: Empty Descending stack STMEA/LDMEA: Empty Ascending stack

Note: ARM Compilers will always use a Full descending stack Addressing modes
Ascending Desceding Full Empty LDMIB LDMED STMIA STMEA LDMIA LDMFD
101816

r9' r5 r1 r9 r0

r9'

r5 r1 r0

101816

101816

101816

Full Before STMIB STMFA

Empty

100c16

r9

100c16

r9

r5 r1 r0

100c16

r9 r5 r1

100c16

Increment After

100016

100016

r9'

100016

r9'

r0

100016

Before Decrement After LDMDA LDMFA

LDMDB STMDB LDMEA STMFD STMDA STMED

STMIA r9!, {r0, r1, r5}

STMIB r9!, {r0, r1, r5}

STMDA r9!, {r0, r1, r5}

STMDB r9!, {r0, r1, r5}

Swap Memory and Register Instructions

Syntax
SWP{<cond>}{B} Rd,Rm,[Rn] Rd <- [Rn], [Rn] <- Rm

Combine a load and a store of a word or an unsigned byte in a single instruction Example
ADR r0,SEMAPHORE SWPB r1,r1,[r0]
;exchange byte

Status Register to General Register Transfer instructions

Syntax
MRS{<cond>}

Rd,CPSR|SPSR

The CPSR or the current mode SPSR is copied into the destination register. All 32 bits are copied.

Example
MRS r0,CPSR MRS r3,SPSR

General Register to Status Register Transfer instructions

Syntax

MSR{<cond>} CPSR_<field>|SPSR_<field>,#<32bit immediate> MSR{<cond>} CPSR_<field>|SPSR_<field>,Rm <field> is one of

c the control field PSR[7:0] x the extension field PSR[15:8] s the status field PSR[23:16] f the flag field PSR[31:24]

Example

Set N, X, C, V flags

MSR CPSR_f, #&f0000000

Branch Instructions

Syntax

Branch: Branch with Link:

31 28 27 25 24 23

B{<cond>} Label BL{<cond>} subroutine_label

0

cond

101 L

24-bit signed w ord off set

Link bit
0 = Branch 1 = Branch with Link

Condition field

The PC-relative offset for branch instructions is calculated by:

Taking the difference between the branch instruction and the target address minus 8 (to allow for the pipeline) This gives a 26 bit offset which is right shifted 2 bits (as the bottom two bits are always zero as instruction are word-aligned) and stored into the instruction encoding This gives a range of +/- 32Mbytes.

Conditional Branch (1/2)

The branch has a condition associated with it and it is only executed if the condition codes have the correct value taken or not taken
MOV r0,#0 ;initialize counter ADD r0,r0,#1 ;increment loop CMP r0,#10 ;compare with limit BNE Loop ;repeat if not equal ;else fail through

Loop counter

Conditional Branch (2/2)

B ran c h B BAL BEQ BNE BPL BMI BCC BLO BCS BHS BVC BVS BGT BGE BLT BLE BHI BLS In t e rp re t at i o n Unconditional Always Equal Not equal Plus Minus Carry clear Lower Carry set Higher or same Overflow clear Overflow set Greater than Greater or equal Less than Less or equal Higher Lower or same No rmal us e s Always take this branch Always take this branch Comparison equal or zero result Comparison not equal or non-zero result Result positive or zero Result minus or negative Arithmetic operation did not give carry-out Unsigned comparison gave lower Arithmetic operation gave carry-out Unsigned comparison gave higher or same Signed integer operation; no overflow occurred Signed integer operation; overflow occurred Signed integer comparison gave greater than Signed integer comparison gave greater or equal Signed integer comparison gave less than Signed integer comparison gave less than or equal Unsigned comparison gave higher Unsigned comparison gave lower or same

Examples Unconditional jump

LABEL
B LABEL

Conditional subroutine call

CMP r0,#5 BLLT SUB1 ;if r0<5, ;call sub1 BLGE SUB2 ;else call ;SUB2

Loop ten times

Loop MOV r0,#10 SUBS r0,#1 BNE Loop BL SUB MOV PC,r14

Call a subroutine
SUB

Branch, Branch with Link and eXchange B{L}X{<cond>} Rm

The branch target is specified in a register, Rm Bit[0] of Rm is copied into the T bit in CPSR; bit[31:1] is moved into PC If Rm[0] is 1, the processor switches to execute Thumb instructions and begins executing at the address in Rm aligned to a half-word boundary by clearing the bottom bit If Rm[0] is 0, the processor continues executing ARM instructions and begins executing at the address in Rm aligned to a word boundary by clearing Rm[1]

BLX <target address>

Call Thumb subroutine from ARM The H bit (bit 24) is also added into bit 1 of the resulting addressing, allowing an odd half-word address to be selected for the target instruction which will always be a Thumb instruction

Software Interrupt (SWI)

SWI{<cond>}<24-bit immediate>
Used for calls to the operating system and is often called a supervisor call It puts the processor into supervisor mode and begins executing instruction from address 0x08 (refer to P.21)

Save the address of the instruction after SWI in r14_svc Save the CPSR in SPSR_svc Enter supervisor mode and disable IRQs by setting CPSR[4:0] to 100112 and CPSR[7] to 1 Set PC to 0816 and begin executing the instruction there

The 24-bit immediate does not influence the operation of the instruction but may be interpreted by the system code

Supervisor Calls

The supervisor is a program which operates at a privileged level, which means that it can do things that a use-level program cannot do directly (e.g. input or output) SWI instruction
Software

interrupt or supervisor call ;output r0[7:0] ;return to

SWI SWI_WriteC SWI SWI_Exit monitor program

ARM Instruction Set Summary (1/4)

ARM Instruction Set Summary (2/4)

ARM Instruction Set Summary (3/4)

ARM Instruction Set Format

Instruction Pipeline

The ARM7TDMI-S core uses a pipeline to increase the speed of the flow of instructions to the processor. This enables several operations to take place simultaneously The Program Counter (PC) points to the instruction being fetched rather than to the instruction being executed During normal operation, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory

3-Stage Instruction Pipeline

ARM Thumb

PC

PC Fetch
Instruction Fetched from Memory

PC - 4

PC - 2 Decode
Thumb only: Thumb instruction decompressed to ARM instruction
Instruction decoded

PC - 8

PC - 4

Execute

Registers read from Register Bank, Shift and ALU operations performed, Registers written back to Register Bank

Optimal Pipelining

In this example it takes 6 clock cycles to execute 6 instructions All operations are on registers (single cycle instructions) Clock cycles per instruction (CPI) = 1
Fetch Decode Fetch Execute Decode Execute

ADD SUB

MOV
AND ORR

Fetch

Decode
Fetch

Execute
Decode Fetch Execute Decode Execute

EOR
CMP RSB

Fetch

Decode
Fetch

Execute
Decode Fetch

1 Cycle

Branch Pipeline Example

Branches break the pipeline Example in ARM state

BL X

0x8000 0x8004

Fetch

Decode Fetch

Execute Decode

Linkret

Adjust

X
ADD SUB

0x8008
0x8FEC 0x8FF0

Fetch
Fetch Decode Fetch Execute Decode Execute Decode Fetch

MOV
AND

0x8FF4
0x8FF8

Fetch

1 Cycle