VERILOG TUTORIAL 1

DaNang University of Technology

Prepaired by:
Kien T.Nguyen, Lab Assistant
Thanh Vu, Lab Assistant
Anh H.D.Nguyen, Lab Assistant
AP-ECE
Materials
Tools:
Specification: Word, AbiWord, Open Office
RTL coding: HDL TurboWriter, Notepad++, Vim,
Emacs, conTEXT
Simulation: iVerilog, ModelSim, Quartus
Simulator, ISE Simulator
Synthesis: Quartus, Xilinx ISE
Website:
www.asic-world.com
www.dut.udn.vn/ece

References
EE271 A Brief Logic Tutorial, Brian J.Tocco
Stephen Brown, Fundamentals of Digital Logic
with Verilog, Verilog reference, App A.
Introductory Digital Systems Laboratory, MIT
Don Thomas, The Verilog Hardware Description
Language, Carnegie Mellon University.
IEEE Verilog 1364 - 1995
IEEE Verilog 1364 - 2001
EVITA-Verilog interactive tutorial (software)
Verilog Tutorial, www.asic-world.com
Lectures Outline
1. Introduction to logic circuit
2. Verilog Tutorial.
3. Lab 1: Design and simulate mux module.
4. Lab 2: Gate level vs behavior level
5. Lab 3: Introduction DE1 Kit
1.Introduction to logic circuit
A binary switch A Light controlled by a switch
Light = X
What is logic circuit ?
1.Introduction to logic circuit
(contd)
Light (Z) = X.Y Light (Z) = X + Y
Basic Logic gate, symbol & function
1.Introduction to logic circuit
(contd)
Z = X.Y
Z = X+Y
Z = X+Y = X.Y + X.Y Z = X+Y = X.Y + X.Y
1.Introduction to logic circuit (contd)
Truth table is a mathematics
table which is used to specify
the functionality of a digital logic
circuit.
Ex1: Check again !!
X Y X Y X.Y X.Y X+Y X+Y X+Y X+Y
0 0
0 1
1 0
1 1

1 1
1 0
0 1
0 0
Ex2: Think more!! And can you draw circuits?
x y z x.y.z x+y+z x.y + z (x+y).z
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Truth Table in Digital circuit
1.Introduction to logic circuit (contd)
Decimal system: S={0;1;2;3;.;9};
123 = 1x10^2 + 2x10^1 + 2x10^0
Binary system: S = {0;1};
1001 = 1x2^3 + 0x2^2 + 0x2^1 + 1x2^0 = 8 + 1 = 9
Convert Decimal to Binary:
11 : 2 remain1
= 5 : 2 remain 1 => 1011
= 2: 2 remain 0
= 1:2 remain 1
=0
Practice covert 1101 to decimal, 15 to binary ?
2.Verilog Tutorial
2.1 Structural Models
2.2 Behavioral Models
2.3 Variable
2.4 Operator
2.5 Complex Statement
2.6 Testbench

2.1 Structural Models
Overview: also call Gate level Models
2.1 Structural Models (contd)
2.1 Structural Models (contd)
2.2 Behavioral Models
2.2 Behavioral Models (contd)
2.2 Behavioral Models (contd)
2.2 Behavioral Models (contd)
2.2 Behavioral Models (contd)
Sensitivity list
2.3 Variable
reg: store value until another value is assigned to
it. Ex: reg sda;
wire: connect signal together
time: 64 bit wide register use to store time value.
Only use in simulate
integer: 32 bit register
real: for store real numeric value
realtime: time value using real type
Arrays: Ex reg sda [7:0]; wire sda_wire [7:0];
Vector: Ex reg [7:0] sda;

2.4 Operator
Arithmetic Operators:
Addition +
Subtraction
Multiplication *
Division :
Modulo %
Relative Operators:
Lower <
Larger >
Lower or equal <=
Larger or equal >=
Read more in EVITA-Verilog: Chapter 5, Section 3
2.4 Operator (contd)
Equality operators
Equal: ==
Not equal: !=
Logical operators
And: && . Ex: A = 2; B = 0; A&&B = 0
Or: ||. Ex: A = 2; B = 0; A||B = 1
Not: !
Bitwise operators
And: & Ex: A = 2b10; B = 2b00; A&B = 2b00
Or: | Ex: A = 2b10; B = 2b00; A|B = 2b10
Not: ~ Ex: A = 2b10; B = ~A = 2b01
Xor: ^ Ex: A = 2b10; B = 2b00; A|B = 2b10
Xnor: ~^ Ex: A = 2b10; B = 2b00; A|B = 2b01
Read more in EVITA-Verilog: Chapter 5, Section 3
2.4 Operator (contd)
Redunction operators
And: & Ex: A = 4b1010; B = &A = A[3] & A[2] & A[1] &
A[0] = 1b0
Or: | Ex: A = 4b1010; B = |A = 1b1
Nand: ~& Ex: A = 4b1010; B = ~&A = 1b1
Nor: ~| Ex: A = 4b1010; B = ~|A = 1b0
Xor: ^ Ex: A = 4b1010; B = ^A = 1b0
Xnor: ~^ Ex: A = 4b1010; B = ~^A = 1b1
Shift operators
Shift left: <<
Shift right: >>
Concatenation and Replication Operators
Read more in EVITA-Verilog: Chapter 5, Section 3
2.5 Complex statements
Always and initial blocks (already know)
The if-else statement (already know)
The case statement
Loop statements
The case statement
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
output out; input i0, i1, i2, i3;
input s1, s0;
reg out;

always @(s1 or s0 or i0 or i1 or i2 or i3)
begin
case ({s1, s0})
2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;
2'b11: out = i3;
default: out = 1'bx;
endcase
end
endmodule
Loop statements
Why loop

integer count;
initial
begin
count = 0;
while (count < 128)
begin
$display("Count = %d", count);
count = count + 1;
end
end
For loop

integer count;
initial
begin
count = 0;
for (count = 0;count < 128; count = count
+1 )
begin
$display("Count = %d", count);
count = count + 1;
end
end
2.6 Test bench
UUT is an instance module which map to the
real modules for simulating
Test bench Mux model
dut
f
b
c
sel
stimulus
measure
mux_tb
Icarus Simulation
Compile verilog file to data
out file

Generate vcd file for
simulation

Run gtkwave simulation
with that vcd file
iverilog *.v
vvp a.out
gtkwave dump.vcd
See more in: How to run Icarus?
Lab 1
Coding mux module and mux_tb module using
notepad++.
Complile verilog file with iverilog
iverilog [path]/mux.v
Generate vcd file with vvp
vpp a.out
Simulation mux module in GTKWAVE
gtkwave dump.vcd
Save the result waveform to a picture
Lab 2
Coding gate level mux module using
notepad++. (Slide 10)
Compile, Simulation mux module in
GTKWAVE
Save result waveform to a picture. Compare
the results between Lab 1 and Lab 2. What are
differences? Why ? Why do we have to assign
the delay value ?