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    15MPE1019

    Uploaded by

    Polumuri Ramana
    This document contains a 10 question quiz on ARM processors with multiple choice answers and explanations. It covers topics like which ARM processor is best for hard real-time systems, using call stacks to determine which function caused an abort, using read-modify-write sequences to change control register bits, Program Status Register transfer instructions, the values of the I and F bits in the Program Status Register on reset, ARM instruction encoding, the MVN instruction for 1's complement, the BEQ instruction checking the Z flag, the RN directive for registers, and the purpose of banked registers for mode switching.

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    15MPE1019

    Uploaded by

    Polumuri Ramana
    92 views12 pages
    This document contains a 10 question quiz on ARM processors with multiple choice answers and explanations. It covers topics like which ARM processor is best for hard real-time systems, using call stacks to determine which function caused an abort, using read-modify-write sequences to change control register bits, Program Status Register transfer instructions, the values of the I and F bits in the Program Status Register on reset, ARM instruction encoding, the MVN instruction for 1's complement, the BEQ instruction checking the Z flag, the RN directive for registers, and the purpose of banked registers for mode switching.

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    Processor

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    This document contains a 10 question quiz on ARM processors with multiple choice answers and explanations. It covers topics like which ARM processor is best for hard real-time systems, using call stacks to determine which function caused an abort, using read-modify-write sequences to change control register bits, Program Status Register transfer instructions, the values of the I and F bits in the Program Status Register on reset, ARM instruction encoding, the MVN instruction for 1's complement, the BEQ instruction checking the Z flag, the RN directive for registers, and the purpose of banked registers for mode switching.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    92 views12 pages

    15MPE1019

    Uploaded by

    Polumuri Ramana
    This document contains a 10 question quiz on ARM processors with multiple choice answers and explanations. It covers topics like which ARM processor is best for hard real-time systems, using call stacks to determine which function caused an abort, using read-modify-write sequences to change control register bits, Program Status Register transfer instructions, the values of the I and F bits in the Program Status Register on reset, ARM instruction encoding, the MVN instruction for 1's complement, the BEQ instruction checking the Z flag, the RN directive for registers, and the purpose of banked registers for mode switching.

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    Advanced Processors for

    Power Electronics and


    Drives
    EEE672
    Assignment
    Submitted by
    15MPE1019

    Objective questions
    1) Which of the following processors would be best
    suited to a system requiring hard real-time
    responses, such as a hard drive controller?
    A) ARM1136 B) Cortex-A5
    C) Cortex-R4
    D) Cortex-A9
    Answer C is correct.
    Explanation :- The Real-time profile defines an
    architecture aimed at systems that need
    deterministic timing and low interrupt latency

    2) Program execution has caused an abort. The Call Stack


    view is as follows:
    setup() -> main() -> foo() -> bar() Which function caused
    the abort?
    A) main() B) bar() C) foo() D) setup()
    Answer B is correct.
    Explanation:- ARM DS-5 Using the Debugger , Examining
    the call stack explains that the call stack is an area of
    memory used to store function return information and local
    variables. As each function is called, a record is created on
    the call stack. Also, When a function completes execution
    the associated stack frame is removed from the call stack.
    So the call stack contains entries for all functions which are
    currently active. The last one in the chain must, logically, be
    the one which was executing when the abort occurred

    3) Assume a control register has a value of


    0xFECBCA56.
    Which of the following actions is needed to set bit 3 of
    the control register without changing other bits?
    A) Read-Modify-Write sequence of the control register
    B) No operation is required since bit 3 is already 1
    C) A bitwise AND of the control register value with 0x08
    D) A Write-Modify-Read sequence of the control
    register
    Answer A is correct.
    Explanation:- ARM recommends following good coding
    practice which is to use a read modify-write sequence
    to change hardware registers.

    4) Which of the following instructions are called


    Program Status Register transfer instructions?
    A) LDR, STR B) LDM, STM
    C) MCR, MRC D) MSR, MRS
    Answer D is correct.
    Explanation:- describes the functionality of the
    MSR/MRS instructions as transferring values
    between CPSR/SPSR and a general purpose
    register. LDR/STR are used to transfer single
    words between memory and general purpose
    registers. LDM/STM are used to transfer multiple
    words between memory and general purpose
    registers. MCR/MRC are used to transfer values
    between
    general
    purpose
    registers
    and
    coprocessor registers.

    5) What are the values of the I and F bits in the


    Program Status Register on reset?
    A) I=0, F=0
    B) I=1, F=1
    C) I=0, F=1
    D)
    I=1, F=0
    Answer B is correct.
    Explanation:shows the state of the I and F bits on taking a
    Reset exception. The values shown mean that both
    IRQ and FIQ are disabled on reset.

    6) Each instruction in ARM machines is encoded


    into ____ Word .
    a) 2 byte
    b) 3 byte
    c) 4 byte
    d) 8 byte
    Answer:c
    Explanation:The data is encrypted to make
    them secure.

    7) _____ instruction is used to get the 1s


    compliment of the operand .
    a) COMP
    b) BIC
    c) ~CMP
    d) MVN
    Answer : d
    Explanation:The compliment of all the bits of a
    data is its 1s compliment.

    8) The BEQ instructions is used,


    a) To check the equality condition between the
    operands and then branch
    b) To check if the Operand is greater than the
    condition value and then branch
    c) To check if the flag Z is set to 1 and then
    causes branch
    d) None of the above
    Answer:c
    Explanation:This instruction is basically used to
    check the branch enable bit.

    9) _____ directive is used to name the register


    used for execution of an instruction .
    a) ASSIGN
    b) RN
    c) NAME
    d) DECLARE
    View Answer
    Answer : b
    Explanation:This instruction is used to list the
    registers used for execution.

    10) The banked registers are used for,


    a) Switching between supervisor and interrupt
    mode
    b) Extended storing
    c) Same as other general purpose registers
    d) Both a and c
    Answer:a
    Explanation:When switching from one mode to
    another, instead of storing the register contents
    somewhere else itll be kept in the duplicate
    registers and the new values are stored in the
    actual registers.

    Thank you

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