Contents:: Salient Features of 80386 Functional Block Diagram of 80836 Pin Description of 8086

Contents:
Salient Features of 80386

Functional Block Diagram of 80836
Pin Description of 8086
8/18/16
Architecture of 80386
Salient Features of 80386

It Supports 8 bit, 16 bit, 32 bit data
It has 132 pins.
It has 16, 32-bit registers
It supports 32-bit data bus and 32-bit
non-multiplexed address bus

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Contd
It supports
Physical Memory of 4GB
Maximum Segment size of 4GB
Virtual Memory of 64TB (4GB seg. x 16K (16,384)
segments)
3 Types of 80386
1. 80386DX (floating point capability)

2. 80386SX (16-bit data bus & 24-bit address bus)
3. 80386SL (several power management options)
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Contd
It operates in 3 different modes
Real
Protected
Virtual .
MMU provides virtual memory, paging
and 4 levels of protection

Low cost & low power consumption.
Clock Frequency : 20MHz and 33MHz
It has 16 byte code queue
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**Snapshot of 80386
Central Processing Unit
Memory Management Unit
Bus Control Unit
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Memory Management Unit Bus Control Unit
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Central Processing Unit

Central Processing
Unit
The CPU is further divided into:
Execution Unit
Instruction Unit
Execution Unit:
Execution unit has 8 General and Special purpose
registers, which are either used for handling data or

calculating offset addresses.
The 64-bit barrel shifter increases the
speed of all shift, rotate.
Multiply/divide logic implements the bitshift-rotate algorithms to complete the
operation in minimum time.
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Instruction Unit:
It decodes the opcode bytes received from the
16-byte instruction code queue and arrange

them into a 3-decoded instruction queue.
After decoding it is passed to control section
for deriving necessary control signals

A Protection Test Unit provides/gives
protection to the programs or instruction
based on their Privilege.
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The MMU is further divided into:
Segmentation Unit
Paging Unit
Segmentation Unit:
Uses of two address components - segment and offset
for relocability and sharing of data.

It allows a maximum segment size of 4GB.
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Paging Unit
It organizes physical memory in terms of pages of 4KB
size.
It works under the control of segmentation unit i.e. each
segment is divided into pages.
It converts linear addresses into physical addresses.
The control and attribute PLA checks privileges at page
level.
The virtual memory is also organizes in terms of segments
and pages by the memory management unit.
If paging is not used, then Linear address itself is
the Physical address.
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Bus Control Unit

It has a prioritizer to resolve the priority of various bus
requests. This controls the access of the bus.

The address driver drives the bus enable and address
signals A2 A31.
The pipeline and dynamic bus sizing unit handle the
related control signals.

The data buffers interface the internal data bus with
the system bus.
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Register Organization
The 80386 has eight 32 - bit general purpose registers
which may be used as either 8 bit or 16 bit registers.

A 32 - bit register known as an extended register, is
represented by the register name with prefix E.

Example : A 32 bit register corresponding to AX is EAX,
similarly BX is EBX etc.

The 16 bit registers BP, SP, SI and DI in 8086 are now
available with their extended size of 32 bit and are

names as EBP,ESP,ESI and EDI.
AX represents the lower 16 bit of the 32 bit register
EAX.
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13
Contd
BP, SP, SI, DI represents the lower 16 bit of their
32 bit counterparts, and can be used as

independent 16 bit registers.
The six segment registers available in 80386 are
CS, SS, DS, ES, FS and GS.

The CS and SS are the code and the stack
segment registers respectively, while DS, ES,FS,

GS are 4 data segment registers.
A 16 bit instruction pointer IP is available along
with 32 bit counterpart EIP.

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15
Flag Register
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16
Flag Register of 80386: The Flag register of 80386
is a 32 bit register. Out of the 32 bits, Intel has

reserved bits D18 to D31, D5 and D3, while D1 is
always set at 1.Two extra new flags are added to
the 80286 flag to derive the flag register of 80386.
They are VM and RF flags
VM - Virtual Mode Flag: If this flag is set, the 80386
enters the virtual 8086 mode within the protection

mode. This is to be set only when the 80386 is in
protected mode. In this mode, if any privileged
instruction is executed an exception 13 is
generated. This bit can be set using IRET
instruction or any task switch operation only in the
protected mode.
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RF- Resume Flag: This flag is used with the debug
register breakpoints. It is checked at the starting

of every instruction cycle and if it is set, any
debug fault is ignored during the instruction
cycle. The RF is automatically reset after
successful execution of every instruction, except
for IRET and POPF instructions.
Also, it is not automatically cleared after the
successful execution of JMP, CALL and INT

instruction causing a task switch. These
instruction are used to set the RF to the value
specified by the memory data available at the
stack.
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Segment Descriptor Registers: This registers are not
available for programmers, rather they are internally

used to store the descriptor information, like attributes,
limit and base addresses of segments. The six segment
registers have corresponding six 73 bit descriptor
registers. Each of them contains 32 bit base address,
32 bit base limit and 9 bit attributes. These are
automatically loaded when the corresponding segments
are loaded with selectors.
Control Registers: The 80386 has three 32 bit control
registers CR0, CR2 and CR3 to hold global machine

status independent of the executed task. Load and
store instructions are available to access these
registers.CR1 is INTEL Reserved
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System Address Registers: Four special registers are defined to
refer to the descriptor tables supported by 80386.The 80386

supports four types of descriptor table, viz. Global Descriptor
Table (GDT), Interrupt Descriptor Table (IDT), Local Descriptor
Table (LDT) and Task State Segment Descriptor (TSS). The
system address and system segment registers hold the
addresses of these descriptor tables and the corresponding
segments. These registers are known as GDTR, IDTR, LDTR and
TR respectively. The GDTR & IDTR are called system address and
LDTR & TR are called system segment registers.
Debug and Test Registers: Intel has provide a set of 8 debug
registers for hardware debugging. Out of these eight registers

DR0 to DR7, two registers DR4 and DR5 are Intel reserved. The
initial four registers DR0 to DR3 store four program controllable
breakpoint addresses, while DR6 and DR7 respectively hold
breakpoint status and breakpoint control information. Two more
test registers are provided by 80386 for page caching namely
test control and test status register.
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Debug and Test Registers

0
32
Linear Breakpoint
Address 0
DR0
Linear Breakpoint
Address 1
DR1
DR2
Linear Breakpoint
Address 2
DR3
DR4
Linear Breakpoint
Address 3
DR5
Intel Reserved
DR6
Intel Reserved
DR7
Breakpoint Status
Breakpoint Control
32
Test Control
Test Status
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0
TR6
TR7
21
Pin Layout
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W/R#: The write / read output distinguishes the write and read cycles from one
another.
D/C#: Whether the bus operation is data R/W or control word transfer.
M/IO#: Operation is memory or I/O.
PEREQ: Requset to fetch first part of data word for coprocessor.
BUSY#: Coprocessor uses this to notify that, instruction execution is going on.
LOCK#: The LOCK output pin enables the CPU to prevent the other bus masters
from gaining the control of the system bus.
NA#: The next address input pin, if activated, allows address pipelining.
ADS#: The address status output pin indicates that the address bus and bus cycle
definition pins( W/R#, D/C#, M/IO#, BE0# to BE3# ) are carrying the respective valid
signals.
ERROR#: It indicates to the CPU that the coprocessor has encountered an error
while executing its instruction.
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BS16#: The bus size 16 input pin allows the interfacing of 16 bit devices with the
32 bit wide 80386 data bus.

READY#: The ready signals indicates to the CPU that the previous bus cycle has
been terminated and the bus is ready for the next cycle.
HOLDA: It indicates that a valid bus hold request has been received and the bus
has been relinquished by the CPU

HOLD: Enables the other bus masters to gain control of the system bus if it is
asserted
INTR: Maskable Interrupt Request (IF = 1 Enable, 0 Disable)
NMI: Non Maskable Interrupt
N/C: No Connection
VCC: These are system power supply lines.
VSS/GND: These return lines for the power supply.
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S.
N.
Parameter
8086
80386
Number of Pins
40
132
Pin Nature (Package)
DIP
No DIP (PGA)
Clock rate
Supports 5,8 &

10Mhz
20 & 33 MHz
Operating Mode
2(viz. minimum &

Maximum)
3(viz. real,
protected &
virtual)
Signal Category
Number of Registers
14, 16bit
16, 32 bit
Processor
16bit
32bit
Architecture Composition in
unit
2 (viz. EU, BIU)
3(CPU,MMU &
BCU)
Data Bus
16 bit
32 bit
10
Address Bus
20 bit
32 bit
11
Memory Access
Up to 1 MB
Up to 4 GB
12
Power Consumption
High
Low
Cost
High
Low
13
8/18/16
26

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Contents:

Salient Features of 80386

Salient Features of 80386

non-multiplexed address bus

1. 80386DX (floating point capability)

MMU provides virtual memory, paging

and 4 levels of protection

Memory Management Unit Bus Control Unit

Central Processing Unit

registers, which are either used for handling data or

16-byte instruction code queue and arrange

for deriving necessary control signals

Memory Management Unit

for relocability and sharing of data.

Memory Management Unit

Bus Control Unit

requests. This controls the access of the bus.

related control signals.

which may be used as either 8 bit or 16 bit registers.

represented by the register name with prefix E.

similarly BX is EBX etc.

available with their extended size of 32 bit and are

32 bit counterparts, and can be used as

CS, SS, DS, ES, FS and GS.

segment registers respectively, while DS, ES,FS,

with 32 bit counterpart EIP.

Flag Register of 80386: The Flag register of 80386

is a 32 bit register. Out of the 32 bits, Intel has

enters the virtual 8086 mode within the protection

RF- Resume Flag: This flag is used with the debug

register breakpoints. It is checked at the starting

successful execution of JMP, CALL and INT

Segment Descriptor Registers: This registers are not

available for programmers, rather they are internally

registers CR0, CR2 and CR3 to hold global machine

System Address Registers: Four special registers are defined to

refer to the descriptor tables supported by 80386.The 80386

registers for hardware debugging. Out of these eight registers

Debug and Test Registers

from gaining the control of the system bus.

while executing its instruction.

32 bit wide 80386 data bus.

has been relinquished by the CPU

Pin Nature (Package)

Supports 5,8 &

2(viz. minimum &

2 (viz. EU, BIU)

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