MPMC

Term:2015-2016
III Year B.-tech I Sem

Unit-IV PPT Slides

UNIT 4 SYLLABUS

4.1 Introduction to Micro-Controller

4.2 Over view of 8051
4.3 Architecture
4.4 I/O Ports
4.5 Memory Organization
4.6 Addressing Modes
4.7 Instruction Set
4.8 Simple programs in Embedded C
4.9 AVR RISC Micro Controller Architecture
4.10 Register File and ALU.
4.11 Memory Access and Instruction Execution
4.12 I/O Memory and I/O Ports, Timers, UART, Interrupt Structure
4.13 Introduction to ARM Architecture and Controllers

UNIVERSITY QUESTIONS
1. What is the difference between microprocessor and
microcontroller? Give 8051 architecture.
2)Explain standard AVR architecture.
3. Explain memory organization in AVR.
4. Explain internal and external memory of 8051.
5. Explain interrupt structure in AVR.
6. Give any five instructions of 8051 and explain each.
7. Explain register file of AVR.

4.1 INTRODUCTION

8051 Basic Component

4K bytes internal ROM
128 bytes internal RAM
Four 8-bit I/O ports (P0 - P3).
Two 16-bit timers/counters
One serial interface
CP
U

RAM
ROM

I/O
Time Seri
Port
al
r
CO
COM
M
Port
Port

A single chip
Microcontroller

4.2 Over View of 8081 MC

Microprocessor = CPU on a single
chip.
ALU + registers + control +

Micro-computer = small computer

uP + I/O + memory + peripheral +

Microcontroller (uC)
u-Computer on a single chip of silicon

Other 8051 features contd..

only 1 On chip oscillator (external crystal)
6 interrupt sources (2 external , 3 internal, Reset)
64K external code (program) memory(only
read)PSEN
64K external data memory(can be read and write)
by RD,WR
Code memory is selectable by EA (internal or
external)
We may have External memory as data and code

Block Diagram of 8051

contd..
External Interrupts

Interrupt
Control

4k
ROM

Timer 1
Timer 2

128 bytes
RAM

CPU

OSC

Bus
Control

4 I/O Ports

P0 P2 P1
Addr/Data

Serial

P3

TXD RXD

4.3 Architecture of 8051

4.4 I/O Ports

One of the most useful features = four I/O ports (P0 - P3)

Port 0 P0 P0.0 P0.7

8-bit R/W - General Purpose I/O
low byte address and data bus for external memory

Port 1 P1 P1.0 P1.7

Only 8-bit R/W - General Purpose I/O

Port 2 P2 P2.0 P2.7

8-bit R/W - General Purpose I/O
high byte address for external memory

Port 3 P3 P3.0 P3.7

General Purpose I/O
Timers(T0,T1) ext. int (INT0, INT1) Serial (TXD, RXD)- RD,WR

Each port can be used as input or output (bi-direction)

Port 3 Alternate Functions

contd..

Hardware Structure of I/O Pin

contd..
Read latch
B2

Vcc

Internal
Pull-Up
Internal CPU
bus

Write to
latch

P1.X
Clk
Q

M1

B1
Read pin

P1.X
pin

Hardware Structure of I/O Pin

contd..
Each pin of I/O ports
Internally connected to CPU bus
A D latch store the value of this pin
Write to latch 1 write data into the D latch

2 Tri-state buffer
B1: controlled by Read pin
Read pin 1 really read the data present at the pin

B2: controlled by Read latch

Read latch 1 read value from internal latch

A transistor M1 gate
Gate=0: open
Gate=1: close

Port3 Alternate IO contd..

4.5 Memory Organization

Memory Organization Contd

External Code Memory (64k)

External RAM Data Memory (64k)
Internal Code Memory
4k,8k,12k,20k
ROM, EPROM, EEPROM

Internal RAM
First 128 bytes:
00h to 1Fh Register Banks
20h to 2Fh

Bit Addressable RAM

30 to 7Fh General Purpose RAM

Next 128 bytes:
80h to FFh Special Function Registers

External Memory
/EA pin 31 external access
/EA=0 indicates that code is stored externally.
/PSEN ALE are used for external ROM.
For 8051 internal code, /EA pin is connected to
Vcc.
/ means active low.

/PSEN pin 29 program store enable

Output- connected to OE of ROM.
Read signal fetch from ROM

External Memory contd..

ALE pin 30 : address latch
enable
It is an output pin and is active high
8051 port 0 provides both address and data
The ALE pin is used for de-multiplexing the
address and data by connecting to the G pin of
the 74LS373 latch.

Address Multiplexing for

External Memory (code) contd..

1F

On-Chip Memory Internal RAM

contd..
Bank 3

18
17

Bank 2
10
0F

Bank 1
08
07
06
05
04
03
02
01
00

R7
R6
R5
R4
R3
R2
R1
R0

Bank 0

4 Register Banks
Each bank has R0-R7
Selectable by PSW.2,3

Bit Addressable Memory

contd..
2F 7F
2E

78

20h 2Fh
(16 locations 8-bits = 128 bits)

2D
2C

Bit addressing:
mov C, 1Ah
or
mov C, 23h.2

2B
2A
29
28
27
26
25
1A

24
23

10

22 0F

08

21 07
20

06

05

04

03

02

01

00

Program Status Word (PSW) contd..

TMOD Register

Gate :

When set, timer only runs while INT(0,1)

is high.

C/T : Counter/Timer select bit.

M1 : Mode bit 1.
M0 : Mode bit 0.

TCON Register

TF1: Timer 1 overflow flag.

TR1: Timer 1 run control bit.
TF0: Timer 0 overflag.
TR0: Timer 0 run control bit.
IE1: External interrupt 1 edge flag.
IT1: External interrupt 1 type flag.
IE0: External interrupt 0 edge flag.
IT0: External interrupt 0 type flag.

Interrupt

nterrupt Enable Register

EA

---

: Global enable/disable.
: Undefined.

ET2 :Enable Timer 2 interrupt.

ES :Enable Serial port interrupt.
ET1 :Enable Timer 1 interrupt.
EX1 :Enable External 1 interrupt.
ET0 : Enable Timer 0 interrupt.
EX0 : Enable External 0 interrupt.

4.6 Addressing Modes

Immediate Mode specify data by its
value
mov A, #0

;put 0 in the accumulator

;A = 00000000

mov R4, #11h

;put 11hex in the R4 register

;R4 = 00010001

mov B, #11

;put 11 decimal in b register

;B = 00001011

mov DPTR,#7521h

;put 7521 hex in DPTR

;DPTR = 0111010100100001

Addressing Modes Cntd.

Immediate Mode continue
MOV DPTR,#7521h
MOV DPL,#21H
MOV DPH, #75

COUNT EGU 30
~
~

mov R4, #COUNT

MOV DPTR,#MYDATA
~
~

0RG 200H
MYDATA:DB IRAN

Addressing Modes Cntd.

Register Addressing either source or
destination is one of CPU register
MOV R0,A

MOV
ADD
ADD
MOV
MOV
MOV

A,R7
A,R4
A,R7
DPTR,#25F5H
R5,DPL
R,DPH

Note that MOV R4,R7 is incorrect

Addressing Modes Cntd.

Direct Mode specify data by its 8-bit address
Usually for 30h-7Fh of RAM
Mov
Mov
Mov
Mov

a, 70h
R0,40h
56h,a
0D0h,a

; copy contents of RAM at 70h to a

; copy contents of RAM at 40h to R0
; put contents of a at 56h to a
; put contents of a into PSW

Addressing Modes Cntd.

Direct Mode play with R0-R7 by direct
address
MOV A,4

MOV A,R4

MOV A,7

MOV A,R7

MOV 7,2

MOV R7,R6

MOV R2,#5
MOV R2,5

;Put 5 in R2
;Put content of RAM at 5 in R2

Addressing Modes Cntd.

Register Indirect the address of the source or
destination is specified in registers
Uses registers R0 or R1 for 8-bit address:
mov psw, #0
mov r0, #0x3C
mov @r0, #3

; use register bank 0

; memory at 3C gets #3
; M[3C] 3

Uses DPTR register for 16-bit addresses:

mov dptr, #0x9000
movx a, @dptr

; dptr 9000h
; a M[9000]

Note that 9000 is an address in external memory

Addressing Modes Cntd.

Register Indexed Mode source or
destination address is the sum of the
base address and the
accumulator(Index)
Base address can be DPTR or PC
mov dptr, #4000h
mov a, #5
movc a, @a + dptr

;a M[4005]

Addressing Modes Cntd.

Register Indexed Mode

continue

Base address can be DPTR or PC

ORG 1000h

PC

1000
1002
1003

mov a, #5
movc a, @a + PC
Nop

;a M[1008]

Table Lookup
MOVC only can read internal code
memory

4.7 INSTRUCTION SET

Arithmetic Instructions

Add
Subtract
Increment
Decrement
Multiply
Divide
Decimal adjust

Arithmetic Instructions
Mnemonic

Description

ADD A, byte

add A to byte, put result in A

ADDC A, byte

add with carry

SUBB A, byte

subtract with borrow

INC A

increment A

INC byte

increment byte in memory

INC DPTR

increment data pointer

DEC A

decrement accumulator

DEC byte

decrement byte

MUL AB

multiply accumulator by b register

DIV AB

divide accumulator by b register

DA A

decimal adjust the accumulator

ADD Instruction
add a, byte
; a a + byte
addc a, byte
; a a + byte + C
These instructions affect 3 bits in PSW:
C = 1 if result of add is greater than FF
AC = 1 if there is a carry out of bit 3
OV = 1 if there is a carry out of bit 7, but not from bit 6, or
visa versa.

Instructions that Affect PSW

bits

ADD Examples
What is the value of
the C, AC, OV flags
after the second
instruction is
executed?

mov a, #3Fh
add a, #D3h
0011 1111
1101 0011
10001 0010

C = 1
AC = 1
OV = 0

2s
0000

0111
1000

1111

Signed Addition and

Overflow
0111 1111 (positive 127)

complement:
0000 00 0
1111
0000
1111

7F 127
80 -128
FF -1

0111 0011 (positive 115)

1111 0010 (overflow
cannot represent 242 in 8
bits 2s complement)
1000 1111
1101 0011
0110 0010

(negative 113)
(negative 45)
(overflow)

0011 1111 (positive)

1101 0011 (negative)
0001 0010 (never overflows)

Addition Example
; Computes Z = X + Y
; Adds values at locations 78h and 79h and puts them in 7Ah
;-----------------------------------------------------------------X
equ
78h
Y
equ
79h
Z
equ
7Ah
;----------------------------------------------------------------org 00h
ljmp Main
;----------------------------------------------------------------org 100h
Main:
mov a, X
add a, Y
mov Z, a
end

The 16-bit ADD example

; Computes Z = X + Y
(X,Y,Z are 16 bit)
;-----------------------------------------------------------------X
equ
78h
Y
equ
7Ah
Z
equ
7Ch
;----------------------------------------------------------------org 00h
ljmp Main
;----------------------------------------------------------------org 100h
Main:
mov a, X
add a, Y
mov Z, a
mov a, X+1
adc a, Y+1
mov Z+1, a
end

Subtract
SUBB A, byte

subtract with borrow

Example:
SUBB A, #0x4F

;A A 4F C

Notice that
There is no subtraction WITHOUT borrow.
Therefore, if a subtraction without borrow is desired,
it is necessary to clear the C flag.
Example:
Clr c
SUBB A, #0x4F

;A A 4F

Increment and Decrement

INC A

increment A

INC byte

increment byte in memory

INC DPTR

increment data pointer

DEC A

decrement accumulator

DEC byte

decrement byte

The increment and decrement instructions do NOT

affect the C flag.
Notice we can only INCREMENT the data pointer, not
decrement.

Example: Increment 16-bit

Word

Assume 16-bit word in R3:R2

mov a, r2
add a, #1
mov r2, a
mov a, r3
addc a, #0
mov r3, a

; use add rather than increment to affect C

; add C to most significant byte

Multiply
When multiplying two 8-bit numbers, the size of the
maximum product is 16-bits
FF x FF = FE01
(255 x 255 = 65025)

MUL AB

; BA

Note : B gets the High byte

A gets the Low byte

A * B

Division
Integer Division
DIV AB

; divide A by B

A Quotient(A/B)
B Remainder(A/B)
OV - used to indicate a divide by zero condition.
C set to zero

Decimal Adjust
DA a

; decimal adjust a

Used to facilitate BCD addition.

Adds 6 to either high or low nibble after an addition
to create a valid BCD number.
Example:
mov a, #23h
mov b, #29h
add a, b
DA a

; a 23h + 29h = 4Ch (wanted 52)

; a a + 6 = 52

Logic Instructions
Bitwise logic operations

(AND, OR, XOR, NOT)

Clear
Rotate
Swap
Logic instructions do NOT affect the flags in PSW

Bitwise Logic
ANL AND
ORL OR
XRL XOR
CPL Complement

Examples:

ANL

00001111
10101100
00001100

00001111
ORL 10101100
10101111

XRL

00001111
10101100
10100011

CPL

10101100
01010011

Address Modes with Logic

ANL AND
ORL OR
XRL eXclusive oR

a, byte
direct, reg. indirect, reg,
immediate

byte, a
direct

byte, #constant
CPL Complement

ex:

cpl a

Uses of Logic Instructions

Force individual bits low, without affecting other
bits.
anl PSW, #0xE7
;PSW AND 11100111
Force individual bits high.
orl PSW, #0x18

;PSW OR 00011000

Complement individual bits

xrl P1, #0x40

;P1 XRL 01000000

Other Logic Instructions

CLR
RL
RLC
RR
RRC
SWAP

clear
rotate left
rotate left through Carry
rotate right
rotate right through Carry
swap accumulator nibbles

CLR ( Set all bits to 0)

CLR
CLR
CLR
CLR

A
byte
Ri
@Ri

(direct mode)
(register mode)
(register indirect mode)

Rotate
Rotate instructions operate only on a
RL a
Mov a,#0xF0
; a 11110000
RR a ; a 11100001

RR a
Mov a,#0xF0
; a 11110000
RR a ; a 01111000

Rotate through Carry

RRC a

mov a, #0A9h
add a, #14h

; a A9
; a BD (10111101), C0

rrc a

; a 01011110, C1

RLC a

mov a, #3ch
setb c

; a 3ch(00111100)
; c 1

rlc a

; a 01111001, C1

Rotate and
Multiplication/Division
Note that a shift left is the same as
multiplying by 2, shift right is divide by
2
mov
clr
rlc
rlc
rrc

a, #3 ; A 00000011 (3)
C ; C 0
a ; A 00000110 (6)
a ; A 00001100 (12)
a ; A 00000110 (6)

Swap
SWAP a

mov a, #72h
swap a

; a 27h
; a 27h

Bit Logic Operations

Some logic operations can be used with single bit
operands
ANL C, bit
ORL C, bit
CLR C
CLR bit
CPL C
CPL bit
SETB C
SETB bit

bit can be any of the bit-addressable RAM

locations or SFRs.

Program Flow Control

Unconditional jumps (go to)
Conditional jumps
Call and return

Unconditional Jumps
SJMP <rel addr>

Short jump,
relative address is 8-bit 2s complement number,
so jump can be up to 127 locations forward, or 128
locations back.

LJMP <address 16> ;

AJMP <address 11> ;

Long jump

Absolute jump to
anywhere within 2K block of program memory

JMP @A + DPTR
indexed jump

Long

Infinite Loops

Start: mov C, p3.7

mov p1.6, C
sjmp Start

Microcontroller application programs are almost always infinite loops!

Re-locatable Code
Memory specific NOT Re-locatable (machine
code)
org 8000h
Start: mov C, p1.6
mov p3.7, C
ljmp Start
end

Re-locatable (machine code)

org 8000h
Start: mov C, p1.6
mov p3.7, C
sjmp Start
end

Jump table
Mov
Mov
Rl
Jmp

dptr,#jump_table
a,#index_number
a
@a+dptr
...
Jump_table: ajmp case0
ajmp case1
ajmp case2
ajmp case3

Conditional Jump
These instructions cause a jump to occur only if
a condition is true. Otherwise, program
execution continues with the next instruction.
loop: mov a, P1
jz loop

; if a=0, goto loop,

; else goto next instruction

mov b, a

There is no zero flag (z)

Content of A checked for zero on time

Conditional jumps
Mnemonic

Description

JZ <rel addr>

Jump if a = 0

JNZ <rel addr>

Jump if a != 0

JC <rel addr>

Jump if C = 1

JNC <rel addr>

Jump if C != 1

JB <bit>, <rel addr>

Jump if bit = 1

JNB <bit>,<rel addr>

Jump if bit != 1

JBC <bir>, <rel addr>

Jump if bit =1,

bit

&clear

CJNE A, direct, <rel addr> Compare A and memory,

jump if not equal

Example: Conditional Jumps

if (a = 0) is true

send a 0 to LED
else

send a 1 to LED

jz led_off
Setb P1.6
sjmp skipover
led_off: clr P1.6
mov A, P0
skipover:

More Conditional Jumps

Mnemonic

Description

CJNE A, #data <rel addr>

Compare A and data, jump

if not equal

CJNE Rn, #data <rel addr>

Compare Rn and data,

jump if not equal

CJNE @Rn, #data <rel addr> Compare Rn and memory,

jump if not equal
DJNZ Rn, <rel addr>

Decrement Rn and then

jump if not zero

DJNZ direct, <rel addr>

Decrement memory and

then jump if not zero

Iterative Loops
For A = 0 to 4 do
{}
clr a
loop: ...
...
inc a
cjne a, #4, loop

For A = 4 to 0 do
{}
mov R0, #4
loop: ...
...
djnz R0, loop

Iterative Loops(examples)
mov a,#50h
mov b,#00h
cjne a,#50h,next
mov b,#01h
next: nop
end
mov a,#0aah
mov b,#10h
Back1:mov r6,#50
Back2:cpl a
djnz r6,back2
djnz b,back1
end

mov a,#25h
mov r0,#10h
mov r2,#5
Again: mov @ro,a
inc r0
djnz r2,again
end
mov a,#0h
mov r4,#12h
Back: add a,#05
djnz r4,back
mov r5,a
end

Call and Return

Call is similar to a jump, but

Call pushes PC on stack before branching
acall <address ll>
; stack PC
; PC address 11 bit

lcall <address 16>

; stack PC
; PC address 16 bit

Return
Return is also similar to a jump, but
Return instruction pops PC from stack to
get address to jump to
ret

; PC stack

Subroutines
call to the subroutine
Main:

sublabel:

...
acall sublabel
...
...
...
...
the subroutine
ret

Initializing Stack Pointer

SP is initialized to 07 after reset.(Same address as R7)

With each push operation 1st , pc is increased

When using subroutines, the stack will be used to store the

PC, so it is very important to initialize the stack pointer.
Location 2Fh is often used.

mov SP, #2Fh

Subroutine - Example
square: push b
mov b,a
mul ab
pop b
ret
8 byte and 11 machine cycle

square: inc a
movc a,@a+pc
ret
table: db 0,1,4,9,16,25,36,49,64,81
13 byte and 5 machine cycle

Subroutine another example

; Program to compute square root of value on Port 3
; (bits 3-0) and output on Port 1.
org 0
ljmp Main
Main:
loop:

sqrt:

Sqrs:

mov P3, #0xFF

mov a, P3
anl a, #0x0F
lcall sqrt
mov P1, a
sjmp loop

reset service

; Port 3 is an input
; Clear bits 7..4 of A

inc a
movc a, @a + PC
ret
db 0,1,1,1,2,2,2,2,2,3,3,3,3,3,3,3
end

main program

subroutine
data

Why Subroutines?
Subroutines allow us to have
"structured" assembly language
programs.
This is useful for breaking a large
design into manageable parts.
It saves code space when
subroutines can be called many
times in the same program.

example of delay
mov a,#0aah
Back1:mov p0,a
lcall delay1
cpl a
sjmp back1
Delay1:mov r0,#0ffh;1cycle
Here: djnz r0,here ;2cycle
ret
;2cycle
end
Delay=1+255*2+2=513 cycle

Delay2:
mov r6,#0ffh
back1: mov r7,#0ffh ;1cycle
Here: djnz r7,here ;2cycle
djnz r6,back1;2cycle
ret
;2cycle
end
Delay=1+(1+255*2+2)*255+2
=130818 machine cycle

Long delay Example

GREEN_LED:
org ooh
ljmp Main
org
Main:
Again:

P1.6

reset service

100h

cpl
sjmp

Delay:
Loop1:
Loop0:

clr
GREEN_LED
acall Delay
GREEN_LED
Again

mov
mov
mov

main program

R7, #02
R6, #00h
R5, #00h

djnz
djnz

R5, $
R6, Loop0

djnz

R7, Loop1

ret
END

equ

subroutine

Example
; Move string from code memory to RAM
org 0
mov dptr,#string
mov r0,#10h
Loop1:
clr a
movc a,@a+dptr
jz stop
mov @r0,a
inc dptr
inc r0
sjmp loop1
Stop:
sjmp stop
; on-chip code memory used for string
org 18h
String:
db this is a string,0
end

Example
; p0:input p1:output
mov a,#0ffh
mov p0,a
back:
mov a,p0
mov p1,a
sjmp back

Again:
request

setb p1.2
mov a,#45h
;data
jnb p1.2,again ;wait for data
mov p0,a
setb p2.3
clr p2.3

;enable strobe

Example
; duty cycle 50%
back:
cpl p1.2
acall delay
sjmp back
back:

setb p1.2
acall delay
Clr p1.2
acall delay
sjmp back

Example
; duty cycle 66%
back:
setb p1.2
acall delay
acall delay
Clr p1.2
acall delay
sjmp back

4.9 AVR RISC Micro Controller

Architecture
Harvard Architecture

Harvard Architecture diagram

AVR RISC Micro Controller

Architecture contd.
A series of 8-bit RISC microcontrollers from Atmel.
All AVR microcontrollers share same instruction set and a
basic CPU (Harvard) architecture.
It has 32 8-Bit general purpose registers.
Mostly instruction Execute in Single clock cycle. Which
makes it faster among 8 bit microcontrollers.
AVR was designed for efficient execution of compiled C
code.

4.10 AVR REGISTER

FILE
Registers:

Two types of registers

GERNEL purpose & SPECIAL purpose registers

GERNEL purpose
32 general purpose registers having storage capacity of 8-Bits
Named as R0,R1,R2 to R31.
Register 0 to 15 & 16 to 31 are different.
Can store both Data & Addresses.
SPECIAL purpose: Three registers

Program counter
Stack Pointer
Status Register

AVR REGISTER FILE

contd
Pointer Register

Three 16-bit address registers pairs of registers 26 to 31

have extra meaning in AVR assembly.
X (r27:r26), y (r29:r28), z (r31:r30).
pointer

Sequence

Read/Write from address X,

don't change the pointer

AVR REGISTER FILE

contd
status register (SREG) that contains

It is 8-bit long each bit has a different meaning.

I

I: Global Interrupt Enable/Disable Flag, SREG7

T: Transfer bit used by BLD and BST instructions, SREG6
H: Half Carry Flag, SREG5
S: For signed tests Instruction Set, SREG4
V: Two's complement overflow indicator, SREG3
N: Negative Flag, SREG2
Z: Zero Flag, SREG1
C: Carry Flag, SREG0

4.11 AVR

Memory Access

Memory:
Program Memory (Flask
Memory)
2K Bytes of flash memory
128 Bytes of In-System
Programmable EEPROM
program memory holds
interrupt function addresses,
16 bit and double word (32
bit) opcode, and static data
tables

Data Memory

Used for data and is separate from the program

memory.
128 Bytes of SRAM
Register reassigned the 32 Data Space addresses
($00 - $1F),
I/O memory space contains 64 addresses for CPU
peripheral functions such as
control registers,
Timer/Counters,
A/D converters and other I/O functions. I/O
memory can be accessed directly or as the Data
Space locations those of the Register File, $20 $5F.
Stack is effectively allocated in the general data
SRAM, and consequently the stack size is only limited
by the total SRAM size and the usage of the SRAM.

AVR
AT90S2313 instruction Architecture
AVR Instruction SET
118 Powerful Instructions Most Single Clock Cycle Execution
All arithmetic operations are done on registers R0 - R31
Mostly instructions take one cycle for execution
ADD Rd,Rr
Rd: Destination (and source) register in the Register File
Rr: Source register in the Register File

Instruction Execution
Instruction add R23, R11
Be encoded as the 16-bit opcode 0x0EEB.
Bit pattern :

0000 1110 1110 1011

Three components.
5 red bits 00011 distinguish this as an add
instruction.
5 blue bits 10111 indicates register 23 is the first
operand register.
The 5 green bits 01011 indicates register 11 is
the second operand register.
All add Rd, Rr instructions follow this pattern.

4.12 AVR I/O Memory

and I/O Ports
Three I/O memory address locations are allocated for the Port D:
Data Register (read/write) PORTD
Data Direction Register (read/write) DDRD
Port D Input Pins(read-only) PIND

AVR I/O Memory and I/O

Ports contd..
Port B Data Register PORTB

Port B Data Direction Register DDRB

Port B Input Pins Address PINB

AVR I/O Memory and I/O

Ports contd..
CPU
Up to 10 MIPS Throughput at 10 MHz
The AVR is a Harvard architecture CPU, The AVR is a Harvard
architecture CPU,
Program Memory Is separated from data Memory
Program memory is accessed with a single level pipelining
(Fetch & execute).

AVR

AT90S2313 Extra factures

Peripheral Features

One 8-bit Timer/Counter with Separate Prescaler

One 16-bit Timer/Counter with Separate Prescaler,

Compare, Capture Modes and 8-, 9-, or 10-bit PWM

On-chip Analog Comparator

Programmable Watchdog Timer with On-chip Oscillator

SPI Serial Interface for In-System Programming

FullDuplexUART

4.13 Introduction to ARM

Architecture

ARM provides hard and soft views to licencees

Licencees have the right to use hard or soft views of the IP

RTL and synthesis flows

GDSII layout
soft views include gate level netlists
hard views are DSMs

OEMs must use hard views

to protect ARM IP

Data Sizes and Instruction Sets

The ARM is a 32-bit architecture.
When used in relation to the ARM:
Byte means 8 bits
Halfword means 16 bits (two bytes)
Word means 32 bits (four bytes)

Most ARMs implement two instruction sets

32-bit ARM Instruction Set
16-bit Thumb Instruction Set

Jazelle cores can also execute Java bytecode

Processor Modes
The ARM has seven basic operating modes:
User : unprivileged mode under which most tasks run
FIQ : entered when a high priority (fast) interrupt is raised
IRQ : entered when a low priority (normal) interrupt is raised
Supervisor : entered on reset and when a Software Interrupt
instruction is executed
Abort : used to handle memory access violations
Undef : used to handle undefined instructions
System : privileged mode using the same registers as user mode

Register Organization Summary

User
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)
r15 (pc)

FIQ

User
mode
r0-r7,
r15,
and
cpsr

IRQ

SVC

User
mode
r0-r12,
r15,
and
cpsr

User
mode
r0-r12,
r15,
and
cpsr

Undef

User
mode
r0-r12,
r15,
and
cpsr

Abort

User
mode
r0-r12,
r15,
and
cpsr

r8
r9
r10
r11
r12
r13 (sp)
r14 (lr)

r13 (sp)
r14 (lr)

r13 (sp)
r14 (lr)

r13 (sp)
r14 (lr)

r13 (sp)
r14 (lr)

spsr

spsr

spsr

spsr

spsr

Thumb state
Low registe

Thumb state
High registe

cpsr

Note: System mode uses the User mode register set

The Registers

ARM has 37 registers all of which are 32-bits long.

1 dedicated program counter

1 dedicated current program status register
5 dedicated saved program status registers
30 general purpose registers

The current processor mode governs which of several banks is

accessible. Each mode can access

a particular set of r0-r12 registers

a particular r13 (the stack pointer, sp) and r14 (the link register, lr)
the program counter, r15 (pc)
the current program status register, cpsr

Privileged modes (except System) can also access

a particular spsr (saved program status register)

Program Status Registers

31

28 27

NZCVQ
f

23

16 15

U n d e f i n e d
s
x

Condition code flags

24

N = Negative result from ALU

Z = Zero result from ALU
C = ALU operation Carried out
V = ALU operation oVerflowed

Architecture 5TEJ only

J = 1: Processor in Jazelle state

IFT

mode
c

Interrupt Disable bits.

T Bit
Architecture xT only
T = 0: Processor in ARM state
T = 1: Processor in Thumb state

Sticky Overflow flag - Q flag

J bit

I = 1: Disables the IRQ.

F = 1: Disables the FIQ.

Architecture 5TE/J only

Indicates if saturation has occurred

Mode bits
Specify the processor mode

Program Counter (r15)

When the processor is executing in ARM state:
All instructions are 32 bits wide
All instructions must be word aligned
Therefore the pc value is stored in bits [31:2] with bits [1:0]
undefined (as instruction cannot be halfword or byte aligned).

When the processor is executing in Thumb state:

All instructions are 16 bits wide
All instructions must be halfword aligned
Therefore the pc value is stored in bits [31:1] with bit [0]
undefined (as instruction cannot be byte aligned).

When the processor is executing in Jazelle state:

All instructions are 8 bits wide
Processor performs a word access to read 4 instructions at once

Exception Handling
When an exception occurs, the ARM:
Copies CPSR into SPSR_<mode>
Sets appropriate CPSR bits
0x1C
Change to ARM state
Change to exception mode
Disable interrupts (if appropriate)

FIQ
IRQ
(Reserved)
Data Abort
Prefetch Abort

0x18
0x14
0x10
0x0C
Stores the return address in LR_<mode>
Software Interrupt
0x08
Sets PC to vector address
Undefined Instruction
0x04
To return, exception handler needs
Reset
0x00 to:

Restore CPSR from SPSR_<mode>

Restore PC from LR_<mode>

This can only be done in ARM

Vector
table can
be at
Vector
Table
0xFFFF0000 on
state.and onARM720T
ARM9/10 family
devices

Development of the
ARM Architecture
1
2

Halfword
and
signed
halfword /
byte
support

System
3
mode
Thumb
instructi
Early
on set
ARM
ARM7TD
architectu MI
res
ARM720T

4
SA-110
SA1110

4T
ARM9TD
MI
ARM940
T

Improved
ARM/Thu 5TE
mb
Interworki
ng
Saturated
maths
CLZ
DSP multiplyaccumulate
ARM102
instructions
0E
XScale
ARM9E-S
ARM966E
-S

Jazelle

5TEJ

Java bytecode
execution
ARM9EJS
ARM7EJS

ARM926EJS
ARM1026E
J-S

SIMD
Instructions

Multi-processing
V6 Memory
architecture
(VMSA)

ARM1136EJ
-S

Unaligned data
support

Example ARM-based System

16 bit RAM

32 bit RAM
Interrupt
Controller
nIRQ

8 bit ROM

nFIQ

ARM
Core

Peripherals

I/O

AMBA
Arbiter

External
RAM

ARM

TIC
External
Bus
Interface

Decoder

Remap/
Pause

AHB or ASB

APB

System Bus

Peripheral Bus

AMBA

ADK
Complete AMBA Design Kit

Interrupt
Controller

On-chip
RAM

Advanced Microcontroller Bus

Architecture

Timer

Bus Interface
Bridge

External
ROM

Reset

ACT
AMBA Compliance Testbench

PrimeCell
ARMs AMBA compliant peripherals

AMBA
The objective of the AMBA specification is to:

Facilitate right-first-time development of embedded microcontroller products with one or more CPUs,
GPUs or signal processors,
Be technology independent, to allow reuse of IP cores, peripheral and system macrocells across
diverse IC processes,
Encourage modular system design to improve processor independence, and the development of
reusable peripheral and system IP libraries
Minimize silicon infrastructure while supporting high performance and low power on-chip
communication.