Computer Organization & Design: Bilgisayar Organizasyonu & Tasarimi

BLGSAYAR ORGANZASYONU &
TASARIMI Computer Organization
& Design
Blm 3
DATA-PATH
TASARIMI
stanbul niversitesi
Bilgisayar Temel Bileenleri

Processor
Input
Control
Datapath
Memory
Output
Where Does It All Begin?

In a register called program counter
(PC).
PC contains the memory address of
the next instruction to be executed.
In the beginning, PC contains the
address of the memory location
where the program begins.
Fall 08, Sep 22 . . .
ELEC 5200-001/6200-001 Lecture

5
Where is the Program?

Processor
Memory
Program counter
(register)
Start
address
Fall 08, Sep 22 . . .
ELEC 5200-001/6200-001 Lecture

5
Machine code
of program
Datapath and Control

Datapath: Memory, registers, adders, ALU, and
communication buses. Each step (fetch, decode,
execute) requires communication (data transfer)
paths between memory, registers and ALU.
Control: Datapath for each step is set up by control
signals that set up dataflow directions on
communication buses and select ALU and memory
functions. Control signals are generated by a control
unit consisting of one or more finite-state machines.
Fall 08, Sep 22 . . .
ELEC 5200-001/6200-001 Lecture

5
10
Basic Datapath
Single Registers
Register File
Memory (RAM , optional)
BUS
Data Flow Control Elements (Multiplexer, Decoder
etc.)
Arithmetic&Logic Unit (ALU)
Shifter
Register File: A Datapath

Component
5
Read
registers
Write
register
Write data
reg 1
reg 2
32
reg 1 data
32 Registers
(reg. file)
32
reg 2 data
32
RegWrite
from control
Fall 08, Sep 22 . . .
ELEC 5200-001/6200-001 Lecture

5
12
Multi-Operation ALU
Operation select
ALU function
000
001
010
110
111
AND
OR
Add
Subtract
Set on less than
Operation
select
from control
3
zero
ALU
result
overflow
zero = 1, when all bits of result are 0
Fall 08, Sep 22 . . .
ELEC 5200-001/6200-001 Lecture

5
13
Datapath Representation
n
Write
D address
D data
2m x n
Register file
m
A address
A data
Constant in
n
B data
n
1
0
MUX B
MB select
Bus A
Bus B
FS
V
C
N
Z
B address
Address out
Data out
B
Function
unit
F
n
MD select
0 1
MUX D
Data in
Datapath Example
L oad enable
Four parallel-load
registers
Two mux-based
register selectors
Register destination
decoder
Mux B for external
constant input
Buses A and B with external
address and data outputs
ALU and Shifter with
Mux F for output select
Mux D for external data input
Logic for generating status bits
V, C, N, Z
A select
Write
D data
n
Load
B address
R0
n
B select
A address
Load
R1
0
1
MU X
2
3
n
n
Load
0
1
MU X
2
3
R2
n
Load
R3
0 1 2 3
Register file
Decoder
D address
2
Constant in n
Destination select
MB select
A data
n
MU X B
BusA
C
N
Z
A
B
G select
A
B
4
S2:0 || Cin
A rithmetic/logic
unit (A LU )
G
Zero Detect
MF select
n
0
1
MUX F
F
n
0
1
MD select
MUX D
Bus D
A ddress
out
Data
out
n
n
Bus B
B data
H select
2
0
n
S
IR
B
Shifter
IL
H
n
Function unit
n
Data in
Definition of Function Unit Select (FS)

G Select,H Select,andMF
Codes
in T
of FS Codes
FS(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
MF
Select
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
G
H
Select(3:0) Select(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1X00
1X01
1X10
1X11
XXXX
XXXX
XXXX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
00
01
10
Micr ooperation
F A
F A 1
F A B
F A B 1
F A B
F A B 1
F A 1
F A
F A B
F A B
F A B
F A
F B
F sr B
F sl B
Boolean
Equations:
MFS = F3 F2
GSi = Fi
HSi = Fi
The Control Word

The datapath has many control inputs
The signals driving these inputs can be
defined and organized into a control word
To execute a microinstruction, we apply
control word values for a clock cycle. For
most microoperations, the positive edge of
the clock cycle is needed to perform the
register load
The datapath control word format and the
field definitions are shown on the next slide
The Control Word Fields

1514 13 12 1110 9 8 7 6 5 4 3 2 1 0
DA
Fields
AA
BA
M
B
FS
M R
D W
Control word
DA D Address
AA A Address
BA B Address
MB Mux B
FS Function Select
MD Mux D
RW Register Write
The connections to datapath are shown in the next slide
Control Word
Block Diagram
n
D data
RW 0
Write
15
DA 14
13
D address
12
AA 11
10
A address
8x n
Register file
A data
n
Constant in
MB 6
9
8 BA
7
B address
B data
n
n
1 0
MUX B
Bus A
n
n
Bus B
A
V
C
N
Z
Data out
B
5
4 FS
3
2
Function
unit
n
0
MD 1
Address out
MUX D
Bus D
Data in
Control Word Encoding
Encoding of Control
W
DA, AA, BA
MB
FS
Function
Code
Function
Code Function
R0
R1
R2
R3
R4
R5
R6
R7
000
001
010
011
100
101
110
111
Register 0
Constant1
MD
Code
Function
RW
Code
F A
0000 Function 0
0001 Data In 1
F A 1
0010
F A B
F A B 1 0011
F A B
0100
F A B 1 0101
F A 1
0110
F A
0111
F A B
1000
F A B
1001
1010
F A B
1011
F A
1100
F B
1101
F sr B
1110
F sl B
Function
Code
No write 0
Write
1
Datapath Example: Performing a

Microoperation
Load enable
Microoperation: R0 R1 + R2
Apply 01 to A select to place
contents of R1 onto Bus A
A select
Write
D data
n
Load
Apply 10 to B select to place

contents of R2 onto B data and
apply 0 to MB select to place
B data on Bus B
R1
0
1
MU X
2
3
n
n
Load
0
1
MUX
2
3
R2
n
Load
R3
0 1 2 3
Register file
Decoder
D address
2
Constant in n
Destination select
MB select
Apply 00 to Destination select

to enable the Load input to R0
Apply 1 to Load Enable to force the Load input to R0 to 1 so that
R0 is loaded on the clock pulse (not shown)
The overall microoperation requires
1 clock cycle
2
n
Load
Apply 0010 to G select to perform

addition G = Bus A + Bus B
Apply 0 to MF select and 0 to MD
select to place the value of G onto BUS
D
B address
R0
n
A data
n
N
Z
A
B
G select
A
B
4
S2:0 || Cin
A rithmetic/logic
unit (A L U)
G
Zero Detect
MF select
n
0
1
MU X F
F
n
0
1
MD select
MUX D
Bus D
A ddress
out
Data
out
n
n
Bus B
B data
MU X B
BusA
B select
A address
H select
2
0
n
S
IR
B
Shifter
IL
H
n
Function unit
n
Data in
Datapath Example: Key Control Actions

for Microoperation Alternatives
Perform a shift microoperation

apply 1 to MF select
Use a constant in a microoperation using Bus B apply 1
to MB select
Provide an address and data
for a memory or output write
microoperation apply 0 to
Load enable to prevent register
loading
Provide an address and obtain
data for a memory or output
read microoperation apply 1
to MD select
For some of the above, other
control signals become don't
cares
Load enable
A select
Write
D data
n
Load
B address
R0
n
B select
A address
Load
R1
0
1
MU X
2
3
n
n
Load
0
1
MUX
2
3
R2
n
Load
R3
0 1 2 3
Register file
Decoder
D address
2
Constant in n
Destination select
MB select
A data
n
MU X B
BusA
C
N
Z
A
B
G select
A
B
4
S2:0 || Cin
A rithmetic/logic
unit (A L U)
G
Zero Detect
MF select
n
0
1
MU X F
F
n
0
1
MD select
MUX D
Bus D
A ddress
out
Data
out
n
n
Bus B
B data
H select
2
0
n
S
IR
B
Shifter
IL
H
n
Function unit
n
Data in
Microoperations for the Datapath Symbolic

Representation
Micr oop eratio n
DA
AA
BA
MB
FS
MD
RW
R1 R2 R3
R4 sl R6
R7 R7 + 1
R1 R0 + 2
Data out R3
R4 Data in
R5 0
R1
R4
R7
R1
R4
R5
R2
R7
R0
R3
R6
R3
Register
Register
Register
Constant
Register
Register
F = A++
B 1
F = sl B
F = A+ 1
F = A+ B
F = A B
Function
Function
Function
Function
Data in
Function
Write
Write
Write
Write
No Write
Write
Write
R0 R0
Microoperations for the

m
Microoperations
fromaT - Binary
Binary Co
Datapath
Representation
Microoperatio n
DA
AA
BA
MB
FS
MD
RW
R1 R2 R3
R4 sl R6
R7 R7 + 1
R1 R0 + 2
Data out R3
R4 Data in
R5 0
001
100
111
001
XXX
100
101
010
XXX
111
000
XXX
XXX
000
011
110
XXX
XXX
011
XXX
000
0
0
0
1
0
X
0
0101
1110
0001
0010
0
0
0
0
X
1
0
1
1
1
1
0
XXXX
XXXX
1010
Results of simulation of the above

on the next slide
1
1
Datapath Simulation
Clock
DA
AA
BA
14
FS
Constant_in X
7
5
10
MB
A ddress_out
D ata_out
18
D ata_in
18
MD
RW
reg0
reg1
reg2
reg3
reg4
reg5
reg6
reg7
Status_bits 2
255
12
18
0
8
Arithmetic Logic Unit (ALU)

In this and the next section, we deal with detailed
design of typical ALUs and shifters
Decompose the ALU into:
An arithmetic circuit
A logic circuit
A selector to pick between the two circuits
Arithmetic circuit design

Decompose the arithmetic circuit into:
An n-bit parallel adder
A block of logic that selects four choices for the B input to
the adder
See next slide for diagram
Arithmetic Circuit Design

(continued)
There are only four functions of B to select as Y in G = A
+ Y:
Cin = 0
Cin = 1
G=
G=A+
A =A+
0
1
G
G=A+B+
B
B
G=A+B 1
G=A+B+
1
B
G=A
G=
1
1
A
C
What functions are implemented with carry-in to the
adder = 0? n=1?
in
B
S0
n-bit
parallel
add
n
B input
logic
S1
Cout
Cin
Arithmetic Circuit Design

(continued)
Adding selection codes to the functions of B:
TABLE 9-1
FunctionTable for Arithmetic Circuit
Select
G = A+
1Y +
1Cin
Input
S1
S0
0
0
1
1
0
1
0
1
all 0s
B
B
all 1s
Cin
G
G
G
G
=0
A (transfer)
A +B (add)
A B
A 1 (decrement)
Cin
G
G
G
=1
A
A
A
+1 (increment)
B 1
B 1 (subtract)
(transfer)
The useful arithmetic functions are labeled in the table

Note that all four functions of B produce at least one useful
function
Logic Circuit
Here we custom design a circuit for bit G i by

beginning with a truth table organized as a K-map
and assigning (S1, S0) codes to AND, OR, etc.
Gi = S0AB+S1AB+S0AB+S1S0A
S1S0 AND OR XOR NOT

AiBi
00
01
11
10
00
0
0
1
0
01
0
1
1
1
11
0
1
0
1
10
1
1
0
0
Arithmetic Logic Unit (ALU)

C0 5
Ci
Ci
Ai
Ai
Bi
Bi
S0
S0
S1
S1
Ci 1
One stage of
arithmetic
circuit
Ai
2-to-1
0 MU X
Gi
1
B i One stage of
S logic circuit
Cin
S1
S2
The next most significant select signals, S0 for the arithmetic

circuit and S1 for the logic circuit, are wired together, completing
the two select signals for the logic circuit.
The remaining S1 completes the three select signals for the
arithmetic circuit.
Combinational Shifter
Parameters
Direction: Left, Right
Number of positions with examples:

Single bit:
1 position
0 and 1 positions
Multiple bit:
1 to n 1 positions
0 to n 1 positions
Filling of vacant positions

Many options depending on instruction set
Here, will provide input lines or zero fill
4-Bit Basic Left/Right Shifter

B3
B2
B1
B0
Serial
output L
Serial
output R
IL
IR
0 1 2M
S
U
X
S
0 1 2M
S
U
X
0 1 2M
S
U
X
0 1 2M
S
U
X
2
H3
H2
H1
H0
Serial Inputs:
IR for right shift
IL for left shift
Shift Functions:
(S1, S0) = 00 Pass B
Serial Outputs
unchanged
R for right shift (Same as MSB
01 Right shift
input)
L for left shift (Same as LSB input)
10 Left shift
11 Unused

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BLGSAYAR ORGANZASYONU &

TASARIMI Computer Organization

Bilgisayar Temel Bileenleri

Where Does It All Begin?

Fall 08, Sep 22 . . .

ELEC 5200-001/6200-001 Lecture

Where is the Program?

Fall 08, Sep 22 . . .

ELEC 5200-001/6200-001 Lecture

Datapath and Control

Fall 08, Sep 22 . . .

ELEC 5200-001/6200-001 Lecture

Register File: A Datapath

Fall 08, Sep 22 . . .

ELEC 5200-001/6200-001 Lecture

zero = 1, when all bits of result are 0

Fall 08, Sep 22 . . .

ELEC 5200-001/6200-001 Lecture

Definition of Function Unit Select (FS)

The Control Word

The Control Word Fields

The connections to datapath are shown in the next slide

Control Word Encoding

Datapath Example: Performing a

Apply 10 to B select to place

Apply 00 to Destination select

Apply 0010 to G select to perform

Datapath Example: Key Control Actions

Perform a shift microoperation

Microoperations for the Datapath Symbolic

Microoperations for the

Results of simulation of the above

Arithmetic Logic Unit (ALU)

Arithmetic circuit design

Arithmetic Circuit Design

Arithmetic Circuit Design

Adding selection codes to the functions of B:

The useful arithmetic functions are labeled in the table

Here we custom design a circuit for bit G i by

S1S0 AND OR XOR NOT

Arithmetic Logic Unit (ALU)

The next most significant select signals, S0 for the arithmetic

Number of positions with examples:

Filling of vacant positions

4-Bit Basic Left/Right Shifter

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