What is a Multirate Digital Signal

Processing?
A digital signal processing system
that uses signals with different
sampling frequencies is probably
performing multirate digital signal
processing.Multirate digital signal
processing often uses sample rate
conversion to convert from one
sampling frequency to another
sampling frequency.Sample rate
conversion uses decimation to
 Applications
Up-sampling, i.e., increasing the sampling frequency, before D/A conversion in
order to relax the requirements of the analog lowpass antialiasing filter. This
technique is used in audio CD, where the sampling frequency 44.1 kHz is increased
fourfold to 176.4 kHz before D/A conversion. Various systems in digital audio
signal processing often operate at different sampling rates. The connection of such
systems requires a conversion of sampling rate.
Decomposition of a signal into M components containing various frequency bands.
If the original signal is sampled at the sampling frequency fs (with a frequency
band of width fs/2, or half the sampling frequency), every component then contains
a frequency band of width 1 2 fs/M only, and can be represented using the
sampling rate fs/M. This allows for efficient parallel signal processing with
processors operating at lower sampling rates. The technique is also applied to data
compression in subband coding, for example in speech processing, where the
various frequency band components are represented with different word lengths.
In the implementation of high-performance filtering operations, where a very
narrow transition band is required. The requirement of narrow transition bands
leads to very high filter orders. However, by decomposing the signal into a number
of subbands containing the passband, stopband and transition bands, each
component can be processed at a lower rate, and the transition band will be less
narrow. Hence the required filter complexity may be reduced significantly.
Sample Rate Conversion: Changing
the sampling frequency in the analog
domain requires: digital to analog
conversion then analog to digital
conversion at a different sampling
frequency. Both Digital to analog
conversion Analog to digital
conversion introduce errors and
noise into the signal. Therefore
sample rate conversion is done in
digital domain and uses a
combination of:
Decimation, and Interpolation.
 Finite Word length Effects
Practical digital filters must be implemented with
finite precision numbers and arithmetic. As a
result, both the filter coefficients and the filter
input and output signals are in discrete form. This
leads to four types of finite wordlength effects.
Discretization (quantization) of the filter
coefficients has the effect of perturbing the
location of the filter poles and zeroes. As a result,
the actual filter response differs slightly from the
ideal response. This deterministic frequency
response error is referred to as coefficient
quantization error. The use of finite precision
arithmetic makes it necessary to quantize filter
calculations by rounding or truncation. Roundoff
noise is that errorin the filter output that results
Quantization of the filter calculations also
renders the filter slightly nonlinear. For large
signals this nonlinearity is negligible and
roundoff noise is the major concern.
However, for recursive filters with a zero or
constant input, this nonlinearity can cause
spurious oscillations called limit cycles. With
fixed-point arithmetic it is possible for filter
calculations to overflow. The term overflow
oscillation, sometimes also called adder
overflow limit cycle, refers to a high-level
oscillation that can exist in an otherwise
stable filter due to the nonlinearity
associated with the overflow of internal filter
calculations.
LIMIT CYCLES:A limit cycle, sometimes referred to as
a multiplier roundoff limit cycle, is a low-level
oscillation that can exist in an otherwise stable filter
as a result of the nonlinearity associated with
rounding (or truncating) internal filter calculations
[11]. Limit cycles require recursion to exist and do not
occur in nonrecursive FIR filters.
Limit cycles are primarily of concern in fixed-point
recursive filters. As long as floating-point filters
are realized as the parallel or cascade connection
of first- and second-order subfilters, limit cycles
will generally not be a problem since limit cycles
are practically not observable in first- and second-
order systems implemented with 32-bit floating-
point arithmetic . It has been shown that such
systems must have an extremely small margin of
stability for limit cycles to exist at anything other
than underflow levels, which are at an amplitude
There are at least three ways of dealing with limit
cycles when fixed-point arithmetic is used. One is
to determine a bound on the maximum limit cycle
amplitude, expressed as an integral number of
quantization steps [13]. It is then possible to
choose a word length that makes the limit cycle
amplitude acceptably low. Alternately, limit cycles
can be prevented by randomly rounding
calculations up or down [14]. However, this
approach is complicated to implement. The third
approach is to properly choose the filter realization
structure and then quantize the filter calculations
using magnitude truncation [15, 16]. This approach
has the disadvantage of producing more roundoff
noise than truncation or rounding.
OVER FLOW OSCILLATIONS: An overflow
oscillation, sometimes also referred to as an
adder overflow limit cycle, is a highlevel
oscillation that can exist in an otherwise stable
fixed-point filter due to the gross nonlinearity
associated with the overflow of internal filter
calculations [17]. Like limit cycles, overflow
oscillations require recursion to exist and do not
occur in nonrecursive FIR filters. Overflow
oscillations also do not occur with floating-point
arithmetic due to the virtual impossibility of
overflow
There are several ways to prevent overflow
oscillations in fixed-point filter realizations. The
most obvious is to scale the filter calculations so
as to render overflow impossible. However, this
may unacceptably restrict the filter dynamic
range. Another method is to force completed
sums-of -products to saturate at 1, rather than
overflowing . It is important to saturate only the
completed sum, since intermediate overflows in
twos complement arithmetic do not affect the
accuracy of the final result. Most fixed-point digital
signal processors provide for automatic saturation
of completed sums if their saturation arithmetic
feature is enabled. Yet another way to avoid
overflow oscillations is to use a filter structure for
which any internal filter transient is guaranteed to
decay to zero. Such structures are desirable
Roundoff noise:To determine the roundoff noise at
the output of a digital filter we will assume that the
noise due to a quantization is stationary, white, and
uncorrelated with the filter input, output, and internal
variables. This assumption is good if the filter input
changes from sample to sample in a sufficiently
complex manner. It is not valid for zero or constant
inputs for which the effects of rounding are analyzed
from a limit cycle perspective. To satisfy the
assumption of a sufficiently complex input, roundoff
noise in digital filters is often calculated for the case
of a zero-mean white noise filter input signal x(n) of
variance 2 x .. Another assumption that will be
made in calculating roundoff noise is that the product
of two quantization errors is zero. To justify this
assumption, consider the case of a 16-b fixed-point
processor.